drivers/crypto/caam/ctrl.c

   1 /* * CAAM control-plane driver backend
   2  * Controller-level driver, kernel property detection, initialization
   3  *
   4  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <linux/device.h>
   8 #include <linux/of_address.h>
   9 #include <linux/of_irq.h>
  10
  11 #include "compat.h"
  12 #include "regs.h"
  13 #include "intern.h"
  14 #include "jr.h"
  15 #include "desc_constr.h"
  16 #include "ctrl.h"
  17
  18 bool caam_little_end;
  19 EXPORT_SYMBOL(caam_little_end);
  20
  21 /*
  22  * i.MX targets tend to have clock control subsystems that can
  23  * enable/disable clocking to our device.
  24  */
  25 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
  26 static inline struct clk *caam_drv_identify_clk(struct device *dev,
  27                                                 char *clk_name)
  28 {
  29         return devm_clk_get(dev, clk_name);
  30 }
  31 #else
  32 static inline struct clk *caam_drv_identify_clk(struct device *dev,
  33                                                 char *clk_name)
  34 {
  35         return NULL;
  36 }
  37 #endif
  38
  39 /*
  40  * Descriptor to instantiate RNG State Handle 0 in normal mode and
  41  * load the JDKEK, TDKEK and TDSK registers
  42  */
  43 static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
  44 {
  45         u32 *jump_cmd, op_flags;
  46
  47         init_job_desc(desc, 0);
  48
  49         op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  50                         (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
  51
  52         /* INIT RNG in non-test mode */
  53         append_operation(desc, op_flags);
  54
  55         if (!handle && do_sk) {
  56                 /*
  57                  * For SH0, Secure Keys must be generated as well
  58                  */
  59
  60                 /* wait for done */
  61                 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
  62                 set_jump_tgt_here(desc, jump_cmd);
  63
  64                 /*
  65                  * load 1 to clear written reg:
  66                  * resets the done interrrupt and returns the RNG to idle.
  67                  */
  68                 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
  69
  70                 /* Initialize State Handle  */
  71                 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  72                                  OP_ALG_AAI_RNG4_SK);
  73         }
  74
  75         append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
  76 }
  77
  78 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
  79 static void build_deinstantiation_desc(u32 *desc, int handle)
  80 {
  81         init_job_desc(desc, 0);
  82
  83         /* Uninstantiate State Handle 0 */
  84         append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  85                          (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
  86
  87         append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
  88 }
  89
  90 /*
  91  * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
  92  *                        the software (no JR/QI used).
  93  * @ctrldev - pointer to device
  94  * @status - descriptor status, after being run
  95  *
  96  * Return: - 0 if no error occurred
  97  *         - -ENODEV if the DECO couldn't be acquired
  98  *         - -EAGAIN if an error occurred while executing the descriptor
  99  */
 100 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
 101                                         u32 *status)
 102 {
 103         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 104         struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
 105         struct caam_deco __iomem *deco = ctrlpriv->deco;
 106         unsigned int timeout = 100000;
 107         u32 deco_dbg_reg, flags;
 108         int i;
 109
 110
 111         if (ctrlpriv->virt_en == 1) {
 112                 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
 113
 114                 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
 115                        --timeout)
 116                         cpu_relax();
 117
 118                 timeout = 100000;
 119         }
 120
 121         clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
 122
 123         while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
 124                                                                  --timeout)
 125                 cpu_relax();
 126
 127         if (!timeout) {
 128                 dev_err(ctrldev, "failed to acquire DECO 0\n");
 129                 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 130                 return -ENODEV;
 131         }
 132
 133         for (i = 0; i < desc_len(desc); i++)
 134                 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
 135
 136         flags = DECO_JQCR_WHL;
 137         /*
 138          * If the descriptor length is longer than 4 words, then the
 139          * FOUR bit in JRCTRL register must be set.
 140          */
 141         if (desc_len(desc) >= 4)
 142                 flags |= DECO_JQCR_FOUR;
 143
 144         /* Instruct the DECO to execute it */
 145         clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
 146
 147         timeout = 10000000;
 148         do {
 149                 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
 150                 /*
 151                  * If an error occured in the descriptor, then
 152                  * the DECO status field will be set to 0x0D
 153                  */
 154                 if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) ==
 155                     DESC_DBG_DECO_STAT_HOST_ERR)
 156                         break;
 157                 cpu_relax();
 158         } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
 159
 160         *status = rd_reg32(&deco->op_status_hi) &
 161                   DECO_OP_STATUS_HI_ERR_MASK;
 162
 163         if (ctrlpriv->virt_en == 1)
 164                 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
 165
 166         /* Mark the DECO as free */
 167         clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 168
 169         if (!timeout)
 170                 return -EAGAIN;
 171
 172         return 0;
 173 }
 174
 175 /*
 176  * instantiate_rng - builds and executes a descriptor on DECO0,
 177  *                   which initializes the RNG block.
 178  * @ctrldev - pointer to device
 179  * @state_handle_mask - bitmask containing the instantiation status
 180  *                      for the RNG4 state handles which exist in
 181  *                      the RNG4 block: 1 if it's been instantiated
 182  *                      by an external entry, 0 otherwise.
 183  * @gen_sk  - generate data to be loaded into the JDKEK, TDKEK and TDSK;
 184  *            Caution: this can be done only once; if the keys need to be
 185  *            regenerated, a POR is required
 186  *
 187  * Return: - 0 if no error occurred
 188  *         - -ENOMEM if there isn't enough memory to allocate the descriptor
 189  *         - -ENODEV if DECO0 couldn't be acquired
 190  *         - -EAGAIN if an error occurred when executing the descriptor
 191  *            f.i. there was a RNG hardware error due to not "good enough"
 192  *            entropy being aquired.
 193  */
 194 static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
 195                            int gen_sk)
 196 {
 197         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 198         struct caam_ctrl __iomem *ctrl;
 199         u32 *desc, status = 0, rdsta_val;
 200         int ret = 0, sh_idx;
 201
 202         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 203         desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
 204         if (!desc)
 205                 return -ENOMEM;
 206
 207         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 208                 /*
 209                  * If the corresponding bit is set, this state handle
 210                  * was initialized by somebody else, so it's left alone.
 211                  */
 212                 if ((1 << sh_idx) & state_handle_mask)
 213                         continue;
 214
 215                 /* Create the descriptor for instantiating RNG State Handle */
 216                 build_instantiation_desc(desc, sh_idx, gen_sk);
 217
 218                 /* Try to run it through DECO0 */
 219                 ret = run_descriptor_deco0(ctrldev, desc, &status);
 220
 221                 /*
 222                  * If ret is not 0, or descriptor status is not 0, then
 223                  * something went wrong. No need to try the next state
 224                  * handle (if available), bail out here.
 225                  * Also, if for some reason, the State Handle didn't get
 226                  * instantiated although the descriptor has finished
 227                  * without any error (HW optimizations for later
 228                  * CAAM eras), then try again.
 229                  */
 230                 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
 231                 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
 232                     !(rdsta_val & (1 << sh_idx)))
 233                         ret = -EAGAIN;
 234                 if (ret)
 235                         break;
 236                 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
 237                 /* Clear the contents before recreating the descriptor */
 238                 memset(desc, 0x00, CAAM_CMD_SZ * 7);
 239         }
 240
 241         kfree(desc);
 242
 243         return ret;
 244 }
 245
 246 /*
 247  * deinstantiate_rng - builds and executes a descriptor on DECO0,
 248  *                     which deinitializes the RNG block.
 249  * @ctrldev - pointer to device
 250  * @state_handle_mask - bitmask containing the instantiation status
 251  *                      for the RNG4 state handles which exist in
 252  *                      the RNG4 block: 1 if it's been instantiated
 253  *
 254  * Return: - 0 if no error occurred
 255  *         - -ENOMEM if there isn't enough memory to allocate the descriptor
 256  *         - -ENODEV if DECO0 couldn't be acquired
 257  *         - -EAGAIN if an error occurred when executing the descriptor
 258  */
 259 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
 260 {
 261         u32 *desc, status;
 262         int sh_idx, ret = 0;
 263
 264         desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
 265         if (!desc)
 266                 return -ENOMEM;
 267
 268         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 269                 /*
 270                  * If the corresponding bit is set, then it means the state
 271                  * handle was initialized by us, and thus it needs to be
 272                  * deinitialized as well
 273                  */
 274                 if ((1 << sh_idx) & state_handle_mask) {
 275                         /*
 276                          * Create the descriptor for deinstantating this state
 277                          * handle
 278                          */
 279                         build_deinstantiation_desc(desc, sh_idx);
 280
 281                         /* Try to run it through DECO0 */
 282                         ret = run_descriptor_deco0(ctrldev, desc, &status);
 283
 284                         if (ret ||
 285                             (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
 286                                 dev_err(ctrldev,
 287                                         "Failed to deinstantiate RNG4 SH%d\n",
 288                                         sh_idx);
 289                                 break;
 290                         }
 291                         dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
 292                 }
 293         }
 294
 295         kfree(desc);
 296
 297         return ret;
 298 }
 299
 300 static int caam_remove(struct platform_device *pdev)
 301 {
 302         struct device *ctrldev;
 303         struct caam_drv_private *ctrlpriv;
 304         struct caam_ctrl __iomem *ctrl;
 305
 306         ctrldev = &pdev->dev;
 307         ctrlpriv = dev_get_drvdata(ctrldev);
 308         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 309
 310         /* Remove platform devices under the crypto node */
 311         of_platform_depopulate(ctrldev);
 312
 313         /* De-initialize RNG state handles initialized by this driver. */
 314         if (ctrlpriv->rng4_sh_init)
 315                 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
 316
 317         /* Shut down debug views */
 318 #ifdef CONFIG_DEBUG_FS
 319         debugfs_remove_recursive(ctrlpriv->dfs_root);
 320 #endif
 321
 322         /* Unmap controller region */
 323         iounmap(ctrl);
 324
 325         /* shut clocks off before finalizing shutdown */
 326         clk_disable_unprepare(ctrlpriv->caam_ipg);
 327         clk_disable_unprepare(ctrlpriv->caam_mem);
 328         clk_disable_unprepare(ctrlpriv->caam_aclk);
 329         if (ctrlpriv->caam_emi_slow)
 330                 clk_disable_unprepare(ctrlpriv->caam_emi_slow);
 331         return 0;
 332 }
 333
 334 /*
 335  * kick_trng - sets the various parameters for enabling the initialization
 336  *             of the RNG4 block in CAAM
 337  * @pdev - pointer to the platform device
 338  * @ent_delay - Defines the length (in system clocks) of each entropy sample.
 339  */
 340 static void kick_trng(struct platform_device *pdev, int ent_delay)
 341 {
 342         struct device *ctrldev = &pdev->dev;
 343         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 344         struct caam_ctrl __iomem *ctrl;
 345         struct rng4tst __iomem *r4tst;
 346         u32 val;
 347
 348         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 349         r4tst = &ctrl->r4tst[0];
 350
 351         /* put RNG4 into program mode */
 352         clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM);
 353
 354         /*
 355          * Performance-wise, it does not make sense to
 356          * set the delay to a value that is lower
 357          * than the last one that worked (i.e. the state handles
 358          * were instantiated properly. Thus, instead of wasting
 359          * time trying to set the values controlling the sample
 360          * frequency, the function simply returns.
 361          */
 362         val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
 363               >> RTSDCTL_ENT_DLY_SHIFT;
 364         if (ent_delay <= val)
 365                 goto start_rng;
 366
 367         val = rd_reg32(&r4tst->rtsdctl);
 368         val = (val & ~RTSDCTL_ENT_DLY_MASK) |
 369               (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
 370         wr_reg32(&r4tst->rtsdctl, val);
 371         /* min. freq. count, equal to 1/4 of the entropy sample length */
 372         wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
 373         /* disable maximum frequency count */
 374         wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
 375         /* read the control register */
 376         val = rd_reg32(&r4tst->rtmctl);
 377 start_rng:
 378         /*
 379          * select raw sampling in both entropy shifter
 380          * and statistical checker; ; put RNG4 into run mode
 381          */
 382         clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);
 383 }
 384
 385 /**
 386  * caam_get_era() - Return the ERA of the SEC on SoC, based
 387  * on "sec-era" propery in the DTS. This property is updated by u-boot.
 388  **/
 389 int caam_get_era(void)
 390 {
 391         struct device_node *caam_node;
 392         int ret;
 393         u32 prop;
 394
 395         caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
 396         ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
 397         of_node_put(caam_node);
 398
 399         return ret ? -ENOTSUPP : prop;
 400 }
 401 EXPORT_SYMBOL(caam_get_era);
 402
 403 #ifdef CONFIG_DEBUG_FS
 404 static int caam_debugfs_u64_get(void *data, u64 *val)
 405 {
 406         *val = caam64_to_cpu(*(u64 *)data);
 407         return 0;
 408 }
 409
 410 static int caam_debugfs_u32_get(void *data, u64 *val)
 411 {
 412         *val = caam32_to_cpu(*(u32 *)data);
 413         return 0;
 414 }
 415
 416 DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u32_ro, caam_debugfs_u32_get, NULL, "%llu\n");
 417 DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u64_ro, caam_debugfs_u64_get, NULL, "%llu\n");
 418 #endif
 419
 420 static const struct of_device_id caam_match[] = {
 421         {
 422                 .compatible = "fsl,sec-v4.0",
 423         },
 424         {
 425                 .compatible = "fsl,sec4.0",
 426         },
 427         {},
 428 };
 429 MODULE_DEVICE_TABLE(of, caam_match);
 430
 431 /* Probe routine for CAAM top (controller) level */
 432 static int caam_probe(struct platform_device *pdev)
 433 {
 434         int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
 435         u64 caam_id;
 436         struct device *dev;
 437         struct device_node *nprop, *np;
 438         struct caam_ctrl __iomem *ctrl;
 439         struct caam_drv_private *ctrlpriv;
 440         struct clk *clk;
 441 #ifdef CONFIG_DEBUG_FS
 442         struct caam_perfmon *perfmon;
 443 #endif
 444         u32 scfgr, comp_params;
 445         u32 cha_vid_ls;
 446         int pg_size;
 447         int BLOCK_OFFSET = 0;
 448
 449         ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
 450         if (!ctrlpriv)
 451                 return -ENOMEM;
 452
 453         dev = &pdev->dev;
 454         dev_set_drvdata(dev, ctrlpriv);
 455         ctrlpriv->pdev = pdev;
 456         nprop = pdev->dev.of_node;
 457
 458         /* Enable clocking */
 459         clk = caam_drv_identify_clk(&pdev->dev, "ipg");
 460         if (IS_ERR(clk)) {
 461                 ret = PTR_ERR(clk);
 462                 dev_err(&pdev->dev,
 463                         "can't identify CAAM ipg clk: %d\n", ret);
 464                 return ret;
 465         }
 466         ctrlpriv->caam_ipg = clk;
 467
 468         clk = caam_drv_identify_clk(&pdev->dev, "mem");
 469         if (IS_ERR(clk)) {
 470                 ret = PTR_ERR(clk);
 471                 dev_err(&pdev->dev,
 472                         "can't identify CAAM mem clk: %d\n", ret);
 473                 return ret;
 474         }
 475         ctrlpriv->caam_mem = clk;
 476
 477         clk = caam_drv_identify_clk(&pdev->dev, "aclk");
 478         if (IS_ERR(clk)) {
 479                 ret = PTR_ERR(clk);
 480                 dev_err(&pdev->dev,
 481                         "can't identify CAAM aclk clk: %d\n", ret);
 482                 return ret;
 483         }
 484         ctrlpriv->caam_aclk = clk;
 485
 486         if (!of_machine_is_compatible("fsl,imx6ul")) {
 487                 clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");
 488                 if (IS_ERR(clk)) {
 489                         ret = PTR_ERR(clk);
 490                         dev_err(&pdev->dev,
 491                                 "can't identify CAAM emi_slow clk: %d\n", ret);
 492                         return ret;
 493                 }
 494                 ctrlpriv->caam_emi_slow = clk;
 495         }
 496
 497         ret = clk_prepare_enable(ctrlpriv->caam_ipg);
 498         if (ret < 0) {
 499                 dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
 500                 return ret;
 501         }
 502
 503         ret = clk_prepare_enable(ctrlpriv->caam_mem);
 504         if (ret < 0) {
 505                 dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",
 506                         ret);
 507                 goto disable_caam_ipg;
 508         }
 509
 510         ret = clk_prepare_enable(ctrlpriv->caam_aclk);
 511         if (ret < 0) {
 512                 dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
 513                 goto disable_caam_mem;
 514         }
 515
 516         if (ctrlpriv->caam_emi_slow) {
 517                 ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
 518                 if (ret < 0) {
 519                         dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
 520                                 ret);
 521                         goto disable_caam_aclk;
 522                 }
 523         }
 524
 525         /* Get configuration properties from device tree */
 526         /* First, get register page */
 527         ctrl = of_iomap(nprop, 0);
 528         if (ctrl == NULL) {
 529                 dev_err(dev, "caam: of_iomap() failed\n");
 530                 ret = -ENOMEM;
 531                 goto disable_caam_emi_slow;
 532         }
 533
 534         caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
 535                                   (CSTA_PLEND | CSTA_ALT_PLEND));
 536
 537         /* Finding the page size for using the CTPR_MS register */
 538         comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
 539         pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
 540
 541         /* Allocating the BLOCK_OFFSET based on the supported page size on
 542          * the platform
 543          */
 544         if (pg_size == 0)
 545                 BLOCK_OFFSET = PG_SIZE_4K;
 546         else
 547                 BLOCK_OFFSET = PG_SIZE_64K;
 548
 549         ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
 550         ctrlpriv->assure = (struct caam_assurance __iomem __force *)
 551                            ((__force uint8_t *)ctrl +
 552                             BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
 553                            );
 554         ctrlpriv->deco = (struct caam_deco __iomem __force *)
 555                          ((__force uint8_t *)ctrl +
 556                          BLOCK_OFFSET * DECO_BLOCK_NUMBER
 557                          );
 558
 559         /* Get the IRQ of the controller (for security violations only) */
 560         ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
 561
 562         /*
 563          * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
 564          * long pointers in master configuration register
 565          */
 566         clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR,
 567                       MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
 568                       MCFGR_WDENABLE | MCFGR_LARGE_BURST |
 569                       (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
 570
 571         /*
 572          *  Read the Compile Time paramters and SCFGR to determine
 573          * if Virtualization is enabled for this platform
 574          */
 575         scfgr = rd_reg32(&ctrl->scfgr);
 576
 577         ctrlpriv->virt_en = 0;
 578         if (comp_params & CTPR_MS_VIRT_EN_INCL) {
 579                 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
 580                  * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
 581                  */
 582                 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
 583                     (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
 584                        (scfgr & SCFGR_VIRT_EN)))
 585                                 ctrlpriv->virt_en = 1;
 586         } else {
 587                 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
 588                 if (comp_params & CTPR_MS_VIRT_EN_POR)
 589                                 ctrlpriv->virt_en = 1;
 590         }
 591
 592         if (ctrlpriv->virt_en == 1)
 593                 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
 594                               JRSTART_JR1_START | JRSTART_JR2_START |
 595                               JRSTART_JR3_START);
 596
 597         if (sizeof(dma_addr_t) == sizeof(u64)) {
 598                 if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
 599                         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
 600                 else
 601                         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
 602         } else {
 603                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
 604         }
 605         if (ret) {
 606                 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
 607                 goto iounmap_ctrl;
 608         }
 609
 610         ret = of_platform_populate(nprop, caam_match, NULL, dev);
 611         if (ret) {
 612                 dev_err(dev, "JR platform devices creation error\n");
 613                 goto iounmap_ctrl;
 614         }
 615
 616         ring = 0;
 617         for_each_available_child_of_node(nprop, np)
 618                 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
 619                     of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
 620                         ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
 621                                              ((__force uint8_t *)ctrl +
 622                                              (ring + JR_BLOCK_NUMBER) *
 623                                               BLOCK_OFFSET
 624                                              );
 625                         ctrlpriv->total_jobrs++;
 626                         ring++;
 627                 }
 628
 629         /* Check to see if QI present. If so, enable */
 630         ctrlpriv->qi_present =
 631                         !!(rd_reg32(&ctrl->perfmon.comp_parms_ms) &
 632                            CTPR_MS_QI_MASK);
 633         if (ctrlpriv->qi_present) {
 634                 ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
 635                                ((__force uint8_t *)ctrl +
 636                                  BLOCK_OFFSET * QI_BLOCK_NUMBER
 637                                );
 638                 /* This is all that's required to physically enable QI */
 639                 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
 640         }
 641
 642         /* If no QI and no rings specified, quit and go home */
 643         if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
 644                 dev_err(dev, "no queues configured, terminating\n");
 645                 ret = -ENOMEM;
 646                 goto caam_remove;
 647         }
 648
 649         cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
 650
 651         /*
 652          * If SEC has RNG version >= 4 and RNG state handle has not been
 653          * already instantiated, do RNG instantiation
 654          */
 655         if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
 656                 ctrlpriv->rng4_sh_init =
 657                         rd_reg32(&ctrl->r4tst[0].rdsta);
 658                 /*
 659                  * If the secure keys (TDKEK, JDKEK, TDSK), were already
 660                  * generated, signal this to the function that is instantiating
 661                  * the state handles. An error would occur if RNG4 attempts
 662                  * to regenerate these keys before the next POR.
 663                  */
 664                 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
 665                 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
 666                 do {
 667                         int inst_handles =
 668                                 rd_reg32(&ctrl->r4tst[0].rdsta) &
 669                                                                 RDSTA_IFMASK;
 670                         /*
 671                          * If either SH were instantiated by somebody else
 672                          * (e.g. u-boot) then it is assumed that the entropy
 673                          * parameters are properly set and thus the function
 674                          * setting these (kick_trng(...)) is skipped.
 675                          * Also, if a handle was instantiated, do not change
 676                          * the TRNG parameters.
 677                          */
 678                         if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
 679                                 dev_info(dev,
 680                                          "Entropy delay = %u\n",
 681                                          ent_delay);
 682                                 kick_trng(pdev, ent_delay);
 683                                 ent_delay += 400;
 684                         }
 685                         /*
 686                          * if instantiate_rng(...) fails, the loop will rerun
 687                          * and the kick_trng(...) function will modfiy the
 688                          * upper and lower limits of the entropy sampling
 689                          * interval, leading to a sucessful initialization of
 690                          * the RNG.
 691                          */
 692                         ret = instantiate_rng(dev, inst_handles,
 693                                               gen_sk);
 694                         if (ret == -EAGAIN)
 695                                 /*
 696                                  * if here, the loop will rerun,
 697                                  * so don't hog the CPU
 698                                  */
 699                                 cpu_relax();
 700                 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
 701                 if (ret) {
 702                         dev_err(dev, "failed to instantiate RNG");
 703                         goto caam_remove;
 704                 }
 705                 /*
 706                  * Set handles init'ed by this module as the complement of the
 707                  * already initialized ones
 708                  */
 709                 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
 710
 711                 /* Enable RDB bit so that RNG works faster */
 712                 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
 713         }
 714
 715         /* NOTE: RTIC detection ought to go here, around Si time */
 716
 717         caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
 718                   (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
 719
 720         /* Report "alive" for developer to see */
 721         dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
 722                  caam_get_era());
 723         dev_info(dev, "job rings = %d, qi = %d\n",
 724                  ctrlpriv->total_jobrs, ctrlpriv->qi_present);
 725
 726 #ifdef CONFIG_DEBUG_FS
 727         /*
 728          * FIXME: needs better naming distinction, as some amalgamation of
 729          * "caam" and nprop->full_name. The OF name isn't distinctive,
 730          * but does separate instances
 731          */
 732         perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
 733
 734         ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
 735         ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
 736
 737         /* Controller-level - performance monitor counters */
 738
 739         ctrlpriv->ctl_rq_dequeued =
 740                 debugfs_create_file("rq_dequeued",
 741                                     S_IRUSR | S_IRGRP | S_IROTH,
 742                                     ctrlpriv->ctl, &perfmon->req_dequeued,
 743                                     &caam_fops_u64_ro);
 744         ctrlpriv->ctl_ob_enc_req =
 745                 debugfs_create_file("ob_rq_encrypted",
 746                                     S_IRUSR | S_IRGRP | S_IROTH,
 747                                     ctrlpriv->ctl, &perfmon->ob_enc_req,
 748                                     &caam_fops_u64_ro);
 749         ctrlpriv->ctl_ib_dec_req =
 750                 debugfs_create_file("ib_rq_decrypted",
 751                                     S_IRUSR | S_IRGRP | S_IROTH,
 752                                     ctrlpriv->ctl, &perfmon->ib_dec_req,
 753                                     &caam_fops_u64_ro);
 754         ctrlpriv->ctl_ob_enc_bytes =
 755                 debugfs_create_file("ob_bytes_encrypted",
 756                                     S_IRUSR | S_IRGRP | S_IROTH,
 757                                     ctrlpriv->ctl, &perfmon->ob_enc_bytes,
 758                                     &caam_fops_u64_ro);
 759         ctrlpriv->ctl_ob_prot_bytes =
 760                 debugfs_create_file("ob_bytes_protected",
 761                                     S_IRUSR | S_IRGRP | S_IROTH,
 762                                     ctrlpriv->ctl, &perfmon->ob_prot_bytes,
 763                                     &caam_fops_u64_ro);
 764         ctrlpriv->ctl_ib_dec_bytes =
 765                 debugfs_create_file("ib_bytes_decrypted",
 766                                     S_IRUSR | S_IRGRP | S_IROTH,
 767                                     ctrlpriv->ctl, &perfmon->ib_dec_bytes,
 768                                     &caam_fops_u64_ro);
 769         ctrlpriv->ctl_ib_valid_bytes =
 770                 debugfs_create_file("ib_bytes_validated",
 771                                     S_IRUSR | S_IRGRP | S_IROTH,
 772                                     ctrlpriv->ctl, &perfmon->ib_valid_bytes,
 773                                     &caam_fops_u64_ro);
 774
 775         /* Controller level - global status values */
 776         ctrlpriv->ctl_faultaddr =
 777                 debugfs_create_file("fault_addr",
 778                                     S_IRUSR | S_IRGRP | S_IROTH,
 779                                     ctrlpriv->ctl, &perfmon->faultaddr,
 780                                     &caam_fops_u32_ro);
 781         ctrlpriv->ctl_faultdetail =
 782                 debugfs_create_file("fault_detail",
 783                                     S_IRUSR | S_IRGRP | S_IROTH,
 784                                     ctrlpriv->ctl, &perfmon->faultdetail,
 785                                     &caam_fops_u32_ro);
 786         ctrlpriv->ctl_faultstatus =
 787                 debugfs_create_file("fault_status",
 788                                     S_IRUSR | S_IRGRP | S_IROTH,
 789                                     ctrlpriv->ctl, &perfmon->status,
 790                                     &caam_fops_u32_ro);
 791
 792         /* Internal covering keys (useful in non-secure mode only) */
 793         ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0];
 794         ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 795         ctrlpriv->ctl_kek = debugfs_create_blob("kek",
 796                                                 S_IRUSR |
 797                                                 S_IRGRP | S_IROTH,
 798                                                 ctrlpriv->ctl,
 799                                                 &ctrlpriv->ctl_kek_wrap);
 800
 801         ctrlpriv->ctl_tkek_wrap.data = (__force void *)&ctrlpriv->ctrl->tkek[0];
 802         ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 803         ctrlpriv->ctl_tkek = debugfs_create_blob("tkek",
 804                                                  S_IRUSR |
 805                                                  S_IRGRP | S_IROTH,
 806                                                  ctrlpriv->ctl,
 807                                                  &ctrlpriv->ctl_tkek_wrap);
 808
 809         ctrlpriv->ctl_tdsk_wrap.data = (__force void *)&ctrlpriv->ctrl->tdsk[0];
 810         ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 811         ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk",
 812                                                  S_IRUSR |
 813                                                  S_IRGRP | S_IROTH,
 814                                                  ctrlpriv->ctl,
 815                                                  &ctrlpriv->ctl_tdsk_wrap);
 816 #endif
 817         return 0;
 818
 819 caam_remove:
 820         caam_remove(pdev);
 821         return ret;
 822
 823 iounmap_ctrl:
 824         iounmap(ctrl);
 825 disable_caam_emi_slow:
 826         if (ctrlpriv->caam_emi_slow)
 827                 clk_disable_unprepare(ctrlpriv->caam_emi_slow);
 828 disable_caam_aclk:
 829         clk_disable_unprepare(ctrlpriv->caam_aclk);
 830 disable_caam_mem:
 831         clk_disable_unprepare(ctrlpriv->caam_mem);
 832 disable_caam_ipg:
 833         clk_disable_unprepare(ctrlpriv->caam_ipg);
 834         return ret;
 835 }
 836
 837 static struct platform_driver caam_driver = {
 838         .driver = {
 839                 .name = "caam",
 840                 .of_match_table = caam_match,
 841         },
 842         .probe       = caam_probe,
 843         .remove      = caam_remove,
 844 };
 845
 846 module_platform_driver(caam_driver);
 847
 848 MODULE_LICENSE("GPL");
 849 MODULE_DESCRIPTION("FSL CAAM request backend");
 850 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");