drivers/cpufreq/intel_pstate.c

   1 /*
   2  * intel_pstate.c: Native P state management for Intel processors
   3  *
   4  * (C) Copyright 2012 Intel Corporation
   5  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; version 2
  10  * of the License.
  11  */
  12
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/kernel_stat.h>
  17 #include <linux/module.h>
  18 #include <linux/ktime.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/tick.h>
  21 #include <linux/slab.h>
  22 #include <linux/sched/cpufreq.h>
  23 #include <linux/list.h>
  24 #include <linux/cpu.h>
  25 #include <linux/cpufreq.h>
  26 #include <linux/sysfs.h>
  27 #include <linux/types.h>
  28 #include <linux/fs.h>
  29 #include <linux/acpi.h>
  30 #include <linux/vmalloc.h>
  31 #include <trace/events/power.h>
  32
  33 #include <asm/div64.h>
  34 #include <asm/msr.h>
  35 #include <asm/cpu_device_id.h>
  36 #include <asm/cpufeature.h>
  37 #include <asm/intel-family.h>
  38
  39 #define INTEL_PSTATE_SAMPLING_INTERVAL  (10 * NSEC_PER_MSEC)
  40
  41 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
  42 #define INTEL_CPUFREQ_TRANSITION_DELAY          500
  43
  44 #ifdef CONFIG_ACPI
  45 #include <acpi/processor.h>
  46 #include <acpi/cppc_acpi.h>
  47 #endif
  48
  49 #define FRAC_BITS 8
  50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  51 #define fp_toint(X) ((X) >> FRAC_BITS)
  52
  53 #define EXT_BITS 6
  54 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  55 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
  56 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
  57
  58 static inline int32_t mul_fp(int32_t x, int32_t y)
  59 {
  60         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  61 }
  62
  63 static inline int32_t div_fp(s64 x, s64 y)
  64 {
  65         return div64_s64((int64_t)x << FRAC_BITS, y);
  66 }
  67
  68 static inline int ceiling_fp(int32_t x)
  69 {
  70         int mask, ret;
  71
  72         ret = fp_toint(x);
  73         mask = (1 << FRAC_BITS) - 1;
  74         if (x & mask)
  75                 ret += 1;
  76         return ret;
  77 }
  78
  79 static inline int32_t percent_fp(int percent)
  80 {
  81         return div_fp(percent, 100);
  82 }
  83
  84 static inline u64 mul_ext_fp(u64 x, u64 y)
  85 {
  86         return (x * y) >> EXT_FRAC_BITS;
  87 }
  88
  89 static inline u64 div_ext_fp(u64 x, u64 y)
  90 {
  91         return div64_u64(x << EXT_FRAC_BITS, y);
  92 }
  93
  94 static inline int32_t percent_ext_fp(int percent)
  95 {
  96         return div_ext_fp(percent, 100);
  97 }
  98
  99 /**
 100  * struct sample -      Store performance sample
 101  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
 102  *                      performance during last sample period
 103  * @busy_scaled:        Scaled busy value which is used to calculate next
 104  *                      P state. This can be different than core_avg_perf
 105  *                      to account for cpu idle period
 106  * @aperf:              Difference of actual performance frequency clock count
 107  *                      read from APERF MSR between last and current sample
 108  * @mperf:              Difference of maximum performance frequency clock count
 109  *                      read from MPERF MSR between last and current sample
 110  * @tsc:                Difference of time stamp counter between last and
 111  *                      current sample
 112  * @time:               Current time from scheduler
 113  *
 114  * This structure is used in the cpudata structure to store performance sample
 115  * data for choosing next P State.
 116  */
 117 struct sample {
 118         int32_t core_avg_perf;
 119         int32_t busy_scaled;
 120         u64 aperf;
 121         u64 mperf;
 122         u64 tsc;
 123         u64 time;
 124 };
 125
 126 /**
 127  * struct pstate_data - Store P state data
 128  * @current_pstate:     Current requested P state
 129  * @min_pstate:         Min P state possible for this platform
 130  * @max_pstate:         Max P state possible for this platform
 131  * @max_pstate_physical:This is physical Max P state for a processor
 132  *                      This can be higher than the max_pstate which can
 133  *                      be limited by platform thermal design power limits
 134  * @scaling:            Scaling factor to  convert frequency to cpufreq
 135  *                      frequency units
 136  * @turbo_pstate:       Max Turbo P state possible for this platform
 137  * @max_freq:           @max_pstate frequency in cpufreq units
 138  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
 139  *
 140  * Stores the per cpu model P state limits and current P state.
 141  */
 142 struct pstate_data {
 143         int     current_pstate;
 144         int     min_pstate;
 145         int     max_pstate;
 146         int     max_pstate_physical;
 147         int     scaling;
 148         int     turbo_pstate;
 149         unsigned int max_freq;
 150         unsigned int turbo_freq;
 151 };
 152
 153 /**
 154  * struct vid_data -    Stores voltage information data
 155  * @min:                VID data for this platform corresponding to
 156  *                      the lowest P state
 157  * @max:                VID data corresponding to the highest P State.
 158  * @turbo:              VID data for turbo P state
 159  * @ratio:              Ratio of (vid max - vid min) /
 160  *                      (max P state - Min P State)
 161  *
 162  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 163  * This data is used in Atom platforms, where in addition to target P state,
 164  * the voltage data needs to be specified to select next P State.
 165  */
 166 struct vid_data {
 167         int min;
 168         int max;
 169         int turbo;
 170         int32_t ratio;
 171 };
 172
 173 /**
 174  * struct global_params - Global parameters, mostly tunable via sysfs.
 175  * @no_turbo:           Whether or not to use turbo P-states.
 176  * @turbo_disabled:     Whethet or not turbo P-states are available at all,
 177  *                      based on the MSR_IA32_MISC_ENABLE value and whether or
 178  *                      not the maximum reported turbo P-state is different from
 179  *                      the maximum reported non-turbo one.
 180  * @min_perf_pct:       Minimum capacity limit in percent of the maximum turbo
 181  *                      P-state capacity.
 182  * @max_perf_pct:       Maximum capacity limit in percent of the maximum turbo
 183  *                      P-state capacity.
 184  */
 185 struct global_params {
 186         bool no_turbo;
 187         bool turbo_disabled;
 188         int max_perf_pct;
 189         int min_perf_pct;
 190 };
 191
 192 /**
 193  * struct cpudata -     Per CPU instance data storage
 194  * @cpu:                CPU number for this instance data
 195  * @policy:             CPUFreq policy value
 196  * @update_util:        CPUFreq utility callback information
 197  * @update_util_set:    CPUFreq utility callback is set
 198  * @iowait_boost:       iowait-related boost fraction
 199  * @last_update:        Time of the last update.
 200  * @pstate:             Stores P state limits for this CPU
 201  * @vid:                Stores VID limits for this CPU
 202  * @last_sample_time:   Last Sample time
 203  * @aperf_mperf_shift:  Number of clock cycles after aperf, merf is incremented
 204  *                      This shift is a multiplier to mperf delta to
 205  *                      calculate CPU busy.
 206  * @prev_aperf:         Last APERF value read from APERF MSR
 207  * @prev_mperf:         Last MPERF value read from MPERF MSR
 208  * @prev_tsc:           Last timestamp counter (TSC) value
 209  * @prev_cummulative_iowait: IO Wait time difference from last and
 210  *                      current sample
 211  * @sample:             Storage for storing last Sample data
 212  * @min_perf_ratio:     Minimum capacity in terms of PERF or HWP ratios
 213  * @max_perf_ratio:     Maximum capacity in terms of PERF or HWP ratios
 214  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 215  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 216  * @epp_powersave:      Last saved HWP energy performance preference
 217  *                      (EPP) or energy performance bias (EPB),
 218  *                      when policy switched to performance
 219  * @epp_policy:         Last saved policy used to set EPP/EPB
 220  * @epp_default:        Power on default HWP energy performance
 221  *                      preference/bias
 222  * @epp_saved:          Saved EPP/EPB during system suspend or CPU offline
 223  *                      operation
 224  * @hwp_req_cached:     Cached value of the last HWP Request MSR
 225  * @hwp_cap_cached:     Cached value of the last HWP Capabilities MSR
 226  * @last_io_update:     Last time when IO wake flag was set
 227  * @sched_flags:        Store scheduler flags for possible cross CPU update
 228  * @hwp_boost_min:      Last HWP boosted min performance
 229  *
 230  * This structure stores per CPU instance data for all CPUs.
 231  */
 232 struct cpudata {
 233         int cpu;
 234
 235         unsigned int policy;
 236         struct update_util_data update_util;
 237         bool   update_util_set;
 238
 239         struct pstate_data pstate;
 240         struct vid_data vid;
 241
 242         u64     last_update;
 243         u64     last_sample_time;
 244         u64     aperf_mperf_shift;
 245         u64     prev_aperf;
 246         u64     prev_mperf;
 247         u64     prev_tsc;
 248         u64     prev_cummulative_iowait;
 249         struct sample sample;
 250         int32_t min_perf_ratio;
 251         int32_t max_perf_ratio;
 252 #ifdef CONFIG_ACPI
 253         struct acpi_processor_performance acpi_perf_data;
 254         bool valid_pss_table;
 255 #endif
 256         unsigned int iowait_boost;
 257         s16 epp_powersave;
 258         s16 epp_policy;
 259         s16 epp_default;
 260         s16 epp_saved;
 261         u64 hwp_req_cached;
 262         u64 hwp_cap_cached;
 263         u64 last_io_update;
 264         unsigned int sched_flags;
 265         u32 hwp_boost_min;
 266 };
 267
 268 static struct cpudata **all_cpu_data;
 269
 270 /**
 271  * struct pstate_funcs - Per CPU model specific callbacks
 272  * @get_max:            Callback to get maximum non turbo effective P state
 273  * @get_max_physical:   Callback to get maximum non turbo physical P state
 274  * @get_min:            Callback to get minimum P state
 275  * @get_turbo:          Callback to get turbo P state
 276  * @get_scaling:        Callback to get frequency scaling factor
 277  * @get_val:            Callback to convert P state to actual MSR write value
 278  * @get_vid:            Callback to get VID data for Atom platforms
 279  *
 280  * Core and Atom CPU models have different way to get P State limits. This
 281  * structure is used to store those callbacks.
 282  */
 283 struct pstate_funcs {
 284         int (*get_max)(void);
 285         int (*get_max_physical)(void);
 286         int (*get_min)(void);
 287         int (*get_turbo)(void);
 288         int (*get_scaling)(void);
 289         int (*get_aperf_mperf_shift)(void);
 290         u64 (*get_val)(struct cpudata*, int pstate);
 291         void (*get_vid)(struct cpudata *);
 292 };
 293
 294 static struct pstate_funcs pstate_funcs __read_mostly;
 295
 296 static int hwp_active __read_mostly;
 297 static int hwp_mode_bdw __read_mostly;
 298 static bool per_cpu_limits __read_mostly;
 299 static bool hwp_boost __read_mostly;
 300
 301 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
 302
 303 #ifdef CONFIG_ACPI
 304 static bool acpi_ppc;
 305 #endif
 306
 307 static struct global_params global;
 308
 309 static DEFINE_MUTEX(intel_pstate_driver_lock);
 310 static DEFINE_MUTEX(intel_pstate_limits_lock);
 311
 312 #ifdef CONFIG_ACPI
 313
 314 static bool intel_pstate_get_ppc_enable_status(void)
 315 {
 316         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 317             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 318                 return true;
 319
 320         return acpi_ppc;
 321 }
 322
 323 #ifdef CONFIG_ACPI_CPPC_LIB
 324
 325 /* The work item is needed to avoid CPU hotplug locking issues */
 326 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
 327 {
 328         sched_set_itmt_support();
 329 }
 330
 331 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
 332
 333 static void intel_pstate_set_itmt_prio(int cpu)
 334 {
 335         struct cppc_perf_caps cppc_perf;
 336         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
 337         int ret;
 338
 339         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 340         if (ret)
 341                 return;
 342
 343         /*
 344          * The priorities can be set regardless of whether or not
 345          * sched_set_itmt_support(true) has been called and it is valid to
 346          * update them at any time after it has been called.
 347          */
 348         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
 349
 350         if (max_highest_perf <= min_highest_perf) {
 351                 if (cppc_perf.highest_perf > max_highest_perf)
 352                         max_highest_perf = cppc_perf.highest_perf;
 353
 354                 if (cppc_perf.highest_perf < min_highest_perf)
 355                         min_highest_perf = cppc_perf.highest_perf;
 356
 357                 if (max_highest_perf > min_highest_perf) {
 358                         /*
 359                          * This code can be run during CPU online under the
 360                          * CPU hotplug locks, so sched_set_itmt_support()
 361                          * cannot be called from here.  Queue up a work item
 362                          * to invoke it.
 363                          */
 364                         schedule_work(&sched_itmt_work);
 365                 }
 366         }
 367 }
 368 #else
 369 static void intel_pstate_set_itmt_prio(int cpu)
 370 {
 371 }
 372 #endif
 373
 374 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 375 {
 376         struct cpudata *cpu;
 377         int ret;
 378         int i;
 379
 380         if (hwp_active) {
 381                 intel_pstate_set_itmt_prio(policy->cpu);
 382                 return;
 383         }
 384
 385         if (!intel_pstate_get_ppc_enable_status())
 386                 return;
 387
 388         cpu = all_cpu_data[policy->cpu];
 389
 390         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 391                                                   policy->cpu);
 392         if (ret)
 393                 return;
 394
 395         /*
 396          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 397          * guarantee that the states returned by it map to the states in our
 398          * list directly.
 399          */
 400         if (cpu->acpi_perf_data.control_register.space_id !=
 401                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 402                 goto err;
 403
 404         /*
 405          * If there is only one entry _PSS, simply ignore _PSS and continue as
 406          * usual without taking _PSS into account
 407          */
 408         if (cpu->acpi_perf_data.state_count < 2)
 409                 goto err;
 410
 411         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 412         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 413                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 414                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 415                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 416                          (u32) cpu->acpi_perf_data.states[i].power,
 417                          (u32) cpu->acpi_perf_data.states[i].control);
 418         }
 419
 420         /*
 421          * The _PSS table doesn't contain whole turbo frequency range.
 422          * This just contains +1 MHZ above the max non turbo frequency,
 423          * with control value corresponding to max turbo ratio. But
 424          * when cpufreq set policy is called, it will call with this
 425          * max frequency, which will cause a reduced performance as
 426          * this driver uses real max turbo frequency as the max
 427          * frequency. So correct this frequency in _PSS table to
 428          * correct max turbo frequency based on the turbo state.
 429          * Also need to convert to MHz as _PSS freq is in MHz.
 430          */
 431         if (!global.turbo_disabled)
 432                 cpu->acpi_perf_data.states[0].core_frequency =
 433                                         policy->cpuinfo.max_freq / 1000;
 434         cpu->valid_pss_table = true;
 435         pr_debug("_PPC limits will be enforced\n");
 436
 437         return;
 438
 439  err:
 440         cpu->valid_pss_table = false;
 441         acpi_processor_unregister_performance(policy->cpu);
 442 }
 443
 444 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 445 {
 446         struct cpudata *cpu;
 447
 448         cpu = all_cpu_data[policy->cpu];
 449         if (!cpu->valid_pss_table)
 450                 return;
 451
 452         acpi_processor_unregister_performance(policy->cpu);
 453 }
 454 #else
 455 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 456 {
 457 }
 458
 459 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 460 {
 461 }
 462 #endif
 463
 464 static inline void update_turbo_state(void)
 465 {
 466         u64 misc_en;
 467         struct cpudata *cpu;
 468
 469         cpu = all_cpu_data[0];
 470         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 471         global.turbo_disabled =
 472                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 473                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 474 }
 475
 476 static int min_perf_pct_min(void)
 477 {
 478         struct cpudata *cpu = all_cpu_data[0];
 479         int turbo_pstate = cpu->pstate.turbo_pstate;
 480
 481         return turbo_pstate ?
 482                 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
 483 }
 484
 485 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
 486 {
 487         u64 epb;
 488         int ret;
 489
 490         if (!static_cpu_has(X86_FEATURE_EPB))
 491                 return -ENXIO;
 492
 493         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 494         if (ret)
 495                 return (s16)ret;
 496
 497         return (s16)(epb & 0x0f);
 498 }
 499
 500 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
 501 {
 502         s16 epp;
 503
 504         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 505                 /*
 506                  * When hwp_req_data is 0, means that caller didn't read
 507                  * MSR_HWP_REQUEST, so need to read and get EPP.
 508                  */
 509                 if (!hwp_req_data) {
 510                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
 511                                             &hwp_req_data);
 512                         if (epp)
 513                                 return epp;
 514                 }
 515                 epp = (hwp_req_data >> 24) & 0xff;
 516         } else {
 517                 /* When there is no EPP present, HWP uses EPB settings */
 518                 epp = intel_pstate_get_epb(cpu_data);
 519         }
 520
 521         return epp;
 522 }
 523
 524 static int intel_pstate_set_epb(int cpu, s16 pref)
 525 {
 526         u64 epb;
 527         int ret;
 528
 529         if (!static_cpu_has(X86_FEATURE_EPB))
 530                 return -ENXIO;
 531
 532         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 533         if (ret)
 534                 return ret;
 535
 536         epb = (epb & ~0x0f) | pref;
 537         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
 538
 539         return 0;
 540 }
 541
 542 /*
 543  * EPP/EPB display strings corresponding to EPP index in the
 544  * energy_perf_strings[]
 545  *      index           String
 546  *-------------------------------------
 547  *      0               default
 548  *      1               performance
 549  *      2               balance_performance
 550  *      3               balance_power
 551  *      4               power
 552  */
 553 static const char * const energy_perf_strings[] = {
 554         "default",
 555         "performance",
 556         "balance_performance",
 557         "balance_power",
 558         "power",
 559         NULL
 560 };
 561 static const unsigned int epp_values[] = {
 562         HWP_EPP_PERFORMANCE,
 563         HWP_EPP_BALANCE_PERFORMANCE,
 564         HWP_EPP_BALANCE_POWERSAVE,
 565         HWP_EPP_POWERSAVE
 566 };
 567
 568 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
 569 {
 570         s16 epp;
 571         int index = -EINVAL;
 572
 573         epp = intel_pstate_get_epp(cpu_data, 0);
 574         if (epp < 0)
 575                 return epp;
 576
 577         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 578                 if (epp == HWP_EPP_PERFORMANCE)
 579                         return 1;
 580                 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
 581                         return 2;
 582                 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
 583                         return 3;
 584                 else
 585                         return 4;
 586         } else if (static_cpu_has(X86_FEATURE_EPB)) {
 587                 /*
 588                  * Range:
 589                  *      0x00-0x03       :       Performance
 590                  *      0x04-0x07       :       Balance performance
 591                  *      0x08-0x0B       :       Balance power
 592                  *      0x0C-0x0F       :       Power
 593                  * The EPB is a 4 bit value, but our ranges restrict the
 594                  * value which can be set. Here only using top two bits
 595                  * effectively.
 596                  */
 597                 index = (epp >> 2) + 1;
 598         }
 599
 600         return index;
 601 }
 602
 603 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
 604                                               int pref_index)
 605 {
 606         int epp = -EINVAL;
 607         int ret;
 608
 609         if (!pref_index)
 610                 epp = cpu_data->epp_default;
 611
 612         mutex_lock(&intel_pstate_limits_lock);
 613
 614         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 615                 u64 value;
 616
 617                 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
 618                 if (ret)
 619                         goto return_pref;
 620
 621                 value &= ~GENMASK_ULL(31, 24);
 622
 623                 if (epp == -EINVAL)
 624                         epp = epp_values[pref_index - 1];
 625
 626                 value |= (u64)epp << 24;
 627                 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
 628         } else {
 629                 if (epp == -EINVAL)
 630                         epp = (pref_index - 1) << 2;
 631                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
 632         }
 633 return_pref:
 634         mutex_unlock(&intel_pstate_limits_lock);
 635
 636         return ret;
 637 }
 638
 639 static ssize_t show_energy_performance_available_preferences(
 640                                 struct cpufreq_policy *policy, char *buf)
 641 {
 642         int i = 0;
 643         int ret = 0;
 644
 645         while (energy_perf_strings[i] != NULL)
 646                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
 647
 648         ret += sprintf(&buf[ret], "\n");
 649
 650         return ret;
 651 }
 652
 653 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 654
 655 static ssize_t store_energy_performance_preference(
 656                 struct cpufreq_policy *policy, const char *buf, size_t count)
 657 {
 658         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 659         char str_preference[21];
 660         int ret, i = 0;
 661
 662         ret = sscanf(buf, "%20s", str_preference);
 663         if (ret != 1)
 664                 return -EINVAL;
 665
 666         while (energy_perf_strings[i] != NULL) {
 667                 if (!strcmp(str_preference, energy_perf_strings[i])) {
 668                         intel_pstate_set_energy_pref_index(cpu_data, i);
 669                         return count;
 670                 }
 671                 ++i;
 672         }
 673
 674         return -EINVAL;
 675 }
 676
 677 static ssize_t show_energy_performance_preference(
 678                                 struct cpufreq_policy *policy, char *buf)
 679 {
 680         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 681         int preference;
 682
 683         preference = intel_pstate_get_energy_pref_index(cpu_data);
 684         if (preference < 0)
 685                 return preference;
 686
 687         return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
 688 }
 689
 690 cpufreq_freq_attr_rw(energy_performance_preference);
 691
 692 static struct freq_attr *hwp_cpufreq_attrs[] = {
 693         &energy_performance_preference,
 694         &energy_performance_available_preferences,
 695         NULL,
 696 };
 697
 698 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
 699                                      int *current_max)
 700 {
 701         u64 cap;
 702
 703         rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
 704         WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap);
 705         if (global.no_turbo)
 706                 *current_max = HWP_GUARANTEED_PERF(cap);
 707         else
 708                 *current_max = HWP_HIGHEST_PERF(cap);
 709
 710         *phy_max = HWP_HIGHEST_PERF(cap);
 711 }
 712
 713 static void intel_pstate_hwp_set(unsigned int cpu)
 714 {
 715         struct cpudata *cpu_data = all_cpu_data[cpu];
 716         int max, min;
 717         u64 value;
 718         s16 epp;
 719
 720         max = cpu_data->max_perf_ratio;
 721         min = cpu_data->min_perf_ratio;
 722
 723         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
 724                 min = max;
 725
 726         rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 727
 728         value &= ~HWP_MIN_PERF(~0L);
 729         value |= HWP_MIN_PERF(min);
 730
 731         value &= ~HWP_MAX_PERF(~0L);
 732         value |= HWP_MAX_PERF(max);
 733
 734         if (cpu_data->epp_policy == cpu_data->policy)
 735                 goto skip_epp;
 736
 737         cpu_data->epp_policy = cpu_data->policy;
 738
 739         if (cpu_data->epp_saved >= 0) {
 740                 epp = cpu_data->epp_saved;
 741                 cpu_data->epp_saved = -EINVAL;
 742                 goto update_epp;
 743         }
 744
 745         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
 746                 epp = intel_pstate_get_epp(cpu_data, value);
 747                 cpu_data->epp_powersave = epp;
 748                 /* If EPP read was failed, then don't try to write */
 749                 if (epp < 0)
 750                         goto skip_epp;
 751
 752                 epp = 0;
 753         } else {
 754                 /* skip setting EPP, when saved value is invalid */
 755                 if (cpu_data->epp_powersave < 0)
 756                         goto skip_epp;
 757
 758                 /*
 759                  * No need to restore EPP when it is not zero. This
 760                  * means:
 761                  *  - Policy is not changed
 762                  *  - user has manually changed
 763                  *  - Error reading EPB
 764                  */
 765                 epp = intel_pstate_get_epp(cpu_data, value);
 766                 if (epp)
 767                         goto skip_epp;
 768
 769                 epp = cpu_data->epp_powersave;
 770         }
 771 update_epp:
 772         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 773                 value &= ~GENMASK_ULL(31, 24);
 774                 value |= (u64)epp << 24;
 775         } else {
 776                 intel_pstate_set_epb(cpu, epp);
 777         }
 778 skip_epp:
 779         WRITE_ONCE(cpu_data->hwp_req_cached, value);
 780         wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 781 }
 782
 783 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
 784 {
 785         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 786
 787         if (!hwp_active)
 788                 return 0;
 789
 790         cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
 791
 792         return 0;
 793 }
 794
 795 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
 796
 797 static int intel_pstate_resume(struct cpufreq_policy *policy)
 798 {
 799         if (!hwp_active)
 800                 return 0;
 801
 802         mutex_lock(&intel_pstate_limits_lock);
 803
 804         if (policy->cpu == 0)
 805                 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
 806
 807         all_cpu_data[policy->cpu]->epp_policy = 0;
 808         intel_pstate_hwp_set(policy->cpu);
 809
 810         mutex_unlock(&intel_pstate_limits_lock);
 811
 812         return 0;
 813 }
 814
 815 static void intel_pstate_update_policies(void)
 816 {
 817         int cpu;
 818
 819         for_each_possible_cpu(cpu)
 820                 cpufreq_update_policy(cpu);
 821 }
 822
 823 /************************** sysfs begin ************************/
 824 #define show_one(file_name, object)                                     \
 825         static ssize_t show_##file_name                                 \
 826         (struct kobject *kobj, struct attribute *attr, char *buf)       \
 827         {                                                               \
 828                 return sprintf(buf, "%u\n", global.object);             \
 829         }
 830
 831 static ssize_t intel_pstate_show_status(char *buf);
 832 static int intel_pstate_update_status(const char *buf, size_t size);
 833
 834 static ssize_t show_status(struct kobject *kobj,
 835                            struct attribute *attr, char *buf)
 836 {
 837         ssize_t ret;
 838
 839         mutex_lock(&intel_pstate_driver_lock);
 840         ret = intel_pstate_show_status(buf);
 841         mutex_unlock(&intel_pstate_driver_lock);
 842
 843         return ret;
 844 }
 845
 846 static ssize_t store_status(struct kobject *a, struct attribute *b,
 847                             const char *buf, size_t count)
 848 {
 849         char *p = memchr(buf, '\n', count);
 850         int ret;
 851
 852         mutex_lock(&intel_pstate_driver_lock);
 853         ret = intel_pstate_update_status(buf, p ? p - buf : count);
 854         mutex_unlock(&intel_pstate_driver_lock);
 855
 856         return ret < 0 ? ret : count;
 857 }
 858
 859 static ssize_t show_turbo_pct(struct kobject *kobj,
 860                                 struct attribute *attr, char *buf)
 861 {
 862         struct cpudata *cpu;
 863         int total, no_turbo, turbo_pct;
 864         uint32_t turbo_fp;
 865
 866         mutex_lock(&intel_pstate_driver_lock);
 867
 868         if (!intel_pstate_driver) {
 869                 mutex_unlock(&intel_pstate_driver_lock);
 870                 return -EAGAIN;
 871         }
 872
 873         cpu = all_cpu_data[0];
 874
 875         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
 876         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
 877         turbo_fp = div_fp(no_turbo, total);
 878         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
 879
 880         mutex_unlock(&intel_pstate_driver_lock);
 881
 882         return sprintf(buf, "%u\n", turbo_pct);
 883 }
 884
 885 static ssize_t show_num_pstates(struct kobject *kobj,
 886                                 struct attribute *attr, char *buf)
 887 {
 888         struct cpudata *cpu;
 889         int total;
 890
 891         mutex_lock(&intel_pstate_driver_lock);
 892
 893         if (!intel_pstate_driver) {
 894                 mutex_unlock(&intel_pstate_driver_lock);
 895                 return -EAGAIN;
 896         }
 897
 898         cpu = all_cpu_data[0];
 899         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
 900
 901         mutex_unlock(&intel_pstate_driver_lock);
 902
 903         return sprintf(buf, "%u\n", total);
 904 }
 905
 906 static ssize_t show_no_turbo(struct kobject *kobj,
 907                              struct attribute *attr, char *buf)
 908 {
 909         ssize_t ret;
 910
 911         mutex_lock(&intel_pstate_driver_lock);
 912
 913         if (!intel_pstate_driver) {
 914                 mutex_unlock(&intel_pstate_driver_lock);
 915                 return -EAGAIN;
 916         }
 917
 918         update_turbo_state();
 919         if (global.turbo_disabled)
 920                 ret = sprintf(buf, "%u\n", global.turbo_disabled);
 921         else
 922                 ret = sprintf(buf, "%u\n", global.no_turbo);
 923
 924         mutex_unlock(&intel_pstate_driver_lock);
 925
 926         return ret;
 927 }
 928
 929 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
 930                               const char *buf, size_t count)
 931 {
 932         unsigned int input;
 933         int ret;
 934
 935         ret = sscanf(buf, "%u", &input);
 936         if (ret != 1)
 937                 return -EINVAL;
 938
 939         mutex_lock(&intel_pstate_driver_lock);
 940
 941         if (!intel_pstate_driver) {
 942                 mutex_unlock(&intel_pstate_driver_lock);
 943                 return -EAGAIN;
 944         }
 945
 946         mutex_lock(&intel_pstate_limits_lock);
 947
 948         update_turbo_state();
 949         if (global.turbo_disabled) {
 950                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
 951                 mutex_unlock(&intel_pstate_limits_lock);
 952                 mutex_unlock(&intel_pstate_driver_lock);
 953                 return -EPERM;
 954         }
 955
 956         global.no_turbo = clamp_t(int, input, 0, 1);
 957
 958         if (global.no_turbo) {
 959                 struct cpudata *cpu = all_cpu_data[0];
 960                 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
 961
 962                 /* Squash the global minimum into the permitted range. */
 963                 if (global.min_perf_pct > pct)
 964                         global.min_perf_pct = pct;
 965         }
 966
 967         mutex_unlock(&intel_pstate_limits_lock);
 968
 969         intel_pstate_update_policies();
 970
 971         mutex_unlock(&intel_pstate_driver_lock);
 972
 973         return count;
 974 }
 975
 976 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
 977                                   const char *buf, size_t count)
 978 {
 979         unsigned int input;
 980         int ret;
 981
 982         ret = sscanf(buf, "%u", &input);
 983         if (ret != 1)
 984                 return -EINVAL;
 985
 986         mutex_lock(&intel_pstate_driver_lock);
 987
 988         if (!intel_pstate_driver) {
 989                 mutex_unlock(&intel_pstate_driver_lock);
 990                 return -EAGAIN;
 991         }
 992
 993         mutex_lock(&intel_pstate_limits_lock);
 994
 995         global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
 996
 997         mutex_unlock(&intel_pstate_limits_lock);
 998
 999         intel_pstate_update_policies();
1000
1001         mutex_unlock(&intel_pstate_driver_lock);
1002
1003         return count;
1004 }
1005
1006 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1007                                   const char *buf, size_t count)
1008 {
1009         unsigned int input;
1010         int ret;
1011
1012         ret = sscanf(buf, "%u", &input);
1013         if (ret != 1)
1014                 return -EINVAL;
1015
1016         mutex_lock(&intel_pstate_driver_lock);
1017
1018         if (!intel_pstate_driver) {
1019                 mutex_unlock(&intel_pstate_driver_lock);
1020                 return -EAGAIN;
1021         }
1022
1023         mutex_lock(&intel_pstate_limits_lock);
1024
1025         global.min_perf_pct = clamp_t(int, input,
1026                                       min_perf_pct_min(), global.max_perf_pct);
1027
1028         mutex_unlock(&intel_pstate_limits_lock);
1029
1030         intel_pstate_update_policies();
1031
1032         mutex_unlock(&intel_pstate_driver_lock);
1033
1034         return count;
1035 }
1036
1037 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1038                                 struct attribute *attr, char *buf)
1039 {
1040         return sprintf(buf, "%u\n", hwp_boost);
1041 }
1042
1043 static ssize_t store_hwp_dynamic_boost(struct kobject *a, struct attribute *b,
1044                                        const char *buf, size_t count)
1045 {
1046         unsigned int input;
1047         int ret;
1048
1049         ret = kstrtouint(buf, 10, &input);
1050         if (ret)
1051                 return ret;
1052
1053         mutex_lock(&intel_pstate_driver_lock);
1054         hwp_boost = !!input;
1055         intel_pstate_update_policies();
1056         mutex_unlock(&intel_pstate_driver_lock);
1057
1058         return count;
1059 }
1060
1061 show_one(max_perf_pct, max_perf_pct);
1062 show_one(min_perf_pct, min_perf_pct);
1063
1064 define_one_global_rw(status);
1065 define_one_global_rw(no_turbo);
1066 define_one_global_rw(max_perf_pct);
1067 define_one_global_rw(min_perf_pct);
1068 define_one_global_ro(turbo_pct);
1069 define_one_global_ro(num_pstates);
1070 define_one_global_rw(hwp_dynamic_boost);
1071
1072 static struct attribute *intel_pstate_attributes[] = {
1073         &status.attr,
1074         &no_turbo.attr,
1075         &turbo_pct.attr,
1076         &num_pstates.attr,
1077         NULL
1078 };
1079
1080 static const struct attribute_group intel_pstate_attr_group = {
1081         .attrs = intel_pstate_attributes,
1082 };
1083
1084 static void __init intel_pstate_sysfs_expose_params(void)
1085 {
1086         struct kobject *intel_pstate_kobject;
1087         int rc;
1088
1089         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1090                                                 &cpu_subsys.dev_root->kobj);
1091         if (WARN_ON(!intel_pstate_kobject))
1092                 return;
1093
1094         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1095         if (WARN_ON(rc))
1096                 return;
1097
1098         /*
1099          * If per cpu limits are enforced there are no global limits, so
1100          * return without creating max/min_perf_pct attributes
1101          */
1102         if (per_cpu_limits)
1103                 return;
1104
1105         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1106         WARN_ON(rc);
1107
1108         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1109         WARN_ON(rc);
1110
1111         if (hwp_active) {
1112                 rc = sysfs_create_file(intel_pstate_kobject,
1113                                        &hwp_dynamic_boost.attr);
1114                 WARN_ON(rc);
1115         }
1116 }
1117 /************************** sysfs end ************************/
1118
1119 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1120 {
1121         /* First disable HWP notification interrupt as we don't process them */
1122         if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1123                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1124
1125         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1126         cpudata->epp_policy = 0;
1127         if (cpudata->epp_default == -EINVAL)
1128                 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1129 }
1130
1131 #define MSR_IA32_POWER_CTL_BIT_EE       19
1132
1133 /* Disable energy efficiency optimization */
1134 static void intel_pstate_disable_ee(int cpu)
1135 {
1136         u64 power_ctl;
1137         int ret;
1138
1139         ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1140         if (ret)
1141                 return;
1142
1143         if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1144                 pr_info("Disabling energy efficiency optimization\n");
1145                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1146                 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1147         }
1148 }
1149
1150 static int atom_get_min_pstate(void)
1151 {
1152         u64 value;
1153
1154         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1155         return (value >> 8) & 0x7F;
1156 }
1157
1158 static int atom_get_max_pstate(void)
1159 {
1160         u64 value;
1161
1162         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1163         return (value >> 16) & 0x7F;
1164 }
1165
1166 static int atom_get_turbo_pstate(void)
1167 {
1168         u64 value;
1169
1170         rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1171         return value & 0x7F;
1172 }
1173
1174 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1175 {
1176         u64 val;
1177         int32_t vid_fp;
1178         u32 vid;
1179
1180         val = (u64)pstate << 8;
1181         if (global.no_turbo && !global.turbo_disabled)
1182                 val |= (u64)1 << 32;
1183
1184         vid_fp = cpudata->vid.min + mul_fp(
1185                 int_tofp(pstate - cpudata->pstate.min_pstate),
1186                 cpudata->vid.ratio);
1187
1188         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1189         vid = ceiling_fp(vid_fp);
1190
1191         if (pstate > cpudata->pstate.max_pstate)
1192                 vid = cpudata->vid.turbo;
1193
1194         return val | vid;
1195 }
1196
1197 static int silvermont_get_scaling(void)
1198 {
1199         u64 value;
1200         int i;
1201         /* Defined in Table 35-6 from SDM (Sept 2015) */
1202         static int silvermont_freq_table[] = {
1203                 83300, 100000, 133300, 116700, 80000};
1204
1205         rdmsrl(MSR_FSB_FREQ, value);
1206         i = value & 0x7;
1207         WARN_ON(i > 4);
1208
1209         return silvermont_freq_table[i];
1210 }
1211
1212 static int airmont_get_scaling(void)
1213 {
1214         u64 value;
1215         int i;
1216         /* Defined in Table 35-10 from SDM (Sept 2015) */
1217         static int airmont_freq_table[] = {
1218                 83300, 100000, 133300, 116700, 80000,
1219                 93300, 90000, 88900, 87500};
1220
1221         rdmsrl(MSR_FSB_FREQ, value);
1222         i = value & 0xF;
1223         WARN_ON(i > 8);
1224
1225         return airmont_freq_table[i];
1226 }
1227
1228 static void atom_get_vid(struct cpudata *cpudata)
1229 {
1230         u64 value;
1231
1232         rdmsrl(MSR_ATOM_CORE_VIDS, value);
1233         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1234         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1235         cpudata->vid.ratio = div_fp(
1236                 cpudata->vid.max - cpudata->vid.min,
1237                 int_tofp(cpudata->pstate.max_pstate -
1238                         cpudata->pstate.min_pstate));
1239
1240         rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1241         cpudata->vid.turbo = value & 0x7f;
1242 }
1243
1244 static int core_get_min_pstate(void)
1245 {
1246         u64 value;
1247
1248         rdmsrl(MSR_PLATFORM_INFO, value);
1249         return (value >> 40) & 0xFF;
1250 }
1251
1252 static int core_get_max_pstate_physical(void)
1253 {
1254         u64 value;
1255
1256         rdmsrl(MSR_PLATFORM_INFO, value);
1257         return (value >> 8) & 0xFF;
1258 }
1259
1260 static int core_get_tdp_ratio(u64 plat_info)
1261 {
1262         /* Check how many TDP levels present */
1263         if (plat_info & 0x600000000) {
1264                 u64 tdp_ctrl;
1265                 u64 tdp_ratio;
1266                 int tdp_msr;
1267                 int err;
1268
1269                 /* Get the TDP level (0, 1, 2) to get ratios */
1270                 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1271                 if (err)
1272                         return err;
1273
1274                 /* TDP MSR are continuous starting at 0x648 */
1275                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1276                 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1277                 if (err)
1278                         return err;
1279
1280                 /* For level 1 and 2, bits[23:16] contain the ratio */
1281                 if (tdp_ctrl & 0x03)
1282                         tdp_ratio >>= 16;
1283
1284                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1285                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1286
1287                 return (int)tdp_ratio;
1288         }
1289
1290         return -ENXIO;
1291 }
1292
1293 static int core_get_max_pstate(void)
1294 {
1295         u64 tar;
1296         u64 plat_info;
1297         int max_pstate;
1298         int tdp_ratio;
1299         int err;
1300
1301         rdmsrl(MSR_PLATFORM_INFO, plat_info);
1302         max_pstate = (plat_info >> 8) & 0xFF;
1303
1304         tdp_ratio = core_get_tdp_ratio(plat_info);
1305         if (tdp_ratio <= 0)
1306                 return max_pstate;
1307
1308         if (hwp_active) {
1309                 /* Turbo activation ratio is not used on HWP platforms */
1310                 return tdp_ratio;
1311         }
1312
1313         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1314         if (!err) {
1315                 int tar_levels;
1316
1317                 /* Do some sanity checking for safety */
1318                 tar_levels = tar & 0xff;
1319                 if (tdp_ratio - 1 == tar_levels) {
1320                         max_pstate = tar_levels;
1321                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1322                 }
1323         }
1324
1325         return max_pstate;
1326 }
1327
1328 static int core_get_turbo_pstate(void)
1329 {
1330         u64 value;
1331         int nont, ret;
1332
1333         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1334         nont = core_get_max_pstate();
1335         ret = (value) & 255;
1336         if (ret <= nont)
1337                 ret = nont;
1338         return ret;
1339 }
1340
1341 static inline int core_get_scaling(void)
1342 {
1343         return 100000;
1344 }
1345
1346 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1347 {
1348         u64 val;
1349
1350         val = (u64)pstate << 8;
1351         if (global.no_turbo && !global.turbo_disabled)
1352                 val |= (u64)1 << 32;
1353
1354         return val;
1355 }
1356
1357 static int knl_get_aperf_mperf_shift(void)
1358 {
1359         return 10;
1360 }
1361
1362 static int knl_get_turbo_pstate(void)
1363 {
1364         u64 value;
1365         int nont, ret;
1366
1367         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1368         nont = core_get_max_pstate();
1369         ret = (((value) >> 8) & 0xFF);
1370         if (ret <= nont)
1371                 ret = nont;
1372         return ret;
1373 }
1374
1375 static int intel_pstate_get_base_pstate(struct cpudata *cpu)
1376 {
1377         return global.no_turbo || global.turbo_disabled ?
1378                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1379 }
1380
1381 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1382 {
1383         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1384         cpu->pstate.current_pstate = pstate;
1385         /*
1386          * Generally, there is no guarantee that this code will always run on
1387          * the CPU being updated, so force the register update to run on the
1388          * right CPU.
1389          */
1390         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1391                       pstate_funcs.get_val(cpu, pstate));
1392 }
1393
1394 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1395 {
1396         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1397 }
1398
1399 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1400 {
1401         int pstate;
1402
1403         update_turbo_state();
1404         pstate = intel_pstate_get_base_pstate(cpu);
1405         pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1406         intel_pstate_set_pstate(cpu, pstate);
1407 }
1408
1409 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1410 {
1411         cpu->pstate.min_pstate = pstate_funcs.get_min();
1412         cpu->pstate.max_pstate = pstate_funcs.get_max();
1413         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1414         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1415         cpu->pstate.scaling = pstate_funcs.get_scaling();
1416         cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1417
1418         if (hwp_active && !hwp_mode_bdw) {
1419                 unsigned int phy_max, current_max;
1420
1421                 intel_pstate_get_hwp_max(cpu->cpu, &phy_max, &current_max);
1422                 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling;
1423         } else {
1424                 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1425         }
1426
1427         if (pstate_funcs.get_aperf_mperf_shift)
1428                 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1429
1430         if (pstate_funcs.get_vid)
1431                 pstate_funcs.get_vid(cpu);
1432
1433         intel_pstate_set_min_pstate(cpu);
1434 }
1435
1436 /*
1437  * Long hold time will keep high perf limits for long time,
1438  * which negatively impacts perf/watt for some workloads,
1439  * like specpower. 3ms is based on experiements on some
1440  * workoads.
1441  */
1442 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
1443
1444 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
1445 {
1446         u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
1447         u32 max_limit = (hwp_req & 0xff00) >> 8;
1448         u32 min_limit = (hwp_req & 0xff);
1449         u32 boost_level1;
1450
1451         /*
1452          * Cases to consider (User changes via sysfs or boot time):
1453          * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
1454          *      No boost, return.
1455          * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
1456          *     Should result in one level boost only for P0.
1457          * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
1458          *     Should result in two level boost:
1459          *         (min + p1)/2 and P1.
1460          * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
1461          *     Should result in three level boost:
1462          *        (min + p1)/2, P1 and P0.
1463          */
1464
1465         /* If max and min are equal or already at max, nothing to boost */
1466         if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
1467                 return;
1468
1469         if (!cpu->hwp_boost_min)
1470                 cpu->hwp_boost_min = min_limit;
1471
1472         /* level at half way mark between min and guranteed */
1473         boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1;
1474
1475         if (cpu->hwp_boost_min < boost_level1)
1476                 cpu->hwp_boost_min = boost_level1;
1477         else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1478                 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached);
1479         else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) &&
1480                  max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1481                 cpu->hwp_boost_min = max_limit;
1482         else
1483                 return;
1484
1485         hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
1486         wrmsrl(MSR_HWP_REQUEST, hwp_req);
1487         cpu->last_update = cpu->sample.time;
1488 }
1489
1490 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
1491 {
1492         if (cpu->hwp_boost_min) {
1493                 bool expired;
1494
1495                 /* Check if we are idle for hold time to boost down */
1496                 expired = time_after64(cpu->sample.time, cpu->last_update +
1497                                        hwp_boost_hold_time_ns);
1498                 if (expired) {
1499                         wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
1500                         cpu->hwp_boost_min = 0;
1501                 }
1502         }
1503         cpu->last_update = cpu->sample.time;
1504 }
1505
1506 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
1507                                                       u64 time)
1508 {
1509         cpu->sample.time = time;
1510
1511         if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
1512                 bool do_io = false;
1513
1514                 cpu->sched_flags = 0;
1515                 /*
1516                  * Set iowait_boost flag and update time. Since IO WAIT flag
1517                  * is set all the time, we can't just conclude that there is
1518                  * some IO bound activity is scheduled on this CPU with just
1519                  * one occurrence. If we receive at least two in two
1520                  * consecutive ticks, then we treat as boost candidate.
1521                  */
1522                 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
1523                         do_io = true;
1524
1525                 cpu->last_io_update = time;
1526
1527                 if (do_io)
1528                         intel_pstate_hwp_boost_up(cpu);
1529
1530         } else {
1531                 intel_pstate_hwp_boost_down(cpu);
1532         }
1533 }
1534
1535 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
1536                                                 u64 time, unsigned int flags)
1537 {
1538         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1539
1540         cpu->sched_flags |= flags;
1541
1542         if (smp_processor_id() == cpu->cpu)
1543                 intel_pstate_update_util_hwp_local(cpu, time);
1544 }
1545
1546 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1547 {
1548         struct sample *sample = &cpu->sample;
1549
1550         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1551 }
1552
1553 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1554 {
1555         u64 aperf, mperf;
1556         unsigned long flags;
1557         u64 tsc;
1558
1559         local_irq_save(flags);
1560         rdmsrl(MSR_IA32_APERF, aperf);
1561         rdmsrl(MSR_IA32_MPERF, mperf);
1562         tsc = rdtsc();
1563         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1564                 local_irq_restore(flags);
1565                 return false;
1566         }
1567         local_irq_restore(flags);
1568
1569         cpu->last_sample_time = cpu->sample.time;
1570         cpu->sample.time = time;
1571         cpu->sample.aperf = aperf;
1572         cpu->sample.mperf = mperf;
1573         cpu->sample.tsc =  tsc;
1574         cpu->sample.aperf -= cpu->prev_aperf;
1575         cpu->sample.mperf -= cpu->prev_mperf;
1576         cpu->sample.tsc -= cpu->prev_tsc;
1577
1578         cpu->prev_aperf = aperf;
1579         cpu->prev_mperf = mperf;
1580         cpu->prev_tsc = tsc;
1581         /*
1582          * First time this function is invoked in a given cycle, all of the
1583          * previous sample data fields are equal to zero or stale and they must
1584          * be populated with meaningful numbers for things to work, so assume
1585          * that sample.time will always be reset before setting the utilization
1586          * update hook and make the caller skip the sample then.
1587          */
1588         if (cpu->last_sample_time) {
1589                 intel_pstate_calc_avg_perf(cpu);
1590                 return true;
1591         }
1592         return false;
1593 }
1594
1595 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1596 {
1597         return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1598 }
1599
1600 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1601 {
1602         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1603                           cpu->sample.core_avg_perf);
1604 }
1605
1606 static inline int32_t get_target_pstate(struct cpudata *cpu)
1607 {
1608         struct sample *sample = &cpu->sample;
1609         int32_t busy_frac, boost;
1610         int target, avg_pstate;
1611
1612         busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1613                            sample->tsc);
1614
1615         boost = cpu->iowait_boost;
1616         cpu->iowait_boost >>= 1;
1617
1618         if (busy_frac < boost)
1619                 busy_frac = boost;
1620
1621         sample->busy_scaled = busy_frac * 100;
1622
1623         target = global.no_turbo || global.turbo_disabled ?
1624                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1625         target += target >> 2;
1626         target = mul_fp(target, busy_frac);
1627         if (target < cpu->pstate.min_pstate)
1628                 target = cpu->pstate.min_pstate;
1629
1630         /*
1631          * If the average P-state during the previous cycle was higher than the
1632          * current target, add 50% of the difference to the target to reduce
1633          * possible performance oscillations and offset possible performance
1634          * loss related to moving the workload from one CPU to another within
1635          * a package/module.
1636          */
1637         avg_pstate = get_avg_pstate(cpu);
1638         if (avg_pstate > target)
1639                 target += (avg_pstate - target) >> 1;
1640
1641         return target;
1642 }
1643
1644 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1645 {
1646         int max_pstate = intel_pstate_get_base_pstate(cpu);
1647         int min_pstate;
1648
1649         min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1650         max_pstate = max(min_pstate, cpu->max_perf_ratio);
1651         return clamp_t(int, pstate, min_pstate, max_pstate);
1652 }
1653
1654 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1655 {
1656         if (pstate == cpu->pstate.current_pstate)
1657                 return;
1658
1659         cpu->pstate.current_pstate = pstate;
1660         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1661 }
1662
1663 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
1664 {
1665         int from = cpu->pstate.current_pstate;
1666         struct sample *sample;
1667         int target_pstate;
1668
1669         update_turbo_state();
1670
1671         target_pstate = get_target_pstate(cpu);
1672         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1673         trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1674         intel_pstate_update_pstate(cpu, target_pstate);
1675
1676         sample = &cpu->sample;
1677         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1678                 fp_toint(sample->busy_scaled),
1679                 from,
1680                 cpu->pstate.current_pstate,
1681                 sample->mperf,
1682                 sample->aperf,
1683                 sample->tsc,
1684                 get_avg_frequency(cpu),
1685                 fp_toint(cpu->iowait_boost * 100));
1686 }
1687
1688 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1689                                      unsigned int flags)
1690 {
1691         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1692         u64 delta_ns;
1693
1694         /* Don't allow remote callbacks */
1695         if (smp_processor_id() != cpu->cpu)
1696                 return;
1697
1698         if (flags & SCHED_CPUFREQ_IOWAIT) {
1699                 cpu->iowait_boost = int_tofp(1);
1700                 cpu->last_update = time;
1701                 /*
1702                  * The last time the busy was 100% so P-state was max anyway
1703                  * so avoid overhead of computation.
1704                  */
1705                 if (fp_toint(cpu->sample.busy_scaled) == 100)
1706                         return;
1707
1708                 goto set_pstate;
1709         } else if (cpu->iowait_boost) {
1710                 /* Clear iowait_boost if the CPU may have been idle. */
1711                 delta_ns = time - cpu->last_update;
1712                 if (delta_ns > TICK_NSEC)
1713                         cpu->iowait_boost = 0;
1714         }
1715         cpu->last_update = time;
1716         delta_ns = time - cpu->sample.time;
1717         if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
1718                 return;
1719
1720 set_pstate:
1721         if (intel_pstate_sample(cpu, time))
1722                 intel_pstate_adjust_pstate(cpu);
1723 }
1724
1725 static struct pstate_funcs core_funcs = {
1726         .get_max = core_get_max_pstate,
1727         .get_max_physical = core_get_max_pstate_physical,
1728         .get_min = core_get_min_pstate,
1729         .get_turbo = core_get_turbo_pstate,
1730         .get_scaling = core_get_scaling,
1731         .get_val = core_get_val,
1732 };
1733
1734 static const struct pstate_funcs silvermont_funcs = {
1735         .get_max = atom_get_max_pstate,
1736         .get_max_physical = atom_get_max_pstate,
1737         .get_min = atom_get_min_pstate,
1738         .get_turbo = atom_get_turbo_pstate,
1739         .get_val = atom_get_val,
1740         .get_scaling = silvermont_get_scaling,
1741         .get_vid = atom_get_vid,
1742 };
1743
1744 static const struct pstate_funcs airmont_funcs = {
1745         .get_max = atom_get_max_pstate,
1746         .get_max_physical = atom_get_max_pstate,
1747         .get_min = atom_get_min_pstate,
1748         .get_turbo = atom_get_turbo_pstate,
1749         .get_val = atom_get_val,
1750         .get_scaling = airmont_get_scaling,
1751         .get_vid = atom_get_vid,
1752 };
1753
1754 static const struct pstate_funcs knl_funcs = {
1755         .get_max = core_get_max_pstate,
1756         .get_max_physical = core_get_max_pstate_physical,
1757         .get_min = core_get_min_pstate,
1758         .get_turbo = knl_get_turbo_pstate,
1759         .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
1760         .get_scaling = core_get_scaling,
1761         .get_val = core_get_val,
1762 };
1763
1764 #define ICPU(model, policy) \
1765         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1766                         (unsigned long)&policy }
1767
1768 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1769         ICPU(INTEL_FAM6_SANDYBRIDGE,            core_funcs),
1770         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_funcs),
1771         ICPU(INTEL_FAM6_ATOM_SILVERMONT1,       silvermont_funcs),
1772         ICPU(INTEL_FAM6_IVYBRIDGE,              core_funcs),
1773         ICPU(INTEL_FAM6_HASWELL_CORE,           core_funcs),
1774         ICPU(INTEL_FAM6_BROADWELL_CORE,         core_funcs),
1775         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_funcs),
1776         ICPU(INTEL_FAM6_HASWELL_X,              core_funcs),
1777         ICPU(INTEL_FAM6_HASWELL_ULT,            core_funcs),
1778         ICPU(INTEL_FAM6_HASWELL_GT3E,           core_funcs),
1779         ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_funcs),
1780         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_funcs),
1781         ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         core_funcs),
1782         ICPU(INTEL_FAM6_BROADWELL_X,            core_funcs),
1783         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        core_funcs),
1784         ICPU(INTEL_FAM6_BROADWELL_XEON_D,       core_funcs),
1785         ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_funcs),
1786         ICPU(INTEL_FAM6_XEON_PHI_KNM,           knl_funcs),
1787         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          core_funcs),
1788         ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE,       core_funcs),
1789         ICPU(INTEL_FAM6_SKYLAKE_X,              core_funcs),
1790         {}
1791 };
1792 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1793
1794 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1795         ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1796         ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1797         ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1798         {}
1799 };
1800
1801 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1802         ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1803         {}
1804 };
1805
1806 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
1807         ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1808         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1809         {}
1810 };
1811
1812 static int intel_pstate_init_cpu(unsigned int cpunum)
1813 {
1814         struct cpudata *cpu;
1815
1816         cpu = all_cpu_data[cpunum];
1817
1818         if (!cpu) {
1819                 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1820                 if (!cpu)
1821                         return -ENOMEM;
1822
1823                 all_cpu_data[cpunum] = cpu;
1824
1825                 cpu->epp_default = -EINVAL;
1826                 cpu->epp_powersave = -EINVAL;
1827                 cpu->epp_saved = -EINVAL;
1828         }
1829
1830         cpu = all_cpu_data[cpunum];
1831
1832         cpu->cpu = cpunum;
1833
1834         if (hwp_active) {
1835                 const struct x86_cpu_id *id;
1836
1837                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1838                 if (id)
1839                         intel_pstate_disable_ee(cpunum);
1840
1841                 intel_pstate_hwp_enable(cpu);
1842
1843                 id = x86_match_cpu(intel_pstate_hwp_boost_ids);
1844                 if (id)
1845                         hwp_boost = true;
1846         }
1847
1848         intel_pstate_get_cpu_pstates(cpu);
1849
1850         pr_debug("controlling: cpu %d\n", cpunum);
1851
1852         return 0;
1853 }
1854
1855 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1856 {
1857         struct cpudata *cpu = all_cpu_data[cpu_num];
1858
1859         if (hwp_active && !hwp_boost)
1860                 return;
1861
1862         if (cpu->update_util_set)
1863                 return;
1864
1865         /* Prevent intel_pstate_update_util() from using stale data. */
1866         cpu->sample.time = 0;
1867         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1868                                      (hwp_active ?
1869                                       intel_pstate_update_util_hwp :
1870                                       intel_pstate_update_util));
1871         cpu->update_util_set = true;
1872 }
1873
1874 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1875 {
1876         struct cpudata *cpu_data = all_cpu_data[cpu];
1877
1878         if (!cpu_data->update_util_set)
1879                 return;
1880
1881         cpufreq_remove_update_util_hook(cpu);
1882         cpu_data->update_util_set = false;
1883         synchronize_sched();
1884 }
1885
1886 static int intel_pstate_get_max_freq(struct cpudata *cpu)
1887 {
1888         return global.turbo_disabled || global.no_turbo ?
1889                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1890 }
1891
1892 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1893                                             struct cpudata *cpu)
1894 {
1895         int max_freq = intel_pstate_get_max_freq(cpu);
1896         int32_t max_policy_perf, min_policy_perf;
1897         int max_state, turbo_max;
1898
1899         /*
1900          * HWP needs some special consideration, because on BDX the
1901          * HWP_REQUEST uses abstract value to represent performance
1902          * rather than pure ratios.
1903          */
1904         if (hwp_active) {
1905                 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
1906         } else {
1907                 max_state = intel_pstate_get_base_pstate(cpu);
1908                 turbo_max = cpu->pstate.turbo_pstate;
1909         }
1910
1911         max_policy_perf = max_state * policy->max / max_freq;
1912         if (policy->max == policy->min) {
1913                 min_policy_perf = max_policy_perf;
1914         } else {
1915                 min_policy_perf = max_state * policy->min / max_freq;
1916                 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1917                                           0, max_policy_perf);
1918         }
1919
1920         pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
1921                  policy->cpu, max_state,
1922                  min_policy_perf, max_policy_perf);
1923
1924         /* Normalize user input to [min_perf, max_perf] */
1925         if (per_cpu_limits) {
1926                 cpu->min_perf_ratio = min_policy_perf;
1927                 cpu->max_perf_ratio = max_policy_perf;
1928         } else {
1929                 int32_t global_min, global_max;
1930
1931                 /* Global limits are in percent of the maximum turbo P-state. */
1932                 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
1933                 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
1934                 global_min = clamp_t(int32_t, global_min, 0, global_max);
1935
1936                 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
1937                          global_min, global_max);
1938
1939                 cpu->min_perf_ratio = max(min_policy_perf, global_min);
1940                 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
1941                 cpu->max_perf_ratio = min(max_policy_perf, global_max);
1942                 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
1943
1944                 /* Make sure min_perf <= max_perf */
1945                 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
1946                                           cpu->max_perf_ratio);
1947
1948         }
1949         pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
1950                  cpu->max_perf_ratio,
1951                  cpu->min_perf_ratio);
1952 }
1953
1954 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1955 {
1956         struct cpudata *cpu;
1957
1958         if (!policy->cpuinfo.max_freq)
1959                 return -ENODEV;
1960
1961         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1962                  policy->cpuinfo.max_freq, policy->max);
1963
1964         cpu = all_cpu_data[policy->cpu];
1965         cpu->policy = policy->policy;
1966
1967         mutex_lock(&intel_pstate_limits_lock);
1968
1969         intel_pstate_update_perf_limits(policy, cpu);
1970
1971         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
1972                 /*
1973                  * NOHZ_FULL CPUs need this as the governor callback may not
1974                  * be invoked on them.
1975                  */
1976                 intel_pstate_clear_update_util_hook(policy->cpu);
1977                 intel_pstate_max_within_limits(cpu);
1978         } else {
1979                 intel_pstate_set_update_util_hook(policy->cpu);
1980         }
1981
1982         if (hwp_active) {
1983                 /*
1984                  * When hwp_boost was active before and dynamically it
1985                  * was turned off, in that case we need to clear the
1986                  * update util hook.
1987                  */
1988                 if (!hwp_boost)
1989                         intel_pstate_clear_update_util_hook(policy->cpu);
1990                 intel_pstate_hwp_set(policy->cpu);
1991         }
1992
1993         mutex_unlock(&intel_pstate_limits_lock);
1994
1995         return 0;
1996 }
1997
1998 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
1999                                          struct cpudata *cpu)
2000 {
2001         if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2002             policy->max < policy->cpuinfo.max_freq &&
2003             policy->max > cpu->pstate.max_freq) {
2004                 pr_debug("policy->max > max non turbo frequency\n");
2005                 policy->max = policy->cpuinfo.max_freq;
2006         }
2007 }
2008
2009 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2010 {
2011         struct cpudata *cpu = all_cpu_data[policy->cpu];
2012
2013         update_turbo_state();
2014         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2015                                      intel_pstate_get_max_freq(cpu));
2016
2017         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2018             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2019                 return -EINVAL;
2020
2021         intel_pstate_adjust_policy_max(policy, cpu);
2022
2023         return 0;
2024 }
2025
2026 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2027 {
2028         intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2029 }
2030
2031 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2032 {
2033         pr_debug("CPU %d exiting\n", policy->cpu);
2034
2035         intel_pstate_clear_update_util_hook(policy->cpu);
2036         if (hwp_active)
2037                 intel_pstate_hwp_save_state(policy);
2038         else
2039                 intel_cpufreq_stop_cpu(policy);
2040 }
2041
2042 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2043 {
2044         intel_pstate_exit_perf_limits(policy);
2045
2046         policy->fast_switch_possible = false;
2047
2048         return 0;
2049 }
2050
2051 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2052 {
2053         struct cpudata *cpu;
2054         int rc;
2055
2056         rc = intel_pstate_init_cpu(policy->cpu);
2057         if (rc)
2058                 return rc;
2059
2060         cpu = all_cpu_data[policy->cpu];
2061
2062         cpu->max_perf_ratio = 0xFF;
2063         cpu->min_perf_ratio = 0;
2064
2065         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2066         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2067
2068         /* cpuinfo and default policy values */
2069         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2070         update_turbo_state();
2071         policy->cpuinfo.max_freq = global.turbo_disabled ?
2072                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2073         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2074
2075         intel_pstate_init_acpi_perf_limits(policy);
2076
2077         policy->fast_switch_possible = true;
2078
2079         return 0;
2080 }
2081
2082 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2083 {
2084         int ret = __intel_pstate_cpu_init(policy);
2085
2086         if (ret)
2087                 return ret;
2088
2089         if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2090                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2091         else
2092                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2093
2094         return 0;
2095 }
2096
2097 static struct cpufreq_driver intel_pstate = {
2098         .flags          = CPUFREQ_CONST_LOOPS,
2099         .verify         = intel_pstate_verify_policy,
2100         .setpolicy      = intel_pstate_set_policy,
2101         .suspend        = intel_pstate_hwp_save_state,
2102         .resume         = intel_pstate_resume,
2103         .init           = intel_pstate_cpu_init,
2104         .exit           = intel_pstate_cpu_exit,
2105         .stop_cpu       = intel_pstate_stop_cpu,
2106         .name           = "intel_pstate",
2107 };
2108
2109 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2110 {
2111         struct cpudata *cpu = all_cpu_data[policy->cpu];
2112
2113         update_turbo_state();
2114         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2115                                      intel_pstate_get_max_freq(cpu));
2116
2117         intel_pstate_adjust_policy_max(policy, cpu);
2118
2119         intel_pstate_update_perf_limits(policy, cpu);
2120
2121         return 0;
2122 }
2123
2124 /* Use of trace in passive mode:
2125  *
2126  * In passive mode the trace core_busy field (also known as the
2127  * performance field, and lablelled as such on the graphs; also known as
2128  * core_avg_perf) is not needed and so is re-assigned to indicate if the
2129  * driver call was via the normal or fast switch path. Various graphs
2130  * output from the intel_pstate_tracer.py utility that include core_busy
2131  * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2132  * so we use 10 to indicate the the normal path through the driver, and
2133  * 90 to indicate the fast switch path through the driver.
2134  * The scaled_busy field is not used, and is set to 0.
2135  */
2136
2137 #define INTEL_PSTATE_TRACE_TARGET 10
2138 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2139
2140 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2141 {
2142         struct sample *sample;
2143
2144         if (!trace_pstate_sample_enabled())
2145                 return;
2146
2147         if (!intel_pstate_sample(cpu, ktime_get()))
2148                 return;
2149
2150         sample = &cpu->sample;
2151         trace_pstate_sample(trace_type,
2152                 0,
2153                 old_pstate,
2154                 cpu->pstate.current_pstate,
2155                 sample->mperf,
2156                 sample->aperf,
2157                 sample->tsc,
2158                 get_avg_frequency(cpu),
2159                 fp_toint(cpu->iowait_boost * 100));
2160 }
2161
2162 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2163                                 unsigned int target_freq,
2164                                 unsigned int relation)
2165 {
2166         struct cpudata *cpu = all_cpu_data[policy->cpu];
2167         struct cpufreq_freqs freqs;
2168         int target_pstate, old_pstate;
2169
2170         update_turbo_state();
2171
2172         freqs.old = policy->cur;
2173         freqs.new = target_freq;
2174
2175         cpufreq_freq_transition_begin(policy, &freqs);
2176         switch (relation) {
2177         case CPUFREQ_RELATION_L:
2178                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2179                 break;
2180         case CPUFREQ_RELATION_H:
2181                 target_pstate = freqs.new / cpu->pstate.scaling;
2182                 break;
2183         default:
2184                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2185                 break;
2186         }
2187         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2188         old_pstate = cpu->pstate.current_pstate;
2189         if (target_pstate != cpu->pstate.current_pstate) {
2190                 cpu->pstate.current_pstate = target_pstate;
2191                 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2192                               pstate_funcs.get_val(cpu, target_pstate));
2193         }
2194         freqs.new = target_pstate * cpu->pstate.scaling;
2195         intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_TARGET, old_pstate);
2196         cpufreq_freq_transition_end(policy, &freqs, false);
2197
2198         return 0;
2199 }
2200
2201 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2202                                               unsigned int target_freq)
2203 {
2204         struct cpudata *cpu = all_cpu_data[policy->cpu];
2205         int target_pstate, old_pstate;
2206
2207         update_turbo_state();
2208
2209         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2210         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2211         old_pstate = cpu->pstate.current_pstate;
2212         intel_pstate_update_pstate(cpu, target_pstate);
2213         intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2214         return target_pstate * cpu->pstate.scaling;
2215 }
2216
2217 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2218 {
2219         int ret = __intel_pstate_cpu_init(policy);
2220
2221         if (ret)
2222                 return ret;
2223
2224         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2225         policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2226         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2227         policy->cur = policy->cpuinfo.min_freq;
2228
2229         return 0;
2230 }
2231
2232 static struct cpufreq_driver intel_cpufreq = {
2233         .flags          = CPUFREQ_CONST_LOOPS,
2234         .verify         = intel_cpufreq_verify_policy,
2235         .target         = intel_cpufreq_target,
2236         .fast_switch    = intel_cpufreq_fast_switch,
2237         .init           = intel_cpufreq_cpu_init,
2238         .exit           = intel_pstate_cpu_exit,
2239         .stop_cpu       = intel_cpufreq_stop_cpu,
2240         .name           = "intel_cpufreq",
2241 };
2242
2243 static struct cpufreq_driver *default_driver = &intel_pstate;
2244
2245 static void intel_pstate_driver_cleanup(void)
2246 {
2247         unsigned int cpu;
2248
2249         get_online_cpus();
2250         for_each_online_cpu(cpu) {
2251                 if (all_cpu_data[cpu]) {
2252                         if (intel_pstate_driver == &intel_pstate)
2253                                 intel_pstate_clear_update_util_hook(cpu);
2254
2255                         kfree(all_cpu_data[cpu]);
2256                         all_cpu_data[cpu] = NULL;
2257                 }
2258         }
2259         put_online_cpus();
2260         intel_pstate_driver = NULL;
2261 }
2262
2263 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2264 {
2265         int ret;
2266
2267         memset(&global, 0, sizeof(global));
2268         global.max_perf_pct = 100;
2269
2270         intel_pstate_driver = driver;
2271         ret = cpufreq_register_driver(intel_pstate_driver);
2272         if (ret) {
2273                 intel_pstate_driver_cleanup();
2274                 return ret;
2275         }
2276
2277         global.min_perf_pct = min_perf_pct_min();
2278
2279         return 0;
2280 }
2281
2282 static int intel_pstate_unregister_driver(void)
2283 {
2284         if (hwp_active)
2285                 return -EBUSY;
2286
2287         cpufreq_unregister_driver(intel_pstate_driver);
2288         intel_pstate_driver_cleanup();
2289
2290         return 0;
2291 }
2292
2293 static ssize_t intel_pstate_show_status(char *buf)
2294 {
2295         if (!intel_pstate_driver)
2296                 return sprintf(buf, "off\n");
2297
2298         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2299                                         "active" : "passive");
2300 }
2301
2302 static int intel_pstate_update_status(const char *buf, size_t size)
2303 {
2304         int ret;
2305
2306         if (size == 3 && !strncmp(buf, "off", size))
2307                 return intel_pstate_driver ?
2308                         intel_pstate_unregister_driver() : -EINVAL;
2309
2310         if (size == 6 && !strncmp(buf, "active", size)) {
2311                 if (intel_pstate_driver) {
2312                         if (intel_pstate_driver == &intel_pstate)
2313                                 return 0;
2314
2315                         ret = intel_pstate_unregister_driver();
2316                         if (ret)
2317                                 return ret;
2318                 }
2319
2320                 return intel_pstate_register_driver(&intel_pstate);
2321         }
2322
2323         if (size == 7 && !strncmp(buf, "passive", size)) {
2324                 if (intel_pstate_driver) {
2325                         if (intel_pstate_driver == &intel_cpufreq)
2326                                 return 0;
2327
2328                         ret = intel_pstate_unregister_driver();
2329                         if (ret)
2330                                 return ret;
2331                 }
2332
2333                 return intel_pstate_register_driver(&intel_cpufreq);
2334         }
2335
2336         return -EINVAL;
2337 }
2338
2339 static int no_load __initdata;
2340 static int no_hwp __initdata;
2341 static int hwp_only __initdata;
2342 static unsigned int force_load __initdata;
2343
2344 static int __init intel_pstate_msrs_not_valid(void)
2345 {
2346         if (!pstate_funcs.get_max() ||
2347             !pstate_funcs.get_min() ||
2348             !pstate_funcs.get_turbo())
2349                 return -ENODEV;
2350
2351         return 0;
2352 }
2353
2354 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2355 {
2356         pstate_funcs.get_max   = funcs->get_max;
2357         pstate_funcs.get_max_physical = funcs->get_max_physical;
2358         pstate_funcs.get_min   = funcs->get_min;
2359         pstate_funcs.get_turbo = funcs->get_turbo;
2360         pstate_funcs.get_scaling = funcs->get_scaling;
2361         pstate_funcs.get_val   = funcs->get_val;
2362         pstate_funcs.get_vid   = funcs->get_vid;
2363         pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2364 }
2365
2366 #ifdef CONFIG_ACPI
2367
2368 static bool __init intel_pstate_no_acpi_pss(void)
2369 {
2370         int i;
2371
2372         for_each_possible_cpu(i) {
2373                 acpi_status status;
2374                 union acpi_object *pss;
2375                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2376                 struct acpi_processor *pr = per_cpu(processors, i);
2377
2378                 if (!pr)
2379                         continue;
2380
2381                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2382                 if (ACPI_FAILURE(status))
2383                         continue;
2384
2385                 pss = buffer.pointer;
2386                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2387                         kfree(pss);
2388                         return false;
2389                 }
2390
2391                 kfree(pss);
2392         }
2393
2394         return true;
2395 }
2396
2397 static bool __init intel_pstate_has_acpi_ppc(void)
2398 {
2399         int i;
2400
2401         for_each_possible_cpu(i) {
2402                 struct acpi_processor *pr = per_cpu(processors, i);
2403
2404                 if (!pr)
2405                         continue;
2406                 if (acpi_has_method(pr->handle, "_PPC"))
2407                         return true;
2408         }
2409         return false;
2410 }
2411
2412 enum {
2413         PSS,
2414         PPC,
2415 };
2416
2417 /* Hardware vendor-specific info that has its own power management modes */
2418 static struct acpi_platform_list plat_info[] __initdata = {
2419         {"HP    ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS},
2420         {"ORACLE", "X4-2    ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2421         {"ORACLE", "X4-2L   ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2422         {"ORACLE", "X4-2B   ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2423         {"ORACLE", "X3-2    ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2424         {"ORACLE", "X3-2L   ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2425         {"ORACLE", "X3-2B   ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2426         {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2427         {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2428         {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2429         {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2430         {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2431         {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2432         {"ORACLE", "X6-2    ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2433         {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2434         { } /* End */
2435 };
2436
2437 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2438 {
2439         const struct x86_cpu_id *id;
2440         u64 misc_pwr;
2441         int idx;
2442
2443         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2444         if (id) {
2445                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2446                 if ( misc_pwr & (1 << 8))
2447                         return true;
2448         }
2449
2450         idx = acpi_match_platform_list(plat_info);
2451         if (idx < 0)
2452                 return false;
2453
2454         switch (plat_info[idx].data) {
2455         case PSS:
2456                 return intel_pstate_no_acpi_pss();
2457         case PPC:
2458                 return intel_pstate_has_acpi_ppc() && !force_load;
2459         }
2460
2461         return false;
2462 }
2463
2464 static void intel_pstate_request_control_from_smm(void)
2465 {
2466         /*
2467          * It may be unsafe to request P-states control from SMM if _PPC support
2468          * has not been enabled.
2469          */
2470         if (acpi_ppc)
2471                 acpi_processor_pstate_control();
2472 }
2473 #else /* CONFIG_ACPI not enabled */
2474 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2475 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2476 static inline void intel_pstate_request_control_from_smm(void) {}
2477 #endif /* CONFIG_ACPI */
2478
2479 #define INTEL_PSTATE_HWP_BROADWELL      0x01
2480
2481 #define ICPU_HWP(model, hwp_mode) \
2482         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_HWP, hwp_mode }
2483
2484 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2485         ICPU_HWP(INTEL_FAM6_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
2486         ICPU_HWP(INTEL_FAM6_BROADWELL_XEON_D, INTEL_PSTATE_HWP_BROADWELL),
2487         ICPU_HWP(X86_MODEL_ANY, 0),
2488         {}
2489 };
2490
2491 static int __init intel_pstate_init(void)
2492 {
2493         const struct x86_cpu_id *id;
2494         int rc;
2495
2496         if (no_load)
2497                 return -ENODEV;
2498
2499         id = x86_match_cpu(hwp_support_ids);
2500         if (id) {
2501                 copy_cpu_funcs(&core_funcs);
2502                 if (!no_hwp) {
2503                         hwp_active++;
2504                         hwp_mode_bdw = id->driver_data;
2505                         intel_pstate.attr = hwp_cpufreq_attrs;
2506                         goto hwp_cpu_matched;
2507                 }
2508         } else {
2509                 id = x86_match_cpu(intel_pstate_cpu_ids);
2510                 if (!id)
2511                         return -ENODEV;
2512
2513                 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2514         }
2515
2516         if (intel_pstate_msrs_not_valid())
2517                 return -ENODEV;
2518
2519 hwp_cpu_matched:
2520         /*
2521          * The Intel pstate driver will be ignored if the platform
2522          * firmware has its own power management modes.
2523          */
2524         if (intel_pstate_platform_pwr_mgmt_exists())
2525                 return -ENODEV;
2526
2527         if (!hwp_active && hwp_only)
2528                 return -ENOTSUPP;
2529
2530         pr_info("Intel P-state driver initializing\n");
2531
2532         all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
2533         if (!all_cpu_data)
2534                 return -ENOMEM;
2535
2536         intel_pstate_request_control_from_smm();
2537
2538         intel_pstate_sysfs_expose_params();
2539
2540         mutex_lock(&intel_pstate_driver_lock);
2541         rc = intel_pstate_register_driver(default_driver);
2542         mutex_unlock(&intel_pstate_driver_lock);
2543         if (rc)
2544                 return rc;
2545
2546         if (hwp_active)
2547                 pr_info("HWP enabled\n");
2548
2549         return 0;
2550 }
2551 device_initcall(intel_pstate_init);
2552
2553 static int __init intel_pstate_setup(char *str)
2554 {
2555         if (!str)
2556                 return -EINVAL;
2557
2558         if (!strcmp(str, "disable")) {
2559                 no_load = 1;
2560         } else if (!strcmp(str, "passive")) {
2561                 pr_info("Passive mode enabled\n");
2562                 default_driver = &intel_cpufreq;
2563                 no_hwp = 1;
2564         }
2565         if (!strcmp(str, "no_hwp")) {
2566                 pr_info("HWP disabled\n");
2567                 no_hwp = 1;
2568         }
2569         if (!strcmp(str, "force"))
2570                 force_load = 1;
2571         if (!strcmp(str, "hwp_only"))
2572                 hwp_only = 1;
2573         if (!strcmp(str, "per_cpu_perf_limits"))
2574                 per_cpu_limits = true;
2575
2576 #ifdef CONFIG_ACPI
2577         if (!strcmp(str, "support_acpi_ppc"))
2578                 acpi_ppc = true;
2579 #endif
2580
2581         return 0;
2582 }
2583 early_param("intel_pstate", intel_pstate_setup);
2584
2585 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2586 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2587 MODULE_LICENSE("GPL");