drivers/clocksource/arm_arch_timer.c

   1 /*
   2  *  linux/drivers/clocksource/arm_arch_timer.c
   3  *
   4  *  Copyright (C) 2011 ARM Ltd.
   5  *  All Rights Reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #define pr_fmt(fmt)     "arm_arch_timer: " fmt
  13
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/device.h>
  17 #include <linux/smp.h>
  18 #include <linux/cpu.h>
  19 #include <linux/cpu_pm.h>
  20 #include <linux/clockchips.h>
  21 #include <linux/clocksource.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_address.h>
  25 #include <linux/io.h>
  26 #include <linux/slab.h>
  27 #include <linux/sched_clock.h>
  28 #include <linux/acpi.h>
  29
  30 #include <asm/arch_timer.h>
  31 #include <asm/virt.h>
  32
  33 #include <clocksource/arm_arch_timer.h>
  34
  35 #define CNTTIDR         0x08
  36 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
  37
  38 #define CNTACR(n)       (0x40 + ((n) * 4))
  39 #define CNTACR_RPCT     BIT(0)
  40 #define CNTACR_RVCT     BIT(1)
  41 #define CNTACR_RFRQ     BIT(2)
  42 #define CNTACR_RVOFF    BIT(3)
  43 #define CNTACR_RWVT     BIT(4)
  44 #define CNTACR_RWPT     BIT(5)
  45
  46 #define CNTVCT_LO       0x08
  47 #define CNTVCT_HI       0x0c
  48 #define CNTFRQ          0x10
  49 #define CNTP_TVAL       0x28
  50 #define CNTP_CTL        0x2c
  51 #define CNTV_TVAL       0x38
  52 #define CNTV_CTL        0x3c
  53
  54 #define ARCH_CP15_TIMER BIT(0)
  55 #define ARCH_MEM_TIMER  BIT(1)
  56 static unsigned arch_timers_present __initdata;
  57
  58 static void __iomem *arch_counter_base;
  59
  60 struct arch_timer {
  61         void __iomem *base;
  62         struct clock_event_device evt;
  63 };
  64
  65 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
  66
  67 static u32 arch_timer_rate;
  68
  69 enum ppi_nr {
  70         PHYS_SECURE_PPI,
  71         PHYS_NONSECURE_PPI,
  72         VIRT_PPI,
  73         HYP_PPI,
  74         MAX_TIMER_PPI
  75 };
  76
  77 static int arch_timer_ppi[MAX_TIMER_PPI];
  78
  79 static struct clock_event_device __percpu *arch_timer_evt;
  80
  81 static enum ppi_nr arch_timer_uses_ppi = VIRT_PPI;
  82 static bool arch_timer_c3stop;
  83 static bool arch_timer_mem_use_virtual;
  84 static bool arch_counter_suspend_stop;
  85
  86 static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
  87
  88 static int __init early_evtstrm_cfg(char *buf)
  89 {
  90         return strtobool(buf, &evtstrm_enable);
  91 }
  92 early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
  93
  94 /*
  95  * Architected system timer support.
  96  */
  97
  98 #ifdef CONFIG_FSL_ERRATUM_A008585
  99 /*
 100  * The number of retries is an arbitrary value well beyond the highest number
 101  * of iterations the loop has been observed to take.
 102  */
 103 #define __fsl_a008585_read_reg(reg) ({                  \
 104         u64 _old, _new;                                 \
 105         int _retries = 200;                             \
 106                                                         \
 107         do {                                            \
 108                 _old = read_sysreg(reg);                \
 109                 _new = read_sysreg(reg);                \
 110                 _retries--;                             \
 111         } while (unlikely(_old != _new) && _retries);   \
 112                                                         \
 113         WARN_ON_ONCE(!_retries);                        \
 114         _new;                                           \
 115 })
 116
 117 static u32 notrace fsl_a008585_read_cntp_tval_el0(void)
 118 {
 119         return __fsl_a008585_read_reg(cntp_tval_el0);
 120 }
 121
 122 static u32 notrace fsl_a008585_read_cntv_tval_el0(void)
 123 {
 124         return __fsl_a008585_read_reg(cntv_tval_el0);
 125 }
 126
 127 static u64 notrace fsl_a008585_read_cntvct_el0(void)
 128 {
 129         return __fsl_a008585_read_reg(cntvct_el0);
 130 }
 131 #endif
 132
 133 #ifdef CONFIG_HISILICON_ERRATUM_161010101
 134 /*
 135  * Verify whether the value of the second read is larger than the first by
 136  * less than 32 is the only way to confirm the value is correct, so clear the
 137  * lower 5 bits to check whether the difference is greater than 32 or not.
 138  * Theoretically the erratum should not occur more than twice in succession
 139  * when reading the system counter, but it is possible that some interrupts
 140  * may lead to more than twice read errors, triggering the warning, so setting
 141  * the number of retries far beyond the number of iterations the loop has been
 142  * observed to take.
 143  */
 144 #define __hisi_161010101_read_reg(reg) ({                               \
 145         u64 _old, _new;                                         \
 146         int _retries = 50;                                      \
 147                                                                 \
 148         do {                                                    \
 149                 _old = read_sysreg(reg);                        \
 150                 _new = read_sysreg(reg);                        \
 151                 _retries--;                                     \
 152         } while (unlikely((_new - _old) >> 5) && _retries);     \
 153                                                                 \
 154         WARN_ON_ONCE(!_retries);                                \
 155         _new;                                                   \
 156 })
 157
 158 static u32 notrace hisi_161010101_read_cntp_tval_el0(void)
 159 {
 160         return __hisi_161010101_read_reg(cntp_tval_el0);
 161 }
 162
 163 static u32 notrace hisi_161010101_read_cntv_tval_el0(void)
 164 {
 165         return __hisi_161010101_read_reg(cntv_tval_el0);
 166 }
 167
 168 static u64 notrace hisi_161010101_read_cntvct_el0(void)
 169 {
 170         return __hisi_161010101_read_reg(cntvct_el0);
 171 }
 172 #endif
 173
 174 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
 175 const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL;
 176 EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
 177
 178 DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
 179 EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
 180
 181 static const struct arch_timer_erratum_workaround ool_workarounds[] = {
 182 #ifdef CONFIG_FSL_ERRATUM_A008585
 183         {
 184                 .id = "fsl,erratum-a008585",
 185                 .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
 186                 .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
 187                 .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
 188         },
 189 #endif
 190 #ifdef CONFIG_HISILICON_ERRATUM_161010101
 191         {
 192                 .id = "hisilicon,erratum-161010101",
 193                 .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
 194                 .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
 195                 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
 196         },
 197 #endif
 198 };
 199 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
 200
 201 static __always_inline
 202 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
 203                           struct clock_event_device *clk)
 204 {
 205         if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
 206                 struct arch_timer *timer = to_arch_timer(clk);
 207                 switch (reg) {
 208                 case ARCH_TIMER_REG_CTRL:
 209                         writel_relaxed(val, timer->base + CNTP_CTL);
 210                         break;
 211                 case ARCH_TIMER_REG_TVAL:
 212                         writel_relaxed(val, timer->base + CNTP_TVAL);
 213                         break;
 214                 }
 215         } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
 216                 struct arch_timer *timer = to_arch_timer(clk);
 217                 switch (reg) {
 218                 case ARCH_TIMER_REG_CTRL:
 219                         writel_relaxed(val, timer->base + CNTV_CTL);
 220                         break;
 221                 case ARCH_TIMER_REG_TVAL:
 222                         writel_relaxed(val, timer->base + CNTV_TVAL);
 223                         break;
 224                 }
 225         } else {
 226                 arch_timer_reg_write_cp15(access, reg, val);
 227         }
 228 }
 229
 230 static __always_inline
 231 u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
 232                         struct clock_event_device *clk)
 233 {
 234         u32 val;
 235
 236         if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
 237                 struct arch_timer *timer = to_arch_timer(clk);
 238                 switch (reg) {
 239                 case ARCH_TIMER_REG_CTRL:
 240                         val = readl_relaxed(timer->base + CNTP_CTL);
 241                         break;
 242                 case ARCH_TIMER_REG_TVAL:
 243                         val = readl_relaxed(timer->base + CNTP_TVAL);
 244                         break;
 245                 }
 246         } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
 247                 struct arch_timer *timer = to_arch_timer(clk);
 248                 switch (reg) {
 249                 case ARCH_TIMER_REG_CTRL:
 250                         val = readl_relaxed(timer->base + CNTV_CTL);
 251                         break;
 252                 case ARCH_TIMER_REG_TVAL:
 253                         val = readl_relaxed(timer->base + CNTV_TVAL);
 254                         break;
 255                 }
 256         } else {
 257                 val = arch_timer_reg_read_cp15(access, reg);
 258         }
 259
 260         return val;
 261 }
 262
 263 static __always_inline irqreturn_t timer_handler(const int access,
 264                                         struct clock_event_device *evt)
 265 {
 266         unsigned long ctrl;
 267
 268         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
 269         if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
 270                 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
 271                 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
 272                 evt->event_handler(evt);
 273                 return IRQ_HANDLED;
 274         }
 275
 276         return IRQ_NONE;
 277 }
 278
 279 static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
 280 {
 281         struct clock_event_device *evt = dev_id;
 282
 283         return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
 284 }
 285
 286 static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
 287 {
 288         struct clock_event_device *evt = dev_id;
 289
 290         return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
 291 }
 292
 293 static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
 294 {
 295         struct clock_event_device *evt = dev_id;
 296
 297         return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
 298 }
 299
 300 static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
 301 {
 302         struct clock_event_device *evt = dev_id;
 303
 304         return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
 305 }
 306
 307 static __always_inline int timer_shutdown(const int access,
 308                                           struct clock_event_device *clk)
 309 {
 310         unsigned long ctrl;
 311
 312         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
 313         ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
 314         arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 315
 316         return 0;
 317 }
 318
 319 static int arch_timer_shutdown_virt(struct clock_event_device *clk)
 320 {
 321         return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
 322 }
 323
 324 static int arch_timer_shutdown_phys(struct clock_event_device *clk)
 325 {
 326         return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
 327 }
 328
 329 static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
 330 {
 331         return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
 332 }
 333
 334 static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
 335 {
 336         return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
 337 }
 338
 339 static __always_inline void set_next_event(const int access, unsigned long evt,
 340                                            struct clock_event_device *clk)
 341 {
 342         unsigned long ctrl;
 343         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
 344         ctrl |= ARCH_TIMER_CTRL_ENABLE;
 345         ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
 346         arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
 347         arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 348 }
 349
 350 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
 351 static __always_inline void erratum_set_next_event_generic(const int access,
 352                 unsigned long evt, struct clock_event_device *clk)
 353 {
 354         unsigned long ctrl;
 355         u64 cval = evt + arch_counter_get_cntvct();
 356
 357         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
 358         ctrl |= ARCH_TIMER_CTRL_ENABLE;
 359         ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
 360
 361         if (access == ARCH_TIMER_PHYS_ACCESS)
 362                 write_sysreg(cval, cntp_cval_el0);
 363         else if (access == ARCH_TIMER_VIRT_ACCESS)
 364                 write_sysreg(cval, cntv_cval_el0);
 365
 366         arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 367 }
 368
 369 static int erratum_set_next_event_virt(unsigned long evt,
 370                                            struct clock_event_device *clk)
 371 {
 372         erratum_set_next_event_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
 373         return 0;
 374 }
 375
 376 static int erratum_set_next_event_phys(unsigned long evt,
 377                                            struct clock_event_device *clk)
 378 {
 379         erratum_set_next_event_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
 380         return 0;
 381 }
 382 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
 383
 384 static int arch_timer_set_next_event_virt(unsigned long evt,
 385                                           struct clock_event_device *clk)
 386 {
 387         set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
 388         return 0;
 389 }
 390
 391 static int arch_timer_set_next_event_phys(unsigned long evt,
 392                                           struct clock_event_device *clk)
 393 {
 394         set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
 395         return 0;
 396 }
 397
 398 static int arch_timer_set_next_event_virt_mem(unsigned long evt,
 399                                               struct clock_event_device *clk)
 400 {
 401         set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
 402         return 0;
 403 }
 404
 405 static int arch_timer_set_next_event_phys_mem(unsigned long evt,
 406                                               struct clock_event_device *clk)
 407 {
 408         set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
 409         return 0;
 410 }
 411
 412 static void erratum_workaround_set_sne(struct clock_event_device *clk)
 413 {
 414 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
 415         if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
 416                 return;
 417
 418         if (arch_timer_uses_ppi == VIRT_PPI)
 419                 clk->set_next_event = erratum_set_next_event_virt;
 420         else
 421                 clk->set_next_event = erratum_set_next_event_phys;
 422 #endif
 423 }
 424
 425 static void __arch_timer_setup(unsigned type,
 426                                struct clock_event_device *clk)
 427 {
 428         clk->features = CLOCK_EVT_FEAT_ONESHOT;
 429
 430         if (type == ARCH_CP15_TIMER) {
 431                 if (arch_timer_c3stop)
 432                         clk->features |= CLOCK_EVT_FEAT_C3STOP;
 433                 clk->name = "arch_sys_timer";
 434                 clk->rating = 450;
 435                 clk->cpumask = cpumask_of(smp_processor_id());
 436                 clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
 437                 switch (arch_timer_uses_ppi) {
 438                 case VIRT_PPI:
 439                         clk->set_state_shutdown = arch_timer_shutdown_virt;
 440                         clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
 441                         clk->set_next_event = arch_timer_set_next_event_virt;
 442                         break;
 443                 case PHYS_SECURE_PPI:
 444                 case PHYS_NONSECURE_PPI:
 445                 case HYP_PPI:
 446                         clk->set_state_shutdown = arch_timer_shutdown_phys;
 447                         clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
 448                         clk->set_next_event = arch_timer_set_next_event_phys;
 449                         break;
 450                 default:
 451                         BUG();
 452                 }
 453
 454                 erratum_workaround_set_sne(clk);
 455         } else {
 456                 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
 457                 clk->name = "arch_mem_timer";
 458                 clk->rating = 400;
 459                 clk->cpumask = cpu_all_mask;
 460                 if (arch_timer_mem_use_virtual) {
 461                         clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
 462                         clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem;
 463                         clk->set_next_event =
 464                                 arch_timer_set_next_event_virt_mem;
 465                 } else {
 466                         clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
 467                         clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem;
 468                         clk->set_next_event =
 469                                 arch_timer_set_next_event_phys_mem;
 470                 }
 471         }
 472
 473         clk->set_state_shutdown(clk);
 474
 475         clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
 476 }
 477
 478 static void arch_timer_evtstrm_enable(int divider)
 479 {
 480         u32 cntkctl = arch_timer_get_cntkctl();
 481
 482         cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
 483         /* Set the divider and enable virtual event stream */
 484         cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
 485                         | ARCH_TIMER_VIRT_EVT_EN;
 486         arch_timer_set_cntkctl(cntkctl);
 487         elf_hwcap |= HWCAP_EVTSTRM;
 488 #ifdef CONFIG_COMPAT
 489         compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
 490 #endif
 491 }
 492
 493 static void arch_timer_configure_evtstream(void)
 494 {
 495         int evt_stream_div, pos;
 496
 497         /* Find the closest power of two to the divisor */
 498         evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;
 499         pos = fls(evt_stream_div);
 500         if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))
 501                 pos--;
 502         /* enable event stream */
 503         arch_timer_evtstrm_enable(min(pos, 15));
 504 }
 505
 506 static void arch_counter_set_user_access(void)
 507 {
 508         u32 cntkctl = arch_timer_get_cntkctl();
 509
 510         /* Disable user access to the timers and the physical counter */
 511         /* Also disable virtual event stream */
 512         cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
 513                         | ARCH_TIMER_USR_VT_ACCESS_EN
 514                         | ARCH_TIMER_VIRT_EVT_EN
 515                         | ARCH_TIMER_USR_PCT_ACCESS_EN);
 516
 517         /* Enable user access to the virtual counter */
 518         cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
 519
 520         arch_timer_set_cntkctl(cntkctl);
 521 }
 522
 523 static bool arch_timer_has_nonsecure_ppi(void)
 524 {
 525         return (arch_timer_uses_ppi == PHYS_SECURE_PPI &&
 526                 arch_timer_ppi[PHYS_NONSECURE_PPI]);
 527 }
 528
 529 static u32 check_ppi_trigger(int irq)
 530 {
 531         u32 flags = irq_get_trigger_type(irq);
 532
 533         if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
 534                 pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
 535                 pr_warn("WARNING: Please fix your firmware\n");
 536                 flags = IRQF_TRIGGER_LOW;
 537         }
 538
 539         return flags;
 540 }
 541
 542 static int arch_timer_starting_cpu(unsigned int cpu)
 543 {
 544         struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
 545         u32 flags;
 546
 547         __arch_timer_setup(ARCH_CP15_TIMER, clk);
 548
 549         flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
 550         enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
 551
 552         if (arch_timer_has_nonsecure_ppi()) {
 553                 flags = check_ppi_trigger(arch_timer_ppi[PHYS_NONSECURE_PPI]);
 554                 enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], flags);
 555         }
 556
 557         arch_counter_set_user_access();
 558         if (evtstrm_enable)
 559                 arch_timer_configure_evtstream();
 560
 561         return 0;
 562 }
 563
 564 static void
 565 arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
 566 {
 567         /* Who has more than one independent system counter? */
 568         if (arch_timer_rate)
 569                 return;
 570
 571         /*
 572          * Try to determine the frequency from the device tree or CNTFRQ,
 573          * if ACPI is enabled, get the frequency from CNTFRQ ONLY.
 574          */
 575         if (!acpi_disabled ||
 576             of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
 577                 if (cntbase)
 578                         arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
 579                 else
 580                         arch_timer_rate = arch_timer_get_cntfrq();
 581         }
 582
 583         /* Check the timer frequency. */
 584         if (arch_timer_rate == 0)
 585                 pr_warn("Architected timer frequency not available\n");
 586 }
 587
 588 static void arch_timer_banner(unsigned type)
 589 {
 590         pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
 591                      type & ARCH_CP15_TIMER ? "cp15" : "",
 592                      type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ?  " and " : "",
 593                      type & ARCH_MEM_TIMER ? "mmio" : "",
 594                      (unsigned long)arch_timer_rate / 1000000,
 595                      (unsigned long)(arch_timer_rate / 10000) % 100,
 596                      type & ARCH_CP15_TIMER ?
 597                      (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" :
 598                         "",
 599                      type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ?  "/" : "",
 600                      type & ARCH_MEM_TIMER ?
 601                         arch_timer_mem_use_virtual ? "virt" : "phys" :
 602                         "");
 603 }
 604
 605 u32 arch_timer_get_rate(void)
 606 {
 607         return arch_timer_rate;
 608 }
 609
 610 static u64 arch_counter_get_cntvct_mem(void)
 611 {
 612         u32 vct_lo, vct_hi, tmp_hi;
 613
 614         do {
 615                 vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
 616                 vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
 617                 tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
 618         } while (vct_hi != tmp_hi);
 619
 620         return ((u64) vct_hi << 32) | vct_lo;
 621 }
 622
 623 /*
 624  * Default to cp15 based access because arm64 uses this function for
 625  * sched_clock() before DT is probed and the cp15 method is guaranteed
 626  * to exist on arm64. arm doesn't use this before DT is probed so even
 627  * if we don't have the cp15 accessors we won't have a problem.
 628  */
 629 u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
 630
 631 static u64 arch_counter_read(struct clocksource *cs)
 632 {
 633         return arch_timer_read_counter();
 634 }
 635
 636 static u64 arch_counter_read_cc(const struct cyclecounter *cc)
 637 {
 638         return arch_timer_read_counter();
 639 }
 640
 641 static struct clocksource clocksource_counter = {
 642         .name   = "arch_sys_counter",
 643         .rating = 400,
 644         .read   = arch_counter_read,
 645         .mask   = CLOCKSOURCE_MASK(56),
 646         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 647 };
 648
 649 static struct cyclecounter cyclecounter __ro_after_init = {
 650         .read   = arch_counter_read_cc,
 651         .mask   = CLOCKSOURCE_MASK(56),
 652 };
 653
 654 static struct arch_timer_kvm_info arch_timer_kvm_info;
 655
 656 struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
 657 {
 658         return &arch_timer_kvm_info;
 659 }
 660
 661 static void __init arch_counter_register(unsigned type)
 662 {
 663         u64 start_count;
 664
 665         /* Register the CP15 based counter if we have one */
 666         if (type & ARCH_CP15_TIMER) {
 667                 if (IS_ENABLED(CONFIG_ARM64) || arch_timer_uses_ppi == VIRT_PPI)
 668                         arch_timer_read_counter = arch_counter_get_cntvct;
 669                 else
 670                         arch_timer_read_counter = arch_counter_get_cntpct;
 671
 672                 clocksource_counter.archdata.vdso_direct = true;
 673
 674 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
 675                 /*
 676                  * Don't use the vdso fastpath if errata require using
 677                  * the out-of-line counter accessor.
 678                  */
 679                 if (static_branch_unlikely(&arch_timer_read_ool_enabled))
 680                         clocksource_counter.archdata.vdso_direct = false;
 681 #endif
 682         } else {
 683                 arch_timer_read_counter = arch_counter_get_cntvct_mem;
 684         }
 685
 686         if (!arch_counter_suspend_stop)
 687                 clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
 688         start_count = arch_timer_read_counter();
 689         clocksource_register_hz(&clocksource_counter, arch_timer_rate);
 690         cyclecounter.mult = clocksource_counter.mult;
 691         cyclecounter.shift = clocksource_counter.shift;
 692         timecounter_init(&arch_timer_kvm_info.timecounter,
 693                          &cyclecounter, start_count);
 694
 695         /* 56 bits minimum, so we assume worst case rollover */
 696         sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
 697 }
 698
 699 static void arch_timer_stop(struct clock_event_device *clk)
 700 {
 701         pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
 702                  clk->irq, smp_processor_id());
 703
 704         disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
 705         if (arch_timer_has_nonsecure_ppi())
 706                 disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
 707
 708         clk->set_state_shutdown(clk);
 709 }
 710
 711 static int arch_timer_dying_cpu(unsigned int cpu)
 712 {
 713         struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
 714
 715         arch_timer_stop(clk);
 716         return 0;
 717 }
 718
 719 #ifdef CONFIG_CPU_PM
 720 static unsigned int saved_cntkctl;
 721 static int arch_timer_cpu_pm_notify(struct notifier_block *self,
 722                                     unsigned long action, void *hcpu)
 723 {
 724         if (action == CPU_PM_ENTER)
 725                 saved_cntkctl = arch_timer_get_cntkctl();
 726         else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT)
 727                 arch_timer_set_cntkctl(saved_cntkctl);
 728         return NOTIFY_OK;
 729 }
 730
 731 static struct notifier_block arch_timer_cpu_pm_notifier = {
 732         .notifier_call = arch_timer_cpu_pm_notify,
 733 };
 734
 735 static int __init arch_timer_cpu_pm_init(void)
 736 {
 737         return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
 738 }
 739
 740 static void __init arch_timer_cpu_pm_deinit(void)
 741 {
 742         WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier));
 743 }
 744
 745 #else
 746 static int __init arch_timer_cpu_pm_init(void)
 747 {
 748         return 0;
 749 }
 750
 751 static void __init arch_timer_cpu_pm_deinit(void)
 752 {
 753 }
 754 #endif
 755
 756 static int __init arch_timer_register(void)
 757 {
 758         int err;
 759         int ppi;
 760
 761         arch_timer_evt = alloc_percpu(struct clock_event_device);
 762         if (!arch_timer_evt) {
 763                 err = -ENOMEM;
 764                 goto out;
 765         }
 766
 767         ppi = arch_timer_ppi[arch_timer_uses_ppi];
 768         switch (arch_timer_uses_ppi) {
 769         case VIRT_PPI:
 770                 err = request_percpu_irq(ppi, arch_timer_handler_virt,
 771                                          "arch_timer", arch_timer_evt);
 772                 break;
 773         case PHYS_SECURE_PPI:
 774         case PHYS_NONSECURE_PPI:
 775                 err = request_percpu_irq(ppi, arch_timer_handler_phys,
 776                                          "arch_timer", arch_timer_evt);
 777                 if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
 778                         ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
 779                         err = request_percpu_irq(ppi, arch_timer_handler_phys,
 780                                                  "arch_timer", arch_timer_evt);
 781                         if (err)
 782                                 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
 783                                                 arch_timer_evt);
 784                 }
 785                 break;
 786         case HYP_PPI:
 787                 err = request_percpu_irq(ppi, arch_timer_handler_phys,
 788                                          "arch_timer", arch_timer_evt);
 789                 break;
 790         default:
 791                 BUG();
 792         }
 793
 794         if (err) {
 795                 pr_err("arch_timer: can't register interrupt %d (%d)\n",
 796                        ppi, err);
 797                 goto out_free;
 798         }
 799
 800         err = arch_timer_cpu_pm_init();
 801         if (err)
 802                 goto out_unreg_notify;
 803
 804
 805         /* Register and immediately configure the timer on the boot CPU */
 806         err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
 807                                 "clockevents/arm/arch_timer:starting",
 808                                 arch_timer_starting_cpu, arch_timer_dying_cpu);
 809         if (err)
 810                 goto out_unreg_cpupm;
 811         return 0;
 812
 813 out_unreg_cpupm:
 814         arch_timer_cpu_pm_deinit();
 815
 816 out_unreg_notify:
 817         free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
 818         if (arch_timer_has_nonsecure_ppi())
 819                 free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
 820                                 arch_timer_evt);
 821
 822 out_free:
 823         free_percpu(arch_timer_evt);
 824 out:
 825         return err;
 826 }
 827
 828 static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
 829 {
 830         int ret;
 831         irq_handler_t func;
 832         struct arch_timer *t;
 833
 834         t = kzalloc(sizeof(*t), GFP_KERNEL);
 835         if (!t)
 836                 return -ENOMEM;
 837
 838         t->base = base;
 839         t->evt.irq = irq;
 840         __arch_timer_setup(ARCH_MEM_TIMER, &t->evt);
 841
 842         if (arch_timer_mem_use_virtual)
 843                 func = arch_timer_handler_virt_mem;
 844         else
 845                 func = arch_timer_handler_phys_mem;
 846
 847         ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
 848         if (ret) {
 849                 pr_err("arch_timer: Failed to request mem timer irq\n");
 850                 kfree(t);
 851         }
 852
 853         return ret;
 854 }
 855
 856 static const struct of_device_id arch_timer_of_match[] __initconst = {
 857         { .compatible   = "arm,armv7-timer",    },
 858         { .compatible   = "arm,armv8-timer",    },
 859         {},
 860 };
 861
 862 static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
 863         { .compatible   = "arm,armv7-timer-mem", },
 864         {},
 865 };
 866
 867 static bool __init
 868 arch_timer_needs_probing(int type, const struct of_device_id *matches)
 869 {
 870         struct device_node *dn;
 871         bool needs_probing = false;
 872
 873         dn = of_find_matching_node(NULL, matches);
 874         if (dn && of_device_is_available(dn) && !(arch_timers_present & type))
 875                 needs_probing = true;
 876         of_node_put(dn);
 877
 878         return needs_probing;
 879 }
 880
 881 static int __init arch_timer_common_init(void)
 882 {
 883         unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER;
 884
 885         /* Wait until both nodes are probed if we have two timers */
 886         if ((arch_timers_present & mask) != mask) {
 887                 if (arch_timer_needs_probing(ARCH_MEM_TIMER, arch_timer_mem_of_match))
 888                         return 0;
 889                 if (arch_timer_needs_probing(ARCH_CP15_TIMER, arch_timer_of_match))
 890                         return 0;
 891         }
 892
 893         arch_timer_banner(arch_timers_present);
 894         arch_counter_register(arch_timers_present);
 895         return arch_timer_arch_init();
 896 }
 897
 898 static int __init arch_timer_init(void)
 899 {
 900         int ret;
 901         /*
 902          * If HYP mode is available, we know that the physical timer
 903          * has been configured to be accessible from PL1. Use it, so
 904          * that a guest can use the virtual timer instead.
 905          *
 906          * If no interrupt provided for virtual timer, we'll have to
 907          * stick to the physical timer. It'd better be accessible...
 908          *
 909          * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
 910          * accesses to CNTP_*_EL1 registers are silently redirected to
 911          * their CNTHP_*_EL2 counterparts, and use a different PPI
 912          * number.
 913          */
 914         if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
 915                 bool has_ppi;
 916
 917                 if (is_kernel_in_hyp_mode()) {
 918                         arch_timer_uses_ppi = HYP_PPI;
 919                         has_ppi = !!arch_timer_ppi[HYP_PPI];
 920                 } else {
 921                         arch_timer_uses_ppi = PHYS_SECURE_PPI;
 922                         has_ppi = (!!arch_timer_ppi[PHYS_SECURE_PPI] ||
 923                                    !!arch_timer_ppi[PHYS_NONSECURE_PPI]);
 924                 }
 925
 926                 if (!has_ppi) {
 927                         pr_warn("arch_timer: No interrupt available, giving up\n");
 928                         return -EINVAL;
 929                 }
 930         }
 931
 932         ret = arch_timer_register();
 933         if (ret)
 934                 return ret;
 935
 936         ret = arch_timer_common_init();
 937         if (ret)
 938                 return ret;
 939
 940         arch_timer_kvm_info.virtual_irq = arch_timer_ppi[VIRT_PPI];
 941
 942         return 0;
 943 }
 944
 945 static int __init arch_timer_of_init(struct device_node *np)
 946 {
 947         int i;
 948
 949         if (arch_timers_present & ARCH_CP15_TIMER) {
 950                 pr_warn("arch_timer: multiple nodes in dt, skipping\n");
 951                 return 0;
 952         }
 953
 954         arch_timers_present |= ARCH_CP15_TIMER;
 955         for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
 956                 arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
 957
 958         arch_timer_detect_rate(NULL, np);
 959
 960         arch_timer_c3stop = !of_property_read_bool(np, "always-on");
 961
 962 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
 963         for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
 964                 if (of_property_read_bool(np, ool_workarounds[i].id)) {
 965                         timer_unstable_counter_workaround = &ool_workarounds[i];
 966                         static_branch_enable(&arch_timer_read_ool_enabled);
 967                         pr_info("arch_timer: Enabling workaround for %s\n",
 968                                 timer_unstable_counter_workaround->id);
 969                         break;
 970                 }
 971         }
 972 #endif
 973
 974         /*
 975          * If we cannot rely on firmware initializing the timer registers then
 976          * we should use the physical timers instead.
 977          */
 978         if (IS_ENABLED(CONFIG_ARM) &&
 979             of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
 980                 arch_timer_uses_ppi = PHYS_SECURE_PPI;
 981
 982         /* On some systems, the counter stops ticking when in suspend. */
 983         arch_counter_suspend_stop = of_property_read_bool(np,
 984                                                          "arm,no-tick-in-suspend");
 985
 986         return arch_timer_init();
 987 }
 988 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
 989 CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
 990
 991 static int __init arch_timer_mem_init(struct device_node *np)
 992 {
 993         struct device_node *frame, *best_frame = NULL;
 994         void __iomem *cntctlbase, *base;
 995         unsigned int irq, ret = -EINVAL;
 996         u32 cnttidr;
 997
 998         arch_timers_present |= ARCH_MEM_TIMER;
 999         cntctlbase = of_iomap(np, 0);
1000         if (!cntctlbase) {
1001                 pr_err("arch_timer: Can't find CNTCTLBase\n");
1002                 return -ENXIO;
1003         }
1004
1005         cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
1006
1007         /*
1008          * Try to find a virtual capable frame. Otherwise fall back to a
1009          * physical capable frame.
1010          */
1011         for_each_available_child_of_node(np, frame) {
1012                 int n;
1013                 u32 cntacr;
1014
1015                 if (of_property_read_u32(frame, "frame-number", &n)) {
1016                         pr_err("arch_timer: Missing frame-number\n");
1017                         of_node_put(frame);
1018                         goto out;
1019                 }
1020
1021                 /* Try enabling everything, and see what sticks */
1022                 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
1023                          CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
1024                 writel_relaxed(cntacr, cntctlbase + CNTACR(n));
1025                 cntacr = readl_relaxed(cntctlbase + CNTACR(n));
1026
1027                 if ((cnttidr & CNTTIDR_VIRT(n)) &&
1028                     !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
1029                         of_node_put(best_frame);
1030                         best_frame = frame;
1031                         arch_timer_mem_use_virtual = true;
1032                         break;
1033                 }
1034
1035                 if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
1036                         continue;
1037
1038                 of_node_put(best_frame);
1039                 best_frame = of_node_get(frame);
1040         }
1041
1042         ret= -ENXIO;
1043         base = arch_counter_base = of_io_request_and_map(best_frame, 0,
1044                                                          "arch_mem_timer");
1045         if (IS_ERR(base)) {
1046                 pr_err("arch_timer: Can't map frame's registers\n");
1047                 goto out;
1048         }
1049
1050         if (arch_timer_mem_use_virtual)
1051                 irq = irq_of_parse_and_map(best_frame, 1);
1052         else
1053                 irq = irq_of_parse_and_map(best_frame, 0);
1054
1055         ret = -EINVAL;
1056         if (!irq) {
1057                 pr_err("arch_timer: Frame missing %s irq",
1058                        arch_timer_mem_use_virtual ? "virt" : "phys");
1059                 goto out;
1060         }
1061
1062         arch_timer_detect_rate(base, np);
1063         ret = arch_timer_mem_register(base, irq);
1064         if (ret)
1065                 goto out;
1066
1067         return arch_timer_common_init();
1068 out:
1069         iounmap(cntctlbase);
1070         of_node_put(best_frame);
1071         return ret;
1072 }
1073 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
1074                        arch_timer_mem_init);
1075
1076 #ifdef CONFIG_ACPI
1077 static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags)
1078 {
1079         int trigger, polarity;
1080
1081         if (!interrupt)
1082                 return 0;
1083
1084         trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE
1085                         : ACPI_LEVEL_SENSITIVE;
1086
1087         polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW
1088                         : ACPI_ACTIVE_HIGH;
1089
1090         return acpi_register_gsi(NULL, interrupt, trigger, polarity);
1091 }
1092
1093 /* Initialize per-processor generic timer */
1094 static int __init arch_timer_acpi_init(struct acpi_table_header *table)
1095 {
1096         struct acpi_table_gtdt *gtdt;
1097
1098         if (arch_timers_present & ARCH_CP15_TIMER) {
1099                 pr_warn("arch_timer: already initialized, skipping\n");
1100                 return -EINVAL;
1101         }
1102
1103         gtdt = container_of(table, struct acpi_table_gtdt, header);
1104
1105         arch_timers_present |= ARCH_CP15_TIMER;
1106
1107         arch_timer_ppi[PHYS_SECURE_PPI] =
1108                 map_generic_timer_interrupt(gtdt->secure_el1_interrupt,
1109                 gtdt->secure_el1_flags);
1110
1111         arch_timer_ppi[PHYS_NONSECURE_PPI] =
1112                 map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt,
1113                 gtdt->non_secure_el1_flags);
1114
1115         arch_timer_ppi[VIRT_PPI] =
1116                 map_generic_timer_interrupt(gtdt->virtual_timer_interrupt,
1117                 gtdt->virtual_timer_flags);
1118
1119         arch_timer_ppi[HYP_PPI] =
1120                 map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt,
1121                 gtdt->non_secure_el2_flags);
1122
1123         /* Get the frequency from CNTFRQ */
1124         arch_timer_detect_rate(NULL, NULL);
1125
1126         /* Always-on capability */
1127         arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON);
1128
1129         arch_timer_init();
1130         return 0;
1131 }
1132 CLOCKSOURCE_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
1133 #endif