drivers/clk/ti/fapll.c

   1 /*
   2  * This program is free software; you can redistribute it and/or
   3  * modify it under the terms of the GNU General Public License as
   4  * published by the Free Software Foundation version 2.
   5  *
   6  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   7  * kind, whether express or implied; without even the implied warranty
   8  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
   9  * GNU General Public License for more details.
  10  */
  11
  12 #include <linux/clk-provider.h>
  13 #include <linux/delay.h>
  14 #include <linux/err.h>
  15 #include <linux/math64.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/clk/ti.h>
  19
  20 /* FAPLL Control Register PLL_CTRL */
  21 #define FAPLL_MAIN_MULT_N_SHIFT 16
  22 #define FAPLL_MAIN_DIV_P_SHIFT  8
  23 #define FAPLL_MAIN_LOCK         BIT(7)
  24 #define FAPLL_MAIN_PLLEN        BIT(3)
  25 #define FAPLL_MAIN_BP           BIT(2)
  26 #define FAPLL_MAIN_LOC_CTL      BIT(0)
  27
  28 #define FAPLL_MAIN_MAX_MULT_N   0xffff
  29 #define FAPLL_MAIN_MAX_DIV_P    0xff
  30 #define FAPLL_MAIN_CLEAR_MASK   \
  31         ((FAPLL_MAIN_MAX_MULT_N << FAPLL_MAIN_MULT_N_SHIFT) | \
  32          (FAPLL_MAIN_DIV_P_SHIFT << FAPLL_MAIN_DIV_P_SHIFT) | \
  33          FAPLL_MAIN_LOC_CTL)
  34
  35 /* FAPLL powerdown register PWD */
  36 #define FAPLL_PWD_OFFSET        4
  37
  38 #define MAX_FAPLL_OUTPUTS       7
  39 #define FAPLL_MAX_RETRIES       1000
  40
  41 #define to_fapll(_hw)           container_of(_hw, struct fapll_data, hw)
  42 #define to_synth(_hw)           container_of(_hw, struct fapll_synth, hw)
  43
  44 /* The bypass bit is inverted on the ddr_pll.. */
  45 #define fapll_is_ddr_pll(va)    (((u32)(va) & 0xffff) == 0x0440)
  46
  47 /*
  48  * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock,
  49  * and the audio_pll_clk1 synthesizer is hardwared to 32KiHz output.
  50  */
  51 #define is_ddr_pll_clk1(va)     (((u32)(va) & 0xffff) == 0x044c)
  52 #define is_audio_pll_clk1(va)   (((u32)(va) & 0xffff) == 0x04a8)
  53
  54 /* Synthesizer divider register */
  55 #define SYNTH_LDMDIV1           BIT(8)
  56
  57 /* Synthesizer frequency register */
  58 #define SYNTH_LDFREQ            BIT(31)
  59
  60 #define SYNTH_PHASE_K           8
  61 #define SYNTH_MAX_INT_DIV       0xf
  62 #define SYNTH_MAX_DIV_M         0xff
  63
  64 struct fapll_data {
  65         struct clk_hw hw;
  66         void __iomem *base;
  67         const char *name;
  68         struct clk *clk_ref;
  69         struct clk *clk_bypass;
  70         struct clk_onecell_data outputs;
  71         bool bypass_bit_inverted;
  72 };
  73
  74 struct fapll_synth {
  75         struct clk_hw hw;
  76         struct fapll_data *fd;
  77         int index;
  78         void __iomem *freq;
  79         void __iomem *div;
  80         const char *name;
  81         struct clk *clk_pll;
  82 };
  83
  84 static bool ti_fapll_clock_is_bypass(struct fapll_data *fd)
  85 {
  86         u32 v = readl_relaxed(fd->base);
  87
  88         if (fd->bypass_bit_inverted)
  89                 return !(v & FAPLL_MAIN_BP);
  90         else
  91                 return !!(v & FAPLL_MAIN_BP);
  92 }
  93
  94 static void ti_fapll_set_bypass(struct fapll_data *fd)
  95 {
  96         u32 v = readl_relaxed(fd->base);
  97
  98         if (fd->bypass_bit_inverted)
  99                 v &= ~FAPLL_MAIN_BP;
 100         else
 101                 v |= FAPLL_MAIN_BP;
 102         writel_relaxed(v, fd->base);
 103 }
 104
 105 static void ti_fapll_clear_bypass(struct fapll_data *fd)
 106 {
 107         u32 v = readl_relaxed(fd->base);
 108
 109         if (fd->bypass_bit_inverted)
 110                 v |= FAPLL_MAIN_BP;
 111         else
 112                 v &= ~FAPLL_MAIN_BP;
 113         writel_relaxed(v, fd->base);
 114 }
 115
 116 static int ti_fapll_wait_lock(struct fapll_data *fd)
 117 {
 118         int retries = FAPLL_MAX_RETRIES;
 119         u32 v;
 120
 121         while ((v = readl_relaxed(fd->base))) {
 122                 if (v & FAPLL_MAIN_LOCK)
 123                         return 0;
 124
 125                 if (retries-- <= 0)
 126                         break;
 127
 128                 udelay(1);
 129         }
 130
 131         pr_err("%s failed to lock\n", fd->name);
 132
 133         return -ETIMEDOUT;
 134 }
 135
 136 static int ti_fapll_enable(struct clk_hw *hw)
 137 {
 138         struct fapll_data *fd = to_fapll(hw);
 139         u32 v = readl_relaxed(fd->base);
 140
 141         v |= FAPLL_MAIN_PLLEN;
 142         writel_relaxed(v, fd->base);
 143         ti_fapll_wait_lock(fd);
 144
 145         return 0;
 146 }
 147
 148 static void ti_fapll_disable(struct clk_hw *hw)
 149 {
 150         struct fapll_data *fd = to_fapll(hw);
 151         u32 v = readl_relaxed(fd->base);
 152
 153         v &= ~FAPLL_MAIN_PLLEN;
 154         writel_relaxed(v, fd->base);
 155 }
 156
 157 static int ti_fapll_is_enabled(struct clk_hw *hw)
 158 {
 159         struct fapll_data *fd = to_fapll(hw);
 160         u32 v = readl_relaxed(fd->base);
 161
 162         return v & FAPLL_MAIN_PLLEN;
 163 }
 164
 165 static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,
 166                                           unsigned long parent_rate)
 167 {
 168         struct fapll_data *fd = to_fapll(hw);
 169         u32 fapll_n, fapll_p, v;
 170         long long rate;
 171
 172         if (ti_fapll_clock_is_bypass(fd))
 173                 return parent_rate;
 174
 175         rate = parent_rate;
 176
 177         /* PLL pre-divider is P and multiplier is N */
 178         v = readl_relaxed(fd->base);
 179         fapll_p = (v >> 8) & 0xff;
 180         if (fapll_p)
 181                 do_div(rate, fapll_p);
 182         fapll_n = v >> 16;
 183         if (fapll_n)
 184                 rate *= fapll_n;
 185
 186         return rate;
 187 }
 188
 189 static u8 ti_fapll_get_parent(struct clk_hw *hw)
 190 {
 191         struct fapll_data *fd = to_fapll(hw);
 192
 193         if (ti_fapll_clock_is_bypass(fd))
 194                 return 1;
 195
 196         return 0;
 197 }
 198
 199 static int ti_fapll_set_div_mult(unsigned long rate,
 200                                  unsigned long parent_rate,
 201                                  u32 *pre_div_p, u32 *mult_n)
 202 {
 203         /*
 204          * So far no luck getting decent clock with PLL divider,
 205          * PLL does not seem to lock and the signal does not look
 206          * right. It seems the divider can only be used together
 207          * with the multiplier?
 208          */
 209         if (rate < parent_rate) {
 210                 pr_warn("FAPLL main divider rates unsupported\n");
 211                 return -EINVAL;
 212         }
 213
 214         *mult_n = rate / parent_rate;
 215         if (*mult_n > FAPLL_MAIN_MAX_MULT_N)
 216                 return -EINVAL;
 217         *pre_div_p = 1;
 218
 219         return 0;
 220 }
 221
 222 static long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate,
 223                                 unsigned long *parent_rate)
 224 {
 225         u32 pre_div_p, mult_n;
 226         int error;
 227
 228         if (!rate)
 229                 return -EINVAL;
 230
 231         error = ti_fapll_set_div_mult(rate, *parent_rate,
 232                                       &pre_div_p, &mult_n);
 233         if (error)
 234                 return error;
 235
 236         rate = *parent_rate / pre_div_p;
 237         rate *= mult_n;
 238
 239         return rate;
 240 }
 241
 242 static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate,
 243                              unsigned long parent_rate)
 244 {
 245         struct fapll_data *fd = to_fapll(hw);
 246         u32 pre_div_p, mult_n, v;
 247         int error;
 248
 249         if (!rate)
 250                 return -EINVAL;
 251
 252         error = ti_fapll_set_div_mult(rate, parent_rate,
 253                                       &pre_div_p, &mult_n);
 254         if (error)
 255                 return error;
 256
 257         ti_fapll_set_bypass(fd);
 258         v = readl_relaxed(fd->base);
 259         v &= ~FAPLL_MAIN_CLEAR_MASK;
 260         v |= pre_div_p << FAPLL_MAIN_DIV_P_SHIFT;
 261         v |= mult_n << FAPLL_MAIN_MULT_N_SHIFT;
 262         writel_relaxed(v, fd->base);
 263         if (ti_fapll_is_enabled(hw))
 264                 ti_fapll_wait_lock(fd);
 265         ti_fapll_clear_bypass(fd);
 266
 267         return 0;
 268 }
 269
 270 static struct clk_ops ti_fapll_ops = {
 271         .enable = ti_fapll_enable,
 272         .disable = ti_fapll_disable,
 273         .is_enabled = ti_fapll_is_enabled,
 274         .recalc_rate = ti_fapll_recalc_rate,
 275         .get_parent = ti_fapll_get_parent,
 276         .round_rate = ti_fapll_round_rate,
 277         .set_rate = ti_fapll_set_rate,
 278 };
 279
 280 static int ti_fapll_synth_enable(struct clk_hw *hw)
 281 {
 282         struct fapll_synth *synth = to_synth(hw);
 283         u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
 284
 285         v &= ~(1 << synth->index);
 286         writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
 287
 288         return 0;
 289 }
 290
 291 static void ti_fapll_synth_disable(struct clk_hw *hw)
 292 {
 293         struct fapll_synth *synth = to_synth(hw);
 294         u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
 295
 296         v |= 1 << synth->index;
 297         writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
 298 }
 299
 300 static int ti_fapll_synth_is_enabled(struct clk_hw *hw)
 301 {
 302         struct fapll_synth *synth = to_synth(hw);
 303         u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
 304
 305         return !(v & (1 << synth->index));
 306 }
 307
 308 /*
 309  * See dm816x TRM chapter 1.10.3 Flying Adder PLL fore more info
 310  */
 311 static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
 312                                                 unsigned long parent_rate)
 313 {
 314         struct fapll_synth *synth = to_synth(hw);
 315         u32 synth_div_m;
 316         long long rate;
 317
 318         /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */
 319         if (!synth->div)
 320                 return 32768;
 321
 322         /*
 323          * PLL in bypass sets the synths in bypass mode too. The PLL rate
 324          * can be also be set to 27MHz, so we can't use parent_rate to
 325          * check for bypass mode.
 326          */
 327         if (ti_fapll_clock_is_bypass(synth->fd))
 328                 return parent_rate;
 329
 330         rate = parent_rate;
 331
 332         /*
 333          * Synth frequency integer and fractional divider.
 334          * Note that the phase output K is 8, so the result needs
 335          * to be multiplied by SYNTH_PHASE_K.
 336          */
 337         if (synth->freq) {
 338                 u32 v, synth_int_div, synth_frac_div, synth_div_freq;
 339
 340                 v = readl_relaxed(synth->freq);
 341                 synth_int_div = (v >> 24) & 0xf;
 342                 synth_frac_div = v & 0xffffff;
 343                 synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
 344                 rate *= 10000000;
 345                 do_div(rate, synth_div_freq);
 346                 rate *= SYNTH_PHASE_K;
 347         }
 348
 349         /* Synth post-divider M */
 350         synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
 351
 352         return DIV_ROUND_UP_ULL(rate, synth_div_m);
 353 }
 354
 355 static unsigned long ti_fapll_synth_get_frac_rate(struct clk_hw *hw,
 356                                                   unsigned long parent_rate)
 357 {
 358         struct fapll_synth *synth = to_synth(hw);
 359         unsigned long current_rate, frac_rate;
 360         u32 post_div_m;
 361
 362         current_rate = ti_fapll_synth_recalc_rate(hw, parent_rate);
 363         post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
 364         frac_rate = current_rate * post_div_m;
 365
 366         return frac_rate;
 367 }
 368
 369 static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth,
 370                                         unsigned long rate,
 371                                         unsigned long parent_rate)
 372 {
 373         u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v;
 374
 375         post_div_m = DIV_ROUND_UP_ULL((u64)parent_rate * SYNTH_PHASE_K, rate);
 376         post_div_m = post_div_m / SYNTH_MAX_INT_DIV;
 377         if (post_div_m > SYNTH_MAX_DIV_M)
 378                 return -EINVAL;
 379         if (!post_div_m)
 380                 post_div_m = 1;
 381
 382         for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) {
 383                 synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate *
 384                                                  SYNTH_PHASE_K *
 385                                                  10000000,
 386                                                  rate * post_div_m);
 387                 synth_frac_div = synth_int_div % 10000000;
 388                 synth_int_div /= 10000000;
 389
 390                 if (synth_int_div <= SYNTH_MAX_INT_DIV)
 391                         break;
 392         }
 393
 394         if (synth_int_div > SYNTH_MAX_INT_DIV)
 395                 return -EINVAL;
 396
 397         v = readl_relaxed(synth->freq);
 398         v &= ~0x1fffffff;
 399         v |= (synth_int_div & SYNTH_MAX_INT_DIV) << 24;
 400         v |= (synth_frac_div & 0xffffff);
 401         v |= SYNTH_LDFREQ;
 402         writel_relaxed(v, synth->freq);
 403
 404         return post_div_m;
 405 }
 406
 407 static long ti_fapll_synth_round_rate(struct clk_hw *hw, unsigned long rate,
 408                                       unsigned long *parent_rate)
 409 {
 410         struct fapll_synth *synth = to_synth(hw);
 411         struct fapll_data *fd = synth->fd;
 412         unsigned long r;
 413
 414         if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
 415                 return -EINVAL;
 416
 417         /* Only post divider m available with no fractional divider? */
 418         if (!synth->freq) {
 419                 unsigned long frac_rate;
 420                 u32 synth_post_div_m;
 421
 422                 frac_rate = ti_fapll_synth_get_frac_rate(hw, *parent_rate);
 423                 synth_post_div_m = DIV_ROUND_UP(frac_rate, rate);
 424                 r = DIV_ROUND_UP(frac_rate, synth_post_div_m);
 425                 goto out;
 426         }
 427
 428         r = *parent_rate * SYNTH_PHASE_K;
 429         if (rate > r)
 430                 goto out;
 431
 432         r = DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M);
 433         if (rate < r)
 434                 goto out;
 435
 436         r = rate;
 437 out:
 438         return r;
 439 }
 440
 441 static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate,
 442                                    unsigned long parent_rate)
 443 {
 444         struct fapll_synth *synth = to_synth(hw);
 445         struct fapll_data *fd = synth->fd;
 446         unsigned long frac_rate, post_rate = 0;
 447         u32 post_div_m = 0, v;
 448
 449         if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
 450                 return -EINVAL;
 451
 452         /* Produce the rate with just post divider M? */
 453         frac_rate = ti_fapll_synth_get_frac_rate(hw, parent_rate);
 454         if (frac_rate < rate) {
 455                 if (!synth->freq)
 456                         return -EINVAL;
 457         } else {
 458                 post_div_m = DIV_ROUND_UP(frac_rate, rate);
 459                 if (post_div_m && (post_div_m <= SYNTH_MAX_DIV_M))
 460                         post_rate = DIV_ROUND_UP(frac_rate, post_div_m);
 461                 if (!synth->freq && !post_rate)
 462                         return -EINVAL;
 463         }
 464
 465         /* Need to recalculate the fractional divider? */
 466         if ((post_rate != rate) && synth->freq)
 467                 post_div_m = ti_fapll_synth_set_frac_rate(synth,
 468                                                           rate,
 469                                                           parent_rate);
 470
 471         v = readl_relaxed(synth->div);
 472         v &= ~SYNTH_MAX_DIV_M;
 473         v |= post_div_m;
 474         v |= SYNTH_LDMDIV1;
 475         writel_relaxed(v, synth->div);
 476
 477         return 0;
 478 }
 479
 480 static struct clk_ops ti_fapll_synt_ops = {
 481         .enable = ti_fapll_synth_enable,
 482         .disable = ti_fapll_synth_disable,
 483         .is_enabled = ti_fapll_synth_is_enabled,
 484         .recalc_rate = ti_fapll_synth_recalc_rate,
 485         .round_rate = ti_fapll_synth_round_rate,
 486         .set_rate = ti_fapll_synth_set_rate,
 487 };
 488
 489 static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd,
 490                                                 void __iomem *freq,
 491                                                 void __iomem *div,
 492                                                 int index,
 493                                                 const char *name,
 494                                                 const char *parent,
 495                                                 struct clk *pll_clk)
 496 {
 497         struct clk_init_data *init;
 498         struct fapll_synth *synth;
 499
 500         init = kzalloc(sizeof(*init), GFP_KERNEL);
 501         if (!init)
 502                 return ERR_PTR(-ENOMEM);
 503
 504         init->ops = &ti_fapll_synt_ops;
 505         init->name = name;
 506         init->parent_names = &parent;
 507         init->num_parents = 1;
 508
 509         synth = kzalloc(sizeof(*synth), GFP_KERNEL);
 510         if (!synth)
 511                 goto free;
 512
 513         synth->fd = fd;
 514         synth->index = index;
 515         synth->freq = freq;
 516         synth->div = div;
 517         synth->name = name;
 518         synth->hw.init = init;
 519         synth->clk_pll = pll_clk;
 520
 521         return clk_register(NULL, &synth->hw);
 522
 523 free:
 524         kfree(synth);
 525         kfree(init);
 526
 527         return ERR_PTR(-ENOMEM);
 528 }
 529
 530 static void __init ti_fapll_setup(struct device_node *node)
 531 {
 532         struct fapll_data *fd;
 533         struct clk_init_data *init = NULL;
 534         const char *parent_name[2];
 535         struct clk *pll_clk;
 536         int i;
 537
 538         fd = kzalloc(sizeof(*fd), GFP_KERNEL);
 539         if (!fd)
 540                 return;
 541
 542         fd->outputs.clks = kzalloc(sizeof(struct clk *) *
 543                                    MAX_FAPLL_OUTPUTS + 1,
 544                                    GFP_KERNEL);
 545         if (!fd->outputs.clks)
 546                 goto free;
 547
 548         init = kzalloc(sizeof(*init), GFP_KERNEL);
 549         if (!init)
 550                 goto free;
 551
 552         init->ops = &ti_fapll_ops;
 553         init->name = node->name;
 554
 555         init->num_parents = of_clk_get_parent_count(node);
 556         if (init->num_parents != 2) {
 557                 pr_err("%s must have two parents\n", node->name);
 558                 goto free;
 559         }
 560
 561         parent_name[0] = of_clk_get_parent_name(node, 0);
 562         parent_name[1] = of_clk_get_parent_name(node, 1);
 563         init->parent_names = parent_name;
 564
 565         fd->clk_ref = of_clk_get(node, 0);
 566         if (IS_ERR(fd->clk_ref)) {
 567                 pr_err("%s could not get clk_ref\n", node->name);
 568                 goto free;
 569         }
 570
 571         fd->clk_bypass = of_clk_get(node, 1);
 572         if (IS_ERR(fd->clk_bypass)) {
 573                 pr_err("%s could not get clk_bypass\n", node->name);
 574                 goto free;
 575         }
 576
 577         fd->base = of_iomap(node, 0);
 578         if (!fd->base) {
 579                 pr_err("%s could not get IO base\n", node->name);
 580                 goto free;
 581         }
 582
 583         if (fapll_is_ddr_pll(fd->base))
 584                 fd->bypass_bit_inverted = true;
 585
 586         fd->name = node->name;
 587         fd->hw.init = init;
 588
 589         /* Register the parent PLL */
 590         pll_clk = clk_register(NULL, &fd->hw);
 591         if (IS_ERR(pll_clk))
 592                 goto unmap;
 593
 594         fd->outputs.clks[0] = pll_clk;
 595         fd->outputs.clk_num++;
 596
 597         /*
 598          * Set up the child synthesizers starting at index 1 as the
 599          * PLL output is at index 0. We need to check the clock-indices
 600          * for numbering in case there are holes in the synth mapping,
 601          * and then probe the synth register to see if it has a FREQ
 602          * register available.
 603          */
 604         for (i = 0; i < MAX_FAPLL_OUTPUTS; i++) {
 605                 const char *output_name;
 606                 void __iomem *freq, *div;
 607                 struct clk *synth_clk;
 608                 int output_instance;
 609                 u32 v;
 610
 611                 if (of_property_read_string_index(node, "clock-output-names",
 612                                                   i, &output_name))
 613                         continue;
 614
 615                 if (of_property_read_u32_index(node, "clock-indices", i,
 616                                                &output_instance))
 617                         output_instance = i;
 618
 619                 freq = fd->base + (output_instance * 8);
 620                 div = freq + 4;
 621
 622                 /* Check for hardwired audio_pll_clk1 */
 623                 if (is_audio_pll_clk1(freq)) {
 624                         freq = NULL;
 625                         div = NULL;
 626                 } else {
 627                         /* Does the synthesizer have a FREQ register? */
 628                         v = readl_relaxed(freq);
 629                         if (!v)
 630                                 freq = NULL;
 631                 }
 632                 synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance,
 633                                                  output_name, node->name,
 634                                                  pll_clk);
 635                 if (IS_ERR(synth_clk))
 636                         continue;
 637
 638                 fd->outputs.clks[output_instance] = synth_clk;
 639                 fd->outputs.clk_num++;
 640
 641                 clk_register_clkdev(synth_clk, output_name, NULL);
 642         }
 643
 644         /* Register the child synthesizers as the FAPLL outputs */
 645         of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs);
 646         /* Add clock alias for the outputs */
 647
 648         kfree(init);
 649
 650         return;
 651
 652 unmap:
 653         iounmap(fd->base);
 654 free:
 655         if (fd->clk_bypass)
 656                 clk_put(fd->clk_bypass);
 657         if (fd->clk_ref)
 658                 clk_put(fd->clk_ref);
 659         kfree(fd->outputs.clks);
 660         kfree(fd);
 661         kfree(init);
 662 }
 663
 664 CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup);