drivers/clk/ti/dpll.c

   1 /*
   2  * OMAP DPLL clock support
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * Tero Kristo <t-kristo@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/clk-provider.h>
  20 #include <linux/slab.h>
  21 #include <linux/err.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/clk/ti.h>
  25 #include "clock.h"
  26
  27 #undef pr_fmt
  28 #define pr_fmt(fmt) "%s: " fmt, __func__
  29
  30 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
  31         defined(CONFIG_SOC_DRA7XX)
  32 static const struct clk_ops dpll_m4xen_ck_ops = {
  33         .enable         = &omap3_noncore_dpll_enable,
  34         .disable        = &omap3_noncore_dpll_disable,
  35         .recalc_rate    = &omap4_dpll_regm4xen_recalc,
  36         .round_rate     = &omap4_dpll_regm4xen_round_rate,
  37         .set_rate       = &omap3_noncore_dpll_set_rate,
  38         .set_parent     = &omap3_noncore_dpll_set_parent,
  39         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
  40         .determine_rate = &omap4_dpll_regm4xen_determine_rate,
  41         .get_parent     = &omap2_init_dpll_parent,
  42 };
  43 #else
  44 static const struct clk_ops dpll_m4xen_ck_ops = {};
  45 #endif
  46
  47 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
  48         defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
  49         defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
  50 static const struct clk_ops dpll_core_ck_ops = {
  51         .recalc_rate    = &omap3_dpll_recalc,
  52         .get_parent     = &omap2_init_dpll_parent,
  53 };
  54
  55 static const struct clk_ops dpll_ck_ops = {
  56         .enable         = &omap3_noncore_dpll_enable,
  57         .disable        = &omap3_noncore_dpll_disable,
  58         .recalc_rate    = &omap3_dpll_recalc,
  59         .round_rate     = &omap2_dpll_round_rate,
  60         .set_rate       = &omap3_noncore_dpll_set_rate,
  61         .set_parent     = &omap3_noncore_dpll_set_parent,
  62         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
  63         .determine_rate = &omap3_noncore_dpll_determine_rate,
  64         .get_parent     = &omap2_init_dpll_parent,
  65 };
  66
  67 static const struct clk_ops dpll_no_gate_ck_ops = {
  68         .recalc_rate    = &omap3_dpll_recalc,
  69         .get_parent     = &omap2_init_dpll_parent,
  70         .round_rate     = &omap2_dpll_round_rate,
  71         .set_rate       = &omap3_noncore_dpll_set_rate,
  72         .set_parent     = &omap3_noncore_dpll_set_parent,
  73         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
  74         .determine_rate = &omap3_noncore_dpll_determine_rate,
  75 };
  76 #else
  77 static const struct clk_ops dpll_core_ck_ops = {};
  78 static const struct clk_ops dpll_ck_ops = {};
  79 static const struct clk_ops dpll_no_gate_ck_ops = {};
  80 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
  81 #endif
  82
  83 #ifdef CONFIG_ARCH_OMAP2
  84 static const struct clk_ops omap2_dpll_core_ck_ops = {
  85         .get_parent     = &omap2_init_dpll_parent,
  86         .recalc_rate    = &omap2_dpllcore_recalc,
  87         .round_rate     = &omap2_dpll_round_rate,
  88         .set_rate       = &omap2_reprogram_dpllcore,
  89 };
  90 #else
  91 static const struct clk_ops omap2_dpll_core_ck_ops = {};
  92 #endif
  93
  94 #ifdef CONFIG_ARCH_OMAP3
  95 static const struct clk_ops omap3_dpll_core_ck_ops = {
  96         .get_parent     = &omap2_init_dpll_parent,
  97         .recalc_rate    = &omap3_dpll_recalc,
  98         .round_rate     = &omap2_dpll_round_rate,
  99 };
 100 #else
 101 static const struct clk_ops omap3_dpll_core_ck_ops = {};
 102 #endif
 103
 104 #ifdef CONFIG_ARCH_OMAP3
 105 static const struct clk_ops omap3_dpll_ck_ops = {
 106         .enable         = &omap3_noncore_dpll_enable,
 107         .disable        = &omap3_noncore_dpll_disable,
 108         .get_parent     = &omap2_init_dpll_parent,
 109         .recalc_rate    = &omap3_dpll_recalc,
 110         .set_rate       = &omap3_noncore_dpll_set_rate,
 111         .set_parent     = &omap3_noncore_dpll_set_parent,
 112         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
 113         .determine_rate = &omap3_noncore_dpll_determine_rate,
 114         .round_rate     = &omap2_dpll_round_rate,
 115 };
 116
 117 static const struct clk_ops omap3_dpll5_ck_ops = {
 118         .enable         = &omap3_noncore_dpll_enable,
 119         .disable        = &omap3_noncore_dpll_disable,
 120         .get_parent     = &omap2_init_dpll_parent,
 121         .recalc_rate    = &omap3_dpll_recalc,
 122         .set_rate       = &omap3_dpll5_set_rate,
 123         .set_parent     = &omap3_noncore_dpll_set_parent,
 124         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
 125         .determine_rate = &omap3_noncore_dpll_determine_rate,
 126         .round_rate     = &omap2_dpll_round_rate,
 127 };
 128
 129 static const struct clk_ops omap3_dpll_per_ck_ops = {
 130         .enable         = &omap3_noncore_dpll_enable,
 131         .disable        = &omap3_noncore_dpll_disable,
 132         .get_parent     = &omap2_init_dpll_parent,
 133         .recalc_rate    = &omap3_dpll_recalc,
 134         .set_rate       = &omap3_dpll4_set_rate,
 135         .set_parent     = &omap3_noncore_dpll_set_parent,
 136         .set_rate_and_parent    = &omap3_dpll4_set_rate_and_parent,
 137         .determine_rate = &omap3_noncore_dpll_determine_rate,
 138         .round_rate     = &omap2_dpll_round_rate,
 139 };
 140 #endif
 141
 142 static const struct clk_ops dpll_x2_ck_ops = {
 143         .recalc_rate    = &omap3_clkoutx2_recalc,
 144 };
 145
 146 /**
 147  * _register_dpll - low level registration of a DPLL clock
 148  * @hw: hardware clock definition for the clock
 149  * @node: device node for the clock
 150  *
 151  * Finalizes DPLL registration process. In case a failure (clk-ref or
 152  * clk-bypass is missing), the clock is added to retry list and
 153  * the initialization is retried on later stage.
 154  */
 155 static void __init _register_dpll(struct clk_hw *hw,
 156                                   struct device_node *node)
 157 {
 158         struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
 159         struct dpll_data *dd = clk_hw->dpll_data;
 160         struct clk *clk;
 161
 162         clk = of_clk_get(node, 0);
 163         if (IS_ERR(clk)) {
 164                 pr_debug("clk-ref missing for %s, retry later\n",
 165                          node->name);
 166                 if (!ti_clk_retry_init(node, hw, _register_dpll))
 167                         return;
 168
 169                 goto cleanup;
 170         }
 171
 172         dd->clk_ref = __clk_get_hw(clk);
 173
 174         clk = of_clk_get(node, 1);
 175
 176         if (IS_ERR(clk)) {
 177                 pr_debug("clk-bypass missing for %s, retry later\n",
 178                          node->name);
 179                 if (!ti_clk_retry_init(node, hw, _register_dpll))
 180                         return;
 181
 182                 goto cleanup;
 183         }
 184
 185         dd->clk_bypass = __clk_get_hw(clk);
 186
 187         /* register the clock */
 188         clk = ti_clk_register(NULL, &clk_hw->hw, node->name);
 189
 190         if (!IS_ERR(clk)) {
 191                 omap2_init_clk_hw_omap_clocks(&clk_hw->hw);
 192                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 193                 kfree(clk_hw->hw.init->parent_names);
 194                 kfree(clk_hw->hw.init);
 195                 return;
 196         }
 197
 198 cleanup:
 199         kfree(clk_hw->dpll_data);
 200         kfree(clk_hw->hw.init->parent_names);
 201         kfree(clk_hw->hw.init);
 202         kfree(clk_hw);
 203 }
 204
 205 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
 206 void _get_reg(u8 module, u16 offset, struct clk_omap_reg *reg)
 207 {
 208         reg->index = module;
 209         reg->offset = offset;
 210 }
 211
 212 struct clk *ti_clk_register_dpll(struct ti_clk *setup)
 213 {
 214         struct clk_hw_omap *clk_hw;
 215         struct clk_init_data init = { NULL };
 216         struct dpll_data *dd;
 217         struct clk *clk;
 218         struct ti_clk_dpll *dpll;
 219         const struct clk_ops *ops = &omap3_dpll_ck_ops;
 220         struct clk *clk_ref;
 221         struct clk *clk_bypass;
 222
 223         dpll = setup->data;
 224
 225         if (dpll->num_parents < 2)
 226                 return ERR_PTR(-EINVAL);
 227
 228         clk_ref = clk_get_sys(NULL, dpll->parents[0]);
 229         clk_bypass = clk_get_sys(NULL, dpll->parents[1]);
 230
 231         if (IS_ERR_OR_NULL(clk_ref) || IS_ERR_OR_NULL(clk_bypass))
 232                 return ERR_PTR(-EAGAIN);
 233
 234         dd = kzalloc(sizeof(*dd), GFP_KERNEL);
 235         clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
 236         if (!dd || !clk_hw) {
 237                 clk = ERR_PTR(-ENOMEM);
 238                 goto cleanup;
 239         }
 240
 241         clk_hw->dpll_data = dd;
 242         clk_hw->ops = &clkhwops_omap3_dpll;
 243         clk_hw->hw.init = &init;
 244
 245         init.name = setup->name;
 246         init.ops = ops;
 247
 248         init.num_parents = dpll->num_parents;
 249         init.parent_names = dpll->parents;
 250
 251         _get_reg(dpll->module, dpll->control_reg, &dd->control_reg);
 252         _get_reg(dpll->module, dpll->idlest_reg, &dd->idlest_reg);
 253         _get_reg(dpll->module, dpll->mult_div1_reg, &dd->mult_div1_reg);
 254         _get_reg(dpll->module, dpll->autoidle_reg, &dd->autoidle_reg);
 255
 256         dd->modes = dpll->modes;
 257         dd->div1_mask = dpll->div1_mask;
 258         dd->idlest_mask = dpll->idlest_mask;
 259         dd->mult_mask = dpll->mult_mask;
 260         dd->autoidle_mask = dpll->autoidle_mask;
 261         dd->enable_mask = dpll->enable_mask;
 262         dd->sddiv_mask = dpll->sddiv_mask;
 263         dd->dco_mask = dpll->dco_mask;
 264         dd->max_divider = dpll->max_divider;
 265         dd->min_divider = dpll->min_divider;
 266         dd->max_multiplier = dpll->max_multiplier;
 267         dd->auto_recal_bit = dpll->auto_recal_bit;
 268         dd->recal_en_bit = dpll->recal_en_bit;
 269         dd->recal_st_bit = dpll->recal_st_bit;
 270
 271         dd->clk_ref = __clk_get_hw(clk_ref);
 272         dd->clk_bypass = __clk_get_hw(clk_bypass);
 273
 274         if (dpll->flags & CLKF_CORE)
 275                 ops = &omap3_dpll_core_ck_ops;
 276
 277         if (dpll->flags & CLKF_PER)
 278                 ops = &omap3_dpll_per_ck_ops;
 279
 280         if (dpll->flags & CLKF_J_TYPE)
 281                 dd->flags |= DPLL_J_TYPE;
 282
 283         clk = ti_clk_register(NULL, &clk_hw->hw, setup->name);
 284
 285         if (!IS_ERR(clk))
 286                 return clk;
 287
 288 cleanup:
 289         kfree(dd);
 290         kfree(clk_hw);
 291         return clk;
 292 }
 293 #endif
 294
 295 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
 296         defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
 297         defined(CONFIG_SOC_AM43XX)
 298 /**
 299  * _register_dpll_x2 - Registers a DPLLx2 clock
 300  * @node: device node for this clock
 301  * @ops: clk_ops for this clock
 302  * @hw_ops: clk_hw_ops for this clock
 303  *
 304  * Initializes a DPLL x 2 clock from device tree data.
 305  */
 306 static void _register_dpll_x2(struct device_node *node,
 307                               const struct clk_ops *ops,
 308                               const struct clk_hw_omap_ops *hw_ops)
 309 {
 310         struct clk *clk;
 311         struct clk_init_data init = { NULL };
 312         struct clk_hw_omap *clk_hw;
 313         const char *name = node->name;
 314         const char *parent_name;
 315
 316         parent_name = of_clk_get_parent_name(node, 0);
 317         if (!parent_name) {
 318                 pr_err("%s must have parent\n", node->name);
 319                 return;
 320         }
 321
 322         clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
 323         if (!clk_hw)
 324                 return;
 325
 326         clk_hw->ops = hw_ops;
 327         clk_hw->hw.init = &init;
 328
 329         init.name = name;
 330         init.ops = ops;
 331         init.parent_names = &parent_name;
 332         init.num_parents = 1;
 333
 334 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
 335         defined(CONFIG_SOC_DRA7XX)
 336         if (hw_ops == &clkhwops_omap4_dpllmx) {
 337                 int ret;
 338
 339                 /* Check if register defined, if not, drop hw-ops */
 340                 ret = of_property_count_elems_of_size(node, "reg", 1);
 341                 if (ret <= 0) {
 342                         clk_hw->ops = NULL;
 343                 } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) {
 344                         kfree(clk_hw);
 345                         return;
 346                 }
 347         }
 348 #endif
 349
 350         /* register the clock */
 351         clk = ti_clk_register(NULL, &clk_hw->hw, name);
 352
 353         if (IS_ERR(clk)) {
 354                 kfree(clk_hw);
 355         } else {
 356                 omap2_init_clk_hw_omap_clocks(&clk_hw->hw);
 357                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 358         }
 359 }
 360 #endif
 361
 362 /**
 363  * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
 364  * @node: device node containing the DPLL info
 365  * @ops: ops for the DPLL
 366  * @ddt: DPLL data template to use
 367  *
 368  * Initializes a DPLL clock from device tree data.
 369  */
 370 static void __init of_ti_dpll_setup(struct device_node *node,
 371                                     const struct clk_ops *ops,
 372                                     const struct dpll_data *ddt)
 373 {
 374         struct clk_hw_omap *clk_hw = NULL;
 375         struct clk_init_data *init = NULL;
 376         const char **parent_names = NULL;
 377         struct dpll_data *dd = NULL;
 378         u8 dpll_mode = 0;
 379
 380         dd = kzalloc(sizeof(*dd), GFP_KERNEL);
 381         clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
 382         init = kzalloc(sizeof(*init), GFP_KERNEL);
 383         if (!dd || !clk_hw || !init)
 384                 goto cleanup;
 385
 386         memcpy(dd, ddt, sizeof(*dd));
 387
 388         clk_hw->dpll_data = dd;
 389         clk_hw->ops = &clkhwops_omap3_dpll;
 390         clk_hw->hw.init = init;
 391
 392         init->name = node->name;
 393         init->ops = ops;
 394
 395         init->num_parents = of_clk_get_parent_count(node);
 396         if (!init->num_parents) {
 397                 pr_err("%s must have parent(s)\n", node->name);
 398                 goto cleanup;
 399         }
 400
 401         parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
 402         if (!parent_names)
 403                 goto cleanup;
 404
 405         of_clk_parent_fill(node, parent_names, init->num_parents);
 406
 407         init->parent_names = parent_names;
 408
 409         if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))
 410                 goto cleanup;
 411
 412         /*
 413          * Special case for OMAP2 DPLL, register order is different due to
 414          * missing idlest_reg, also clkhwops is different. Detected from
 415          * missing idlest_mask.
 416          */
 417         if (!dd->idlest_mask) {
 418                 if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg))
 419                         goto cleanup;
 420 #ifdef CONFIG_ARCH_OMAP2
 421                 clk_hw->ops = &clkhwops_omap2xxx_dpll;
 422                 omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
 423 #endif
 424         } else {
 425                 if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg))
 426                         goto cleanup;
 427
 428                 if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg))
 429                         goto cleanup;
 430         }
 431
 432         if (dd->autoidle_mask) {
 433                 if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg))
 434                         goto cleanup;
 435         }
 436
 437         if (of_property_read_bool(node, "ti,low-power-stop"))
 438                 dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
 439
 440         if (of_property_read_bool(node, "ti,low-power-bypass"))
 441                 dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
 442
 443         if (of_property_read_bool(node, "ti,lock"))
 444                 dpll_mode |= 1 << DPLL_LOCKED;
 445
 446         if (dpll_mode)
 447                 dd->modes = dpll_mode;
 448
 449         _register_dpll(&clk_hw->hw, node);
 450         return;
 451
 452 cleanup:
 453         kfree(dd);
 454         kfree(parent_names);
 455         kfree(init);
 456         kfree(clk_hw);
 457 }
 458
 459 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
 460         defined(CONFIG_SOC_DRA7XX)
 461 static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
 462 {
 463         _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
 464 }
 465 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
 466                of_ti_omap4_dpll_x2_setup);
 467 #endif
 468
 469 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 470 static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
 471 {
 472         _register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
 473 }
 474 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
 475                of_ti_am3_dpll_x2_setup);
 476 #endif
 477
 478 #ifdef CONFIG_ARCH_OMAP3
 479 static void __init of_ti_omap3_dpll_setup(struct device_node *node)
 480 {
 481         const struct dpll_data dd = {
 482                 .idlest_mask = 0x1,
 483                 .enable_mask = 0x7,
 484                 .autoidle_mask = 0x7,
 485                 .mult_mask = 0x7ff << 8,
 486                 .div1_mask = 0x7f,
 487                 .max_multiplier = 2047,
 488                 .max_divider = 128,
 489                 .min_divider = 1,
 490                 .freqsel_mask = 0xf0,
 491                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 492         };
 493
 494         if ((of_machine_is_compatible("ti,omap3630") ||
 495              of_machine_is_compatible("ti,omap36xx")) &&
 496             !strcmp(node->name, "dpll5_ck"))
 497                 of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd);
 498         else
 499                 of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
 500 }
 501 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
 502                of_ti_omap3_dpll_setup);
 503
 504 static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
 505 {
 506         const struct dpll_data dd = {
 507                 .idlest_mask = 0x1,
 508                 .enable_mask = 0x7,
 509                 .autoidle_mask = 0x7,
 510                 .mult_mask = 0x7ff << 16,
 511                 .div1_mask = 0x7f << 8,
 512                 .max_multiplier = 2047,
 513                 .max_divider = 128,
 514                 .min_divider = 1,
 515                 .freqsel_mask = 0xf0,
 516         };
 517
 518         of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
 519 }
 520 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
 521                of_ti_omap3_core_dpll_setup);
 522
 523 static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
 524 {
 525         const struct dpll_data dd = {
 526                 .idlest_mask = 0x1 << 1,
 527                 .enable_mask = 0x7 << 16,
 528                 .autoidle_mask = 0x7 << 3,
 529                 .mult_mask = 0x7ff << 8,
 530                 .div1_mask = 0x7f,
 531                 .max_multiplier = 2047,
 532                 .max_divider = 128,
 533                 .min_divider = 1,
 534                 .freqsel_mask = 0xf00000,
 535                 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 536         };
 537
 538         of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
 539 }
 540 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
 541                of_ti_omap3_per_dpll_setup);
 542
 543 static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
 544 {
 545         const struct dpll_data dd = {
 546                 .idlest_mask = 0x1 << 1,
 547                 .enable_mask = 0x7 << 16,
 548                 .autoidle_mask = 0x7 << 3,
 549                 .mult_mask = 0xfff << 8,
 550                 .div1_mask = 0x7f,
 551                 .max_multiplier = 4095,
 552                 .max_divider = 128,
 553                 .min_divider = 1,
 554                 .sddiv_mask = 0xff << 24,
 555                 .dco_mask = 0xe << 20,
 556                 .flags = DPLL_J_TYPE,
 557                 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 558         };
 559
 560         of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
 561 }
 562 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
 563                of_ti_omap3_per_jtype_dpll_setup);
 564 #endif
 565
 566 static void __init of_ti_omap4_dpll_setup(struct device_node *node)
 567 {
 568         const struct dpll_data dd = {
 569                 .idlest_mask = 0x1,
 570                 .enable_mask = 0x7,
 571                 .autoidle_mask = 0x7,
 572                 .mult_mask = 0x7ff << 8,
 573                 .div1_mask = 0x7f,
 574                 .max_multiplier = 2047,
 575                 .max_divider = 128,
 576                 .min_divider = 1,
 577                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 578         };
 579
 580         of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
 581 }
 582 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
 583                of_ti_omap4_dpll_setup);
 584
 585 static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
 586 {
 587         const struct dpll_data dd = {
 588                 .idlest_mask = 0x1,
 589                 .enable_mask = 0x7,
 590                 .autoidle_mask = 0x7,
 591                 .mult_mask = 0x7ff << 8,
 592                 .div1_mask = 0x7f,
 593                 .max_multiplier = 2047,
 594                 .max_divider = 128,
 595                 .dcc_mask = BIT(22),
 596                 .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
 597                 .min_divider = 1,
 598                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 599         };
 600
 601         of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
 602 }
 603 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
 604                of_ti_omap5_mpu_dpll_setup);
 605
 606 static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
 607 {
 608         const struct dpll_data dd = {
 609                 .idlest_mask = 0x1,
 610                 .enable_mask = 0x7,
 611                 .autoidle_mask = 0x7,
 612                 .mult_mask = 0x7ff << 8,
 613                 .div1_mask = 0x7f,
 614                 .max_multiplier = 2047,
 615                 .max_divider = 128,
 616                 .min_divider = 1,
 617                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 618         };
 619
 620         of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
 621 }
 622 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
 623                of_ti_omap4_core_dpll_setup);
 624
 625 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
 626         defined(CONFIG_SOC_DRA7XX)
 627 static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
 628 {
 629         const struct dpll_data dd = {
 630                 .idlest_mask = 0x1,
 631                 .enable_mask = 0x7,
 632                 .autoidle_mask = 0x7,
 633                 .mult_mask = 0x7ff << 8,
 634                 .div1_mask = 0x7f,
 635                 .max_multiplier = 2047,
 636                 .max_divider = 128,
 637                 .min_divider = 1,
 638                 .m4xen_mask = 0x800,
 639                 .lpmode_mask = 1 << 10,
 640                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 641         };
 642
 643         of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
 644 }
 645 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
 646                of_ti_omap4_m4xen_dpll_setup);
 647
 648 static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
 649 {
 650         const struct dpll_data dd = {
 651                 .idlest_mask = 0x1,
 652                 .enable_mask = 0x7,
 653                 .autoidle_mask = 0x7,
 654                 .mult_mask = 0xfff << 8,
 655                 .div1_mask = 0xff,
 656                 .max_multiplier = 4095,
 657                 .max_divider = 256,
 658                 .min_divider = 1,
 659                 .sddiv_mask = 0xff << 24,
 660                 .flags = DPLL_J_TYPE,
 661                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 662         };
 663
 664         of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
 665 }
 666 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
 667                of_ti_omap4_jtype_dpll_setup);
 668 #endif
 669
 670 static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
 671 {
 672         const struct dpll_data dd = {
 673                 .idlest_mask = 0x1,
 674                 .enable_mask = 0x7,
 675                 .mult_mask = 0x7ff << 8,
 676                 .div1_mask = 0x7f,
 677                 .max_multiplier = 2047,
 678                 .max_divider = 128,
 679                 .min_divider = 1,
 680                 .max_rate = 1000000000,
 681                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 682         };
 683
 684         of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
 685 }
 686 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
 687                of_ti_am3_no_gate_dpll_setup);
 688
 689 static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
 690 {
 691         const struct dpll_data dd = {
 692                 .idlest_mask = 0x1,
 693                 .enable_mask = 0x7,
 694                 .mult_mask = 0x7ff << 8,
 695                 .div1_mask = 0x7f,
 696                 .max_multiplier = 4095,
 697                 .max_divider = 256,
 698                 .min_divider = 2,
 699                 .flags = DPLL_J_TYPE,
 700                 .max_rate = 2000000000,
 701                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 702         };
 703
 704         of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
 705 }
 706 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
 707                of_ti_am3_jtype_dpll_setup);
 708
 709 static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
 710 {
 711         const struct dpll_data dd = {
 712                 .idlest_mask = 0x1,
 713                 .enable_mask = 0x7,
 714                 .mult_mask = 0x7ff << 8,
 715                 .div1_mask = 0x7f,
 716                 .max_multiplier = 2047,
 717                 .max_divider = 128,
 718                 .min_divider = 1,
 719                 .max_rate = 2000000000,
 720                 .flags = DPLL_J_TYPE,
 721                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 722         };
 723
 724         of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
 725 }
 726 CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
 727                "ti,am3-dpll-no-gate-j-type-clock",
 728                of_ti_am3_no_gate_jtype_dpll_setup);
 729
 730 static void __init of_ti_am3_dpll_setup(struct device_node *node)
 731 {
 732         const struct dpll_data dd = {
 733                 .idlest_mask = 0x1,
 734                 .enable_mask = 0x7,
 735                 .mult_mask = 0x7ff << 8,
 736                 .div1_mask = 0x7f,
 737                 .max_multiplier = 2047,
 738                 .max_divider = 128,
 739                 .min_divider = 1,
 740                 .max_rate = 1000000000,
 741                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 742         };
 743
 744         of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
 745 }
 746 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
 747
 748 static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
 749 {
 750         const struct dpll_data dd = {
 751                 .idlest_mask = 0x1,
 752                 .enable_mask = 0x7,
 753                 .mult_mask = 0x7ff << 8,
 754                 .div1_mask = 0x7f,
 755                 .max_multiplier = 2047,
 756                 .max_divider = 128,
 757                 .min_divider = 1,
 758                 .max_rate = 1000000000,
 759                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 760         };
 761
 762         of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
 763 }
 764 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
 765                of_ti_am3_core_dpll_setup);
 766
 767 static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
 768 {
 769         const struct dpll_data dd = {
 770                 .enable_mask = 0x3,
 771                 .mult_mask = 0x3ff << 12,
 772                 .div1_mask = 0xf << 8,
 773                 .max_divider = 16,
 774                 .min_divider = 1,
 775         };
 776
 777         of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
 778 }
 779 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
 780                of_ti_omap2_core_dpll_setup);