drivers/clk/ti/clk-3xxx.c

   1 /*
   2  * OMAP3 Clock init
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc
   5  *     Tero Kristo (t-kristo@ti.com)
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/list.h>
  19 #include <linux/clk-provider.h>
  20 #include <linux/clk/ti.h>
  21
  22
  23 static struct ti_dt_clk omap3xxx_clks[] = {
  24         DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
  25         DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
  26         DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
  27         DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
  28         DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
  29         DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
  30         DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"),
  31         DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"),
  32         DT_CLK("twl", "fck", "osc_sys_ck"),
  33         DT_CLK(NULL, "sys_ck", "sys_ck"),
  34         DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
  35         DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
  36         DT_CLK(NULL, "sys_altclk", "sys_altclk"),
  37         DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
  38         DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
  39         DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
  40         DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
  41         DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"),
  42         DT_CLK(NULL, "dpll3_ck", "dpll3_ck"),
  43         DT_CLK(NULL, "core_ck", "core_ck"),
  44         DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"),
  45         DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"),
  46         DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"),
  47         DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"),
  48         DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"),
  49         DT_CLK(NULL, "dpll4_ck", "dpll4_ck"),
  50         DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"),
  51         DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"),
  52         DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"),
  53         DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"),
  54         DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"),
  55         DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"),
  56         DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"),
  57         DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"),
  58         DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"),
  59         DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"),
  60         DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"),
  61         DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"),
  62         DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"),
  63         DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"),
  64         DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"),
  65         DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"),
  66         DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
  67         DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"),
  68         DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
  69         DT_CLK(NULL, "corex2_fck", "corex2_fck"),
  70         DT_CLK(NULL, "dpll1_fck", "dpll1_fck"),
  71         DT_CLK(NULL, "mpu_ck", "mpu_ck"),
  72         DT_CLK(NULL, "arm_fck", "arm_fck"),
  73         DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"),
  74         DT_CLK(NULL, "l3_ick", "l3_ick"),
  75         DT_CLK(NULL, "l4_ick", "l4_ick"),
  76         DT_CLK(NULL, "rm_ick", "rm_ick"),
  77         DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
  78         DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
  79         DT_CLK(NULL, "core_96m_fck", "core_96m_fck"),
  80         DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
  81         DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
  82         DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
  83         DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
  84         DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
  85         DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
  86         DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
  87         DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
  88         DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
  89         DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
  90         DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
  91         DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
  92         DT_CLK(NULL, "uart2_fck", "uart2_fck"),
  93         DT_CLK(NULL, "uart1_fck", "uart1_fck"),
  94         DT_CLK(NULL, "core_12m_fck", "core_12m_fck"),
  95         DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
  96         DT_CLK(NULL, "hdq_fck", "hdq_fck"),
  97         DT_CLK(NULL, "core_l3_ick", "core_l3_ick"),
  98         DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
  99         DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
 100         DT_CLK(NULL, "core_l4_ick", "core_l4_ick"),
 101         DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
 102         DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
 103         DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
 104         DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
 105         DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
 106         DT_CLK(NULL, "hdq_ick", "hdq_ick"),
 107         DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"),
 108         DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
 109         DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
 110         DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
 111         DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"),
 112         DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
 113         DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
 114         DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
 115         DT_CLK("omap_i2c.3", "ick", "i2c3_ick"),
 116         DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
 117         DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
 118         DT_CLK(NULL, "i2c3_ick", "i2c3_ick"),
 119         DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
 120         DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
 121         DT_CLK(NULL, "uart2_ick", "uart2_ick"),
 122         DT_CLK(NULL, "uart1_ick", "uart1_ick"),
 123         DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
 124         DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
 125         DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"),
 126         DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"),
 127         DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
 128         DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
 129         DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
 130         DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
 131         DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
 132         DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"),
 133         DT_CLK(NULL, "init_60m_fclk", "dummy_ck"),
 134         DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
 135         DT_CLK(NULL, "aes2_ick", "aes2_ick"),
 136         DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"),
 137         DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"),
 138         DT_CLK(NULL, "sha12_ick", "sha12_ick"),
 139         DT_CLK(NULL, "wdt2_fck", "wdt2_fck"),
 140         DT_CLK("omap_wdt", "ick", "wdt2_ick"),
 141         DT_CLK(NULL, "wdt2_ick", "wdt2_ick"),
 142         DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
 143         DT_CLK(NULL, "gpio1_ick", "gpio1_ick"),
 144         DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"),
 145         DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
 146         DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
 147         DT_CLK(NULL, "per_96m_fck", "per_96m_fck"),
 148         DT_CLK(NULL, "per_48m_fck", "per_48m_fck"),
 149         DT_CLK(NULL, "uart3_fck", "uart3_fck"),
 150         DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
 151         DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
 152         DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
 153         DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
 154         DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
 155         DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
 156         DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
 157         DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
 158         DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"),
 159         DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"),
 160         DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"),
 161         DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"),
 162         DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"),
 163         DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"),
 164         DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
 165         DT_CLK(NULL, "per_l4_ick", "per_l4_ick"),
 166         DT_CLK(NULL, "gpio6_ick", "gpio6_ick"),
 167         DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
 168         DT_CLK(NULL, "gpio4_ick", "gpio4_ick"),
 169         DT_CLK(NULL, "gpio3_ick", "gpio3_ick"),
 170         DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),
 171         DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
 172         DT_CLK(NULL, "uart3_ick", "uart3_ick"),
 173         DT_CLK(NULL, "uart4_ick", "uart4_ick"),
 174         DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
 175         DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
 176         DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
 177         DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
 178         DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
 179         DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
 180         DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
 181         DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
 182         DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"),
 183         DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"),
 184         DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"),
 185         DT_CLK(NULL, "mcbsp4_ick", "mcbsp2_ick"),
 186         DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
 187         DT_CLK(NULL, "mcbsp2_ick", "mcbsp4_ick"),
 188         DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
 189         DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
 190         DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
 191         DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
 192         DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
 193         DT_CLK(NULL, "pclk_fck", "pclk_fck"),
 194         DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"),
 195         DT_CLK(NULL, "atclk_fck", "atclk_fck"),
 196         DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"),
 197         DT_CLK(NULL, "traceclk_fck", "traceclk_fck"),
 198         DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"),
 199         DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
 200         DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
 201         DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
 202         DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
 203         DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"),
 204         { .node_name = NULL },
 205 };
 206
 207 static struct ti_dt_clk omap34xx_omap36xx_clks[] = {
 208         DT_CLK(NULL, "aes1_ick", "aes1_ick"),
 209         DT_CLK("omap_rng", "ick", "rng_ick"),
 210         DT_CLK("omap3-rom-rng", "ick", "rng_ick"),
 211         DT_CLK(NULL, "sha11_ick", "sha11_ick"),
 212         DT_CLK(NULL, "des1_ick", "des1_ick"),
 213         DT_CLK(NULL, "cam_mclk", "cam_mclk"),
 214         DT_CLK(NULL, "cam_ick", "cam_ick"),
 215         DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"),
 216         DT_CLK(NULL, "security_l3_ick", "security_l3_ick"),
 217         DT_CLK(NULL, "pka_ick", "pka_ick"),
 218         DT_CLK(NULL, "icr_ick", "icr_ick"),
 219         DT_CLK("omap-aes", "ick", "aes2_ick"),
 220         DT_CLK("omap-sham", "ick", "sha12_ick"),
 221         DT_CLK(NULL, "des2_ick", "des2_ick"),
 222         DT_CLK(NULL, "mspro_ick", "mspro_ick"),
 223         DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
 224         DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
 225         DT_CLK(NULL, "sr1_fck", "sr1_fck"),
 226         DT_CLK(NULL, "sr2_fck", "sr2_fck"),
 227         DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"),
 228         DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"),
 229         DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"),
 230         DT_CLK(NULL, "dpll2_fck", "dpll2_fck"),
 231         DT_CLK(NULL, "iva2_ck", "iva2_ck"),
 232         DT_CLK(NULL, "modem_fck", "modem_fck"),
 233         DT_CLK(NULL, "sad2d_ick", "sad2d_ick"),
 234         DT_CLK(NULL, "mad2d_ick", "mad2d_ick"),
 235         DT_CLK(NULL, "mspro_fck", "mspro_fck"),
 236         DT_CLK(NULL, "dpll2_ck", "dpll2_ck"),
 237         DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"),
 238         { .node_name = NULL },
 239 };
 240
 241 static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = {
 242         DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),
 243         DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"),
 244         DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"),
 245         DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
 246         DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
 247         DT_CLK(NULL, "usim_fck", "usim_fck"),
 248         DT_CLK(NULL, "usim_ick", "usim_ick"),
 249         { .node_name = NULL },
 250 };
 251
 252 static struct ti_dt_clk omap3430es1_clks[] = {
 253         DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"),
 254         DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"),
 255         DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"),
 256         DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"),
 257         DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"),
 258         DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"),
 259         DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"),
 260         DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
 261         DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
 262         DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"),
 263         DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
 264         DT_CLK(NULL, "fac_ick", "fac_ick"),
 265         DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
 266         DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
 267         DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
 268         DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"),
 269         DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
 270         { .node_name = NULL },
 271 };
 272
 273 static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
 274         DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"),
 275         DT_CLK(NULL, "dpll5_ck", "dpll5_ck"),
 276         DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"),
 277         DT_CLK(NULL, "sgx_fck", "sgx_fck"),
 278         DT_CLK(NULL, "sgx_ick", "sgx_ick"),
 279         DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"),
 280         DT_CLK(NULL, "ts_fck", "ts_fck"),
 281         DT_CLK(NULL, "usbtll_fck", "usbtll_fck"),
 282         DT_CLK(NULL, "usbtll_ick", "usbtll_ick"),
 283         DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"),
 284         DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"),
 285         DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"),
 286         DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
 287         DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"),
 288         DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
 289         DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"),
 290         DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"),
 291         DT_CLK(NULL, "usbhost_ick", "usbhost_ick"),
 292         { .node_name = NULL },
 293 };
 294
 295 static struct ti_dt_clk am35xx_clks[] = {
 296         DT_CLK(NULL, "ipss_ick", "ipss_ick"),
 297         DT_CLK(NULL, "rmii_ck", "rmii_ck"),
 298         DT_CLK(NULL, "pclk_ck", "pclk_ck"),
 299         DT_CLK(NULL, "emac_ick", "emac_ick"),
 300         DT_CLK(NULL, "emac_fck", "emac_fck"),
 301         DT_CLK("davinci_emac.0", NULL, "emac_ick"),
 302         DT_CLK("davinci_mdio.0", NULL, "emac_fck"),
 303         DT_CLK("vpfe-capture", "master", "vpfe_ick"),
 304         DT_CLK("vpfe-capture", "slave", "vpfe_fck"),
 305         DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
 306         DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
 307         DT_CLK(NULL, "hecc_ck", "hecc_ck"),
 308         DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
 309         DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
 310         { .node_name = NULL },
 311 };
 312
 313 static struct ti_dt_clk omap36xx_clks[] = {
 314         DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"),
 315         DT_CLK(NULL, "uart4_fck", "uart4_fck"),
 316         { .node_name = NULL },
 317 };
 318
 319 static const char *enable_init_clks[] = {
 320         "sdrc_ick",
 321         "gpmc_fck",
 322         "omapctrl_ick",
 323 };
 324
 325 enum {
 326         OMAP3_SOC_AM35XX,
 327         OMAP3_SOC_OMAP3430_ES1,
 328         OMAP3_SOC_OMAP3430_ES2_PLUS,
 329         OMAP3_SOC_OMAP3630,
 330         OMAP3_SOC_TI81XX,
 331 };
 332
 333 static int __init omap3xxx_dt_clk_init(int soc_type)
 334 {
 335         if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||
 336             soc_type == OMAP3_SOC_OMAP3430_ES1 ||
 337             soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
 338                 ti_dt_clocks_register(omap3xxx_clks);
 339
 340         if (soc_type == OMAP3_SOC_AM35XX)
 341                 ti_dt_clocks_register(am35xx_clks);
 342
 343         if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX ||
 344             soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
 345                 ti_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks);
 346
 347         if (soc_type == OMAP3_SOC_OMAP3430_ES1)
 348                 ti_dt_clocks_register(omap3430es1_clks);
 349
 350         if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
 351             soc_type == OMAP3_SOC_OMAP3630)
 352                 ti_dt_clocks_register(omap36xx_omap3430es2plus_clks);
 353
 354         if (soc_type == OMAP3_SOC_OMAP3430_ES1 ||
 355             soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
 356             soc_type == OMAP3_SOC_OMAP3630)
 357                 ti_dt_clocks_register(omap34xx_omap36xx_clks);
 358
 359         if (soc_type == OMAP3_SOC_OMAP3630)
 360                 ti_dt_clocks_register(omap36xx_clks);
 361
 362         omap2_clk_disable_autoidle_all();
 363
 364         omap2_clk_enable_init_clocks(enable_init_clks,
 365                                      ARRAY_SIZE(enable_init_clks));
 366
 367         pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
 368                 (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
 369                 (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
 370                 (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
 371                 (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
 372
 373         if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1)
 374                 omap3_clk_lock_dpll5();
 375
 376         return 0;
 377 }
 378
 379 int __init omap3430_dt_clk_init(void)
 380 {
 381         return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS);
 382 }
 383
 384 int __init omap3630_dt_clk_init(void)
 385 {
 386         return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3630);
 387 }
 388
 389 int __init am35xx_dt_clk_init(void)
 390 {
 391         return omap3xxx_dt_clk_init(OMAP3_SOC_AM35XX);
 392 }
 393
 394 int __init ti81xx_dt_clk_init(void)
 395 {
 396         return omap3xxx_dt_clk_init(OMAP3_SOC_TI81XX);
 397 }