drivers/clk/ti/adpll.c

   1 /*
   2  * This program is free software; you can redistribute it and/or
   3  * modify it under the terms of the GNU General Public License as
   4  * published by the Free Software Foundation version 2.
   5  *
   6  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   7  * kind, whether express or implied; without even the implied warranty
   8  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
   9  * GNU General Public License for more details.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/math64.h>
  18 #include <linux/module.h>
  19 #include <linux/of_device.h>
  20 #include <linux/string.h>
  21
  22 #define ADPLL_PLLSS_MMR_LOCK_OFFSET     0x00    /* Managed by MPPULL */
  23 #define ADPLL_PLLSS_MMR_LOCK_ENABLED    0x1f125B64
  24 #define ADPLL_PLLSS_MMR_UNLOCK_MAGIC    0x1eda4c3d
  25
  26 #define ADPLL_PWRCTRL_OFFSET            0x00
  27 #define ADPLL_PWRCTRL_PONIN             5
  28 #define ADPLL_PWRCTRL_PGOODIN           4
  29 #define ADPLL_PWRCTRL_RET               3
  30 #define ADPLL_PWRCTRL_ISORET            2
  31 #define ADPLL_PWRCTRL_ISOSCAN           1
  32 #define ADPLL_PWRCTRL_OFFMODE           0
  33
  34 #define ADPLL_CLKCTRL_OFFSET            0x04
  35 #define ADPLL_CLKCTRL_CLKDCOLDOEN       29
  36 #define ADPLL_CLKCTRL_IDLE              23
  37 #define ADPLL_CLKCTRL_CLKOUTEN          20
  38 #define ADPLL_CLKINPHIFSEL_ADPLL_S      19      /* REVISIT: which bit? */
  39 #define ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ 19
  40 #define ADPLL_CLKCTRL_ULOWCLKEN         18
  41 #define ADPLL_CLKCTRL_CLKDCOLDOPWDNZ    17
  42 #define ADPLL_CLKCTRL_M2PWDNZ           16
  43 #define ADPLL_CLKCTRL_M3PWDNZ_ADPLL_S   15
  44 #define ADPLL_CLKCTRL_LOWCURRSTDBY_ADPLL_S 13
  45 #define ADPLL_CLKCTRL_LPMODE_ADPLL_S    12
  46 #define ADPLL_CLKCTRL_REGM4XEN_ADPLL_S  10
  47 #define ADPLL_CLKCTRL_SELFREQDCO_ADPLL_LJ 10
  48 #define ADPLL_CLKCTRL_TINITZ            0
  49
  50 #define ADPLL_TENABLE_OFFSET            0x08
  51 #define ADPLL_TENABLEDIV_OFFSET         0x8c
  52
  53 #define ADPLL_M2NDIV_OFFSET             0x10
  54 #define ADPLL_M2NDIV_M2                 16
  55 #define ADPLL_M2NDIV_M2_ADPLL_S_WIDTH   5
  56 #define ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH  7
  57
  58 #define ADPLL_MN2DIV_OFFSET             0x14
  59 #define ADPLL_MN2DIV_N2                 16
  60
  61 #define ADPLL_FRACDIV_OFFSET            0x18
  62 #define ADPLL_FRACDIV_REGSD             24
  63 #define ADPLL_FRACDIV_FRACTIONALM       0
  64 #define ADPLL_FRACDIV_FRACTIONALM_MASK  0x3ffff
  65
  66 #define ADPLL_BWCTRL_OFFSET             0x1c
  67 #define ADPLL_BWCTRL_BWCONTROL          1
  68 #define ADPLL_BWCTRL_BW_INCR_DECRZ      0
  69
  70 #define ADPLL_RESERVED_OFFSET           0x20
  71
  72 #define ADPLL_STATUS_OFFSET             0x24
  73 #define ADPLL_STATUS_PONOUT             31
  74 #define ADPLL_STATUS_PGOODOUT           30
  75 #define ADPLL_STATUS_LDOPWDN            29
  76 #define ADPLL_STATUS_RECAL_BSTATUS3     28
  77 #define ADPLL_STATUS_RECAL_OPPIN        27
  78 #define ADPLL_STATUS_PHASELOCK          10
  79 #define ADPLL_STATUS_FREQLOCK           9
  80 #define ADPLL_STATUS_BYPASSACK          8
  81 #define ADPLL_STATUS_LOSSREF            6
  82 #define ADPLL_STATUS_CLKOUTENACK        5
  83 #define ADPLL_STATUS_LOCK2              4
  84 #define ADPLL_STATUS_M2CHANGEACK        3
  85 #define ADPLL_STATUS_HIGHJITTER         1
  86 #define ADPLL_STATUS_BYPASS             0
  87 #define ADPLL_STATUS_PREPARED_MASK      (BIT(ADPLL_STATUS_PHASELOCK) | \
  88                                          BIT(ADPLL_STATUS_FREQLOCK))
  89
  90 #define ADPLL_M3DIV_OFFSET              0x28    /* Only on MPUPLL */
  91 #define ADPLL_M3DIV_M3                  0
  92 #define ADPLL_M3DIV_M3_WIDTH            5
  93 #define ADPLL_M3DIV_M3_MASK             0x1f
  94
  95 #define ADPLL_RAMPCTRL_OFFSET           0x2c    /* Only on MPUPLL */
  96 #define ADPLL_RAMPCTRL_CLKRAMPLEVEL     19
  97 #define ADPLL_RAMPCTRL_CLKRAMPRATE      16
  98 #define ADPLL_RAMPCTRL_RELOCK_RAMP_EN   0
  99
 100 #define MAX_ADPLL_INPUTS                3
 101 #define MAX_ADPLL_OUTPUTS               4
 102 #define ADPLL_MAX_RETRIES               5
 103
 104 #define to_dco(_hw)     container_of(_hw, struct ti_adpll_dco_data, hw)
 105 #define to_adpll(_hw)   container_of(_hw, struct ti_adpll_data, dco)
 106 #define to_clkout(_hw)  container_of(_hw, struct ti_adpll_clkout_data, hw)
 107
 108 enum ti_adpll_clocks {
 109         TI_ADPLL_DCO,
 110         TI_ADPLL_DCO_GATE,
 111         TI_ADPLL_N2,
 112         TI_ADPLL_M2,
 113         TI_ADPLL_M2_GATE,
 114         TI_ADPLL_BYPASS,
 115         TI_ADPLL_HIF,
 116         TI_ADPLL_DIV2,
 117         TI_ADPLL_CLKOUT,
 118         TI_ADPLL_CLKOUT2,
 119         TI_ADPLL_M3,
 120 };
 121
 122 #define TI_ADPLL_NR_CLOCKS      (TI_ADPLL_M3 + 1)
 123
 124 enum ti_adpll_inputs {
 125         TI_ADPLL_CLKINP,
 126         TI_ADPLL_CLKINPULOW,
 127         TI_ADPLL_CLKINPHIF,
 128 };
 129
 130 enum ti_adpll_s_outputs {
 131         TI_ADPLL_S_DCOCLKLDO,
 132         TI_ADPLL_S_CLKOUT,
 133         TI_ADPLL_S_CLKOUTX2,
 134         TI_ADPLL_S_CLKOUTHIF,
 135 };
 136
 137 enum ti_adpll_lj_outputs {
 138         TI_ADPLL_LJ_CLKDCOLDO,
 139         TI_ADPLL_LJ_CLKOUT,
 140         TI_ADPLL_LJ_CLKOUTLDO,
 141 };
 142
 143 struct ti_adpll_platform_data {
 144         const bool is_type_s;
 145         const int nr_max_inputs;
 146         const int nr_max_outputs;
 147         const int output_index;
 148 };
 149
 150 struct ti_adpll_clock {
 151         struct clk *clk;
 152         struct clk_lookup *cl;
 153         void (*unregister)(struct clk *clk);
 154 };
 155
 156 struct ti_adpll_dco_data {
 157         struct clk_hw hw;
 158 };
 159
 160 struct ti_adpll_clkout_data {
 161         struct ti_adpll_data *adpll;
 162         struct clk_gate gate;
 163         struct clk_hw hw;
 164 };
 165
 166 struct ti_adpll_data {
 167         struct device *dev;
 168         const struct ti_adpll_platform_data *c;
 169         struct device_node *np;
 170         unsigned long pa;
 171         void __iomem *iobase;
 172         void __iomem *regs;
 173         spinlock_t lock;        /* For ADPLL shared register access */
 174         const char *parent_names[MAX_ADPLL_INPUTS];
 175         struct clk *parent_clocks[MAX_ADPLL_INPUTS];
 176         struct ti_adpll_clock *clocks;
 177         struct clk_onecell_data outputs;
 178         struct ti_adpll_dco_data dco;
 179 };
 180
 181 static const char *ti_adpll_clk_get_name(struct ti_adpll_data *d,
 182                                          int output_index,
 183                                          const char *postfix)
 184 {
 185         const char *name;
 186         int err;
 187
 188         if (output_index >= 0) {
 189                 err = of_property_read_string_index(d->np,
 190                                                     "clock-output-names",
 191                                                     output_index,
 192                                                     &name);
 193                 if (err)
 194                         return NULL;
 195         } else {
 196                 const char *base_name = "adpll";
 197                 char *buf;
 198
 199                 buf = devm_kzalloc(d->dev, 8 + 1 + strlen(base_name) + 1 +
 200                                     strlen(postfix), GFP_KERNEL);
 201                 if (!buf)
 202                         return NULL;
 203                 sprintf(buf, "%08lx.%s.%s", d->pa, base_name, postfix);
 204                 name = buf;
 205         }
 206
 207         return name;
 208 }
 209
 210 #define ADPLL_MAX_CON_ID        16      /* See MAX_CON_ID */
 211
 212 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock,
 213                                 int index, int output_index, const char *name,
 214                                 void (*unregister)(struct clk *clk))
 215 {
 216         struct clk_lookup *cl;
 217         const char *postfix = NULL;
 218         char con_id[ADPLL_MAX_CON_ID];
 219
 220         d->clocks[index].clk = clock;
 221         d->clocks[index].unregister = unregister;
 222
 223         /* Separate con_id in format "pll040dcoclkldo" to fit MAX_CON_ID */
 224         postfix = strrchr(name, '.');
 225         if (postfix && strlen(postfix) > 1) {
 226                 if (strlen(postfix) > ADPLL_MAX_CON_ID)
 227                         dev_warn(d->dev, "clock %s con_id lookup may fail\n",
 228                                  name);
 229                 snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1);
 230                 cl = clkdev_create(clock, con_id, NULL);
 231                 if (!cl)
 232                         return -ENOMEM;
 233                 d->clocks[index].cl = cl;
 234         } else {
 235                 dev_warn(d->dev, "no con_id for clock %s\n", name);
 236         }
 237
 238         if (output_index < 0)
 239                 return 0;
 240
 241         d->outputs.clks[output_index] = clock;
 242         d->outputs.clk_num++;
 243
 244         return 0;
 245 }
 246
 247 static int ti_adpll_init_divider(struct ti_adpll_data *d,
 248                                  enum ti_adpll_clocks index,
 249                                  int output_index, char *name,
 250                                  struct clk *parent_clock,
 251                                  void __iomem *reg,
 252                                  u8 shift, u8 width,
 253                                  u8 clk_divider_flags)
 254 {
 255         const char *child_name;
 256         const char *parent_name;
 257         struct clk *clock;
 258
 259         child_name = ti_adpll_clk_get_name(d, output_index, name);
 260         if (!child_name)
 261                 return -EINVAL;
 262
 263         parent_name = __clk_get_name(parent_clock);
 264         clock = clk_register_divider(d->dev, child_name, parent_name, 0,
 265                                      reg, shift, width, clk_divider_flags,
 266                                      &d->lock);
 267         if (IS_ERR(clock)) {
 268                 dev_err(d->dev, "failed to register divider %s: %li\n",
 269                         name, PTR_ERR(clock));
 270                 return PTR_ERR(clock);
 271         }
 272
 273         return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
 274                                     clk_unregister_divider);
 275 }
 276
 277 static int ti_adpll_init_mux(struct ti_adpll_data *d,
 278                              enum ti_adpll_clocks index,
 279                              char *name, struct clk *clk0,
 280                              struct clk *clk1,
 281                              void __iomem *reg,
 282                              u8 shift)
 283 {
 284         const char *child_name;
 285         const char *parents[2];
 286         struct clk *clock;
 287
 288         child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
 289         if (!child_name)
 290                 return -ENOMEM;
 291         parents[0] = __clk_get_name(clk0);
 292         parents[1] = __clk_get_name(clk1);
 293         clock = clk_register_mux(d->dev, child_name, parents, 2, 0,
 294                                  reg, shift, 1, 0, &d->lock);
 295         if (IS_ERR(clock)) {
 296                 dev_err(d->dev, "failed to register mux %s: %li\n",
 297                         name, PTR_ERR(clock));
 298                 return PTR_ERR(clock);
 299         }
 300
 301         return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
 302                                     clk_unregister_mux);
 303 }
 304
 305 static int ti_adpll_init_gate(struct ti_adpll_data *d,
 306                               enum ti_adpll_clocks index,
 307                               int output_index, char *name,
 308                               struct clk *parent_clock,
 309                               void __iomem *reg,
 310                               u8 bit_idx,
 311                               u8 clk_gate_flags)
 312 {
 313         const char *child_name;
 314         const char *parent_name;
 315         struct clk *clock;
 316
 317         child_name = ti_adpll_clk_get_name(d, output_index, name);
 318         if (!child_name)
 319                 return -EINVAL;
 320
 321         parent_name = __clk_get_name(parent_clock);
 322         clock = clk_register_gate(d->dev, child_name, parent_name, 0,
 323                                   reg, bit_idx, clk_gate_flags,
 324                                   &d->lock);
 325         if (IS_ERR(clock)) {
 326                 dev_err(d->dev, "failed to register gate %s: %li\n",
 327                         name, PTR_ERR(clock));
 328                 return PTR_ERR(clock);
 329         }
 330
 331         return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
 332                                     clk_unregister_gate);
 333 }
 334
 335 static int ti_adpll_init_fixed_factor(struct ti_adpll_data *d,
 336                                       enum ti_adpll_clocks index,
 337                                       char *name,
 338                                       struct clk *parent_clock,
 339                                       unsigned int mult,
 340                                       unsigned int div)
 341 {
 342         const char *child_name;
 343         const char *parent_name;
 344         struct clk *clock;
 345
 346         child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
 347         if (!child_name)
 348                 return -ENOMEM;
 349
 350         parent_name = __clk_get_name(parent_clock);
 351         clock = clk_register_fixed_factor(d->dev, child_name, parent_name,
 352                                           0, mult, div);
 353         if (IS_ERR(clock))
 354                 return PTR_ERR(clock);
 355
 356         return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
 357                                     clk_unregister);
 358 }
 359
 360 static void ti_adpll_set_idle_bypass(struct ti_adpll_data *d)
 361 {
 362         unsigned long flags;
 363         u32 v;
 364
 365         spin_lock_irqsave(&d->lock, flags);
 366         v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
 367         v |= BIT(ADPLL_CLKCTRL_IDLE);
 368         writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
 369         spin_unlock_irqrestore(&d->lock, flags);
 370 }
 371
 372 static void ti_adpll_clear_idle_bypass(struct ti_adpll_data *d)
 373 {
 374         unsigned long flags;
 375         u32 v;
 376
 377         spin_lock_irqsave(&d->lock, flags);
 378         v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
 379         v &= ~BIT(ADPLL_CLKCTRL_IDLE);
 380         writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
 381         spin_unlock_irqrestore(&d->lock, flags);
 382 }
 383
 384 static bool ti_adpll_clock_is_bypass(struct ti_adpll_data *d)
 385 {
 386         u32 v;
 387
 388         v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
 389
 390         return v & BIT(ADPLL_STATUS_BYPASS);
 391 }
 392
 393 /*
 394  * Locked and bypass are not actually mutually exclusive:  if you only care
 395  * about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling
 396  * the PLL, resulting in status (FREQLOCK | PHASELOCK | BYPASS) after lock.
 397  */
 398 static bool ti_adpll_is_locked(struct ti_adpll_data *d)
 399 {
 400         u32 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
 401
 402         return (v & ADPLL_STATUS_PREPARED_MASK) == ADPLL_STATUS_PREPARED_MASK;
 403 }
 404
 405 static int ti_adpll_wait_lock(struct ti_adpll_data *d)
 406 {
 407         int retries = ADPLL_MAX_RETRIES;
 408
 409         do {
 410                 if (ti_adpll_is_locked(d))
 411                         return 0;
 412                 usleep_range(200, 300);
 413         } while (retries--);
 414
 415         dev_err(d->dev, "pll failed to lock\n");
 416         return -ETIMEDOUT;
 417 }
 418
 419 static int ti_adpll_prepare(struct clk_hw *hw)
 420 {
 421         struct ti_adpll_dco_data *dco = to_dco(hw);
 422         struct ti_adpll_data *d = to_adpll(dco);
 423
 424         ti_adpll_clear_idle_bypass(d);
 425         ti_adpll_wait_lock(d);
 426
 427         return 0;
 428 }
 429
 430 static void ti_adpll_unprepare(struct clk_hw *hw)
 431 {
 432         struct ti_adpll_dco_data *dco = to_dco(hw);
 433         struct ti_adpll_data *d = to_adpll(dco);
 434
 435         ti_adpll_set_idle_bypass(d);
 436 }
 437
 438 static int ti_adpll_is_prepared(struct clk_hw *hw)
 439 {
 440         struct ti_adpll_dco_data *dco = to_dco(hw);
 441         struct ti_adpll_data *d = to_adpll(dco);
 442
 443         return ti_adpll_is_locked(d);
 444 }
 445
 446 /*
 447  * Note that the DCO clock is never subject to bypass: if the PLL is off,
 448  * dcoclk is low.
 449  */
 450 static unsigned long ti_adpll_recalc_rate(struct clk_hw *hw,
 451                                           unsigned long parent_rate)
 452 {
 453         struct ti_adpll_dco_data *dco = to_dco(hw);
 454         struct ti_adpll_data *d = to_adpll(dco);
 455         u32 frac_m, divider, v;
 456         u64 rate;
 457         unsigned long flags;
 458
 459         if (ti_adpll_clock_is_bypass(d))
 460                 return 0;
 461
 462         spin_lock_irqsave(&d->lock, flags);
 463         frac_m = readl_relaxed(d->regs + ADPLL_FRACDIV_OFFSET);
 464         frac_m &= ADPLL_FRACDIV_FRACTIONALM_MASK;
 465         rate = (u64)readw_relaxed(d->regs + ADPLL_MN2DIV_OFFSET) << 18;
 466         rate += frac_m;
 467         rate *= parent_rate;
 468         divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18;
 469         spin_unlock_irqrestore(&d->lock, flags);
 470
 471         do_div(rate, divider);
 472
 473         if (d->c->is_type_s) {
 474                 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
 475                 if (v & BIT(ADPLL_CLKCTRL_REGM4XEN_ADPLL_S))
 476                         rate *= 4;
 477                 rate *= 2;
 478         }
 479
 480         return rate;
 481 }
 482
 483 /* PLL parent is always clkinp, bypass only affects the children */
 484 static u8 ti_adpll_get_parent(struct clk_hw *hw)
 485 {
 486         return 0;
 487 }
 488
 489 static const struct clk_ops ti_adpll_ops = {
 490         .prepare = ti_adpll_prepare,
 491         .unprepare = ti_adpll_unprepare,
 492         .is_prepared = ti_adpll_is_prepared,
 493         .recalc_rate = ti_adpll_recalc_rate,
 494         .get_parent = ti_adpll_get_parent,
 495 };
 496
 497 static int ti_adpll_init_dco(struct ti_adpll_data *d)
 498 {
 499         struct clk_init_data init;
 500         struct clk *clock;
 501         const char *postfix;
 502         int width, err;
 503
 504         d->outputs.clks = devm_kcalloc(d->dev,
 505                                        MAX_ADPLL_OUTPUTS,
 506                                        sizeof(struct clk *),
 507                                        GFP_KERNEL);
 508         if (!d->outputs.clks)
 509                 return -ENOMEM;
 510
 511         if (d->c->output_index < 0)
 512                 postfix = "dco";
 513         else
 514                 postfix = NULL;
 515
 516         init.name = ti_adpll_clk_get_name(d, d->c->output_index, postfix);
 517         if (!init.name)
 518                 return -EINVAL;
 519
 520         init.parent_names = d->parent_names;
 521         init.num_parents = d->c->nr_max_inputs;
 522         init.ops = &ti_adpll_ops;
 523         init.flags = CLK_GET_RATE_NOCACHE;
 524         d->dco.hw.init = &init;
 525
 526         if (d->c->is_type_s)
 527                 width = 5;
 528         else
 529                 width = 4;
 530
 531         /* Internal input clock divider N2 */
 532         err = ti_adpll_init_divider(d, TI_ADPLL_N2, -ENODEV, "n2",
 533                                     d->parent_clocks[TI_ADPLL_CLKINP],
 534                                     d->regs + ADPLL_MN2DIV_OFFSET,
 535                                     ADPLL_MN2DIV_N2, width, 0);
 536         if (err)
 537                 return err;
 538
 539         clock = devm_clk_register(d->dev, &d->dco.hw);
 540         if (IS_ERR(clock))
 541                 return PTR_ERR(clock);
 542
 543         return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index,
 544                                     init.name, NULL);
 545 }
 546
 547 static int ti_adpll_clkout_enable(struct clk_hw *hw)
 548 {
 549         struct ti_adpll_clkout_data *co = to_clkout(hw);
 550         struct clk_hw *gate_hw = &co->gate.hw;
 551
 552         __clk_hw_set_clk(gate_hw, hw);
 553
 554         return clk_gate_ops.enable(gate_hw);
 555 }
 556
 557 static void ti_adpll_clkout_disable(struct clk_hw *hw)
 558 {
 559         struct ti_adpll_clkout_data *co = to_clkout(hw);
 560         struct clk_hw *gate_hw = &co->gate.hw;
 561
 562         __clk_hw_set_clk(gate_hw, hw);
 563         clk_gate_ops.disable(gate_hw);
 564 }
 565
 566 static int ti_adpll_clkout_is_enabled(struct clk_hw *hw)
 567 {
 568         struct ti_adpll_clkout_data *co = to_clkout(hw);
 569         struct clk_hw *gate_hw = &co->gate.hw;
 570
 571         __clk_hw_set_clk(gate_hw, hw);
 572
 573         return clk_gate_ops.is_enabled(gate_hw);
 574 }
 575
 576 /* Setting PLL bypass puts clkout and clkoutx2 into bypass */
 577 static u8 ti_adpll_clkout_get_parent(struct clk_hw *hw)
 578 {
 579         struct ti_adpll_clkout_data *co = to_clkout(hw);
 580         struct ti_adpll_data *d = co->adpll;
 581
 582         return ti_adpll_clock_is_bypass(d);
 583 }
 584
 585 static int ti_adpll_init_clkout(struct ti_adpll_data *d,
 586                                 enum ti_adpll_clocks index,
 587                                 int output_index, int gate_bit,
 588                                 char *name, struct clk *clk0,
 589                                 struct clk *clk1)
 590 {
 591         struct ti_adpll_clkout_data *co;
 592         struct clk_init_data init;
 593         struct clk_ops *ops;
 594         const char *parent_names[2];
 595         const char *child_name;
 596         struct clk *clock;
 597         int err;
 598
 599         co = devm_kzalloc(d->dev, sizeof(*co), GFP_KERNEL);
 600         if (!co)
 601                 return -ENOMEM;
 602         co->adpll = d;
 603
 604         err = of_property_read_string_index(d->np,
 605                                             "clock-output-names",
 606                                             output_index,
 607                                             &child_name);
 608         if (err)
 609                 return err;
 610
 611         ops = devm_kzalloc(d->dev, sizeof(*ops), GFP_KERNEL);
 612         if (!ops)
 613                 return -ENOMEM;
 614
 615         init.name = child_name;
 616         init.ops = ops;
 617         init.flags = 0;
 618         co->hw.init = &init;
 619         parent_names[0] = __clk_get_name(clk0);
 620         parent_names[1] = __clk_get_name(clk1);
 621         init.parent_names = parent_names;
 622         init.num_parents = 2;
 623
 624         ops->get_parent = ti_adpll_clkout_get_parent;
 625         ops->determine_rate = __clk_mux_determine_rate;
 626         if (gate_bit) {
 627                 co->gate.lock = &d->lock;
 628                 co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET;
 629                 co->gate.bit_idx = gate_bit;
 630                 ops->enable = ti_adpll_clkout_enable;
 631                 ops->disable = ti_adpll_clkout_disable;
 632                 ops->is_enabled = ti_adpll_clkout_is_enabled;
 633         }
 634
 635         clock = devm_clk_register(d->dev, &co->hw);
 636         if (IS_ERR(clock)) {
 637                 dev_err(d->dev, "failed to register output %s: %li\n",
 638                         name, PTR_ERR(clock));
 639                 return PTR_ERR(clock);
 640         }
 641
 642         return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
 643                                     NULL);
 644 }
 645
 646 static int ti_adpll_init_children_adpll_s(struct ti_adpll_data *d)
 647 {
 648         int err;
 649
 650         if (!d->c->is_type_s)
 651                 return 0;
 652
 653         /* Internal mux, sources from divider N2 or clkinpulow */
 654         err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
 655                                 d->clocks[TI_ADPLL_N2].clk,
 656                                 d->parent_clocks[TI_ADPLL_CLKINPULOW],
 657                                 d->regs + ADPLL_CLKCTRL_OFFSET,
 658                                 ADPLL_CLKCTRL_ULOWCLKEN);
 659         if (err)
 660                 return err;
 661
 662         /* Internal divider M2, sources DCO */
 663         err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, "m2",
 664                                     d->clocks[TI_ADPLL_DCO].clk,
 665                                     d->regs + ADPLL_M2NDIV_OFFSET,
 666                                     ADPLL_M2NDIV_M2,
 667                                     ADPLL_M2NDIV_M2_ADPLL_S_WIDTH,
 668                                     CLK_DIVIDER_ONE_BASED);
 669         if (err)
 670                 return err;
 671
 672         /* Internal fixed divider, after M2 before clkout */
 673         err = ti_adpll_init_fixed_factor(d, TI_ADPLL_DIV2, "div2",
 674                                          d->clocks[TI_ADPLL_M2].clk,
 675                                          1, 2);
 676         if (err)
 677                 return err;
 678
 679         /* Output clkout with a mux and gate, sources from div2 or bypass */
 680         err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
 681                                    ADPLL_CLKCTRL_CLKOUTEN, "clkout",
 682                                    d->clocks[TI_ADPLL_DIV2].clk,
 683                                    d->clocks[TI_ADPLL_BYPASS].clk);
 684         if (err)
 685                 return err;
 686
 687         /* Output clkoutx2 with a mux and gate, sources from M2 or bypass */
 688         err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT2, TI_ADPLL_S_CLKOUTX2, 0,
 689                                    "clkout2", d->clocks[TI_ADPLL_M2].clk,
 690                                    d->clocks[TI_ADPLL_BYPASS].clk);
 691         if (err)
 692                 return err;
 693
 694         /* Internal mux, sources from DCO and clkinphif */
 695         if (d->parent_clocks[TI_ADPLL_CLKINPHIF]) {
 696                 err = ti_adpll_init_mux(d, TI_ADPLL_HIF, "hif",
 697                                         d->clocks[TI_ADPLL_DCO].clk,
 698                                         d->parent_clocks[TI_ADPLL_CLKINPHIF],
 699                                         d->regs + ADPLL_CLKCTRL_OFFSET,
 700                                         ADPLL_CLKINPHIFSEL_ADPLL_S);
 701                 if (err)
 702                         return err;
 703         }
 704
 705         /* Output clkouthif with a divider M3, sources from hif */
 706         err = ti_adpll_init_divider(d, TI_ADPLL_M3, TI_ADPLL_S_CLKOUTHIF, "m3",
 707                                     d->clocks[TI_ADPLL_HIF].clk,
 708                                     d->regs + ADPLL_M3DIV_OFFSET,
 709                                     ADPLL_M3DIV_M3,
 710                                     ADPLL_M3DIV_M3_WIDTH,
 711                                     CLK_DIVIDER_ONE_BASED);
 712         if (err)
 713                 return err;
 714
 715         /* Output clock dcoclkldo is the DCO */
 716
 717         return 0;
 718 }
 719
 720 static int ti_adpll_init_children_adpll_lj(struct ti_adpll_data *d)
 721 {
 722         int err;
 723
 724         if (d->c->is_type_s)
 725                 return 0;
 726
 727         /* Output clkdcoldo, gated output of DCO */
 728         err = ti_adpll_init_gate(d, TI_ADPLL_DCO_GATE, TI_ADPLL_LJ_CLKDCOLDO,
 729                                  "clkdcoldo", d->clocks[TI_ADPLL_DCO].clk,
 730                                  d->regs + ADPLL_CLKCTRL_OFFSET,
 731                                  ADPLL_CLKCTRL_CLKDCOLDOEN, 0);
 732         if (err)
 733                 return err;
 734
 735         /* Internal divider M2, sources from DCO */
 736         err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV,
 737                                     "m2", d->clocks[TI_ADPLL_DCO].clk,
 738                                     d->regs + ADPLL_M2NDIV_OFFSET,
 739                                     ADPLL_M2NDIV_M2,
 740                                     ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH,
 741                                     CLK_DIVIDER_ONE_BASED);
 742         if (err)
 743                 return err;
 744
 745         /* Output clkoutldo, gated output of M2 */
 746         err = ti_adpll_init_gate(d, TI_ADPLL_M2_GATE, TI_ADPLL_LJ_CLKOUTLDO,
 747                                  "clkoutldo", d->clocks[TI_ADPLL_M2].clk,
 748                                  d->regs + ADPLL_CLKCTRL_OFFSET,
 749                                  ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ,
 750                                  0);
 751         if (err)
 752                 return err;
 753
 754         /* Internal mux, sources from divider N2 or clkinpulow */
 755         err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
 756                                 d->clocks[TI_ADPLL_N2].clk,
 757                                 d->parent_clocks[TI_ADPLL_CLKINPULOW],
 758                                 d->regs + ADPLL_CLKCTRL_OFFSET,
 759                                 ADPLL_CLKCTRL_ULOWCLKEN);
 760         if (err)
 761                 return err;
 762
 763         /* Output clkout, sources M2 or bypass */
 764         err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
 765                                    ADPLL_CLKCTRL_CLKOUTEN, "clkout",
 766                                    d->clocks[TI_ADPLL_M2].clk,
 767                                    d->clocks[TI_ADPLL_BYPASS].clk);
 768         if (err)
 769                 return err;
 770
 771         return 0;
 772 }
 773
 774 static void ti_adpll_free_resources(struct ti_adpll_data *d)
 775 {
 776         int i;
 777
 778         for (i = TI_ADPLL_M3; i >= 0; i--) {
 779                 struct ti_adpll_clock *ac = &d->clocks[i];
 780
 781                 if (!ac || IS_ERR_OR_NULL(ac->clk))
 782                         continue;
 783                 if (ac->cl)
 784                         clkdev_drop(ac->cl);
 785                 if (ac->unregister)
 786                         ac->unregister(ac->clk);
 787         }
 788 }
 789
 790 /* MPU PLL manages the lock register for all PLLs */
 791 static void ti_adpll_unlock_all(void __iomem *reg)
 792 {
 793         u32 v;
 794
 795         v = readl_relaxed(reg);
 796         if (v == ADPLL_PLLSS_MMR_LOCK_ENABLED)
 797                 writel_relaxed(ADPLL_PLLSS_MMR_UNLOCK_MAGIC, reg);
 798 }
 799
 800 static int ti_adpll_init_registers(struct ti_adpll_data *d)
 801 {
 802         int register_offset = 0;
 803
 804         if (d->c->is_type_s) {
 805                 register_offset = 8;
 806                 ti_adpll_unlock_all(d->iobase + ADPLL_PLLSS_MMR_LOCK_OFFSET);
 807         }
 808
 809         d->regs = d->iobase + register_offset + ADPLL_PWRCTRL_OFFSET;
 810
 811         return 0;
 812 }
 813
 814 static int ti_adpll_init_inputs(struct ti_adpll_data *d)
 815 {
 816         const char *error = "need at least %i inputs";
 817         struct clk *clock;
 818         int nr_inputs;
 819
 820         nr_inputs = of_clk_get_parent_count(d->np);
 821         if (nr_inputs < d->c->nr_max_inputs) {
 822                 dev_err(d->dev, error, nr_inputs);
 823                 return -EINVAL;
 824         }
 825         of_clk_parent_fill(d->np, d->parent_names, nr_inputs);
 826
 827         clock = devm_clk_get(d->dev, d->parent_names[0]);
 828         if (IS_ERR(clock)) {
 829                 dev_err(d->dev, "could not get clkinp\n");
 830                 return PTR_ERR(clock);
 831         }
 832         d->parent_clocks[TI_ADPLL_CLKINP] = clock;
 833
 834         clock = devm_clk_get(d->dev, d->parent_names[1]);
 835         if (IS_ERR(clock)) {
 836                 dev_err(d->dev, "could not get clkinpulow clock\n");
 837                 return PTR_ERR(clock);
 838         }
 839         d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock;
 840
 841         if (d->c->is_type_s) {
 842                 clock =  devm_clk_get(d->dev, d->parent_names[2]);
 843                 if (IS_ERR(clock)) {
 844                         dev_err(d->dev, "could not get clkinphif clock\n");
 845                         return PTR_ERR(clock);
 846                 }
 847                 d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock;
 848         }
 849
 850         return 0;
 851 }
 852
 853 static const struct ti_adpll_platform_data ti_adpll_type_s = {
 854         .is_type_s = true,
 855         .nr_max_inputs = MAX_ADPLL_INPUTS,
 856         .nr_max_outputs = MAX_ADPLL_OUTPUTS,
 857         .output_index = TI_ADPLL_S_DCOCLKLDO,
 858 };
 859
 860 static const struct ti_adpll_platform_data ti_adpll_type_lj = {
 861         .is_type_s = false,
 862         .nr_max_inputs = MAX_ADPLL_INPUTS - 1,
 863         .nr_max_outputs = MAX_ADPLL_OUTPUTS - 1,
 864         .output_index = -EINVAL,
 865 };
 866
 867 static const struct of_device_id ti_adpll_match[] = {
 868         { .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s },
 869         { .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj },
 870         {},
 871 };
 872 MODULE_DEVICE_TABLE(of, ti_adpll_match);
 873
 874 static int ti_adpll_probe(struct platform_device *pdev)
 875 {
 876         struct device_node *node = pdev->dev.of_node;
 877         struct device *dev = &pdev->dev;
 878         const struct of_device_id *match;
 879         const struct ti_adpll_platform_data *pdata;
 880         struct ti_adpll_data *d;
 881         struct resource *res;
 882         int err;
 883
 884         match = of_match_device(ti_adpll_match, dev);
 885         if (match)
 886                 pdata = match->data;
 887         else
 888                 return -ENODEV;
 889
 890         d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
 891         if (!d)
 892                 return -ENOMEM;
 893         d->dev = dev;
 894         d->np = node;
 895         d->c = pdata;
 896         dev_set_drvdata(d->dev, d);
 897         spin_lock_init(&d->lock);
 898
 899         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 900         if (!res)
 901                 return -ENODEV;
 902         d->pa = res->start;
 903
 904         d->iobase = devm_ioremap_resource(dev, res);
 905         if (IS_ERR(d->iobase)) {
 906                 dev_err(dev, "could not get IO base: %li\n",
 907                         PTR_ERR(d->iobase));
 908                 return PTR_ERR(d->iobase);
 909         }
 910
 911         err = ti_adpll_init_registers(d);
 912         if (err)
 913                 return err;
 914
 915         err = ti_adpll_init_inputs(d);
 916         if (err)
 917                 return err;
 918
 919         d->clocks = devm_kcalloc(d->dev,
 920                                  TI_ADPLL_NR_CLOCKS,
 921                                  sizeof(struct ti_adpll_clock),
 922                                  GFP_KERNEL);
 923         if (!d->clocks)
 924                 return -ENOMEM;
 925
 926         err = ti_adpll_init_dco(d);
 927         if (err) {
 928                 dev_err(dev, "could not register dco: %i\n", err);
 929                 goto free;
 930         }
 931
 932         err = ti_adpll_init_children_adpll_s(d);
 933         if (err)
 934                 goto free;
 935         err = ti_adpll_init_children_adpll_lj(d);
 936         if (err)
 937                 goto free;
 938
 939         err = of_clk_add_provider(d->np, of_clk_src_onecell_get, &d->outputs);
 940         if (err)
 941                 goto free;
 942
 943         return 0;
 944
 945 free:
 946         WARN_ON(1);
 947         ti_adpll_free_resources(d);
 948
 949         return err;
 950 }
 951
 952 static int ti_adpll_remove(struct platform_device *pdev)
 953 {
 954         struct ti_adpll_data *d = dev_get_drvdata(&pdev->dev);
 955
 956         ti_adpll_free_resources(d);
 957
 958         return 0;
 959 }
 960
 961 static struct platform_driver ti_adpll_driver = {
 962         .driver = {
 963                 .name = "ti-adpll",
 964                 .of_match_table = ti_adpll_match,
 965         },
 966         .probe = ti_adpll_probe,
 967         .remove = ti_adpll_remove,
 968 };
 969
 970 static int __init ti_adpll_init(void)
 971 {
 972         return platform_driver_register(&ti_adpll_driver);
 973 }
 974 core_initcall(ti_adpll_init);
 975
 976 static void __exit ti_adpll_exit(void)
 977 {
 978         platform_driver_unregister(&ti_adpll_driver);
 979 }
 980 module_exit(ti_adpll_exit);
 981
 982 MODULE_DESCRIPTION("Clock driver for dm814x ADPLL");
 983 MODULE_ALIAS("platform:dm814-adpll-clock");
 984 MODULE_AUTHOR("Tony LIndgren <tony@atomide.com>");
 985 MODULE_LICENSE("GPL v2");