drivers/clk/sunxi/clk-sun9i-mmc.c

   1 /*
   2  * Copyright 2015 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/reset.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/reset-controller.h>
  27 #include <linux/slab.h>
  28 #include <linux/spinlock.h>
  29
  30 #define SUN9I_MMC_WIDTH         4
  31
  32 #define SUN9I_MMC_GATE_BIT      16
  33 #define SUN9I_MMC_RESET_BIT     18
  34
  35 struct sun9i_mmc_clk_data {
  36         spinlock_t                      lock;
  37         void __iomem                    *membase;
  38         struct clk                      *clk;
  39         struct reset_control            *reset;
  40         struct clk_onecell_data         clk_data;
  41         struct reset_controller_dev     rcdev;
  42 };
  43
  44 static int sun9i_mmc_reset_assert(struct reset_controller_dev *rcdev,
  45                               unsigned long id)
  46 {
  47         struct sun9i_mmc_clk_data *data = container_of(rcdev,
  48                                                        struct sun9i_mmc_clk_data,
  49                                                        rcdev);
  50         unsigned long flags;
  51         void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id;
  52         u32 val;
  53
  54         clk_prepare_enable(data->clk);
  55         spin_lock_irqsave(&data->lock, flags);
  56
  57         val = readl(reg);
  58         writel(val & ~BIT(SUN9I_MMC_RESET_BIT), reg);
  59
  60         spin_unlock_irqrestore(&data->lock, flags);
  61         clk_disable_unprepare(data->clk);
  62
  63         return 0;
  64 }
  65
  66 static int sun9i_mmc_reset_deassert(struct reset_controller_dev *rcdev,
  67                                 unsigned long id)
  68 {
  69         struct sun9i_mmc_clk_data *data = container_of(rcdev,
  70                                                        struct sun9i_mmc_clk_data,
  71                                                        rcdev);
  72         unsigned long flags;
  73         void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id;
  74         u32 val;
  75
  76         clk_prepare_enable(data->clk);
  77         spin_lock_irqsave(&data->lock, flags);
  78
  79         val = readl(reg);
  80         writel(val | BIT(SUN9I_MMC_RESET_BIT), reg);
  81
  82         spin_unlock_irqrestore(&data->lock, flags);
  83         clk_disable_unprepare(data->clk);
  84
  85         return 0;
  86 }
  87
  88 static int sun9i_mmc_reset_reset(struct reset_controller_dev *rcdev,
  89                                  unsigned long id)
  90 {
  91         sun9i_mmc_reset_assert(rcdev, id);
  92         udelay(10);
  93         sun9i_mmc_reset_deassert(rcdev, id);
  94
  95         return 0;
  96 }
  97
  98 static const struct reset_control_ops sun9i_mmc_reset_ops = {
  99         .assert         = sun9i_mmc_reset_assert,
 100         .deassert       = sun9i_mmc_reset_deassert,
 101         .reset          = sun9i_mmc_reset_reset,
 102 };
 103
 104 static int sun9i_a80_mmc_config_clk_probe(struct platform_device *pdev)
 105 {
 106         struct device_node *np = pdev->dev.of_node;
 107         struct sun9i_mmc_clk_data *data;
 108         struct clk_onecell_data *clk_data;
 109         const char *clk_name = np->name;
 110         const char *clk_parent;
 111         struct resource *r;
 112         int count, i, ret;
 113
 114         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 115         if (!data)
 116                 return -ENOMEM;
 117
 118         spin_lock_init(&data->lock);
 119
 120         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 121         /* one clock/reset pair per word */
 122         count = DIV_ROUND_UP((resource_size(r)), SUN9I_MMC_WIDTH);
 123         data->membase = devm_ioremap_resource(&pdev->dev, r);
 124         if (IS_ERR(data->membase))
 125                 return PTR_ERR(data->membase);
 126
 127         clk_data = &data->clk_data;
 128         clk_data->clk_num = count;
 129         clk_data->clks = devm_kcalloc(&pdev->dev, count, sizeof(struct clk *),
 130                                       GFP_KERNEL);
 131         if (!clk_data->clks)
 132                 return -ENOMEM;
 133
 134         data->clk = devm_clk_get(&pdev->dev, NULL);
 135         if (IS_ERR(data->clk)) {
 136                 dev_err(&pdev->dev, "Could not get clock\n");
 137                 return PTR_ERR(data->clk);
 138         }
 139
 140         data->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 141         if (IS_ERR(data->reset)) {
 142                 dev_err(&pdev->dev, "Could not get reset control\n");
 143                 return PTR_ERR(data->reset);
 144         }
 145
 146         ret = reset_control_deassert(data->reset);
 147         if (ret) {
 148                 dev_err(&pdev->dev, "Reset deassert err %d\n", ret);
 149                 return ret;
 150         }
 151
 152         clk_parent = __clk_get_name(data->clk);
 153         for (i = 0; i < count; i++) {
 154                 of_property_read_string_index(np, "clock-output-names",
 155                                               i, &clk_name);
 156
 157                 clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name,
 158                                                       clk_parent, 0,
 159                                                       data->membase + SUN9I_MMC_WIDTH * i,
 160                                                       SUN9I_MMC_GATE_BIT, 0,
 161                                                       &data->lock);
 162
 163                 if (IS_ERR(clk_data->clks[i])) {
 164                         ret = PTR_ERR(clk_data->clks[i]);
 165                         goto err_clk_register;
 166                 }
 167         }
 168
 169         ret = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
 170         if (ret)
 171                 goto err_clk_provider;
 172
 173         data->rcdev.owner = THIS_MODULE;
 174         data->rcdev.nr_resets = count;
 175         data->rcdev.ops = &sun9i_mmc_reset_ops;
 176         data->rcdev.of_node = pdev->dev.of_node;
 177
 178         ret = reset_controller_register(&data->rcdev);
 179         if (ret)
 180                 goto err_rc_reg;
 181
 182         platform_set_drvdata(pdev, data);
 183
 184         return 0;
 185
 186 err_rc_reg:
 187         of_clk_del_provider(np);
 188
 189 err_clk_provider:
 190         for (i = 0; i < count; i++)
 191                 clk_unregister(clk_data->clks[i]);
 192
 193 err_clk_register:
 194         reset_control_assert(data->reset);
 195
 196         return ret;
 197 }
 198
 199 static const struct of_device_id sun9i_a80_mmc_config_clk_dt_ids[] = {
 200         { .compatible = "allwinner,sun9i-a80-mmc-config-clk" },
 201         { /* sentinel */ }
 202 };
 203
 204 static struct platform_driver sun9i_a80_mmc_config_clk_driver = {
 205         .driver = {
 206                 .name = "sun9i-a80-mmc-config-clk",
 207                 .suppress_bind_attrs = true,
 208                 .of_match_table = sun9i_a80_mmc_config_clk_dt_ids,
 209         },
 210         .probe = sun9i_a80_mmc_config_clk_probe,
 211 };
 212 builtin_platform_driver(sun9i_a80_mmc_config_clk_driver);