treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
[sfrench/cifs-2.6.git] / drivers / clk / sunxi / clk-sun4i-pll3.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright 2015 Maxime Ripard
4  *
5  * Maxime Ripard <maxime.ripard@free-electrons.com>
6  */
7
8 #include <linux/clk-provider.h>
9 #include <linux/io.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/slab.h>
13 #include <linux/spinlock.h>
14
15 #define SUN4I_A10_PLL3_GATE_BIT 31
16 #define SUN4I_A10_PLL3_DIV_WIDTH        7
17 #define SUN4I_A10_PLL3_DIV_SHIFT        0
18
19 static DEFINE_SPINLOCK(sun4i_a10_pll3_lock);
20
21 static void __init sun4i_a10_pll3_setup(struct device_node *node)
22 {
23         const char *clk_name = node->name, *parent;
24         struct clk_multiplier *mult;
25         struct clk_gate *gate;
26         struct resource res;
27         void __iomem *reg;
28         struct clk *clk;
29         int ret;
30
31         of_property_read_string(node, "clock-output-names", &clk_name);
32         parent = of_clk_get_parent_name(node, 0);
33
34         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
35         if (IS_ERR(reg)) {
36                 pr_err("%s: Could not map the clock registers\n", clk_name);
37                 return;
38         }
39
40         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
41         if (!gate)
42                 goto err_unmap;
43
44         gate->reg = reg;
45         gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT;
46         gate->lock = &sun4i_a10_pll3_lock;
47
48         mult = kzalloc(sizeof(*mult), GFP_KERNEL);
49         if (!mult)
50                 goto err_free_gate;
51
52         mult->reg = reg;
53         mult->shift = SUN4I_A10_PLL3_DIV_SHIFT;
54         mult->width = SUN4I_A10_PLL3_DIV_WIDTH;
55         mult->lock = &sun4i_a10_pll3_lock;
56
57         clk = clk_register_composite(NULL, clk_name,
58                                      &parent, 1,
59                                      NULL, NULL,
60                                      &mult->hw, &clk_multiplier_ops,
61                                      &gate->hw, &clk_gate_ops,
62                                      0);
63         if (IS_ERR(clk)) {
64                 pr_err("%s: Couldn't register the clock\n", clk_name);
65                 goto err_free_mult;
66         }
67
68         ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
69         if (ret) {
70                 pr_err("%s: Couldn't register DT provider\n",
71                        clk_name);
72                 goto err_clk_unregister;
73         }
74
75         return;
76
77 err_clk_unregister:
78         clk_unregister_composite(clk);
79 err_free_mult:
80         kfree(mult);
81 err_free_gate:
82         kfree(gate);
83 err_unmap:
84         iounmap(reg);
85         of_address_to_resource(node, 0, &res);
86         release_mem_region(res.start, resource_size(&res));
87 }
88
89 CLK_OF_DECLARE(sun4i_a10_pll3, "allwinner,sun4i-a10-pll3-clk",
90                sun4i_a10_pll3_setup);