drivers/clk/sunxi-ng/ccu-sun8i-a33.c

   1 /*
   2  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/clk-provider.h>
  15 #include <linux/of_address.h>
  16
  17 #include "ccu_common.h"
  18 #include "ccu_reset.h"
  19
  20 #include "ccu_div.h"
  21 #include "ccu_gate.h"
  22 #include "ccu_mp.h"
  23 #include "ccu_mult.h"
  24 #include "ccu_nk.h"
  25 #include "ccu_nkm.h"
  26 #include "ccu_nkmp.h"
  27 #include "ccu_nm.h"
  28 #include "ccu_phase.h"
  29
  30 #include "ccu-sun8i-a23-a33.h"
  31
  32 static struct ccu_nkmp pll_cpux_clk = {
  33         .enable = BIT(31),
  34         .lock   = BIT(28),
  35
  36         .n      = _SUNXI_CCU_MULT(8, 5),
  37         .k      = _SUNXI_CCU_MULT(4, 2),
  38         .m      = _SUNXI_CCU_DIV(0, 2),
  39         .p      = _SUNXI_CCU_DIV_MAX(16, 2, 4),
  40
  41         .common = {
  42                 .reg            = 0x000,
  43                 .hw.init        = CLK_HW_INIT("pll-cpux", "osc24M",
  44                                               &ccu_nkmp_ops,
  45                                               0),
  46         },
  47 };
  48
  49 /*
  50  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
  51  * the base (2x, 4x and 8x), and one variable divider (the one true
  52  * pll audio).
  53  *
  54  * We don't have any need for the variable divider for now, so we just
  55  * hardcode it to match with the clock names
  56  */
  57 #define SUN8I_A33_PLL_AUDIO_REG 0x008
  58
  59 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
  60                                    "osc24M", 0x008,
  61                                    8, 7,                /* N */
  62                                    0, 5,                /* M */
  63                                    BIT(31),             /* gate */
  64                                    BIT(28),             /* lock */
  65                                    CLK_SET_RATE_UNGATE);
  66
  67 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
  68                                         "osc24M", 0x010,
  69                                         8, 7,           /* N */
  70                                         0, 4,           /* M */
  71                                         BIT(24),        /* frac enable */
  72                                         BIT(25),        /* frac select */
  73                                         270000000,      /* frac rate 0 */
  74                                         297000000,      /* frac rate 1 */
  75                                         BIT(31),        /* gate */
  76                                         BIT(28),        /* lock */
  77                                         CLK_SET_RATE_UNGATE);
  78
  79 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
  80                                         "osc24M", 0x018,
  81                                         8, 7,           /* N */
  82                                         0, 4,           /* M */
  83                                         BIT(24),        /* frac enable */
  84                                         BIT(25),        /* frac select */
  85                                         270000000,      /* frac rate 0 */
  86                                         297000000,      /* frac rate 1 */
  87                                         BIT(31),        /* gate */
  88                                         BIT(28),        /* lock */
  89                                         CLK_SET_RATE_UNGATE);
  90
  91 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
  92                                     "osc24M", 0x020,
  93                                     8, 5,               /* N */
  94                                     4, 2,               /* K */
  95                                     0, 2,               /* M */
  96                                     BIT(31),            /* gate */
  97                                     BIT(28),            /* lock */
  98                                     0);
  99
 100 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
 101                                            "osc24M", 0x028,
 102                                            8, 5,        /* N */
 103                                            4, 2,        /* K */
 104                                            BIT(31),     /* gate */
 105                                            BIT(28),     /* lock */
 106                                            2,           /* post-div */
 107                                            CLK_SET_RATE_UNGATE);
 108
 109 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
 110                                         "osc24M", 0x038,
 111                                         8, 7,           /* N */
 112                                         0, 4,           /* M */
 113                                         BIT(24),        /* frac enable */
 114                                         BIT(25),        /* frac select */
 115                                         270000000,      /* frac rate 0 */
 116                                         297000000,      /* frac rate 1 */
 117                                         BIT(31),        /* gate */
 118                                         BIT(28),        /* lock */
 119                                         CLK_SET_RATE_UNGATE);
 120
 121 /*
 122  * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
 123  *
 124  * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
 125  * integer / fractional clock with switchable multipliers and dividers.
 126  * This is not supported here. We hardcode the PLL to MIPI mode.
 127  */
 128 #define SUN8I_A33_PLL_MIPI_REG  0x040
 129 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
 130                                     "pll-video", 0x040,
 131                                     8, 4,               /* N */
 132                                     4, 2,               /* K */
 133                                     0, 4,               /* M */
 134                                     BIT(31) | BIT(23) | BIT(22), /* gate */
 135                                     BIT(28),            /* lock */
 136                                     CLK_SET_RATE_UNGATE);
 137
 138 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
 139                                         "osc24M", 0x044,
 140                                         8, 7,           /* N */
 141                                         0, 4,           /* M */
 142                                         BIT(24),        /* frac enable */
 143                                         BIT(25),        /* frac select */
 144                                         270000000,      /* frac rate 0 */
 145                                         297000000,      /* frac rate 1 */
 146                                         BIT(31),        /* gate */
 147                                         BIT(28),        /* lock */
 148                                         CLK_SET_RATE_UNGATE);
 149
 150 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
 151                                         "osc24M", 0x048,
 152                                         8, 7,           /* N */
 153                                         0, 4,           /* M */
 154                                         BIT(24),        /* frac enable */
 155                                         BIT(25),        /* frac select */
 156                                         270000000,      /* frac rate 0 */
 157                                         297000000,      /* frac rate 1 */
 158                                         BIT(31),        /* gate */
 159                                         BIT(28),        /* lock */
 160                                         CLK_SET_RATE_UNGATE);
 161
 162 /* TODO: Fix N */
 163 static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
 164                                   "osc24M", 0x04c,
 165                                   8, 6,                 /* N */
 166                                   BIT(31),              /* gate */
 167                                   BIT(28),              /* lock */
 168                                   CLK_SET_RATE_UNGATE);
 169
 170 static const char * const cpux_parents[] = { "osc32k", "osc24M",
 171                                              "pll-cpux" , "pll-cpux" };
 172 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
 173                      0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
 174
 175 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 176
 177 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 178                                              "axi" , "pll-periph" };
 179 static struct ccu_div ahb1_clk = {
 180         .div            = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 181
 182         .mux            = {
 183                 .shift  = 12,
 184                 .width  = 2,
 185
 186                 .variable_prediv        = {
 187                         .index  = 3,
 188                         .shift  = 6,
 189                         .width  = 2,
 190                 },
 191         },
 192
 193         .common         = {
 194                 .reg            = 0x054,
 195                 .features       = CCU_FEATURE_VARIABLE_PREDIV,
 196                 .hw.init        = CLK_HW_INIT_PARENTS("ahb1",
 197                                                       ahb1_parents,
 198                                                       &ccu_div_ops,
 199                                                       0),
 200         },
 201 };
 202
 203 static struct clk_div_table apb1_div_table[] = {
 204         { .val = 0, .div = 2 },
 205         { .val = 1, .div = 2 },
 206         { .val = 2, .div = 4 },
 207         { .val = 3, .div = 8 },
 208         { /* Sentinel */ },
 209 };
 210 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
 211                            0x054, 8, 2, apb1_div_table, 0);
 212
 213 static const char * const apb2_parents[] = { "osc32k", "osc24M",
 214                                              "pll-periph" , "pll-periph" };
 215 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
 216                              0, 5,      /* M */
 217                              16, 2,     /* P */
 218                              24, 2,     /* mux */
 219                              0);
 220
 221 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
 222                       0x060, BIT(1), 0);
 223 static SUNXI_CCU_GATE(bus_ss_clk,       "bus-ss",       "ahb1",
 224                       0x060, BIT(5), 0);
 225 static SUNXI_CCU_GATE(bus_dma_clk,      "bus-dma",      "ahb1",
 226                       0x060, BIT(6), 0);
 227 static SUNXI_CCU_GATE(bus_mmc0_clk,     "bus-mmc0",     "ahb1",
 228                       0x060, BIT(8), 0);
 229 static SUNXI_CCU_GATE(bus_mmc1_clk,     "bus-mmc1",     "ahb1",
 230                       0x060, BIT(9), 0);
 231 static SUNXI_CCU_GATE(bus_mmc2_clk,     "bus-mmc2",     "ahb1",
 232                       0x060, BIT(10), 0);
 233 static SUNXI_CCU_GATE(bus_nand_clk,     "bus-nand",     "ahb1",
 234                       0x060, BIT(13), 0);
 235 static SUNXI_CCU_GATE(bus_dram_clk,     "bus-dram",     "ahb1",
 236                       0x060, BIT(14), 0);
 237 static SUNXI_CCU_GATE(bus_hstimer_clk,  "bus-hstimer",  "ahb1",
 238                       0x060, BIT(19), 0);
 239 static SUNXI_CCU_GATE(bus_spi0_clk,     "bus-spi0",     "ahb1",
 240                       0x060, BIT(20), 0);
 241 static SUNXI_CCU_GATE(bus_spi1_clk,     "bus-spi1",     "ahb1",
 242                       0x060, BIT(21), 0);
 243 static SUNXI_CCU_GATE(bus_otg_clk,      "bus-otg",      "ahb1",
 244                       0x060, BIT(24), 0);
 245 static SUNXI_CCU_GATE(bus_ehci_clk,     "bus-ehci",     "ahb1",
 246                       0x060, BIT(26), 0);
 247 static SUNXI_CCU_GATE(bus_ohci_clk,     "bus-ohci",     "ahb1",
 248                       0x060, BIT(29), 0);
 249
 250 static SUNXI_CCU_GATE(bus_ve_clk,       "bus-ve",       "ahb1",
 251                       0x064, BIT(0), 0);
 252 static SUNXI_CCU_GATE(bus_lcd_clk,      "bus-lcd",      "ahb1",
 253                       0x064, BIT(4), 0);
 254 static SUNXI_CCU_GATE(bus_csi_clk,      "bus-csi",      "ahb1",
 255                       0x064, BIT(8), 0);
 256 static SUNXI_CCU_GATE(bus_de_be_clk,    "bus-de-be",    "ahb1",
 257                       0x064, BIT(12), 0);
 258 static SUNXI_CCU_GATE(bus_de_fe_clk,    "bus-de-fe",    "ahb1",
 259                       0x064, BIT(14), 0);
 260 static SUNXI_CCU_GATE(bus_gpu_clk,      "bus-gpu",      "ahb1",
 261                       0x064, BIT(20), 0);
 262 static SUNXI_CCU_GATE(bus_msgbox_clk,   "bus-msgbox",   "ahb1",
 263                       0x064, BIT(21), 0);
 264 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
 265                       0x064, BIT(22), 0);
 266 static SUNXI_CCU_GATE(bus_drc_clk,      "bus-drc",      "ahb1",
 267                       0x064, BIT(25), 0);
 268 static SUNXI_CCU_GATE(bus_sat_clk,      "bus-sat",      "ahb1",
 269                       0x064, BIT(26), 0);
 270
 271 static SUNXI_CCU_GATE(bus_codec_clk,    "bus-codec",    "apb1",
 272                       0x068, BIT(0), 0);
 273 static SUNXI_CCU_GATE(bus_pio_clk,      "bus-pio",      "apb1",
 274                       0x068, BIT(5), 0);
 275 static SUNXI_CCU_GATE(bus_i2s0_clk,     "bus-i2s0",     "apb1",
 276                       0x068, BIT(12), 0);
 277 static SUNXI_CCU_GATE(bus_i2s1_clk,     "bus-i2s1",     "apb1",
 278                       0x068, BIT(13), 0);
 279
 280 static SUNXI_CCU_GATE(bus_i2c0_clk,     "bus-i2c0",     "apb2",
 281                       0x06c, BIT(0), 0);
 282 static SUNXI_CCU_GATE(bus_i2c1_clk,     "bus-i2c1",     "apb2",
 283                       0x06c, BIT(1), 0);
 284 static SUNXI_CCU_GATE(bus_i2c2_clk,     "bus-i2c2",     "apb2",
 285                       0x06c, BIT(2), 0);
 286 static SUNXI_CCU_GATE(bus_uart0_clk,    "bus-uart0",    "apb2",
 287                       0x06c, BIT(16), 0);
 288 static SUNXI_CCU_GATE(bus_uart1_clk,    "bus-uart1",    "apb2",
 289                       0x06c, BIT(17), 0);
 290 static SUNXI_CCU_GATE(bus_uart2_clk,    "bus-uart2",    "apb2",
 291                       0x06c, BIT(18), 0);
 292 static SUNXI_CCU_GATE(bus_uart3_clk,    "bus-uart3",    "apb2",
 293                       0x06c, BIT(19), 0);
 294 static SUNXI_CCU_GATE(bus_uart4_clk,    "bus-uart4",    "apb2",
 295                       0x06c, BIT(20), 0);
 296
 297 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
 298 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
 299                                   0, 4,         /* M */
 300                                   16, 2,        /* P */
 301                                   24, 2,        /* mux */
 302                                   BIT(31),      /* gate */
 303                                   0);
 304
 305 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
 306                                   0, 4,         /* M */
 307                                   16, 2,        /* P */
 308                                   24, 2,        /* mux */
 309                                   BIT(31),      /* gate */
 310                                   0);
 311
 312 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
 313                        0x088, 20, 3, 0);
 314 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
 315                        0x088, 8, 3, 0);
 316
 317 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
 318                                   0, 4,         /* M */
 319                                   16, 2,        /* P */
 320                                   24, 2,        /* mux */
 321                                   BIT(31),      /* gate */
 322                                   0);
 323
 324 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
 325                        0x08c, 20, 3, 0);
 326 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
 327                        0x08c, 8, 3, 0);
 328
 329 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
 330                                   0, 4,         /* M */
 331                                   16, 2,        /* P */
 332                                   24, 2,        /* mux */
 333                                   BIT(31),      /* gate */
 334                                   0);
 335
 336 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
 337                        0x090, 20, 3, 0);
 338 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
 339                        0x090, 8, 3, 0);
 340
 341 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
 342                                   0, 4,         /* M */
 343                                   16, 2,        /* P */
 344                                   24, 2,        /* mux */
 345                                   BIT(31),      /* gate */
 346                                   0);
 347
 348 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
 349                                   0, 4,         /* M */
 350                                   16, 2,        /* P */
 351                                   24, 2,        /* mux */
 352                                   BIT(31),      /* gate */
 353                                   0);
 354
 355 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
 356                                   0, 4,         /* M */
 357                                   16, 2,        /* P */
 358                                   24, 2,        /* mux */
 359                                   BIT(31),      /* gate */
 360                                   0);
 361
 362 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
 363                                             "pll-audio-2x", "pll-audio" };
 364 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
 365                                0x0b0, 16, 2, BIT(31), 0);
 366
 367 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
 368                                0x0b4, 16, 2, BIT(31), 0);
 369
 370 /* TODO: the parent for most of the USB clocks is not known */
 371 static SUNXI_CCU_GATE(usb_phy0_clk,     "usb-phy0",     "osc24M",
 372                       0x0cc, BIT(8), 0);
 373 static SUNXI_CCU_GATE(usb_phy1_clk,     "usb-phy1",     "osc24M",
 374                       0x0cc, BIT(9), 0);
 375 static SUNXI_CCU_GATE(usb_hsic_clk,     "usb-hsic",     "pll-hsic",
 376                       0x0cc, BIT(10), 0);
 377 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
 378                       0x0cc, BIT(11), 0);
 379 static SUNXI_CCU_GATE(usb_ohci_clk,     "usb-ohci",     "osc24M",
 380                       0x0cc, BIT(16), 0);
 381
 382 static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr",
 383                    0x0f4, 0, 4, CLK_IS_CRITICAL);
 384
 385 static const char * const pll_ddr_parents[] = { "pll-ddr0", "pll-ddr1" };
 386 static SUNXI_CCU_MUX(pll_ddr_clk, "pll-ddr", pll_ddr_parents,
 387                      0x0f8, 16, 1, 0);
 388
 389 static SUNXI_CCU_GATE(dram_ve_clk,      "dram-ve",      "dram",
 390                       0x100, BIT(0), 0);
 391 static SUNXI_CCU_GATE(dram_csi_clk,     "dram-csi",     "dram",
 392                       0x100, BIT(1), 0);
 393 static SUNXI_CCU_GATE(dram_drc_clk,     "dram-drc",     "dram",
 394                       0x100, BIT(16), 0);
 395 static SUNXI_CCU_GATE(dram_de_fe_clk,   "dram-de-fe",   "dram",
 396                       0x100, BIT(24), 0);
 397 static SUNXI_CCU_GATE(dram_de_be_clk,   "dram-de-be",   "dram",
 398                       0x100, BIT(26), 0);
 399
 400 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
 401                                            "pll-gpu", "pll-de" };
 402 static const u8 de_table[] = { 0, 2, 3, 5 };
 403 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
 404                                        de_parents, de_table,
 405                                        0x104, 0, 4, 24, 3, BIT(31), 0);
 406
 407 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
 408                                        de_parents, de_table,
 409                                        0x10c, 0, 4, 24, 3, BIT(31), 0);
 410
 411 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
 412                                                 "pll-mipi" };
 413 static const u8 lcd_ch0_table[] = { 0, 2, 4 };
 414 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
 415                                      lcd_ch0_parents, lcd_ch0_table,
 416                                      0x118, 24, 3, BIT(31),
 417                                      CLK_SET_RATE_PARENT);
 418
 419 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
 420 static const u8 lcd_ch1_table[] = { 0, 2 };
 421 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
 422                                        lcd_ch1_parents, lcd_ch1_table,
 423                                        0x12c, 0, 4, 24, 2, BIT(31), 0);
 424
 425 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
 426                                                  "pll-mipi", "pll-ve" };
 427 static const u8 csi_sclk_table[] = { 0, 3, 4, 5 };
 428 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
 429                                        csi_sclk_parents, csi_sclk_table,
 430                                        0x134, 16, 4, 24, 3, BIT(31), 0);
 431
 432 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
 433                                                  "osc24M" };
 434 static const u8 csi_mclk_table[] = { 0, 3, 5 };
 435 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
 436                                        csi_mclk_parents, csi_mclk_table,
 437                                        0x134, 0, 5, 8, 3, BIT(15), 0);
 438
 439 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
 440                              0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
 441
 442 static SUNXI_CCU_GATE(ac_dig_clk,       "ac-dig",       "pll-audio",
 443                       0x140, BIT(31), CLK_SET_RATE_PARENT);
 444 static SUNXI_CCU_GATE(ac_dig_4x_clk,    "ac-dig-4x",    "pll-audio-4x",
 445                       0x140, BIT(30), 0);
 446 static SUNXI_CCU_GATE(avs_clk,          "avs",          "osc24M",
 447                       0x144, BIT(31), 0);
 448
 449 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
 450                                              "pll-ddr0", "pll-ddr1" };
 451 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
 452                                  0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
 453
 454 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
 455 static const u8 dsi_sclk_table[] = { 0, 2 };
 456 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
 457                                        dsi_sclk_parents, dsi_sclk_table,
 458                                        0x168, 16, 4, 24, 2, BIT(31), 0);
 459
 460 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
 461 static const u8 dsi_dphy_table[] = { 0, 2 };
 462 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
 463                                        dsi_dphy_parents, dsi_dphy_table,
 464                                        0x168, 0, 4, 8, 2, BIT(15), 0);
 465
 466 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
 467                                        de_parents, de_table,
 468                                        0x180, 0, 4, 24, 3, BIT(31), 0);
 469
 470 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
 471                              0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
 472
 473 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
 474 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
 475                                  0x1b0, 0, 3, 24, 2, BIT(31), 0);
 476
 477 static struct ccu_common *sun8i_a33_ccu_clks[] = {
 478         &pll_cpux_clk.common,
 479         &pll_audio_base_clk.common,
 480         &pll_video_clk.common,
 481         &pll_ve_clk.common,
 482         &pll_ddr0_clk.common,
 483         &pll_periph_clk.common,
 484         &pll_gpu_clk.common,
 485         &pll_mipi_clk.common,
 486         &pll_hsic_clk.common,
 487         &pll_de_clk.common,
 488         &pll_ddr1_clk.common,
 489         &pll_ddr_clk.common,
 490         &cpux_clk.common,
 491         &axi_clk.common,
 492         &ahb1_clk.common,
 493         &apb1_clk.common,
 494         &apb2_clk.common,
 495         &bus_mipi_dsi_clk.common,
 496         &bus_ss_clk.common,
 497         &bus_dma_clk.common,
 498         &bus_mmc0_clk.common,
 499         &bus_mmc1_clk.common,
 500         &bus_mmc2_clk.common,
 501         &bus_nand_clk.common,
 502         &bus_dram_clk.common,
 503         &bus_hstimer_clk.common,
 504         &bus_spi0_clk.common,
 505         &bus_spi1_clk.common,
 506         &bus_otg_clk.common,
 507         &bus_ehci_clk.common,
 508         &bus_ohci_clk.common,
 509         &bus_ve_clk.common,
 510         &bus_lcd_clk.common,
 511         &bus_csi_clk.common,
 512         &bus_de_fe_clk.common,
 513         &bus_de_be_clk.common,
 514         &bus_gpu_clk.common,
 515         &bus_msgbox_clk.common,
 516         &bus_spinlock_clk.common,
 517         &bus_drc_clk.common,
 518         &bus_sat_clk.common,
 519         &bus_codec_clk.common,
 520         &bus_pio_clk.common,
 521         &bus_i2s0_clk.common,
 522         &bus_i2s1_clk.common,
 523         &bus_i2c0_clk.common,
 524         &bus_i2c1_clk.common,
 525         &bus_i2c2_clk.common,
 526         &bus_uart0_clk.common,
 527         &bus_uart1_clk.common,
 528         &bus_uart2_clk.common,
 529         &bus_uart3_clk.common,
 530         &bus_uart4_clk.common,
 531         &nand_clk.common,
 532         &mmc0_clk.common,
 533         &mmc0_sample_clk.common,
 534         &mmc0_output_clk.common,
 535         &mmc1_clk.common,
 536         &mmc1_sample_clk.common,
 537         &mmc1_output_clk.common,
 538         &mmc2_clk.common,
 539         &mmc2_sample_clk.common,
 540         &mmc2_output_clk.common,
 541         &ss_clk.common,
 542         &spi0_clk.common,
 543         &spi1_clk.common,
 544         &i2s0_clk.common,
 545         &i2s1_clk.common,
 546         &usb_phy0_clk.common,
 547         &usb_phy1_clk.common,
 548         &usb_hsic_clk.common,
 549         &usb_hsic_12M_clk.common,
 550         &usb_ohci_clk.common,
 551         &dram_clk.common,
 552         &dram_ve_clk.common,
 553         &dram_csi_clk.common,
 554         &dram_drc_clk.common,
 555         &dram_de_fe_clk.common,
 556         &dram_de_be_clk.common,
 557         &de_be_clk.common,
 558         &de_fe_clk.common,
 559         &lcd_ch0_clk.common,
 560         &lcd_ch1_clk.common,
 561         &csi_sclk_clk.common,
 562         &csi_mclk_clk.common,
 563         &ve_clk.common,
 564         &ac_dig_clk.common,
 565         &ac_dig_4x_clk.common,
 566         &avs_clk.common,
 567         &mbus_clk.common,
 568         &dsi_sclk_clk.common,
 569         &dsi_dphy_clk.common,
 570         &drc_clk.common,
 571         &gpu_clk.common,
 572         &ats_clk.common,
 573 };
 574
 575 /* We hardcode the divider to 4 for now */
 576 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
 577                         "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
 578 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
 579                         "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
 580 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
 581                         "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
 582 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
 583                         "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
 584 static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
 585                         "pll-periph", 1, 2, 0);
 586 static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x",
 587                         "pll-video", 1, 2, 0);
 588
 589 static struct clk_hw_onecell_data sun8i_a33_hw_clks = {
 590         .hws    = {
 591                 [CLK_PLL_CPUX]          = &pll_cpux_clk.common.hw,
 592                 [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
 593                 [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
 594                 [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
 595                 [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
 596                 [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
 597                 [CLK_PLL_VIDEO]         = &pll_video_clk.common.hw,
 598                 [CLK_PLL_VIDEO_2X]      = &pll_video_2x_clk.hw,
 599                 [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
 600                 [CLK_PLL_DDR0]          = &pll_ddr0_clk.common.hw,
 601                 [CLK_PLL_PERIPH]        = &pll_periph_clk.common.hw,
 602                 [CLK_PLL_PERIPH_2X]     = &pll_periph_2x_clk.hw,
 603                 [CLK_PLL_GPU]           = &pll_gpu_clk.common.hw,
 604                 [CLK_PLL_MIPI]          = &pll_mipi_clk.common.hw,
 605                 [CLK_PLL_HSIC]          = &pll_hsic_clk.common.hw,
 606                 [CLK_PLL_DE]            = &pll_de_clk.common.hw,
 607                 [CLK_PLL_DDR1]          = &pll_ddr1_clk.common.hw,
 608                 [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
 609                 [CLK_CPUX]              = &cpux_clk.common.hw,
 610                 [CLK_AXI]               = &axi_clk.common.hw,
 611                 [CLK_AHB1]              = &ahb1_clk.common.hw,
 612                 [CLK_APB1]              = &apb1_clk.common.hw,
 613                 [CLK_APB2]              = &apb2_clk.common.hw,
 614                 [CLK_BUS_MIPI_DSI]      = &bus_mipi_dsi_clk.common.hw,
 615                 [CLK_BUS_SS]            = &bus_ss_clk.common.hw,
 616                 [CLK_BUS_DMA]           = &bus_dma_clk.common.hw,
 617                 [CLK_BUS_MMC0]          = &bus_mmc0_clk.common.hw,
 618                 [CLK_BUS_MMC1]          = &bus_mmc1_clk.common.hw,
 619                 [CLK_BUS_MMC2]          = &bus_mmc2_clk.common.hw,
 620                 [CLK_BUS_NAND]          = &bus_nand_clk.common.hw,
 621                 [CLK_BUS_DRAM]          = &bus_dram_clk.common.hw,
 622                 [CLK_BUS_HSTIMER]       = &bus_hstimer_clk.common.hw,
 623                 [CLK_BUS_SPI0]          = &bus_spi0_clk.common.hw,
 624                 [CLK_BUS_SPI1]          = &bus_spi1_clk.common.hw,
 625                 [CLK_BUS_OTG]           = &bus_otg_clk.common.hw,
 626                 [CLK_BUS_EHCI]          = &bus_ehci_clk.common.hw,
 627                 [CLK_BUS_OHCI]          = &bus_ohci_clk.common.hw,
 628                 [CLK_BUS_VE]            = &bus_ve_clk.common.hw,
 629                 [CLK_BUS_LCD]           = &bus_lcd_clk.common.hw,
 630                 [CLK_BUS_CSI]           = &bus_csi_clk.common.hw,
 631                 [CLK_BUS_DE_BE]         = &bus_de_be_clk.common.hw,
 632                 [CLK_BUS_DE_FE]         = &bus_de_fe_clk.common.hw,
 633                 [CLK_BUS_GPU]           = &bus_gpu_clk.common.hw,
 634                 [CLK_BUS_MSGBOX]        = &bus_msgbox_clk.common.hw,
 635                 [CLK_BUS_SPINLOCK]      = &bus_spinlock_clk.common.hw,
 636                 [CLK_BUS_DRC]           = &bus_drc_clk.common.hw,
 637                 [CLK_BUS_SAT]           = &bus_sat_clk.common.hw,
 638                 [CLK_BUS_CODEC]         = &bus_codec_clk.common.hw,
 639                 [CLK_BUS_PIO]           = &bus_pio_clk.common.hw,
 640                 [CLK_BUS_I2S0]          = &bus_i2s0_clk.common.hw,
 641                 [CLK_BUS_I2S1]          = &bus_i2s1_clk.common.hw,
 642                 [CLK_BUS_I2C0]          = &bus_i2c0_clk.common.hw,
 643                 [CLK_BUS_I2C1]          = &bus_i2c1_clk.common.hw,
 644                 [CLK_BUS_I2C2]          = &bus_i2c2_clk.common.hw,
 645                 [CLK_BUS_UART0]         = &bus_uart0_clk.common.hw,
 646                 [CLK_BUS_UART1]         = &bus_uart1_clk.common.hw,
 647                 [CLK_BUS_UART2]         = &bus_uart2_clk.common.hw,
 648                 [CLK_BUS_UART3]         = &bus_uart3_clk.common.hw,
 649                 [CLK_BUS_UART4]         = &bus_uart4_clk.common.hw,
 650                 [CLK_NAND]              = &nand_clk.common.hw,
 651                 [CLK_MMC0]              = &mmc0_clk.common.hw,
 652                 [CLK_MMC0_SAMPLE]       = &mmc0_sample_clk.common.hw,
 653                 [CLK_MMC0_OUTPUT]       = &mmc0_output_clk.common.hw,
 654                 [CLK_MMC1]              = &mmc1_clk.common.hw,
 655                 [CLK_MMC1_SAMPLE]       = &mmc1_sample_clk.common.hw,
 656                 [CLK_MMC1_OUTPUT]       = &mmc1_output_clk.common.hw,
 657                 [CLK_MMC2]              = &mmc2_clk.common.hw,
 658                 [CLK_MMC2_SAMPLE]       = &mmc2_sample_clk.common.hw,
 659                 [CLK_MMC2_OUTPUT]       = &mmc2_output_clk.common.hw,
 660                 [CLK_SS]                = &ss_clk.common.hw,
 661                 [CLK_SPI0]              = &spi0_clk.common.hw,
 662                 [CLK_SPI1]              = &spi1_clk.common.hw,
 663                 [CLK_I2S0]              = &i2s0_clk.common.hw,
 664                 [CLK_I2S1]              = &i2s1_clk.common.hw,
 665                 [CLK_USB_PHY0]          = &usb_phy0_clk.common.hw,
 666                 [CLK_USB_PHY1]          = &usb_phy1_clk.common.hw,
 667                 [CLK_USB_HSIC]          = &usb_hsic_clk.common.hw,
 668                 [CLK_USB_HSIC_12M]      = &usb_hsic_12M_clk.common.hw,
 669                 [CLK_USB_OHCI]          = &usb_ohci_clk.common.hw,
 670                 [CLK_DRAM]              = &dram_clk.common.hw,
 671                 [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
 672                 [CLK_DRAM_CSI]          = &dram_csi_clk.common.hw,
 673                 [CLK_DRAM_DRC]          = &dram_drc_clk.common.hw,
 674                 [CLK_DRAM_DE_FE]        = &dram_de_fe_clk.common.hw,
 675                 [CLK_DRAM_DE_BE]        = &dram_de_be_clk.common.hw,
 676                 [CLK_DE_BE]             = &de_be_clk.common.hw,
 677                 [CLK_DE_FE]             = &de_fe_clk.common.hw,
 678                 [CLK_LCD_CH0]           = &lcd_ch0_clk.common.hw,
 679                 [CLK_LCD_CH1]           = &lcd_ch1_clk.common.hw,
 680                 [CLK_CSI_SCLK]          = &csi_sclk_clk.common.hw,
 681                 [CLK_CSI_MCLK]          = &csi_mclk_clk.common.hw,
 682                 [CLK_VE]                = &ve_clk.common.hw,
 683                 [CLK_AC_DIG]            = &ac_dig_clk.common.hw,
 684                 [CLK_AC_DIG_4X]         = &ac_dig_4x_clk.common.hw,
 685                 [CLK_AVS]               = &avs_clk.common.hw,
 686                 [CLK_MBUS]              = &mbus_clk.common.hw,
 687                 [CLK_DSI_SCLK]          = &dsi_sclk_clk.common.hw,
 688                 [CLK_DSI_DPHY]          = &dsi_dphy_clk.common.hw,
 689                 [CLK_DRC]               = &drc_clk.common.hw,
 690                 [CLK_GPU]               = &gpu_clk.common.hw,
 691                 [CLK_ATS]               = &ats_clk.common.hw,
 692         },
 693         .num    = CLK_NUMBER,
 694 };
 695
 696 static struct ccu_reset_map sun8i_a33_ccu_resets[] = {
 697         [RST_USB_PHY0]          =  { 0x0cc, BIT(0) },
 698         [RST_USB_PHY1]          =  { 0x0cc, BIT(1) },
 699         [RST_USB_HSIC]          =  { 0x0cc, BIT(2) },
 700
 701         [RST_MBUS]              =  { 0x0fc, BIT(31) },
 702
 703         [RST_BUS_MIPI_DSI]      =  { 0x2c0, BIT(1) },
 704         [RST_BUS_SS]            =  { 0x2c0, BIT(5) },
 705         [RST_BUS_DMA]           =  { 0x2c0, BIT(6) },
 706         [RST_BUS_MMC0]          =  { 0x2c0, BIT(8) },
 707         [RST_BUS_MMC1]          =  { 0x2c0, BIT(9) },
 708         [RST_BUS_MMC2]          =  { 0x2c0, BIT(10) },
 709         [RST_BUS_NAND]          =  { 0x2c0, BIT(13) },
 710         [RST_BUS_DRAM]          =  { 0x2c0, BIT(14) },
 711         [RST_BUS_HSTIMER]       =  { 0x2c0, BIT(19) },
 712         [RST_BUS_SPI0]          =  { 0x2c0, BIT(20) },
 713         [RST_BUS_SPI1]          =  { 0x2c0, BIT(21) },
 714         [RST_BUS_OTG]           =  { 0x2c0, BIT(24) },
 715         [RST_BUS_EHCI]          =  { 0x2c0, BIT(26) },
 716         [RST_BUS_OHCI]          =  { 0x2c0, BIT(29) },
 717
 718         [RST_BUS_VE]            =  { 0x2c4, BIT(0) },
 719         [RST_BUS_LCD]           =  { 0x2c4, BIT(4) },
 720         [RST_BUS_CSI]           =  { 0x2c4, BIT(8) },
 721         [RST_BUS_DE_BE]         =  { 0x2c4, BIT(12) },
 722         [RST_BUS_DE_FE]         =  { 0x2c4, BIT(14) },
 723         [RST_BUS_GPU]           =  { 0x2c4, BIT(20) },
 724         [RST_BUS_MSGBOX]        =  { 0x2c4, BIT(21) },
 725         [RST_BUS_SPINLOCK]      =  { 0x2c4, BIT(22) },
 726         [RST_BUS_DRC]           =  { 0x2c4, BIT(25) },
 727         [RST_BUS_SAT]           =  { 0x2c4, BIT(26) },
 728
 729         [RST_BUS_LVDS]          =  { 0x2c8, BIT(0) },
 730
 731         [RST_BUS_CODEC]         =  { 0x2d0, BIT(0) },
 732         [RST_BUS_I2S0]          =  { 0x2d0, BIT(12) },
 733         [RST_BUS_I2S1]          =  { 0x2d0, BIT(13) },
 734
 735         [RST_BUS_I2C0]          =  { 0x2d8, BIT(0) },
 736         [RST_BUS_I2C1]          =  { 0x2d8, BIT(1) },
 737         [RST_BUS_I2C2]          =  { 0x2d8, BIT(2) },
 738         [RST_BUS_UART0]         =  { 0x2d8, BIT(16) },
 739         [RST_BUS_UART1]         =  { 0x2d8, BIT(17) },
 740         [RST_BUS_UART2]         =  { 0x2d8, BIT(18) },
 741         [RST_BUS_UART3]         =  { 0x2d8, BIT(19) },
 742         [RST_BUS_UART4]         =  { 0x2d8, BIT(20) },
 743 };
 744
 745 static const struct sunxi_ccu_desc sun8i_a33_ccu_desc = {
 746         .ccu_clks       = sun8i_a33_ccu_clks,
 747         .num_ccu_clks   = ARRAY_SIZE(sun8i_a33_ccu_clks),
 748
 749         .hw_clks        = &sun8i_a33_hw_clks,
 750
 751         .resets         = sun8i_a33_ccu_resets,
 752         .num_resets     = ARRAY_SIZE(sun8i_a33_ccu_resets),
 753 };
 754
 755 static struct ccu_pll_nb sun8i_a33_pll_cpu_nb = {
 756         .common = &pll_cpux_clk.common,
 757         /* copy from pll_cpux_clk */
 758         .enable = BIT(31),
 759         .lock   = BIT(28),
 760 };
 761
 762 static struct ccu_mux_nb sun8i_a33_cpu_nb = {
 763         .common         = &cpux_clk.common,
 764         .cm             = &cpux_clk.mux,
 765         .delay_us       = 1, /* > 8 clock cycles at 24 MHz */
 766         .bypass_index   = 1, /* index of 24 MHz oscillator */
 767 };
 768
 769 static void __init sun8i_a33_ccu_setup(struct device_node *node)
 770 {
 771         void __iomem *reg;
 772         u32 val;
 773
 774         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
 775         if (IS_ERR(reg)) {
 776                 pr_err("%s: Could not map the clock registers\n",
 777                        of_node_full_name(node));
 778                 return;
 779         }
 780
 781         /* Force the PLL-Audio-1x divider to 4 */
 782         val = readl(reg + SUN8I_A33_PLL_AUDIO_REG);
 783         val &= ~GENMASK(19, 16);
 784         writel(val | (3 << 16), reg + SUN8I_A33_PLL_AUDIO_REG);
 785
 786         /* Force PLL-MIPI to MIPI mode */
 787         val = readl(reg + SUN8I_A33_PLL_MIPI_REG);
 788         val &= ~BIT(16);
 789         writel(val, reg + SUN8I_A33_PLL_MIPI_REG);
 790
 791         sunxi_ccu_probe(node, reg, &sun8i_a33_ccu_desc);
 792
 793         /* Gate then ungate PLL CPU after any rate changes */
 794         ccu_pll_notifier_register(&sun8i_a33_pll_cpu_nb);
 795
 796         /* Reparent CPU during PLL CPU rate changes */
 797         ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
 798                                   &sun8i_a33_cpu_nb);
 799 }
 800 CLK_OF_DECLARE(sun8i_a33_ccu, "allwinner,sun8i-a33-ccu",
 801                sun8i_a33_ccu_setup);