drivers/clk/samsung/clk-exynos5433.c

   1 /*
   2  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   3  * Author: Chanwoo Choi <cw00.choi@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * Common Clock Framework support for Exynos5433 SoC.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19
  20 #include <dt-bindings/clock/exynos5433.h>
  21
  22 #include "clk.h"
  23 #include "clk-cpu.h"
  24 #include "clk-pll.h"
  25
  26 /*
  27  * Register offset definitions for CMU_TOP
  28  */
  29 #define ISP_PLL_LOCK                    0x0000
  30 #define AUD_PLL_LOCK                    0x0004
  31 #define ISP_PLL_CON0                    0x0100
  32 #define ISP_PLL_CON1                    0x0104
  33 #define ISP_PLL_FREQ_DET                0x0108
  34 #define AUD_PLL_CON0                    0x0110
  35 #define AUD_PLL_CON1                    0x0114
  36 #define AUD_PLL_CON2                    0x0118
  37 #define AUD_PLL_FREQ_DET                0x011c
  38 #define MUX_SEL_TOP0                    0x0200
  39 #define MUX_SEL_TOP1                    0x0204
  40 #define MUX_SEL_TOP2                    0x0208
  41 #define MUX_SEL_TOP3                    0x020c
  42 #define MUX_SEL_TOP4                    0x0210
  43 #define MUX_SEL_TOP_MSCL                0x0220
  44 #define MUX_SEL_TOP_CAM1                0x0224
  45 #define MUX_SEL_TOP_DISP                0x0228
  46 #define MUX_SEL_TOP_FSYS0               0x0230
  47 #define MUX_SEL_TOP_FSYS1               0x0234
  48 #define MUX_SEL_TOP_PERIC0              0x0238
  49 #define MUX_SEL_TOP_PERIC1              0x023c
  50 #define MUX_ENABLE_TOP0                 0x0300
  51 #define MUX_ENABLE_TOP1                 0x0304
  52 #define MUX_ENABLE_TOP2                 0x0308
  53 #define MUX_ENABLE_TOP3                 0x030c
  54 #define MUX_ENABLE_TOP4                 0x0310
  55 #define MUX_ENABLE_TOP_MSCL             0x0320
  56 #define MUX_ENABLE_TOP_CAM1             0x0324
  57 #define MUX_ENABLE_TOP_DISP             0x0328
  58 #define MUX_ENABLE_TOP_FSYS0            0x0330
  59 #define MUX_ENABLE_TOP_FSYS1            0x0334
  60 #define MUX_ENABLE_TOP_PERIC0           0x0338
  61 #define MUX_ENABLE_TOP_PERIC1           0x033c
  62 #define MUX_STAT_TOP0                   0x0400
  63 #define MUX_STAT_TOP1                   0x0404
  64 #define MUX_STAT_TOP2                   0x0408
  65 #define MUX_STAT_TOP3                   0x040c
  66 #define MUX_STAT_TOP4                   0x0410
  67 #define MUX_STAT_TOP_MSCL               0x0420
  68 #define MUX_STAT_TOP_CAM1               0x0424
  69 #define MUX_STAT_TOP_FSYS0              0x0430
  70 #define MUX_STAT_TOP_FSYS1              0x0434
  71 #define MUX_STAT_TOP_PERIC0             0x0438
  72 #define MUX_STAT_TOP_PERIC1             0x043c
  73 #define DIV_TOP0                        0x0600
  74 #define DIV_TOP1                        0x0604
  75 #define DIV_TOP2                        0x0608
  76 #define DIV_TOP3                        0x060c
  77 #define DIV_TOP4                        0x0610
  78 #define DIV_TOP_MSCL                    0x0618
  79 #define DIV_TOP_CAM10                   0x061c
  80 #define DIV_TOP_CAM11                   0x0620
  81 #define DIV_TOP_FSYS0                   0x062c
  82 #define DIV_TOP_FSYS1                   0x0630
  83 #define DIV_TOP_FSYS2                   0x0634
  84 #define DIV_TOP_PERIC0                  0x0638
  85 #define DIV_TOP_PERIC1                  0x063c
  86 #define DIV_TOP_PERIC2                  0x0640
  87 #define DIV_TOP_PERIC3                  0x0644
  88 #define DIV_TOP_PERIC4                  0x0648
  89 #define DIV_TOP_PLL_FREQ_DET            0x064c
  90 #define DIV_STAT_TOP0                   0x0700
  91 #define DIV_STAT_TOP1                   0x0704
  92 #define DIV_STAT_TOP2                   0x0708
  93 #define DIV_STAT_TOP3                   0x070c
  94 #define DIV_STAT_TOP4                   0x0710
  95 #define DIV_STAT_TOP_MSCL               0x0718
  96 #define DIV_STAT_TOP_CAM10              0x071c
  97 #define DIV_STAT_TOP_CAM11              0x0720
  98 #define DIV_STAT_TOP_FSYS0              0x072c
  99 #define DIV_STAT_TOP_FSYS1              0x0730
 100 #define DIV_STAT_TOP_FSYS2              0x0734
 101 #define DIV_STAT_TOP_PERIC0             0x0738
 102 #define DIV_STAT_TOP_PERIC1             0x073c
 103 #define DIV_STAT_TOP_PERIC2             0x0740
 104 #define DIV_STAT_TOP_PERIC3             0x0744
 105 #define DIV_STAT_TOP_PLL_FREQ_DET       0x074c
 106 #define ENABLE_ACLK_TOP                 0x0800
 107 #define ENABLE_SCLK_TOP                 0x0a00
 108 #define ENABLE_SCLK_TOP_MSCL            0x0a04
 109 #define ENABLE_SCLK_TOP_CAM1            0x0a08
 110 #define ENABLE_SCLK_TOP_DISP            0x0a0c
 111 #define ENABLE_SCLK_TOP_FSYS            0x0a10
 112 #define ENABLE_SCLK_TOP_PERIC           0x0a14
 113 #define ENABLE_IP_TOP                   0x0b00
 114 #define ENABLE_CMU_TOP                  0x0c00
 115 #define ENABLE_CMU_TOP_DIV_STAT         0x0c04
 116
 117 static const unsigned long top_clk_regs[] __initconst = {
 118         ISP_PLL_LOCK,
 119         AUD_PLL_LOCK,
 120         ISP_PLL_CON0,
 121         ISP_PLL_CON1,
 122         ISP_PLL_FREQ_DET,
 123         AUD_PLL_CON0,
 124         AUD_PLL_CON1,
 125         AUD_PLL_CON2,
 126         AUD_PLL_FREQ_DET,
 127         MUX_SEL_TOP0,
 128         MUX_SEL_TOP1,
 129         MUX_SEL_TOP2,
 130         MUX_SEL_TOP3,
 131         MUX_SEL_TOP4,
 132         MUX_SEL_TOP_MSCL,
 133         MUX_SEL_TOP_CAM1,
 134         MUX_SEL_TOP_DISP,
 135         MUX_SEL_TOP_FSYS0,
 136         MUX_SEL_TOP_FSYS1,
 137         MUX_SEL_TOP_PERIC0,
 138         MUX_SEL_TOP_PERIC1,
 139         MUX_ENABLE_TOP0,
 140         MUX_ENABLE_TOP1,
 141         MUX_ENABLE_TOP2,
 142         MUX_ENABLE_TOP3,
 143         MUX_ENABLE_TOP4,
 144         MUX_ENABLE_TOP_MSCL,
 145         MUX_ENABLE_TOP_CAM1,
 146         MUX_ENABLE_TOP_DISP,
 147         MUX_ENABLE_TOP_FSYS0,
 148         MUX_ENABLE_TOP_FSYS1,
 149         MUX_ENABLE_TOP_PERIC0,
 150         MUX_ENABLE_TOP_PERIC1,
 151         DIV_TOP0,
 152         DIV_TOP1,
 153         DIV_TOP2,
 154         DIV_TOP3,
 155         DIV_TOP4,
 156         DIV_TOP_MSCL,
 157         DIV_TOP_CAM10,
 158         DIV_TOP_CAM11,
 159         DIV_TOP_FSYS0,
 160         DIV_TOP_FSYS1,
 161         DIV_TOP_FSYS2,
 162         DIV_TOP_PERIC0,
 163         DIV_TOP_PERIC1,
 164         DIV_TOP_PERIC2,
 165         DIV_TOP_PERIC3,
 166         DIV_TOP_PERIC4,
 167         DIV_TOP_PLL_FREQ_DET,
 168         ENABLE_ACLK_TOP,
 169         ENABLE_SCLK_TOP,
 170         ENABLE_SCLK_TOP_MSCL,
 171         ENABLE_SCLK_TOP_CAM1,
 172         ENABLE_SCLK_TOP_DISP,
 173         ENABLE_SCLK_TOP_FSYS,
 174         ENABLE_SCLK_TOP_PERIC,
 175         ENABLE_IP_TOP,
 176         ENABLE_CMU_TOP,
 177         ENABLE_CMU_TOP_DIV_STAT,
 178 };
 179
 180 static const struct samsung_clk_reg_dump top_suspend_regs[] = {
 181         /* force all aclk clocks enabled */
 182         { ENABLE_ACLK_TOP, 0x67ecffed },
 183         /* force all sclk_uart clocks enabled */
 184         { ENABLE_SCLK_TOP_PERIC, 0x38 },
 185         /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
 186         { ISP_PLL_CON0, 0x85cc0502 },
 187         /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
 188         { AUD_PLL_CON0, 0x84830202 },
 189 };
 190
 191 /* list of all parent clock list */
 192 PNAME(mout_aud_pll_p)           = { "oscclk", "fout_aud_pll", };
 193 PNAME(mout_isp_pll_p)           = { "oscclk", "fout_isp_pll", };
 194 PNAME(mout_aud_pll_user_p)      = { "oscclk", "mout_aud_pll", };
 195 PNAME(mout_mphy_pll_user_p)     = { "oscclk", "sclk_mphy_pll", };
 196 PNAME(mout_mfc_pll_user_p)      = { "oscclk", "sclk_mfc_pll", };
 197 PNAME(mout_bus_pll_user_p)      = { "oscclk", "sclk_bus_pll", };
 198 PNAME(mout_bus_pll_user_t_p)    = { "oscclk", "mout_bus_pll_user", };
 199 PNAME(mout_mphy_pll_user_t_p)   = { "oscclk", "mout_mphy_pll_user", };
 200
 201 PNAME(mout_bus_mfc_pll_user_p)  = { "mout_bus_pll_user", "mout_mfc_pll_user",};
 202 PNAME(mout_mfc_bus_pll_user_p)  = { "mout_mfc_pll_user", "mout_bus_pll_user",};
 203 PNAME(mout_aclk_cam1_552_b_p)   = { "mout_aclk_cam1_552_a",
 204                                     "mout_mfc_pll_user", };
 205 PNAME(mout_aclk_cam1_552_a_p)   = { "mout_isp_pll", "mout_bus_pll_user", };
 206
 207 PNAME(mout_aclk_mfc_400_c_p)    = { "mout_aclk_mfc_400_b",
 208                                     "mout_mphy_pll_user", };
 209 PNAME(mout_aclk_mfc_400_b_p)    = { "mout_aclk_mfc_400_a",
 210                                     "mout_bus_pll_user", };
 211 PNAME(mout_aclk_mfc_400_a_p)    = { "mout_mfc_pll_user", "mout_isp_pll", };
 212
 213 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
 214                                     "mout_mphy_pll_user", };
 215 PNAME(mout_aclk_mscl_b_p)       = { "mout_aclk_mscl_400_a",
 216                                     "mout_mphy_pll_user", };
 217 PNAME(mout_aclk_g2d_400_b_p)    = { "mout_aclk_g2d_400_a",
 218                                     "mout_mphy_pll_user", };
 219
 220 PNAME(mout_sclk_jpeg_c_p)       = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
 221 PNAME(mout_sclk_jpeg_b_p)       = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
 222
 223 PNAME(mout_sclk_mmc2_b_p)       = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
 224 PNAME(mout_sclk_mmc1_b_p)       = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
 225 PNAME(mout_sclk_mmc0_d_p)       = { "mout_sclk_mmc0_c", "mout_isp_pll", };
 226 PNAME(mout_sclk_mmc0_c_p)       = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
 227 PNAME(mout_sclk_mmc0_b_p)       = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
 228
 229 PNAME(mout_sclk_spdif_p)        = { "sclk_audio0", "sclk_audio1",
 230                                     "oscclk", "ioclk_spdif_extclk", };
 231 PNAME(mout_sclk_audio1_p)       = { "ioclk_audiocdclk1", "oscclk",
 232                                     "mout_aud_pll_user_t",};
 233 PNAME(mout_sclk_audio0_p)       = { "ioclk_audiocdclk0", "oscclk",
 234                                     "mout_aud_pll_user_t",};
 235
 236 PNAME(mout_sclk_hdmi_spdif_p)   = { "sclk_audio1", "ioclk_spdif_extclk", };
 237
 238 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
 239         FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
 240 };
 241
 242 static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {
 243         /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
 244         FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000),
 245         FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000),
 246         /* Xi2s1SDI input clock for SPDIF */
 247         FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000),
 248         /* XspiCLK[4:0] input clock for SPI */
 249         FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000),
 250         FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000),
 251         FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000),
 252         FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000),
 253         FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000),
 254         /* Xi2s1SCLK input clock for I2S1_BCLK */
 255         FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000),
 256 };
 257
 258 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
 259         /* MUX_SEL_TOP0 */
 260         MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
 261                         4, 1),
 262         MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
 263                         0, 1),
 264
 265         /* MUX_SEL_TOP1 */
 266         MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
 267                         mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
 268         MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
 269                         MUX_SEL_TOP1, 8, 1),
 270         MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
 271                         MUX_SEL_TOP1, 4, 1),
 272         MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
 273                         MUX_SEL_TOP1, 0, 1),
 274
 275         /* MUX_SEL_TOP2 */
 276         MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
 277                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
 278         MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
 279                         mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
 280         MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
 281                         mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
 282         MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
 283                         mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
 284         MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
 285                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
 286         MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
 287                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
 288
 289         /* MUX_SEL_TOP3 */
 290         MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
 291                         mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
 292         MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
 293                         mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
 294         MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
 295                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
 296         MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
 297                         mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
 298         MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
 299                         mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
 300         MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
 301                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
 302
 303         /* MUX_SEL_TOP4 */
 304         MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
 305                         mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
 306         MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
 307                         mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
 308         MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
 309                         mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
 310
 311         /* MUX_SEL_TOP_MSCL */
 312         MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
 313                         MUX_SEL_TOP_MSCL, 8, 1),
 314         MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
 315                         MUX_SEL_TOP_MSCL, 4, 1),
 316         MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
 317                         MUX_SEL_TOP_MSCL, 0, 1),
 318
 319         /* MUX_SEL_TOP_CAM1 */
 320         MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
 321                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
 322         MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
 323                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
 324         MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
 325                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
 326         MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
 327                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
 328         MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
 329                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
 330         MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
 331                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
 332
 333         /* MUX_SEL_TOP_FSYS0 */
 334         MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
 335                         MUX_SEL_TOP_FSYS0, 28, 1),
 336         MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
 337                         MUX_SEL_TOP_FSYS0, 24, 1),
 338         MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
 339                         MUX_SEL_TOP_FSYS0, 20, 1),
 340         MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
 341                         MUX_SEL_TOP_FSYS0, 16, 1),
 342         MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
 343                         MUX_SEL_TOP_FSYS0, 12, 1),
 344         MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
 345                         MUX_SEL_TOP_FSYS0, 8, 1),
 346         MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
 347                         MUX_SEL_TOP_FSYS0, 4, 1),
 348         MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
 349                         MUX_SEL_TOP_FSYS0, 0, 1),
 350
 351         /* MUX_SEL_TOP_FSYS1 */
 352         MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
 353                         MUX_SEL_TOP_FSYS1, 12, 1),
 354         MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
 355                         mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
 356         MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
 357                         mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
 358         MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
 359                         mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
 360
 361         /* MUX_SEL_TOP_PERIC0 */
 362         MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
 363                         MUX_SEL_TOP_PERIC0, 28, 1),
 364         MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
 365                         MUX_SEL_TOP_PERIC0, 24, 1),
 366         MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
 367                         MUX_SEL_TOP_PERIC0, 20, 1),
 368         MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
 369                         MUX_SEL_TOP_PERIC0, 16, 1),
 370         MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
 371                         MUX_SEL_TOP_PERIC0, 12, 1),
 372         MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
 373                         MUX_SEL_TOP_PERIC0, 8, 1),
 374         MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
 375                         MUX_SEL_TOP_PERIC0, 4, 1),
 376         MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
 377                         MUX_SEL_TOP_PERIC0, 0, 1),
 378
 379         /* MUX_SEL_TOP_PERIC1 */
 380         MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
 381                         MUX_SEL_TOP_PERIC1, 16, 1),
 382         MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
 383                         MUX_SEL_TOP_PERIC1, 12, 2),
 384         MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
 385                         MUX_SEL_TOP_PERIC1, 4, 2),
 386         MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
 387                         MUX_SEL_TOP_PERIC1, 0, 2),
 388
 389         /* MUX_SEL_TOP_DISP */
 390         MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
 391                         mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
 392 };
 393
 394 static const struct samsung_div_clock top_div_clks[] __initconst = {
 395         /* DIV_TOP0 */
 396         DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
 397                         DIV_TOP0, 28, 3),
 398         DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user",
 399                         DIV_TOP0, 24, 3),
 400         DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
 401                         DIV_TOP0, 20, 3),
 402         DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user",
 403                         DIV_TOP0, 16, 3),
 404         DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user",
 405                         DIV_TOP0, 12, 3),
 406         DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll",
 407                         DIV_TOP0, 8, 3),
 408         DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
 409                         "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
 410         DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
 411                         "mout_aclk_isp_400", DIV_TOP0, 0, 4),
 412
 413         /* DIV_TOP1 */
 414         DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
 415                         DIV_TOP1, 28, 3),
 416         DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
 417                         DIV_TOP1, 24, 3),
 418         DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
 419                         DIV_TOP1, 20, 3),
 420         DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
 421                         DIV_TOP1, 12, 3),
 422         DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
 423                         DIV_TOP1, 8, 3),
 424         DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
 425                         DIV_TOP1, 0, 3),
 426
 427         /* DIV_TOP2 */
 428         DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
 429                         DIV_TOP2, 4, 3),
 430         DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
 431                         DIV_TOP2, 0, 3),
 432
 433         /* DIV_TOP3 */
 434         DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
 435                         "mout_bus_pll_user", DIV_TOP3, 24, 3),
 436         DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
 437                         "mout_bus_pll_user", DIV_TOP3, 20, 3),
 438         DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
 439                         "mout_bus_pll_user", DIV_TOP3, 16, 3),
 440         DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
 441                         "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
 442         DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
 443                         "mout_bus_pll_user", DIV_TOP3, 8, 3),
 444         DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
 445                         "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
 446         DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
 447                         "mout_bus_pll_user", DIV_TOP3, 0, 3),
 448
 449         /* DIV_TOP4 */
 450         DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
 451                         DIV_TOP4, 8, 3),
 452         DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
 453                         DIV_TOP4, 4, 3),
 454         DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
 455                         DIV_TOP4, 0, 3),
 456
 457         /* DIV_TOP_MSCL */
 458         DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
 459                         DIV_TOP_MSCL, 0, 4),
 460
 461         /* DIV_TOP_CAM10 */
 462         DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart",
 463                         DIV_TOP_CAM10, 24, 5),
 464         DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b",
 465                         "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8),
 466         DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a",
 467                         "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4),
 468         DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b",
 469                         "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8),
 470         DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a",
 471                         "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
 472
 473         /* DIV_TOP_CAM11 */
 474         DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b",
 475                         "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4),
 476         DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a",
 477                         "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4),
 478         DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b",
 479                         "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4),
 480         DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a",
 481                         "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4),
 482         DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b",
 483                         "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4),
 484         DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a",
 485                         "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4),
 486
 487         /* DIV_TOP_FSYS0 */
 488         DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
 489                         DIV_TOP_FSYS0, 16, 8),
 490         DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
 491                         DIV_TOP_FSYS0, 12, 4),
 492         DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
 493                         DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
 494         DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
 495                         DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
 496
 497         /* DIV_TOP_FSYS1 */
 498         DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
 499                         DIV_TOP_FSYS1, 4, 8),
 500         DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
 501                         DIV_TOP_FSYS1, 0, 4),
 502
 503         /* DIV_TOP_FSYS2 */
 504         DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
 505                         DIV_TOP_FSYS2, 12, 3),
 506         DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
 507                         "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
 508         DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
 509                         "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
 510         DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
 511                         DIV_TOP_FSYS2, 0, 4),
 512
 513         /* DIV_TOP_PERIC0 */
 514         DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
 515                         DIV_TOP_PERIC0, 16, 8),
 516         DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
 517                         DIV_TOP_PERIC0, 12, 4),
 518         DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
 519                         DIV_TOP_PERIC0, 4, 8),
 520         DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
 521                         DIV_TOP_PERIC0, 0, 4),
 522
 523         /* DIV_TOP_PERIC1 */
 524         DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
 525                         DIV_TOP_PERIC1, 4, 8),
 526         DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
 527                         DIV_TOP_PERIC1, 0, 4),
 528
 529         /* DIV_TOP_PERIC2 */
 530         DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
 531                         DIV_TOP_PERIC2, 8, 4),
 532         DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
 533                         DIV_TOP_PERIC2, 4, 4),
 534         DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
 535                         DIV_TOP_PERIC2, 0, 4),
 536
 537         /* DIV_TOP_PERIC3 */
 538         DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
 539                         DIV_TOP_PERIC3, 16, 6),
 540         DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
 541                         DIV_TOP_PERIC3, 8, 8),
 542         DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
 543                         DIV_TOP_PERIC3, 4, 4),
 544         DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
 545                         DIV_TOP_PERIC3, 0, 4),
 546
 547         /* DIV_TOP_PERIC4 */
 548         DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
 549                         DIV_TOP_PERIC4, 16, 8),
 550         DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
 551                         DIV_TOP_PERIC4, 12, 4),
 552         DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
 553                         DIV_TOP_PERIC4, 4, 8),
 554         DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
 555                         DIV_TOP_PERIC4, 0, 4),
 556 };
 557
 558 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
 559         /* ENABLE_ACLK_TOP */
 560         GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
 561                         ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0),
 562         GATE(CLK_ACLK_IMEM_SSSX_266, "aclk_imem_sssx_266",
 563                         "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
 564                         29, CLK_IGNORE_UNUSED, 0),
 565         GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
 566                         ENABLE_ACLK_TOP, 26,
 567                         CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
 568         GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
 569                         ENABLE_ACLK_TOP, 25,
 570                         CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
 571         GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_200",
 572                         ENABLE_ACLK_TOP, 24,
 573                         CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
 574         GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_266",
 575                         ENABLE_ACLK_TOP, 23,
 576                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
 577         GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
 578                         ENABLE_ACLK_TOP, 22,
 579                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 580         GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
 581                         ENABLE_ACLK_TOP, 21,
 582                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 583         GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
 584                         ENABLE_ACLK_TOP, 19,
 585                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 586         GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
 587                         ENABLE_ACLK_TOP, 18,
 588                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 589         GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
 590                         ENABLE_ACLK_TOP, 15,
 591                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 592         GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
 593                         ENABLE_ACLK_TOP, 14,
 594                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 595         GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
 596                         ENABLE_ACLK_TOP, 13,
 597                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 598         GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
 599                         ENABLE_ACLK_TOP, 12,
 600                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 601         GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
 602                         ENABLE_ACLK_TOP, 11,
 603                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 604         GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
 605                         ENABLE_ACLK_TOP, 10,
 606                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 607         GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
 608                         ENABLE_ACLK_TOP, 9,
 609                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 610         GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
 611                         ENABLE_ACLK_TOP, 8,
 612                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 613         GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
 614                         ENABLE_ACLK_TOP, 7,
 615                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 616         GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
 617                         ENABLE_ACLK_TOP, 6,
 618                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 619         GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
 620                         ENABLE_ACLK_TOP, 5,
 621                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 622         GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
 623                         ENABLE_ACLK_TOP, 3,
 624                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 625         GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
 626                         ENABLE_ACLK_TOP, 2,
 627                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 628         GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
 629                         ENABLE_ACLK_TOP, 0,
 630                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 631
 632         /* ENABLE_SCLK_TOP_MSCL */
 633         GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
 634                         ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0),
 635
 636         /* ENABLE_SCLK_TOP_CAM1 */
 637         GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
 638                         ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
 639         GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
 640                         ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
 641         GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
 642                         ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
 643         GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
 644                         ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
 645         GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
 646                         ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
 647         GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
 648                         ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
 649         GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
 650                         ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
 651
 652         /* ENABLE_SCLK_TOP_DISP */
 653         GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
 654                         "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
 655                         CLK_IGNORE_UNUSED, 0),
 656
 657         /* ENABLE_SCLK_TOP_FSYS */
 658         GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
 659                         ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
 660         GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
 661                         ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
 662         GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
 663                         ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
 664         GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
 665                         ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
 666         GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
 667                         "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
 668                         3, CLK_SET_RATE_PARENT, 0),
 669         GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
 670                         "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
 671                         1, CLK_SET_RATE_PARENT, 0),
 672         GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
 673                         "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
 674                         0, CLK_SET_RATE_PARENT, 0),
 675
 676         /* ENABLE_SCLK_TOP_PERIC */
 677         GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
 678                         ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
 679         GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
 680                         ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
 681         GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
 682                         ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
 683         GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
 684                         ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
 685         GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
 686                         ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
 687         GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
 688                         ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT |
 689                         CLK_IGNORE_UNUSED, 0),
 690         GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
 691                         ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT |
 692                         CLK_IGNORE_UNUSED, 0),
 693         GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
 694                         ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT |
 695                         CLK_IGNORE_UNUSED, 0),
 696         GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
 697                         ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
 698         GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
 699                         ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
 700         GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
 701                         ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
 702
 703         /* MUX_ENABLE_TOP_PERIC1 */
 704         GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
 705                         MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
 706         GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
 707                         MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
 708         GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
 709                         MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
 710 };
 711
 712 /*
 713  * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
 714  * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
 715  */
 716 static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = {
 717         PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6,  0),
 718         PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5,  0),
 719         PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6,  0),
 720         PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6,  0),
 721         PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4,  0),
 722         PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6,  0),
 723         PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6,  0),
 724         PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5,  0),
 725         PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6,  0),
 726         PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6,  0),
 727         PLL_35XX_RATE(24 * MHZ, 1500000000U, 250, 4,  0),
 728         PLL_35XX_RATE(24 * MHZ, 1400000000U, 350, 6,  0),
 729         PLL_35XX_RATE(24 * MHZ, 1332000000U, 222, 4,  0),
 730         PLL_35XX_RATE(24 * MHZ, 1300000000U, 325, 6,  0),
 731         PLL_35XX_RATE(24 * MHZ, 1200000000U, 500, 5,  1),
 732         PLL_35XX_RATE(24 * MHZ, 1100000000U, 550, 6,  1),
 733         PLL_35XX_RATE(24 * MHZ, 1086000000U, 362, 4,  1),
 734         PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 6,  1),
 735         PLL_35XX_RATE(24 * MHZ, 1000000000U, 500, 6,  1),
 736         PLL_35XX_RATE(24 * MHZ, 933000000U,  311, 4,  1),
 737         PLL_35XX_RATE(24 * MHZ, 921000000U,  307, 4,  1),
 738         PLL_35XX_RATE(24 * MHZ, 900000000U,  375, 5,  1),
 739         PLL_35XX_RATE(24 * MHZ, 825000000U,  275, 4,  1),
 740         PLL_35XX_RATE(24 * MHZ, 800000000U,  400, 6,  1),
 741         PLL_35XX_RATE(24 * MHZ, 733000000U,  733, 12, 1),
 742         PLL_35XX_RATE(24 * MHZ, 700000000U,  175, 3,  1),
 743         PLL_35XX_RATE(24 * MHZ, 666000000U,  222, 4,  1),
 744         PLL_35XX_RATE(24 * MHZ, 633000000U,  211, 4,  1),
 745         PLL_35XX_RATE(24 * MHZ, 600000000U,  500, 5,  2),
 746         PLL_35XX_RATE(24 * MHZ, 552000000U,  460, 5,  2),
 747         PLL_35XX_RATE(24 * MHZ, 550000000U,  550, 6,  2),
 748         PLL_35XX_RATE(24 * MHZ, 543000000U,  362, 4,  2),
 749         PLL_35XX_RATE(24 * MHZ, 533000000U,  533, 6,  2),
 750         PLL_35XX_RATE(24 * MHZ, 500000000U,  500, 6,  2),
 751         PLL_35XX_RATE(24 * MHZ, 444000000U,  370, 5,  2),
 752         PLL_35XX_RATE(24 * MHZ, 420000000U,  350, 5,  2),
 753         PLL_35XX_RATE(24 * MHZ, 400000000U,  400, 6,  2),
 754         PLL_35XX_RATE(24 * MHZ, 350000000U,  350, 6,  2),
 755         PLL_35XX_RATE(24 * MHZ, 333000000U,  222, 4,  2),
 756         PLL_35XX_RATE(24 * MHZ, 300000000U,  500, 5,  3),
 757         PLL_35XX_RATE(24 * MHZ, 278000000U,  556, 6,  3),
 758         PLL_35XX_RATE(24 * MHZ, 266000000U,  532, 6,  3),
 759         PLL_35XX_RATE(24 * MHZ, 250000000U,  500, 6,  3),
 760         PLL_35XX_RATE(24 * MHZ, 200000000U,  400, 6,  3),
 761         PLL_35XX_RATE(24 * MHZ, 166000000U,  332, 6,  3),
 762         PLL_35XX_RATE(24 * MHZ, 160000000U,  320, 6,  3),
 763         PLL_35XX_RATE(24 * MHZ, 133000000U,  532, 6,  4),
 764         PLL_35XX_RATE(24 * MHZ, 100000000U,  400, 6,  4),
 765         { /* sentinel */ }
 766 };
 767
 768 /* AUD_PLL */
 769 static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = {
 770         PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2,      0),
 771         PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
 772         PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2,      0),
 773         PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729),
 774         PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148),
 775         PLL_36XX_RATE(24 * MHZ, 338687988U, 113, 2, 2,  -6816),
 776         PLL_36XX_RATE(24 * MHZ, 294912002U,  98, 1, 3,  19923),
 777         PLL_36XX_RATE(24 * MHZ, 288000000U,  96, 1, 3,      0),
 778         PLL_36XX_RATE(24 * MHZ, 252000000U,  84, 1, 3,      0),
 779         PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
 780         { /* sentinel */ }
 781 };
 782
 783 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
 784         PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
 785                 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5433_pll_rates),
 786         PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
 787                 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5433_aud_pll_rates),
 788 };
 789
 790 static const struct samsung_cmu_info top_cmu_info __initconst = {
 791         .pll_clks               = top_pll_clks,
 792         .nr_pll_clks            = ARRAY_SIZE(top_pll_clks),
 793         .mux_clks               = top_mux_clks,
 794         .nr_mux_clks            = ARRAY_SIZE(top_mux_clks),
 795         .div_clks               = top_div_clks,
 796         .nr_div_clks            = ARRAY_SIZE(top_div_clks),
 797         .gate_clks              = top_gate_clks,
 798         .nr_gate_clks           = ARRAY_SIZE(top_gate_clks),
 799         .fixed_clks             = top_fixed_clks,
 800         .nr_fixed_clks          = ARRAY_SIZE(top_fixed_clks),
 801         .fixed_factor_clks      = top_fixed_factor_clks,
 802         .nr_fixed_factor_clks   = ARRAY_SIZE(top_fixed_factor_clks),
 803         .nr_clk_ids             = TOP_NR_CLK,
 804         .clk_regs               = top_clk_regs,
 805         .nr_clk_regs            = ARRAY_SIZE(top_clk_regs),
 806         .suspend_regs           = top_suspend_regs,
 807         .nr_suspend_regs        = ARRAY_SIZE(top_suspend_regs),
 808 };
 809
 810 static void __init exynos5433_cmu_top_init(struct device_node *np)
 811 {
 812         samsung_cmu_register_one(np, &top_cmu_info);
 813 }
 814 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
 815                 exynos5433_cmu_top_init);
 816
 817 /*
 818  * Register offset definitions for CMU_CPIF
 819  */
 820 #define MPHY_PLL_LOCK           0x0000
 821 #define MPHY_PLL_CON0           0x0100
 822 #define MPHY_PLL_CON1           0x0104
 823 #define MPHY_PLL_FREQ_DET       0x010c
 824 #define MUX_SEL_CPIF0           0x0200
 825 #define DIV_CPIF                0x0600
 826 #define ENABLE_SCLK_CPIF        0x0a00
 827
 828 static const unsigned long cpif_clk_regs[] __initconst = {
 829         MPHY_PLL_LOCK,
 830         MPHY_PLL_CON0,
 831         MPHY_PLL_CON1,
 832         MPHY_PLL_FREQ_DET,
 833         MUX_SEL_CPIF0,
 834         DIV_CPIF,
 835         ENABLE_SCLK_CPIF,
 836 };
 837
 838 static const struct samsung_clk_reg_dump cpif_suspend_regs[] = {
 839         /* force all sclk clocks enabled */
 840         { ENABLE_SCLK_CPIF, 0x3ff },
 841         /* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */
 842         { MPHY_PLL_CON0, 0x81c70601 },
 843 };
 844
 845 /* list of all parent clock list */
 846 PNAME(mout_mphy_pll_p)          = { "oscclk", "fout_mphy_pll", };
 847
 848 static const struct samsung_pll_clock cpif_pll_clks[] __initconst = {
 849         PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
 850                 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5433_pll_rates),
 851 };
 852
 853 static const struct samsung_mux_clock cpif_mux_clks[] __initconst = {
 854         /* MUX_SEL_CPIF0 */
 855         MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
 856                         0, 1),
 857 };
 858
 859 static const struct samsung_div_clock cpif_div_clks[] __initconst = {
 860         /* DIV_CPIF */
 861         DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
 862                         0, 6),
 863 };
 864
 865 static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {
 866         /* ENABLE_SCLK_CPIF */
 867         GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
 868                         ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
 869         GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
 870                         ENABLE_SCLK_CPIF, 4, 0, 0),
 871 };
 872
 873 static const struct samsung_cmu_info cpif_cmu_info __initconst = {
 874         .pll_clks               = cpif_pll_clks,
 875         .nr_pll_clks            = ARRAY_SIZE(cpif_pll_clks),
 876         .mux_clks               = cpif_mux_clks,
 877         .nr_mux_clks            = ARRAY_SIZE(cpif_mux_clks),
 878         .div_clks               = cpif_div_clks,
 879         .nr_div_clks            = ARRAY_SIZE(cpif_div_clks),
 880         .gate_clks              = cpif_gate_clks,
 881         .nr_gate_clks           = ARRAY_SIZE(cpif_gate_clks),
 882         .nr_clk_ids             = CPIF_NR_CLK,
 883         .clk_regs               = cpif_clk_regs,
 884         .nr_clk_regs            = ARRAY_SIZE(cpif_clk_regs),
 885         .suspend_regs           = cpif_suspend_regs,
 886         .nr_suspend_regs        = ARRAY_SIZE(cpif_suspend_regs),
 887 };
 888
 889 static void __init exynos5433_cmu_cpif_init(struct device_node *np)
 890 {
 891         samsung_cmu_register_one(np, &cpif_cmu_info);
 892 }
 893 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
 894                 exynos5433_cmu_cpif_init);
 895
 896 /*
 897  * Register offset definitions for CMU_MIF
 898  */
 899 #define MEM0_PLL_LOCK                   0x0000
 900 #define MEM1_PLL_LOCK                   0x0004
 901 #define BUS_PLL_LOCK                    0x0008
 902 #define MFC_PLL_LOCK                    0x000c
 903 #define MEM0_PLL_CON0                   0x0100
 904 #define MEM0_PLL_CON1                   0x0104
 905 #define MEM0_PLL_FREQ_DET               0x010c
 906 #define MEM1_PLL_CON0                   0x0110
 907 #define MEM1_PLL_CON1                   0x0114
 908 #define MEM1_PLL_FREQ_DET               0x011c
 909 #define BUS_PLL_CON0                    0x0120
 910 #define BUS_PLL_CON1                    0x0124
 911 #define BUS_PLL_FREQ_DET                0x012c
 912 #define MFC_PLL_CON0                    0x0130
 913 #define MFC_PLL_CON1                    0x0134
 914 #define MFC_PLL_FREQ_DET                0x013c
 915 #define MUX_SEL_MIF0                    0x0200
 916 #define MUX_SEL_MIF1                    0x0204
 917 #define MUX_SEL_MIF2                    0x0208
 918 #define MUX_SEL_MIF3                    0x020c
 919 #define MUX_SEL_MIF4                    0x0210
 920 #define MUX_SEL_MIF5                    0x0214
 921 #define MUX_SEL_MIF6                    0x0218
 922 #define MUX_SEL_MIF7                    0x021c
 923 #define MUX_ENABLE_MIF0                 0x0300
 924 #define MUX_ENABLE_MIF1                 0x0304
 925 #define MUX_ENABLE_MIF2                 0x0308
 926 #define MUX_ENABLE_MIF3                 0x030c
 927 #define MUX_ENABLE_MIF4                 0x0310
 928 #define MUX_ENABLE_MIF5                 0x0314
 929 #define MUX_ENABLE_MIF6                 0x0318
 930 #define MUX_ENABLE_MIF7                 0x031c
 931 #define MUX_STAT_MIF0                   0x0400
 932 #define MUX_STAT_MIF1                   0x0404
 933 #define MUX_STAT_MIF2                   0x0408
 934 #define MUX_STAT_MIF3                   0x040c
 935 #define MUX_STAT_MIF4                   0x0410
 936 #define MUX_STAT_MIF5                   0x0414
 937 #define MUX_STAT_MIF6                   0x0418
 938 #define MUX_STAT_MIF7                   0x041c
 939 #define DIV_MIF1                        0x0604
 940 #define DIV_MIF2                        0x0608
 941 #define DIV_MIF3                        0x060c
 942 #define DIV_MIF4                        0x0610
 943 #define DIV_MIF5                        0x0614
 944 #define DIV_MIF_PLL_FREQ_DET            0x0618
 945 #define DIV_STAT_MIF1                   0x0704
 946 #define DIV_STAT_MIF2                   0x0708
 947 #define DIV_STAT_MIF3                   0x070c
 948 #define DIV_STAT_MIF4                   0x0710
 949 #define DIV_STAT_MIF5                   0x0714
 950 #define DIV_STAT_MIF_PLL_FREQ_DET       0x0718
 951 #define ENABLE_ACLK_MIF0                0x0800
 952 #define ENABLE_ACLK_MIF1                0x0804
 953 #define ENABLE_ACLK_MIF2                0x0808
 954 #define ENABLE_ACLK_MIF3                0x080c
 955 #define ENABLE_PCLK_MIF                 0x0900
 956 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
 957 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
 958 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT    0x090c
 959 #define ENABLE_PCLK_MIF_SECURE_RTC      0x0910
 960 #define ENABLE_SCLK_MIF                 0x0a00
 961 #define ENABLE_IP_MIF0                  0x0b00
 962 #define ENABLE_IP_MIF1                  0x0b04
 963 #define ENABLE_IP_MIF2                  0x0b08
 964 #define ENABLE_IP_MIF3                  0x0b0c
 965 #define ENABLE_IP_MIF_SECURE_DREX0_TZ   0x0b10
 966 #define ENABLE_IP_MIF_SECURE_DREX1_TZ   0x0b14
 967 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT      0x0b18
 968 #define ENABLE_IP_MIF_SECURE_RTC        0x0b1c
 969 #define CLKOUT_CMU_MIF                  0x0c00
 970 #define CLKOUT_CMU_MIF_DIV_STAT         0x0c04
 971 #define DREX_FREQ_CTRL0                 0x1000
 972 #define DREX_FREQ_CTRL1                 0x1004
 973 #define PAUSE                           0x1008
 974 #define DDRPHY_LOCK_CTRL                0x100c
 975
 976 static const unsigned long mif_clk_regs[] __initconst = {
 977         MEM0_PLL_LOCK,
 978         MEM1_PLL_LOCK,
 979         BUS_PLL_LOCK,
 980         MFC_PLL_LOCK,
 981         MEM0_PLL_CON0,
 982         MEM0_PLL_CON1,
 983         MEM0_PLL_FREQ_DET,
 984         MEM1_PLL_CON0,
 985         MEM1_PLL_CON1,
 986         MEM1_PLL_FREQ_DET,
 987         BUS_PLL_CON0,
 988         BUS_PLL_CON1,
 989         BUS_PLL_FREQ_DET,
 990         MFC_PLL_CON0,
 991         MFC_PLL_CON1,
 992         MFC_PLL_FREQ_DET,
 993         MUX_SEL_MIF0,
 994         MUX_SEL_MIF1,
 995         MUX_SEL_MIF2,
 996         MUX_SEL_MIF3,
 997         MUX_SEL_MIF4,
 998         MUX_SEL_MIF5,
 999         MUX_SEL_MIF6,
1000         MUX_SEL_MIF7,
1001         MUX_ENABLE_MIF0,
1002         MUX_ENABLE_MIF1,
1003         MUX_ENABLE_MIF2,
1004         MUX_ENABLE_MIF3,
1005         MUX_ENABLE_MIF4,
1006         MUX_ENABLE_MIF5,
1007         MUX_ENABLE_MIF6,
1008         MUX_ENABLE_MIF7,
1009         DIV_MIF1,
1010         DIV_MIF2,
1011         DIV_MIF3,
1012         DIV_MIF4,
1013         DIV_MIF5,
1014         DIV_MIF_PLL_FREQ_DET,
1015         ENABLE_ACLK_MIF0,
1016         ENABLE_ACLK_MIF1,
1017         ENABLE_ACLK_MIF2,
1018         ENABLE_ACLK_MIF3,
1019         ENABLE_PCLK_MIF,
1020         ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
1021         ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
1022         ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
1023         ENABLE_PCLK_MIF_SECURE_RTC,
1024         ENABLE_SCLK_MIF,
1025         ENABLE_IP_MIF0,
1026         ENABLE_IP_MIF1,
1027         ENABLE_IP_MIF2,
1028         ENABLE_IP_MIF3,
1029         ENABLE_IP_MIF_SECURE_DREX0_TZ,
1030         ENABLE_IP_MIF_SECURE_DREX1_TZ,
1031         ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
1032         ENABLE_IP_MIF_SECURE_RTC,
1033         CLKOUT_CMU_MIF,
1034         CLKOUT_CMU_MIF_DIV_STAT,
1035         DREX_FREQ_CTRL0,
1036         DREX_FREQ_CTRL1,
1037         PAUSE,
1038         DDRPHY_LOCK_CTRL,
1039 };
1040
1041 static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
1042         PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
1043                 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5433_pll_rates),
1044         PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
1045                 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5433_pll_rates),
1046         PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
1047                 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5433_pll_rates),
1048         PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
1049                 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5433_pll_rates),
1050 };
1051
1052 /* list of all parent clock list */
1053 PNAME(mout_mfc_pll_div2_p)      = { "mout_mfc_pll", "dout_mfc_pll", };
1054 PNAME(mout_bus_pll_div2_p)      = { "mout_bus_pll", "dout_bus_pll", };
1055 PNAME(mout_mem1_pll_div2_p)     = { "mout_mem1_pll", "dout_mem1_pll", };
1056 PNAME(mout_mem0_pll_div2_p)     = { "mout_mem0_pll", "dout_mem0_pll", };
1057 PNAME(mout_mfc_pll_p)           = { "oscclk", "fout_mfc_pll", };
1058 PNAME(mout_bus_pll_p)           = { "oscclk", "fout_bus_pll", };
1059 PNAME(mout_mem1_pll_p)          = { "oscclk", "fout_mem1_pll", };
1060 PNAME(mout_mem0_pll_p)          = { "oscclk", "fout_mem0_pll", };
1061
1062 PNAME(mout_clk2x_phy_c_p)       = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
1063 PNAME(mout_clk2x_phy_b_p)       = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
1064 PNAME(mout_clk2x_phy_a_p)       = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
1065 PNAME(mout_clkm_phy_b_p)        = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
1066
1067 PNAME(mout_aclk_mifnm_200_p)    = { "mout_mem0_pll_div2", "div_mif_pre", };
1068 PNAME(mout_aclk_mifnm_400_p)    = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
1069
1070 PNAME(mout_aclk_disp_333_b_p)   = { "mout_aclk_disp_333_a",
1071                                     "mout_bus_pll_div2", };
1072 PNAME(mout_aclk_disp_333_a_p)   = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
1073
1074 PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
1075                                     "sclk_mphy_pll", };
1076 PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
1077                                     "mout_mfc_pll_div2", };
1078 PNAME(mout_sclk_decon_p)        = { "oscclk", "mout_bus_pll_div2", };
1079 PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
1080                                     "sclk_mphy_pll", };
1081 PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
1082                                     "mout_mfc_pll_div2", };
1083
1084 PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
1085                                        "sclk_mphy_pll", };
1086 PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
1087                                        "mout_mfc_pll_div2", };
1088 PNAME(mout_sclk_dsd_c_p)        = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
1089 PNAME(mout_sclk_dsd_b_p)        = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
1090 PNAME(mout_sclk_dsd_a_p)        = { "oscclk", "mout_mfc_pll_div2", };
1091
1092 PNAME(mout_sclk_dsim0_c_p)      = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
1093 PNAME(mout_sclk_dsim0_b_p)      = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
1094
1095 PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
1096                                        "sclk_mphy_pll", };
1097 PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1098                                        "mout_mfc_pll_div2", };
1099 PNAME(mout_sclk_dsim1_c_p)      = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1100 PNAME(mout_sclk_dsim1_b_p)      = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1101
1102 static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {
1103         /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1104         FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1105         FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1106         FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1107         FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1108 };
1109
1110 static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
1111         /* MUX_SEL_MIF0 */
1112         MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1113                         MUX_SEL_MIF0, 28, 1),
1114         MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
1115                         MUX_SEL_MIF0, 24, 1),
1116         MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
1117                         MUX_SEL_MIF0, 20, 1),
1118         MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
1119                         MUX_SEL_MIF0, 16, 1),
1120         MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
1121                         12, 1),
1122         MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
1123                         8, 1),
1124         MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
1125                         4, 1),
1126         MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
1127                         0, 1),
1128
1129         /* MUX_SEL_MIF1 */
1130         MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
1131                         MUX_SEL_MIF1, 24, 1),
1132         MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
1133                         MUX_SEL_MIF1, 20, 1),
1134         MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
1135                         MUX_SEL_MIF1, 16, 1),
1136         MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
1137                         MUX_SEL_MIF1, 12, 1),
1138         MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
1139                         MUX_SEL_MIF1, 8, 1),
1140         MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
1141                         MUX_SEL_MIF1, 4, 1),
1142
1143         /* MUX_SEL_MIF2 */
1144         MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
1145                         mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
1146         MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
1147                         mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1148
1149         /* MUX_SEL_MIF3 */
1150         MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
1151                         mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
1152         MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
1153                         mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1154
1155         /* MUX_SEL_MIF4 */
1156         MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
1157                         mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1158         MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1159                         mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1160         MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1161                         mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1162         MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1163                         mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1164         MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1165                         mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1166         MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1167                         mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1168
1169         /* MUX_SEL_MIF5 */
1170         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1171                         mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1172         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1173                         mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1174         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1175                         mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1176         MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1177                         MUX_SEL_MIF5, 8, 1),
1178         MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1179                         MUX_SEL_MIF5, 4, 1),
1180         MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1181                         MUX_SEL_MIF5, 0, 1),
1182
1183         /* MUX_SEL_MIF6 */
1184         MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1185                         MUX_SEL_MIF6, 8, 1),
1186         MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1187                         MUX_SEL_MIF6, 4, 1),
1188         MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1189                         MUX_SEL_MIF6, 0, 1),
1190
1191         /* MUX_SEL_MIF7 */
1192         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1193                         mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1194         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1195                         mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1196         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1197                         mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1198         MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1199                         MUX_SEL_MIF7, 8, 1),
1200         MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1201                         MUX_SEL_MIF7, 4, 1),
1202         MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1203                         MUX_SEL_MIF7, 0, 1),
1204 };
1205
1206 static const struct samsung_div_clock mif_div_clks[] __initconst = {
1207         /* DIV_MIF1 */
1208         DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1209                         DIV_MIF1, 16, 2),
1210         DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1211                         12, 2),
1212         DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1213                         8, 2),
1214         DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1215                         4, 4),
1216
1217         /* DIV_MIF2 */
1218         DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1219                         DIV_MIF2, 20, 3),
1220         DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1221                         DIV_MIF2, 16, 4),
1222         DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1223                         DIV_MIF2, 12, 4),
1224         DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1225                         "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1226         DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1227                         DIV_MIF2, 4, 2),
1228         DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1229                         DIV_MIF2, 0, 3),
1230
1231         /* DIV_MIF3 */
1232         DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1233                         DIV_MIF3, 16, 4),
1234         DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1235                         DIV_MIF3, 4, 3),
1236         DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1237                         DIV_MIF3, 0, 3),
1238
1239         /* DIV_MIF4 */
1240         DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1241                         DIV_MIF4, 24, 4),
1242         DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1243                         "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1244         DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1245                         DIV_MIF4, 16, 4),
1246         DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1247                         DIV_MIF4, 12, 4),
1248         DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1249                         "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1250         DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1251                         "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1252         DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1253                         "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1254
1255         /* DIV_MIF5 */
1256         DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1257                         0, 3),
1258 };
1259
1260 static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
1261         /* ENABLE_ACLK_MIF0 */
1262         GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1263                         19, CLK_IGNORE_UNUSED, 0),
1264         GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1265                         18, CLK_IGNORE_UNUSED, 0),
1266         GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1267                         17, CLK_IGNORE_UNUSED, 0),
1268         GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1269                         16, CLK_IGNORE_UNUSED, 0),
1270         GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1271                         15, CLK_IGNORE_UNUSED, 0),
1272         GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1273                         14, CLK_IGNORE_UNUSED, 0),
1274         GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1275                         ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1276         GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1277                         ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1278         GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1279                         ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1280         GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1281                         ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1282         GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1283                         ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1284         GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1285                         ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1286         GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1287                         ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1288         GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1289                         ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1290         GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1291                         ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1292         GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1293                         ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1294         GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1295                         ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1296         GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1297                         ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1298         GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1299                         ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1300         GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1301                         ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1302
1303         /* ENABLE_ACLK_MIF1 */
1304         GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1305                         "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1306                         CLK_IGNORE_UNUSED, 0),
1307         GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1308                         "div_aclk_mif_200", ENABLE_ACLK_MIF1,
1309                         27, CLK_IGNORE_UNUSED, 0),
1310         GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1311                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1312                         26, CLK_IGNORE_UNUSED, 0),
1313         GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1314                         "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1315                         25, CLK_IGNORE_UNUSED, 0),
1316         GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1317                         "div_aclk_drex1", ENABLE_ACLK_MIF1,
1318                         24, CLK_IGNORE_UNUSED, 0),
1319         GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1320                         "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1321                         23, CLK_IGNORE_UNUSED, 0),
1322         GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1323                         "div_aclk_drex0", ENABLE_ACLK_MIF1,
1324                         22, CLK_IGNORE_UNUSED, 0),
1325         GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1326                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1327                         21, CLK_IGNORE_UNUSED, 0),
1328         GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1329                         "div_aclk_drex1", ENABLE_ACLK_MIF1,
1330                         20, CLK_IGNORE_UNUSED, 0),
1331         GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1332                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1333                         19, CLK_IGNORE_UNUSED, 0),
1334         GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1335                         "div_aclk_drex1", ENABLE_ACLK_MIF1,
1336                         18, CLK_IGNORE_UNUSED, 0),
1337         GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1338                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1339                         17, CLK_IGNORE_UNUSED, 0),
1340         GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1341                         "div_aclk_drex1", ENABLE_ACLK_MIF1,
1342                         16, CLK_IGNORE_UNUSED, 0),
1343         GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1344                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1345                         15, CLK_IGNORE_UNUSED, 0),
1346         GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1347                         "div_aclk_drex0", ENABLE_ACLK_MIF1,
1348                         14, CLK_IGNORE_UNUSED, 0),
1349         GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1350                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1351                         13, CLK_IGNORE_UNUSED, 0),
1352         GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1353                         "div_aclk_drex0", ENABLE_ACLK_MIF1,
1354                         12, CLK_IGNORE_UNUSED, 0),
1355         GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1356                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1357                         11, CLK_IGNORE_UNUSED, 0),
1358         GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1359                         "div_aclk_drex0", ENABLE_ACLK_MIF1,
1360                         10, CLK_IGNORE_UNUSED, 0),
1361         GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1362                         ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1363         GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1364                         ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1365         GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1366                         ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1367         GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1368                         ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1369         GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1370                         ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1371         GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1372                         ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1373         GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1374                         ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1375         GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1376                         ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1377         GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1378                         ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1379         GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1380                         0, CLK_IGNORE_UNUSED, 0),
1381
1382         /* ENABLE_ACLK_MIF2 */
1383         GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1384                         ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0),
1385         GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1386                         ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1387         GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1388                         ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1389         GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1390                         ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1391         GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1392                         ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1393         GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1394                         ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1395         GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1396                         ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1397         GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1398                         "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1399                         CLK_IGNORE_UNUSED, 0),
1400         GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1401                         "div_aclk_mif_400", ENABLE_ACLK_MIF2,
1402                         5, CLK_IGNORE_UNUSED, 0),
1403         GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1404                         ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1405         GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1406                         "div_aclk_mif_200", ENABLE_ACLK_MIF2,
1407                         3, CLK_IGNORE_UNUSED, 0),
1408         GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1409                         "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1410
1411         /* ENABLE_ACLK_MIF3 */
1412         GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1413                         ENABLE_ACLK_MIF3, 4,
1414                         CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1415         GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1416                         ENABLE_ACLK_MIF3, 1,
1417                         CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1418         GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1419                         ENABLE_ACLK_MIF3, 0,
1420                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1421
1422         /* ENABLE_PCLK_MIF */
1423         GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1424                         ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1425         GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1426                         ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1427         GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1428                         ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1429         GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1430                         ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1431         GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1432                         ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1433         GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1434                         ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1435         GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1436                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1437                         CLK_IGNORE_UNUSED, 0),
1438         GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1439                         ENABLE_PCLK_MIF, 19, 0, 0),
1440         GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1441                         ENABLE_PCLK_MIF, 18, 0, 0),
1442         GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1443                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1444         GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1445                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1446         GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1447                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1448         GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1449                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1450         GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1451                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1452         GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1453                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1454         GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1455                         ENABLE_PCLK_MIF, 11, 0, 0),
1456         GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1457                         ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1458         GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1459                         ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1460         GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1461                         ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1462         GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1463                         ENABLE_PCLK_MIF, 7, 0, 0),
1464         GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1465                         ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1466         GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1467                         ENABLE_PCLK_MIF, 5, 0, 0),
1468         GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1469                         ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1470         GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1471                         ENABLE_PCLK_MIF, 2, 0, 0),
1472         GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1473                         ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1474
1475         /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1476         GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1477                         ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
1478                         CLK_IGNORE_UNUSED, 0),
1479
1480         /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1481         GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1482                         ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
1483                         CLK_IGNORE_UNUSED, 0),
1484
1485         /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1486         GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1487                         ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
1488
1489         /* ENABLE_PCLK_MIF_SECURE_RTC */
1490         GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1491                         ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1492
1493         /* ENABLE_SCLK_MIF */
1494         GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1495                         ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1496         GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1497                         "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1498                         14, CLK_IGNORE_UNUSED, 0),
1499         GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1500                         ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1501         GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1502                         ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1503         GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1504                         "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1505                         7, CLK_IGNORE_UNUSED, 0),
1506         GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1507                         "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1508                         6, CLK_IGNORE_UNUSED, 0),
1509         GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1510                         "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1511                         5, CLK_IGNORE_UNUSED, 0),
1512         GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1513                         ENABLE_SCLK_MIF, 4,
1514                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1515         GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1516                         ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1517         GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1518                         ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1519         GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1520                         ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1521         GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1522                         ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1523 };
1524
1525 static const struct samsung_cmu_info mif_cmu_info __initconst = {
1526         .pll_clks               = mif_pll_clks,
1527         .nr_pll_clks            = ARRAY_SIZE(mif_pll_clks),
1528         .mux_clks               = mif_mux_clks,
1529         .nr_mux_clks            = ARRAY_SIZE(mif_mux_clks),
1530         .div_clks               = mif_div_clks,
1531         .nr_div_clks            = ARRAY_SIZE(mif_div_clks),
1532         .gate_clks              = mif_gate_clks,
1533         .nr_gate_clks           = ARRAY_SIZE(mif_gate_clks),
1534         .fixed_factor_clks      = mif_fixed_factor_clks,
1535         .nr_fixed_factor_clks   = ARRAY_SIZE(mif_fixed_factor_clks),
1536         .nr_clk_ids             = MIF_NR_CLK,
1537         .clk_regs               = mif_clk_regs,
1538         .nr_clk_regs            = ARRAY_SIZE(mif_clk_regs),
1539 };
1540
1541 static void __init exynos5433_cmu_mif_init(struct device_node *np)
1542 {
1543         samsung_cmu_register_one(np, &mif_cmu_info);
1544 }
1545 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1546                 exynos5433_cmu_mif_init);
1547
1548 /*
1549  * Register offset definitions for CMU_PERIC
1550  */
1551 #define DIV_PERIC                       0x0600
1552 #define DIV_STAT_PERIC                  0x0700
1553 #define ENABLE_ACLK_PERIC               0x0800
1554 #define ENABLE_PCLK_PERIC0              0x0900
1555 #define ENABLE_PCLK_PERIC1              0x0904
1556 #define ENABLE_SCLK_PERIC               0x0A00
1557 #define ENABLE_IP_PERIC0                0x0B00
1558 #define ENABLE_IP_PERIC1                0x0B04
1559 #define ENABLE_IP_PERIC2                0x0B08
1560
1561 static const unsigned long peric_clk_regs[] __initconst = {
1562         DIV_PERIC,
1563         ENABLE_ACLK_PERIC,
1564         ENABLE_PCLK_PERIC0,
1565         ENABLE_PCLK_PERIC1,
1566         ENABLE_SCLK_PERIC,
1567         ENABLE_IP_PERIC0,
1568         ENABLE_IP_PERIC1,
1569         ENABLE_IP_PERIC2,
1570 };
1571
1572 static const struct samsung_clk_reg_dump peric_suspend_regs[] = {
1573         /* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */
1574         { ENABLE_PCLK_PERIC0, 0xe00ff000 },
1575         /* sclk: uart2-0 */
1576         { ENABLE_SCLK_PERIC, 0x7 },
1577 };
1578
1579 static const struct samsung_div_clock peric_div_clks[] __initconst = {
1580         /* DIV_PERIC */
1581         DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1582         DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1583 };
1584
1585 static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
1586         /* ENABLE_ACLK_PERIC */
1587         GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1588                         ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1589         GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1590                         ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1591         GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1592                         ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1593         GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
1594                         ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1595
1596         /* ENABLE_PCLK_PERIC0 */
1597         GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1598                         31, CLK_SET_RATE_PARENT, 0),
1599         GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
1600                         ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1601         GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
1602                         ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1603         GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1604                         28, CLK_SET_RATE_PARENT, 0),
1605         GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1606                         26, CLK_SET_RATE_PARENT, 0),
1607         GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1608                         25, CLK_SET_RATE_PARENT, 0),
1609         GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1610                         24, CLK_SET_RATE_PARENT, 0),
1611         GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1612                         23, CLK_SET_RATE_PARENT, 0),
1613         GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1614                         22, CLK_SET_RATE_PARENT, 0),
1615         GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1616                         21, CLK_SET_RATE_PARENT, 0),
1617         GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1618                         20, CLK_SET_RATE_PARENT, 0),
1619         GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
1620                         ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1621         GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
1622                         ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1623         GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
1624                         ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1625         GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
1626                         ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1627         GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
1628                         ENABLE_PCLK_PERIC0, 15,
1629                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1630         GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1631                         14, CLK_SET_RATE_PARENT, 0),
1632         GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1633                         13, CLK_SET_RATE_PARENT, 0),
1634         GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1635                         12, CLK_SET_RATE_PARENT, 0),
1636         GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
1637                         ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1638         GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
1639                         ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1640         GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
1641                         ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1642         GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
1643                         ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1644         GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1645                         7, CLK_SET_RATE_PARENT, 0),
1646         GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1647                         6, CLK_SET_RATE_PARENT, 0),
1648         GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1649                         5, CLK_SET_RATE_PARENT, 0),
1650         GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1651                         4, CLK_SET_RATE_PARENT, 0),
1652         GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1653                         3, CLK_SET_RATE_PARENT, 0),
1654         GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1655                         2, CLK_SET_RATE_PARENT, 0),
1656         GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1657                         1, CLK_SET_RATE_PARENT, 0),
1658         GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1659                         0, CLK_SET_RATE_PARENT, 0),
1660
1661         /* ENABLE_PCLK_PERIC1 */
1662         GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1663                         9, CLK_SET_RATE_PARENT, 0),
1664         GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1665                         8, CLK_SET_RATE_PARENT, 0),
1666         GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
1667                         ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1668         GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
1669                         ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1670         GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
1671                         ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1672         GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
1673                         ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1674         GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
1675                         ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1676         GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
1677                         ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1678         GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
1679                         ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1680         GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
1681                         ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1682
1683         /* ENABLE_SCLK_PERIC */
1684         GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1685                         ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1686         GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1687                         ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1688         GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1689                         19, CLK_SET_RATE_PARENT, 0),
1690         GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1691                         18, CLK_SET_RATE_PARENT, 0),
1692         GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1693                         17, 0, 0),
1694         GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1695                         16, 0, 0),
1696         GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1697         GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1698                         ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1699         GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1700                         ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
1701         GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1702                         ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1703         GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
1704                         "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1705                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1706         GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
1707                         ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1708         GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
1709                         ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1710         GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
1711                         ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
1712         GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1713                         5, CLK_SET_RATE_PARENT, 0),
1714         GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1715                         4, CLK_SET_RATE_PARENT, 0),
1716         GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1717                         3, CLK_SET_RATE_PARENT, 0),
1718         GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1719                         ENABLE_SCLK_PERIC, 2,
1720                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1721         GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1722                         ENABLE_SCLK_PERIC, 1,
1723                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1724         GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1725                         ENABLE_SCLK_PERIC, 0,
1726                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1727 };
1728
1729 static const struct samsung_cmu_info peric_cmu_info __initconst = {
1730         .div_clks               = peric_div_clks,
1731         .nr_div_clks            = ARRAY_SIZE(peric_div_clks),
1732         .gate_clks              = peric_gate_clks,
1733         .nr_gate_clks           = ARRAY_SIZE(peric_gate_clks),
1734         .nr_clk_ids             = PERIC_NR_CLK,
1735         .clk_regs               = peric_clk_regs,
1736         .nr_clk_regs            = ARRAY_SIZE(peric_clk_regs),
1737         .suspend_regs           = peric_suspend_regs,
1738         .nr_suspend_regs        = ARRAY_SIZE(peric_suspend_regs),
1739 };
1740
1741 static void __init exynos5433_cmu_peric_init(struct device_node *np)
1742 {
1743         samsung_cmu_register_one(np, &peric_cmu_info);
1744 }
1745
1746 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1747                 exynos5433_cmu_peric_init);
1748
1749 /*
1750  * Register offset definitions for CMU_PERIS
1751  */
1752 #define ENABLE_ACLK_PERIS                               0x0800
1753 #define ENABLE_PCLK_PERIS                               0x0900
1754 #define ENABLE_PCLK_PERIS_SECURE_TZPC                   0x0904
1755 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF           0x0908
1756 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF           0x090c
1757 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC                 0x0910
1758 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF     0x0914
1759 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF      0x0918
1760 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF          0x091c
1761 #define ENABLE_SCLK_PERIS                               0x0a00
1762 #define ENABLE_SCLK_PERIS_SECURE_SECKEY                 0x0a04
1763 #define ENABLE_SCLK_PERIS_SECURE_CHIPID                 0x0a08
1764 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC                 0x0a0c
1765 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE           0x0a10
1766 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT            0x0a14
1767 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON                0x0a18
1768 #define ENABLE_IP_PERIS0                                0x0b00
1769 #define ENABLE_IP_PERIS1                                0x0b04
1770 #define ENABLE_IP_PERIS_SECURE_TZPC                     0x0b08
1771 #define ENABLE_IP_PERIS_SECURE_SECKEY                   0x0b0c
1772 #define ENABLE_IP_PERIS_SECURE_CHIPID                   0x0b10
1773 #define ENABLE_IP_PERIS_SECURE_TOPRTC                   0x0b14
1774 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE             0x0b18
1775 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT              0x0b1c
1776 #define ENABLE_IP_PERIS_SECURE_OTP_CON                  0x0b20
1777
1778 static const unsigned long peris_clk_regs[] __initconst = {
1779         ENABLE_ACLK_PERIS,
1780         ENABLE_PCLK_PERIS,
1781         ENABLE_PCLK_PERIS_SECURE_TZPC,
1782         ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
1783         ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
1784         ENABLE_PCLK_PERIS_SECURE_TOPRTC,
1785         ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
1786         ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
1787         ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1788         ENABLE_SCLK_PERIS,
1789         ENABLE_SCLK_PERIS_SECURE_SECKEY,
1790         ENABLE_SCLK_PERIS_SECURE_CHIPID,
1791         ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1792         ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1793         ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1794         ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1795         ENABLE_IP_PERIS0,
1796         ENABLE_IP_PERIS1,
1797         ENABLE_IP_PERIS_SECURE_TZPC,
1798         ENABLE_IP_PERIS_SECURE_SECKEY,
1799         ENABLE_IP_PERIS_SECURE_CHIPID,
1800         ENABLE_IP_PERIS_SECURE_TOPRTC,
1801         ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1802         ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1803         ENABLE_IP_PERIS_SECURE_OTP_CON,
1804 };
1805
1806 static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
1807         /* ENABLE_ACLK_PERIS */
1808         GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1809                         ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1810         GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1811                         ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1812         GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1813                         ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1814
1815         /* ENABLE_PCLK_PERIS */
1816         GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1817                         ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1818         GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1819                         ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1820         GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1821                         ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1822         GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1823                         ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1824         GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1825                         ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1826         GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1827                         ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1828         GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1829                         ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1830         GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1831                         ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1832         GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1833                         ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1834         GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1835                         ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1836
1837         /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1838         GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1839                         ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0),
1840         GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1841                         ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0),
1842         GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1843                         ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0),
1844         GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1845                         ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0),
1846         GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1847                         ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0),
1848         GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1849                         ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0),
1850         GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1851                         ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0),
1852         GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1853                         ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0),
1854         GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1855                         ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0),
1856         GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1857                         ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0),
1858         GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1859                         ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0),
1860         GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1861                         ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0),
1862         GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1863                         ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0),
1864
1865         /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1866         GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1867                         ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1868
1869         /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1870         GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1871                         ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1872
1873         /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1874         GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1875                         ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1876
1877         /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1878         GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1879                         "aclk_peris_66",
1880                         ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1881
1882         /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1883         GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1884                         "aclk_peris_66",
1885                         ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1886
1887         /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1888         GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1889                         "aclk_peris_66",
1890                         ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1891
1892         /* ENABLE_SCLK_PERIS */
1893         GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1894                         ENABLE_SCLK_PERIS, 10, 0, 0),
1895         GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1896                         ENABLE_SCLK_PERIS, 4, 0, 0),
1897         GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1898                         ENABLE_SCLK_PERIS, 3, 0, 0),
1899
1900         /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1901         GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1902                         ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0),
1903
1904         /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1905         GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1906                         ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0),
1907
1908         /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1909         GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1910                         ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1911
1912         /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1913         GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1914                         ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1915
1916         /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1917         GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
1918                         ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1919
1920         /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1921         GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
1922                         ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1923 };
1924
1925 static const struct samsung_cmu_info peris_cmu_info __initconst = {
1926         .gate_clks              = peris_gate_clks,
1927         .nr_gate_clks           = ARRAY_SIZE(peris_gate_clks),
1928         .nr_clk_ids             = PERIS_NR_CLK,
1929         .clk_regs               = peris_clk_regs,
1930         .nr_clk_regs            = ARRAY_SIZE(peris_clk_regs),
1931 };
1932
1933 static void __init exynos5433_cmu_peris_init(struct device_node *np)
1934 {
1935         samsung_cmu_register_one(np, &peris_cmu_info);
1936 }
1937
1938 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1939                 exynos5433_cmu_peris_init);
1940
1941 /*
1942  * Register offset definitions for CMU_FSYS
1943  */
1944 #define MUX_SEL_FSYS0                   0x0200
1945 #define MUX_SEL_FSYS1                   0x0204
1946 #define MUX_SEL_FSYS2                   0x0208
1947 #define MUX_SEL_FSYS3                   0x020c
1948 #define MUX_SEL_FSYS4                   0x0210
1949 #define MUX_ENABLE_FSYS0                0x0300
1950 #define MUX_ENABLE_FSYS1                0x0304
1951 #define MUX_ENABLE_FSYS2                0x0308
1952 #define MUX_ENABLE_FSYS3                0x030c
1953 #define MUX_ENABLE_FSYS4                0x0310
1954 #define MUX_STAT_FSYS0                  0x0400
1955 #define MUX_STAT_FSYS1                  0x0404
1956 #define MUX_STAT_FSYS2                  0x0408
1957 #define MUX_STAT_FSYS3                  0x040c
1958 #define MUX_STAT_FSYS4                  0x0410
1959 #define MUX_IGNORE_FSYS2                0x0508
1960 #define MUX_IGNORE_FSYS3                0x050c
1961 #define ENABLE_ACLK_FSYS0               0x0800
1962 #define ENABLE_ACLK_FSYS1               0x0804
1963 #define ENABLE_PCLK_FSYS                0x0900
1964 #define ENABLE_SCLK_FSYS                0x0a00
1965 #define ENABLE_IP_FSYS0                 0x0b00
1966 #define ENABLE_IP_FSYS1                 0x0b04
1967
1968 /* list of all parent clock list */
1969 PNAME(mout_sclk_ufs_mphy_user_p)        = { "oscclk", "sclk_ufs_mphy", };
1970 PNAME(mout_aclk_fsys_200_user_p)        = { "oscclk", "aclk_fsys_200", };
1971 PNAME(mout_sclk_pcie_100_user_p)        = { "oscclk", "sclk_pcie_100_fsys",};
1972 PNAME(mout_sclk_ufsunipro_user_p)       = { "oscclk", "sclk_ufsunipro_fsys",};
1973 PNAME(mout_sclk_mmc2_user_p)            = { "oscclk", "sclk_mmc2_fsys", };
1974 PNAME(mout_sclk_mmc1_user_p)            = { "oscclk", "sclk_mmc1_fsys", };
1975 PNAME(mout_sclk_mmc0_user_p)            = { "oscclk", "sclk_mmc0_fsys", };
1976 PNAME(mout_sclk_usbhost30_user_p)       = { "oscclk", "sclk_usbhost30_fsys",};
1977 PNAME(mout_sclk_usbdrd30_user_p)        = { "oscclk", "sclk_usbdrd30_fsys", };
1978
1979 PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
1980                 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
1981 PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
1982                 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
1983 PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
1984                 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
1985 PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
1986                 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
1987 PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
1988                 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
1989 PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
1990                 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
1991 PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
1992                 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
1993 PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
1994                 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
1995 PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
1996                 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
1997 PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
1998                 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
1999 PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
2000                 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
2001 PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
2002                 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
2003 PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
2004                 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
2005 PNAME(mout_sclk_mphy_p)
2006                 = { "mout_sclk_ufs_mphy_user",
2007                             "mout_phyclk_lli_mphy_to_ufs_user", };
2008
2009 static const unsigned long fsys_clk_regs[] __initconst = {
2010         MUX_SEL_FSYS0,
2011         MUX_SEL_FSYS1,
2012         MUX_SEL_FSYS2,
2013         MUX_SEL_FSYS3,
2014         MUX_SEL_FSYS4,
2015         MUX_ENABLE_FSYS0,
2016         MUX_ENABLE_FSYS1,
2017         MUX_ENABLE_FSYS2,
2018         MUX_ENABLE_FSYS3,
2019         MUX_ENABLE_FSYS4,
2020         MUX_IGNORE_FSYS2,
2021         MUX_IGNORE_FSYS3,
2022         ENABLE_ACLK_FSYS0,
2023         ENABLE_ACLK_FSYS1,
2024         ENABLE_PCLK_FSYS,
2025         ENABLE_SCLK_FSYS,
2026         ENABLE_IP_FSYS0,
2027         ENABLE_IP_FSYS1,
2028 };
2029
2030 static const struct samsung_clk_reg_dump fsys_suspend_regs[] = {
2031         { MUX_SEL_FSYS0, 0 },
2032         { MUX_SEL_FSYS1, 0 },
2033         { MUX_SEL_FSYS2, 0 },
2034         { MUX_SEL_FSYS3, 0 },
2035         { MUX_SEL_FSYS4, 0 },
2036 };
2037
2038 static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {
2039         /* PHY clocks from USBDRD30_PHY */
2040         FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
2041                         "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
2042                         0, 60000000),
2043         FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
2044                         "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
2045                         0, 125000000),
2046         /* PHY clocks from USBHOST30_PHY */
2047         FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
2048                         "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
2049                         0, 60000000),
2050         FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
2051                         "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
2052                         0, 125000000),
2053         /* PHY clocks from USBHOST20_PHY */
2054         FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
2055                         "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000),
2056         FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
2057                         "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000),
2058         FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
2059                         "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
2060                         0, 48000000),
2061         FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
2062                         "phyclk_usbhost20_phy_hsic1_phy", NULL, 0,
2063                         60000000),
2064         /* PHY clocks from UFS_PHY */
2065         FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
2066                         NULL, 0, 300000000),
2067         FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
2068                         NULL, 0, 300000000),
2069         FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
2070                         NULL, 0, 300000000),
2071         FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
2072                         NULL, 0, 300000000),
2073         /* PHY clocks from LLI_PHY */
2074         FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
2075                         NULL, 0, 26000000),
2076 };
2077
2078 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
2079         /* MUX_SEL_FSYS0 */
2080         MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
2081                         mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
2082         MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
2083                         mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
2084
2085         /* MUX_SEL_FSYS1 */
2086         MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
2087                         mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
2088         MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
2089                         mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
2090         MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
2091                         mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
2092         MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
2093                         mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
2094         MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
2095                         mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
2096         MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
2097                         mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
2098         MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
2099                         mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2100
2101         /* MUX_SEL_FSYS2 */
2102         MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
2103                         "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2104                         mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
2105                         MUX_SEL_FSYS2, 28, 1),
2106         MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
2107                         "mout_phyclk_usbhost30_uhost30_phyclock_user",
2108                         mout_phyclk_usbhost30_uhost30_phyclock_user_p,
2109                         MUX_SEL_FSYS2, 24, 1),
2110         MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
2111                         "mout_phyclk_usbhost20_phy_hsic1",
2112                         mout_phyclk_usbhost20_phy_hsic1_p,
2113                         MUX_SEL_FSYS2, 20, 1),
2114         MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
2115                         "mout_phyclk_usbhost20_phy_clk48mohci_user",
2116                         mout_phyclk_usbhost20_phy_clk48mohci_user_p,
2117                         MUX_SEL_FSYS2, 16, 1),
2118         MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
2119                         "mout_phyclk_usbhost20_phy_phyclock_user",
2120                         mout_phyclk_usbhost20_phy_phyclock_user_p,
2121                         MUX_SEL_FSYS2, 12, 1),
2122         MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
2123                         "mout_phyclk_usbhost20_phy_freeclk_user",
2124                         mout_phyclk_usbhost20_phy_freeclk_user_p,
2125                         MUX_SEL_FSYS2, 8, 1),
2126         MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
2127                         "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2128                         mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
2129                         MUX_SEL_FSYS2, 4, 1),
2130         MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
2131                         "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2132                         mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
2133                         MUX_SEL_FSYS2, 0, 1),
2134
2135         /* MUX_SEL_FSYS3 */
2136         MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2137                         "mout_phyclk_ufs_rx1_symbol_user",
2138                         mout_phyclk_ufs_rx1_symbol_user_p,
2139                         MUX_SEL_FSYS3, 16, 1),
2140         MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2141                         "mout_phyclk_ufs_rx0_symbol_user",
2142                         mout_phyclk_ufs_rx0_symbol_user_p,
2143                         MUX_SEL_FSYS3, 12, 1),
2144         MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2145                         "mout_phyclk_ufs_tx1_symbol_user",
2146                         mout_phyclk_ufs_tx1_symbol_user_p,
2147                         MUX_SEL_FSYS3, 8, 1),
2148         MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2149                         "mout_phyclk_ufs_tx0_symbol_user",
2150                         mout_phyclk_ufs_tx0_symbol_user_p,
2151                         MUX_SEL_FSYS3, 4, 1),
2152         MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2153                         "mout_phyclk_lli_mphy_to_ufs_user",
2154                         mout_phyclk_lli_mphy_to_ufs_user_p,
2155                         MUX_SEL_FSYS3, 0, 1),
2156
2157         /* MUX_SEL_FSYS4 */
2158         MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
2159                         MUX_SEL_FSYS4, 0, 1),
2160 };
2161
2162 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
2163         /* ENABLE_ACLK_FSYS0 */
2164         GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2165                         ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2166         GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
2167                         ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2168         GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
2169                         ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2170         GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
2171                         ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2172         GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
2173                         ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2174         GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
2175                         ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2176         GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
2177                         ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2178         GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
2179                         ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2180         GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
2181                         ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2182         GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
2183                         ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2184         GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
2185                         ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2186
2187         /* ENABLE_ACLK_FSYS1 */
2188         GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2189                         ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2190         GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
2191                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2192                         26, CLK_IGNORE_UNUSED, 0),
2193         GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2194                         ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2195         GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2196                         ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
2197         GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2198                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2199                         22, CLK_IGNORE_UNUSED, 0),
2200         GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2201                         ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2202         GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2203                         ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2204         GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
2205                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2206                         13, 0, 0),
2207         GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
2208                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2209                         12, 0, 0),
2210         GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
2211                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2212                         11, CLK_IGNORE_UNUSED, 0),
2213         GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
2214                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2215                         10, CLK_IGNORE_UNUSED, 0),
2216         GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
2217                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2218                         9, CLK_IGNORE_UNUSED, 0),
2219         GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
2220                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2221                         8, CLK_IGNORE_UNUSED, 0),
2222         GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
2223                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2224                         7, CLK_IGNORE_UNUSED, 0),
2225         GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
2226                         "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2227                         6, CLK_IGNORE_UNUSED, 0),
2228         GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2229                         ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2230         GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2231                         ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2232         GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2233                         ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2234         GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2235                         ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2236         GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2237                         ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2238         GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2239                         ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2240
2241         /* ENABLE_PCLK_FSYS */
2242         GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2243                         ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
2244         GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2245                         ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2246         GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2247                         ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
2248         GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2249                         ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
2250         GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2251                         ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2252         GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2253                         ENABLE_PCLK_FSYS, 5, 0, 0),
2254         GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
2255                         "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2256         GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
2257                         "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2258         GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2259                         ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2260         GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2261                         ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2262         GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
2263                         "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
2264                         0, CLK_IGNORE_UNUSED, 0),
2265
2266         /* ENABLE_SCLK_FSYS */
2267         GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2268                         ENABLE_SCLK_FSYS, 21, 0, 0),
2269         GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2270                         "phyclk_usbhost30_uhost30_pipe_pclk",
2271                         "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2272                         ENABLE_SCLK_FSYS, 18, 0, 0),
2273         GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2274                         "phyclk_usbhost30_uhost30_phyclock",
2275                         "mout_phyclk_usbhost30_uhost30_phyclock_user",
2276                         ENABLE_SCLK_FSYS, 17, 0, 0),
2277         GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
2278                         "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
2279                         16, 0, 0),
2280         GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
2281                         "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
2282                         15, 0, 0),
2283         GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
2284                         "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
2285                         14, 0, 0),
2286         GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
2287                         "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
2288                         13, 0, 0),
2289         GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
2290                         "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
2291                         12, 0, 0),
2292         GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2293                         "phyclk_usbhost20_phy_clk48mohci",
2294                         "mout_phyclk_usbhost20_phy_clk48mohci_user",
2295                         ENABLE_SCLK_FSYS, 11, 0, 0),
2296         GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2297                         "phyclk_usbhost20_phy_phyclock",
2298                         "mout_phyclk_usbhost20_phy_phyclock_user",
2299                         ENABLE_SCLK_FSYS, 10, 0, 0),
2300         GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2301                         "phyclk_usbhost20_phy_freeclk",
2302                         "mout_phyclk_usbhost20_phy_freeclk_user",
2303                         ENABLE_SCLK_FSYS, 9, 0, 0),
2304         GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2305                         "phyclk_usbdrd30_udrd30_pipe_pclk",
2306                         "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2307                         ENABLE_SCLK_FSYS, 8, 0, 0),
2308         GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
2309                         "phyclk_usbdrd30_udrd30_phyclock",
2310                         "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2311                         ENABLE_SCLK_FSYS, 7, 0, 0),
2312         GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
2313                         ENABLE_SCLK_FSYS, 6, 0, 0),
2314         GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2315                         ENABLE_SCLK_FSYS, 5, 0, 0),
2316         GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
2317                         ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2318         GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
2319                         ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2320         GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
2321                         ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2322         GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2323                         ENABLE_SCLK_FSYS, 1, 0, 0),
2324         GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2325                         ENABLE_SCLK_FSYS, 0, 0, 0),
2326
2327         /* ENABLE_IP_FSYS0 */
2328         GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
2329         GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2330         GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2331 };
2332
2333 static const struct samsung_cmu_info fsys_cmu_info __initconst = {
2334         .mux_clks               = fsys_mux_clks,
2335         .nr_mux_clks            = ARRAY_SIZE(fsys_mux_clks),
2336         .gate_clks              = fsys_gate_clks,
2337         .nr_gate_clks           = ARRAY_SIZE(fsys_gate_clks),
2338         .fixed_clks             = fsys_fixed_clks,
2339         .nr_fixed_clks          = ARRAY_SIZE(fsys_fixed_clks),
2340         .nr_clk_ids             = FSYS_NR_CLK,
2341         .clk_regs               = fsys_clk_regs,
2342         .nr_clk_regs            = ARRAY_SIZE(fsys_clk_regs),
2343         .suspend_regs           = fsys_suspend_regs,
2344         .nr_suspend_regs        = ARRAY_SIZE(fsys_suspend_regs),
2345         .clk_name               = "aclk_fsys_200",
2346 };
2347
2348 /*
2349  * Register offset definitions for CMU_G2D
2350  */
2351 #define MUX_SEL_G2D0                            0x0200
2352 #define MUX_SEL_ENABLE_G2D0                     0x0300
2353 #define MUX_SEL_STAT_G2D0                       0x0400
2354 #define DIV_G2D                                 0x0600
2355 #define DIV_STAT_G2D                            0x0700
2356 #define DIV_ENABLE_ACLK_G2D                     0x0800
2357 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D     0x0804
2358 #define DIV_ENABLE_PCLK_G2D                     0x0900
2359 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D     0x0904
2360 #define DIV_ENABLE_IP_G2D0                      0x0b00
2361 #define DIV_ENABLE_IP_G2D1                      0x0b04
2362 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D       0x0b08
2363
2364 static const unsigned long g2d_clk_regs[] __initconst = {
2365         MUX_SEL_G2D0,
2366         MUX_SEL_ENABLE_G2D0,
2367         DIV_G2D,
2368         DIV_ENABLE_ACLK_G2D,
2369         DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
2370         DIV_ENABLE_PCLK_G2D,
2371         DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
2372         DIV_ENABLE_IP_G2D0,
2373         DIV_ENABLE_IP_G2D1,
2374         DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
2375 };
2376
2377 static const struct samsung_clk_reg_dump g2d_suspend_regs[] = {
2378         { MUX_SEL_G2D0, 0 },
2379 };
2380
2381 /* list of all parent clock list */
2382 PNAME(mout_aclk_g2d_266_user_p)         = { "oscclk", "aclk_g2d_266", };
2383 PNAME(mout_aclk_g2d_400_user_p)         = { "oscclk", "aclk_g2d_400", };
2384
2385 static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
2386         /* MUX_SEL_G2D0 */
2387         MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2388                         mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
2389         MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
2390                         mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2391 };
2392
2393 static const struct samsung_div_clock g2d_div_clks[] __initconst = {
2394         /* DIV_G2D */
2395         DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2396                         DIV_G2D, 0, 2),
2397 };
2398
2399 static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
2400         /* DIV_ENABLE_ACLK_G2D */
2401         GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2402                         DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2403         GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
2404                         DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2405         GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
2406                         DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2407         GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
2408                         DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2409         GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
2410                         DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2411         GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
2412                         "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
2413                         7, 0, 0),
2414         GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
2415                         DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2416         GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
2417                         DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2418         GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
2419                         DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2420         GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
2421                         DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2422         GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
2423                         DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2424         GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
2425                         DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2426         GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
2427                         DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2428
2429         /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
2430         GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
2431                 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2432
2433         /* DIV_ENABLE_PCLK_G2D */
2434         GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
2435                         DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2436         GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
2437                         DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2438         GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
2439                         DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2440         GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
2441                         DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2442         GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
2443                         DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2444         GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
2445                         DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2446         GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
2447                         DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2448         GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
2449                         0, 0, 0),
2450
2451         /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2452         GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
2453                 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2454 };
2455
2456 static const struct samsung_cmu_info g2d_cmu_info __initconst = {
2457         .mux_clks               = g2d_mux_clks,
2458         .nr_mux_clks            = ARRAY_SIZE(g2d_mux_clks),
2459         .div_clks               = g2d_div_clks,
2460         .nr_div_clks            = ARRAY_SIZE(g2d_div_clks),
2461         .gate_clks              = g2d_gate_clks,
2462         .nr_gate_clks           = ARRAY_SIZE(g2d_gate_clks),
2463         .nr_clk_ids             = G2D_NR_CLK,
2464         .clk_regs               = g2d_clk_regs,
2465         .nr_clk_regs            = ARRAY_SIZE(g2d_clk_regs),
2466         .suspend_regs           = g2d_suspend_regs,
2467         .nr_suspend_regs        = ARRAY_SIZE(g2d_suspend_regs),
2468         .clk_name               = "aclk_g2d_400",
2469 };
2470
2471 /*
2472  * Register offset definitions for CMU_DISP
2473  */
2474 #define DISP_PLL_LOCK                   0x0000
2475 #define DISP_PLL_CON0                   0x0100
2476 #define DISP_PLL_CON1                   0x0104
2477 #define DISP_PLL_FREQ_DET               0x0108
2478 #define MUX_SEL_DISP0                   0x0200
2479 #define MUX_SEL_DISP1                   0x0204
2480 #define MUX_SEL_DISP2                   0x0208
2481 #define MUX_SEL_DISP3                   0x020c
2482 #define MUX_SEL_DISP4                   0x0210
2483 #define MUX_ENABLE_DISP0                0x0300
2484 #define MUX_ENABLE_DISP1                0x0304
2485 #define MUX_ENABLE_DISP2                0x0308
2486 #define MUX_ENABLE_DISP3                0x030c
2487 #define MUX_ENABLE_DISP4                0x0310
2488 #define MUX_STAT_DISP0                  0x0400
2489 #define MUX_STAT_DISP1                  0x0404
2490 #define MUX_STAT_DISP2                  0x0408
2491 #define MUX_STAT_DISP3                  0x040c
2492 #define MUX_STAT_DISP4                  0x0410
2493 #define MUX_IGNORE_DISP2                0x0508
2494 #define DIV_DISP                        0x0600
2495 #define DIV_DISP_PLL_FREQ_DET           0x0604
2496 #define DIV_STAT_DISP                   0x0700
2497 #define DIV_STAT_DISP_PLL_FREQ_DET      0x0704
2498 #define ENABLE_ACLK_DISP0               0x0800
2499 #define ENABLE_ACLK_DISP1               0x0804
2500 #define ENABLE_PCLK_DISP                0x0900
2501 #define ENABLE_SCLK_DISP                0x0a00
2502 #define ENABLE_IP_DISP0                 0x0b00
2503 #define ENABLE_IP_DISP1                 0x0b04
2504 #define CLKOUT_CMU_DISP                 0x0c00
2505 #define CLKOUT_CMU_DISP_DIV_STAT        0x0c04
2506
2507 static const unsigned long disp_clk_regs[] __initconst = {
2508         DISP_PLL_LOCK,
2509         DISP_PLL_CON0,
2510         DISP_PLL_CON1,
2511         DISP_PLL_FREQ_DET,
2512         MUX_SEL_DISP0,
2513         MUX_SEL_DISP1,
2514         MUX_SEL_DISP2,
2515         MUX_SEL_DISP3,
2516         MUX_SEL_DISP4,
2517         MUX_ENABLE_DISP0,
2518         MUX_ENABLE_DISP1,
2519         MUX_ENABLE_DISP2,
2520         MUX_ENABLE_DISP3,
2521         MUX_ENABLE_DISP4,
2522         MUX_IGNORE_DISP2,
2523         DIV_DISP,
2524         DIV_DISP_PLL_FREQ_DET,
2525         ENABLE_ACLK_DISP0,
2526         ENABLE_ACLK_DISP1,
2527         ENABLE_PCLK_DISP,
2528         ENABLE_SCLK_DISP,
2529         ENABLE_IP_DISP0,
2530         ENABLE_IP_DISP1,
2531         CLKOUT_CMU_DISP,
2532         CLKOUT_CMU_DISP_DIV_STAT,
2533 };
2534
2535 static const struct samsung_clk_reg_dump disp_suspend_regs[] = {
2536         /* PLL has to be enabled for suspend */
2537         { DISP_PLL_CON0, 0x85f40502 },
2538         /* ignore status of external PHY muxes during suspend to avoid hangs */
2539         { MUX_IGNORE_DISP2, 0x00111111 },
2540         { MUX_SEL_DISP0, 0 },
2541         { MUX_SEL_DISP1, 0 },
2542         { MUX_SEL_DISP2, 0 },
2543         { MUX_SEL_DISP3, 0 },
2544         { MUX_SEL_DISP4, 0 },
2545 };
2546
2547 /* list of all parent clock list */
2548 PNAME(mout_disp_pll_p)                  = { "oscclk", "fout_disp_pll", };
2549 PNAME(mout_sclk_dsim1_user_p)           = { "oscclk", "sclk_dsim1_disp", };
2550 PNAME(mout_sclk_dsim0_user_p)           = { "oscclk", "sclk_dsim0_disp", };
2551 PNAME(mout_sclk_dsd_user_p)             = { "oscclk", "sclk_dsd_disp", };
2552 PNAME(mout_sclk_decon_tv_eclk_user_p)   = { "oscclk",
2553                                             "sclk_decon_tv_eclk_disp", };
2554 PNAME(mout_sclk_decon_vclk_user_p)      = { "oscclk",
2555                                             "sclk_decon_vclk_disp", };
2556 PNAME(mout_sclk_decon_eclk_user_p)      = { "oscclk",
2557                                             "sclk_decon_eclk_disp", };
2558 PNAME(mout_sclk_decon_tv_vlkc_user_p)   = { "oscclk",
2559                                             "sclk_decon_tv_vclk_disp", };
2560 PNAME(mout_aclk_disp_333_user_p)        = { "oscclk", "aclk_disp_333", };
2561
2562 PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p)  = { "oscclk",
2563                                         "phyclk_mipidphy1_bitclkdiv8_phy", };
2564 PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p)   = { "oscclk",
2565                                         "phyclk_mipidphy1_rxclkesc0_phy", };
2566 PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p)  = { "oscclk",
2567                                         "phyclk_mipidphy0_bitclkdiv8_phy", };
2568 PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p)   = { "oscclk",
2569                                         "phyclk_mipidphy0_rxclkesc0_phy", };
2570 PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p)     = { "oscclk",
2571                                         "phyclk_hdmiphy_tmds_clko_phy", };
2572 PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p)    = { "oscclk",
2573                                         "phyclk_hdmiphy_pixel_clko_phy", };
2574
2575 PNAME(mout_sclk_dsim0_p)                = { "mout_disp_pll",
2576                                             "mout_sclk_dsim0_user", };
2577 PNAME(mout_sclk_decon_tv_eclk_p)        = { "mout_disp_pll",
2578                                             "mout_sclk_decon_tv_eclk_user", };
2579 PNAME(mout_sclk_decon_vclk_p)           = { "mout_disp_pll",
2580                                             "mout_sclk_decon_vclk_user", };
2581 PNAME(mout_sclk_decon_eclk_p)           = { "mout_disp_pll",
2582                                             "mout_sclk_decon_eclk_user", };
2583
2584 PNAME(mout_sclk_dsim1_b_disp_p)         = { "mout_sclk_dsim1_a_disp",
2585                                             "mout_sclk_dsim1_user", };
2586 PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2587                                 "mout_phyclk_hdmiphy_pixel_clko_user",
2588                                 "mout_sclk_decon_tv_vclk_b_disp", };
2589 PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2590                                             "mout_sclk_decon_tv_vclk_user", };
2591
2592 static const struct samsung_pll_clock disp_pll_clks[] __initconst = {
2593         PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2594                 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5433_pll_rates),
2595 };
2596
2597 static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = {
2598         /*
2599          * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2600          * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2601          * and sclk_decon_{vclk|tv_vclk}.
2602          */
2603         FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
2604                         1, 2, 0),
2605         FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2606                         1, 2, 0),
2607 };
2608
2609 static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
2610         /* PHY clocks from MIPI_DPHY1 */
2611         FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
2612         FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
2613         /* PHY clocks from MIPI_DPHY0 */
2614         FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
2615                         NULL, 0, 188000000),
2616         FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
2617                         NULL, 0, 100000000),
2618         /* PHY clocks from HDMI_PHY */
2619         FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
2620                         NULL, 0, 300000000),
2621         FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy",
2622                         NULL, 0, 166000000),
2623 };
2624
2625 static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
2626         /* MUX_SEL_DISP0 */
2627         MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2628                         0, 1),
2629
2630         /* MUX_SEL_DISP1 */
2631         MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
2632                         mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2633         MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
2634                         mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2635         MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
2636                         MUX_SEL_DISP1, 20, 1),
2637         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
2638                         mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2639         MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
2640                         mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2641         MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
2642                         mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2643         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
2644                         mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2645         MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
2646                         mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2647
2648         /* MUX_SEL_DISP2 */
2649         MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
2650                         "mout_phyclk_mipidphy1_bitclkdiv8_user",
2651                         mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
2652                         20, 1),
2653         MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
2654                         "mout_phyclk_mipidphy1_rxclkesc0_user",
2655                         mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
2656                         16, 1),
2657         MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
2658                         "mout_phyclk_mipidphy0_bitclkdiv8_user",
2659                         mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
2660                         12, 1),
2661         MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
2662                         "mout_phyclk_mipidphy0_rxclkesc0_user",
2663                         mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
2664                         8, 1),
2665         MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
2666                         "mout_phyclk_hdmiphy_tmds_clko_user",
2667                         mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
2668                         4, 1),
2669         MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
2670                         "mout_phyclk_hdmiphy_pixel_clko_user",
2671                         mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
2672                         0, 1),
2673
2674         /* MUX_SEL_DISP3 */
2675         MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
2676                         MUX_SEL_DISP3, 12, 1),
2677         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
2678                         mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
2679         MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
2680                         mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
2681         MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
2682                         mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2683
2684         /* MUX_SEL_DISP4 */
2685         MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
2686                         mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
2687         MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
2688                         mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
2689         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2690                         "mout_sclk_decon_tv_vclk_c_disp",
2691                         mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
2692         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2693                         "mout_sclk_decon_tv_vclk_b_disp",
2694                         mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
2695         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
2696                         "mout_sclk_decon_tv_vclk_a_disp",
2697                         mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2698 };
2699
2700 static const struct samsung_div_clock disp_div_clks[] __initconst = {
2701         /* DIV_DISP */
2702         DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2703                         "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
2704         DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
2705                         "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
2706         DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2707                         DIV_DISP, 16, 3),
2708         DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
2709                         "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
2710         DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
2711                         "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
2712         DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
2713                         "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
2714         DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
2715                         DIV_DISP, 0, 2),
2716 };
2717
2718 static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
2719         /* ENABLE_ACLK_DISP0 */
2720         GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2721                         ENABLE_ACLK_DISP0, 2, 0, 0),
2722         GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
2723                         ENABLE_ACLK_DISP0, 0, 0, 0),
2724
2725         /* ENABLE_ACLK_DISP1 */
2726         GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2727                         ENABLE_ACLK_DISP1, 25, 0, 0),
2728         GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2729                         ENABLE_ACLK_DISP1, 24, 0, 0),
2730         GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
2731                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2732         GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
2733                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2734         GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
2735                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2736         GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
2737                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2738         GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
2739                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2740         GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
2741                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2742         GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
2743                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2744         GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
2745                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2746         GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
2747                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2748         GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
2749                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2750         GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
2751                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2752         GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
2753                         "div_pclk_disp", ENABLE_ACLK_DISP1,
2754                         12, CLK_IGNORE_UNUSED, 0),
2755         GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
2756                         "div_pclk_disp", ENABLE_ACLK_DISP1,
2757                         11, CLK_IGNORE_UNUSED, 0),
2758         GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
2759                         "div_pclk_disp", ENABLE_ACLK_DISP1,
2760                         10, CLK_IGNORE_UNUSED, 0),
2761         GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
2762                         ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2763         GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2764                         ENABLE_ACLK_DISP1, 7, 0, 0),
2765         GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2766                         ENABLE_ACLK_DISP1, 6, 0, 0),
2767         GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
2768                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2769         GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
2770                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2771         GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2772                         ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2773         GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
2774                         ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2775         GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
2776                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
2777                         CLK_IGNORE_UNUSED, 0),
2778         GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
2779                         "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
2780                         0, CLK_IGNORE_UNUSED, 0),
2781
2782         /* ENABLE_PCLK_DISP */
2783         GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
2784                         ENABLE_PCLK_DISP, 23, 0, 0),
2785         GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
2786                         ENABLE_PCLK_DISP, 22, 0, 0),
2787         GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
2788                         ENABLE_PCLK_DISP, 21, 0, 0),
2789         GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
2790                         ENABLE_PCLK_DISP, 20, 0, 0),
2791         GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2792                         ENABLE_PCLK_DISP, 19, 0, 0),
2793         GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2794                         ENABLE_PCLK_DISP, 18, 0, 0),
2795         GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2796                         ENABLE_PCLK_DISP, 17, 0, 0),
2797         GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2798                         ENABLE_PCLK_DISP, 16, 0, 0),
2799         GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
2800                         ENABLE_PCLK_DISP, 15, 0, 0),
2801         GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
2802                         ENABLE_PCLK_DISP, 14, 0, 0),
2803         GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
2804                         ENABLE_PCLK_DISP, 13, 0, 0),
2805         GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
2806                         ENABLE_PCLK_DISP, 12, 0, 0),
2807         GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
2808                         ENABLE_PCLK_DISP, 11, 0, 0),
2809         GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
2810                         ENABLE_PCLK_DISP, 10, 0, 0),
2811         GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
2812                         ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2813         GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
2814                         ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2815         GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
2816                         ENABLE_PCLK_DISP, 7, 0, 0),
2817         GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
2818                         ENABLE_PCLK_DISP, 6, 0, 0),
2819         GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
2820                         ENABLE_PCLK_DISP, 5, 0, 0),
2821         GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
2822                         ENABLE_PCLK_DISP, 3, 0, 0),
2823         GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
2824                         ENABLE_PCLK_DISP, 2, 0, 0),
2825         GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
2826                         ENABLE_PCLK_DISP, 1, 0, 0),
2827         GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp",
2828                         ENABLE_PCLK_DISP, 0, 0, 0),
2829
2830         /* ENABLE_SCLK_DISP */
2831         GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
2832                         "mout_phyclk_mipidphy1_bitclkdiv8_user",
2833                         ENABLE_SCLK_DISP, 26, 0, 0),
2834         GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
2835                         "mout_phyclk_mipidphy1_rxclkesc0_user",
2836                         ENABLE_SCLK_DISP, 25, 0, 0),
2837         GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
2838                         "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2839         GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
2840                         "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2841         GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
2842                         ENABLE_SCLK_DISP, 22, 0, 0),
2843         GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
2844                         "div_sclk_decon_tv_vclk_disp",
2845                         ENABLE_SCLK_DISP, 21, 0, 0),
2846         GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
2847                         "mout_phyclk_mipidphy0_bitclkdiv8_user",
2848                         ENABLE_SCLK_DISP, 15, 0, 0),
2849         GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
2850                         "mout_phyclk_mipidphy0_rxclkesc0_user",
2851                         ENABLE_SCLK_DISP, 14, 0, 0),
2852         GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
2853                         "mout_phyclk_hdmiphy_tmds_clko_user",
2854                         ENABLE_SCLK_DISP, 13, 0, 0),
2855         GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
2856                         "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2857         GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
2858                         "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2859         GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
2860                         "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2861         GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
2862                         "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2863         GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
2864                         ENABLE_SCLK_DISP, 7, 0, 0),
2865         GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2866                         ENABLE_SCLK_DISP, 6, 0, 0),
2867         GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
2868                         ENABLE_SCLK_DISP, 5, 0, 0),
2869         GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
2870                         "div_sclk_decon_tv_eclk_disp",
2871                         ENABLE_SCLK_DISP, 4, 0, 0),
2872         GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
2873                         "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2874         GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
2875                         "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2876 };
2877
2878 static const struct samsung_cmu_info disp_cmu_info __initconst = {
2879         .pll_clks               = disp_pll_clks,
2880         .nr_pll_clks            = ARRAY_SIZE(disp_pll_clks),
2881         .mux_clks               = disp_mux_clks,
2882         .nr_mux_clks            = ARRAY_SIZE(disp_mux_clks),
2883         .div_clks               = disp_div_clks,
2884         .nr_div_clks            = ARRAY_SIZE(disp_div_clks),
2885         .gate_clks              = disp_gate_clks,
2886         .nr_gate_clks           = ARRAY_SIZE(disp_gate_clks),
2887         .fixed_clks             = disp_fixed_clks,
2888         .nr_fixed_clks          = ARRAY_SIZE(disp_fixed_clks),
2889         .fixed_factor_clks      = disp_fixed_factor_clks,
2890         .nr_fixed_factor_clks   = ARRAY_SIZE(disp_fixed_factor_clks),
2891         .nr_clk_ids             = DISP_NR_CLK,
2892         .clk_regs               = disp_clk_regs,
2893         .nr_clk_regs            = ARRAY_SIZE(disp_clk_regs),
2894         .suspend_regs           = disp_suspend_regs,
2895         .nr_suspend_regs        = ARRAY_SIZE(disp_suspend_regs),
2896         .clk_name               = "aclk_disp_333",
2897 };
2898
2899 /*
2900  * Register offset definitions for CMU_AUD
2901  */
2902 #define MUX_SEL_AUD0                    0x0200
2903 #define MUX_SEL_AUD1                    0x0204
2904 #define MUX_ENABLE_AUD0                 0x0300
2905 #define MUX_ENABLE_AUD1                 0x0304
2906 #define MUX_STAT_AUD0                   0x0400
2907 #define DIV_AUD0                        0x0600
2908 #define DIV_AUD1                        0x0604
2909 #define DIV_STAT_AUD0                   0x0700
2910 #define DIV_STAT_AUD1                   0x0704
2911 #define ENABLE_ACLK_AUD                 0x0800
2912 #define ENABLE_PCLK_AUD                 0x0900
2913 #define ENABLE_SCLK_AUD0                0x0a00
2914 #define ENABLE_SCLK_AUD1                0x0a04
2915 #define ENABLE_IP_AUD0                  0x0b00
2916 #define ENABLE_IP_AUD1                  0x0b04
2917
2918 static const unsigned long aud_clk_regs[] __initconst = {
2919         MUX_SEL_AUD0,
2920         MUX_SEL_AUD1,
2921         MUX_ENABLE_AUD0,
2922         MUX_ENABLE_AUD1,
2923         DIV_AUD0,
2924         DIV_AUD1,
2925         ENABLE_ACLK_AUD,
2926         ENABLE_PCLK_AUD,
2927         ENABLE_SCLK_AUD0,
2928         ENABLE_SCLK_AUD1,
2929         ENABLE_IP_AUD0,
2930         ENABLE_IP_AUD1,
2931 };
2932
2933 static const struct samsung_clk_reg_dump aud_suspend_regs[] = {
2934         { MUX_SEL_AUD0, 0 },
2935         { MUX_SEL_AUD1, 0 },
2936 };
2937
2938 /* list of all parent clock list */
2939 PNAME(mout_aud_pll_user_aud_p)  = { "oscclk", "fout_aud_pll", };
2940 PNAME(mout_sclk_aud_pcm_p)      = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2941
2942 static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
2943         FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000),
2944         FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000),
2945         FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000),
2946 };
2947
2948 static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
2949         /* MUX_SEL_AUD0 */
2950         MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2951                         mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2952
2953         /* MUX_SEL_AUD1 */
2954         MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
2955                         MUX_SEL_AUD1, 8, 1),
2956         MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
2957                         MUX_SEL_AUD1, 0, 1),
2958 };
2959
2960 static const struct samsung_div_clock aud_div_clks[] __initconst = {
2961         /* DIV_AUD0 */
2962         DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2963                         12, 4),
2964         DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
2965                         8, 4),
2966         DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
2967                         4, 4),
2968         DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
2969                         0, 4),
2970
2971         /* DIV_AUD1 */
2972         DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
2973                         "mout_aud_pll_user", DIV_AUD1, 16, 5),
2974         DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
2975                         DIV_AUD1, 12, 4),
2976         DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
2977                         DIV_AUD1, 4, 8),
2978         DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s",  "mout_sclk_aud_i2s",
2979                         DIV_AUD1, 0, 4),
2980 };
2981
2982 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
2983         /* ENABLE_ACLK_AUD */
2984         GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
2985                         ENABLE_ACLK_AUD, 12, 0, 0),
2986         GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
2987                         ENABLE_ACLK_AUD, 7, 0, 0),
2988         GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
2989                         ENABLE_ACLK_AUD, 0, 4, 0),
2990         GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
2991                         ENABLE_ACLK_AUD, 0, 3, 0),
2992         GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
2993                         ENABLE_ACLK_AUD, 0, 2, 0),
2994         GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
2995                         0, 1, 0),
2996         GATE(CLK_ACLK_DMAC, "aclk_dmac",  "div_aclk_aud", ENABLE_ACLK_AUD,
2997                         0, CLK_IGNORE_UNUSED, 0),
2998
2999         /* ENABLE_PCLK_AUD */
3000         GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
3001                         13, 0, 0),
3002         GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
3003                         12, 0, 0),
3004         GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
3005                         11, 0, 0),
3006         GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
3007                         ENABLE_PCLK_AUD, 10, 0, 0),
3008         GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
3009                         ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
3010         GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
3011                         ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
3012         GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
3013                         ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
3014         GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
3015                         ENABLE_PCLK_AUD, 6, 0, 0),
3016         GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
3017                         ENABLE_PCLK_AUD, 5, 0, 0),
3018         GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
3019                         ENABLE_PCLK_AUD, 4, 0, 0),
3020         GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
3021                         ENABLE_PCLK_AUD, 3, 0, 0),
3022         GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
3023                         2, 0, 0),
3024         GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
3025                         ENABLE_PCLK_AUD, 0, 0, 0),
3026
3027         /* ENABLE_SCLK_AUD0 */
3028         GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
3029                         2, CLK_IGNORE_UNUSED, 0),
3030         GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
3031                         ENABLE_SCLK_AUD0, 1, 0, 0),
3032         GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
3033                         0, 0, 0),
3034
3035         /* ENABLE_SCLK_AUD1 */
3036         GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
3037                         ENABLE_SCLK_AUD1, 6, 0, 0),
3038         GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
3039                         ENABLE_SCLK_AUD1, 5, 0, 0),
3040         GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
3041                         ENABLE_SCLK_AUD1, 4, 0, 0),
3042         GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
3043                         ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
3044         GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
3045                         ENABLE_SCLK_AUD1, 2, 0, 0),
3046         GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
3047                         ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
3048         GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
3049                         ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
3050 };
3051
3052 static const struct samsung_cmu_info aud_cmu_info __initconst = {
3053         .mux_clks               = aud_mux_clks,
3054         .nr_mux_clks            = ARRAY_SIZE(aud_mux_clks),
3055         .div_clks               = aud_div_clks,
3056         .nr_div_clks            = ARRAY_SIZE(aud_div_clks),
3057         .gate_clks              = aud_gate_clks,
3058         .nr_gate_clks           = ARRAY_SIZE(aud_gate_clks),
3059         .fixed_clks             = aud_fixed_clks,
3060         .nr_fixed_clks          = ARRAY_SIZE(aud_fixed_clks),
3061         .nr_clk_ids             = AUD_NR_CLK,
3062         .clk_regs               = aud_clk_regs,
3063         .nr_clk_regs            = ARRAY_SIZE(aud_clk_regs),
3064         .suspend_regs           = aud_suspend_regs,
3065         .nr_suspend_regs        = ARRAY_SIZE(aud_suspend_regs),
3066         .clk_name               = "fout_aud_pll",
3067 };
3068
3069 /*
3070  * Register offset definitions for CMU_BUS{0|1|2}
3071  */
3072 #define DIV_BUS                         0x0600
3073 #define DIV_STAT_BUS                    0x0700
3074 #define ENABLE_ACLK_BUS                 0x0800
3075 #define ENABLE_PCLK_BUS                 0x0900
3076 #define ENABLE_IP_BUS0                  0x0b00
3077 #define ENABLE_IP_BUS1                  0x0b04
3078
3079 #define MUX_SEL_BUS2                    0x0200  /* Only for CMU_BUS2 */
3080 #define MUX_ENABLE_BUS2                 0x0300  /* Only for CMU_BUS2 */
3081 #define MUX_STAT_BUS2                   0x0400  /* Only for CMU_BUS2 */
3082
3083 /* list of all parent clock list */
3084 PNAME(mout_aclk_bus2_400_p)     = { "oscclk", "aclk_bus2_400", };
3085
3086 #define CMU_BUS_COMMON_CLK_REGS \
3087         DIV_BUS,                \
3088         ENABLE_ACLK_BUS,        \
3089         ENABLE_PCLK_BUS,        \
3090         ENABLE_IP_BUS0,         \
3091         ENABLE_IP_BUS1
3092
3093 static const unsigned long bus01_clk_regs[] __initconst = {
3094         CMU_BUS_COMMON_CLK_REGS,
3095 };
3096
3097 static const unsigned long bus2_clk_regs[] __initconst = {
3098         MUX_SEL_BUS2,
3099         MUX_ENABLE_BUS2,
3100         CMU_BUS_COMMON_CLK_REGS,
3101 };
3102
3103 static const struct samsung_div_clock bus0_div_clks[] __initconst = {
3104         /* DIV_BUS0 */
3105         DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3106                         DIV_BUS, 0, 3),
3107 };
3108
3109 /* CMU_BUS0 clocks */
3110 static const struct samsung_gate_clock bus0_gate_clks[] __initconst = {
3111         /* ENABLE_ACLK_BUS0 */
3112         GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3113                         ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3114         GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
3115                         ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3116         GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
3117                         ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3118
3119         /* ENABLE_PCLK_BUS0 */
3120         GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
3121                         ENABLE_PCLK_BUS, 2, 0, 0),
3122         GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
3123                         ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3124         GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3125                         ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3126 };
3127
3128 /* CMU_BUS1 clocks */
3129 static const struct samsung_div_clock bus1_div_clks[] __initconst = {
3130         /* DIV_BUS1 */
3131         DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3132                         DIV_BUS, 0, 3),
3133 };
3134
3135 static const struct samsung_gate_clock bus1_gate_clks[] __initconst = {
3136         /* ENABLE_ACLK_BUS1 */
3137         GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3138                         ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3139         GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
3140                         ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3141         GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
3142                         ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3143
3144         /* ENABLE_PCLK_BUS1 */
3145         GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
3146                         ENABLE_PCLK_BUS, 2, 0, 0),
3147         GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
3148                         ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3149         GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3150                         ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3151 };
3152
3153 /* CMU_BUS2 clocks */
3154 static const struct samsung_mux_clock bus2_mux_clks[] __initconst = {
3155         /* MUX_SEL_BUS2 */
3156         MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3157                         mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3158 };
3159
3160 static const struct samsung_div_clock bus2_div_clks[] __initconst = {
3161         /* DIV_BUS2 */
3162         DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3163                         "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3164 };
3165
3166 static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {
3167         /* ENABLE_ACLK_BUS2 */
3168         GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3169                         ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3170         GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
3171                         ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3172         GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
3173                         "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3174                         1, CLK_IGNORE_UNUSED, 0),
3175         GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
3176                         "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3177                         0, CLK_IGNORE_UNUSED, 0),
3178
3179         /* ENABLE_PCLK_BUS2 */
3180         GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
3181                         ENABLE_PCLK_BUS, 2, 0, 0),
3182         GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
3183                         ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3184         GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
3185                         ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3186 };
3187
3188 #define CMU_BUS_INFO_CLKS(id)                                           \
3189         .div_clks               = bus##id##_div_clks,                   \
3190         .nr_div_clks            = ARRAY_SIZE(bus##id##_div_clks),       \
3191         .gate_clks              = bus##id##_gate_clks,                  \
3192         .nr_gate_clks           = ARRAY_SIZE(bus##id##_gate_clks),      \
3193         .nr_clk_ids             = BUSx_NR_CLK
3194
3195 static const struct samsung_cmu_info bus0_cmu_info __initconst = {
3196         CMU_BUS_INFO_CLKS(0),
3197         .clk_regs               = bus01_clk_regs,
3198         .nr_clk_regs            = ARRAY_SIZE(bus01_clk_regs),
3199 };
3200
3201 static const struct samsung_cmu_info bus1_cmu_info __initconst = {
3202         CMU_BUS_INFO_CLKS(1),
3203         .clk_regs               = bus01_clk_regs,
3204         .nr_clk_regs            = ARRAY_SIZE(bus01_clk_regs),
3205 };
3206
3207 static const struct samsung_cmu_info bus2_cmu_info __initconst = {
3208         CMU_BUS_INFO_CLKS(2),
3209         .mux_clks               = bus2_mux_clks,
3210         .nr_mux_clks            = ARRAY_SIZE(bus2_mux_clks),
3211         .clk_regs               = bus2_clk_regs,
3212         .nr_clk_regs            = ARRAY_SIZE(bus2_clk_regs),
3213 };
3214
3215 #define exynos5433_cmu_bus_init(id)                                     \
3216 static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
3217 {                                                                       \
3218         samsung_cmu_register_one(np, &bus##id##_cmu_info);              \
3219 }                                                                       \
3220 CLK_OF_DECLARE(exynos5433_cmu_bus##id,                                  \
3221                 "samsung,exynos5433-cmu-bus"#id,                        \
3222                 exynos5433_cmu_bus##id##_init)
3223
3224 exynos5433_cmu_bus_init(0);
3225 exynos5433_cmu_bus_init(1);
3226 exynos5433_cmu_bus_init(2);
3227
3228 /*
3229  * Register offset definitions for CMU_G3D
3230  */
3231 #define G3D_PLL_LOCK                    0x0000
3232 #define G3D_PLL_CON0                    0x0100
3233 #define G3D_PLL_CON1                    0x0104
3234 #define G3D_PLL_FREQ_DET                0x010c
3235 #define MUX_SEL_G3D                     0x0200
3236 #define MUX_ENABLE_G3D                  0x0300
3237 #define MUX_STAT_G3D                    0x0400
3238 #define DIV_G3D                         0x0600
3239 #define DIV_G3D_PLL_FREQ_DET            0x0604
3240 #define DIV_STAT_G3D                    0x0700
3241 #define DIV_STAT_G3D_PLL_FREQ_DET       0x0704
3242 #define ENABLE_ACLK_G3D                 0x0800
3243 #define ENABLE_PCLK_G3D                 0x0900
3244 #define ENABLE_SCLK_G3D                 0x0a00
3245 #define ENABLE_IP_G3D0                  0x0b00
3246 #define ENABLE_IP_G3D1                  0x0b04
3247 #define CLKOUT_CMU_G3D                  0x0c00
3248 #define CLKOUT_CMU_G3D_DIV_STAT         0x0c04
3249 #define CLK_STOPCTRL                    0x1000
3250
3251 static const unsigned long g3d_clk_regs[] __initconst = {
3252         G3D_PLL_LOCK,
3253         G3D_PLL_CON0,
3254         G3D_PLL_CON1,
3255         G3D_PLL_FREQ_DET,
3256         MUX_SEL_G3D,
3257         MUX_ENABLE_G3D,
3258         DIV_G3D,
3259         DIV_G3D_PLL_FREQ_DET,
3260         ENABLE_ACLK_G3D,
3261         ENABLE_PCLK_G3D,
3262         ENABLE_SCLK_G3D,
3263         ENABLE_IP_G3D0,
3264         ENABLE_IP_G3D1,
3265         CLKOUT_CMU_G3D,
3266         CLKOUT_CMU_G3D_DIV_STAT,
3267         CLK_STOPCTRL,
3268 };
3269
3270 static const struct samsung_clk_reg_dump g3d_suspend_regs[] = {
3271         { MUX_SEL_G3D, 0 },
3272 };
3273
3274 /* list of all parent clock list */
3275 PNAME(mout_aclk_g3d_400_p)      = { "mout_g3d_pll", "aclk_g3d_400", };
3276 PNAME(mout_g3d_pll_p)           = { "oscclk", "fout_g3d_pll", };
3277
3278 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
3279         PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3280                 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5433_pll_rates),
3281 };
3282
3283 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
3284         /* MUX_SEL_G3D */
3285         MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3286                         MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
3287         MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
3288                         MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
3289 };
3290
3291 static const struct samsung_div_clock g3d_div_clks[] __initconst = {
3292         /* DIV_G3D */
3293         DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3294                         8, 2),
3295         DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
3296                         4, 3),
3297         DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
3298                         0, 3, CLK_SET_RATE_PARENT, 0),
3299 };
3300
3301 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
3302         /* ENABLE_ACLK_G3D */
3303         GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3304                         ENABLE_ACLK_G3D, 7, 0, 0),
3305         GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
3306                         ENABLE_ACLK_G3D, 6, 0, 0),
3307         GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
3308                         ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0),
3309         GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
3310                         ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0),
3311         GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
3312                         ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3313         GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
3314                         ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3315         GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
3316                         ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3317         GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
3318                         ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
3319
3320         /* ENABLE_PCLK_G3D */
3321         GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
3322                         ENABLE_PCLK_G3D, 3, 0, 0),
3323         GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
3324                         ENABLE_PCLK_G3D, 2, 0, 0),
3325         GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
3326                         ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3327         GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
3328                         ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3329
3330         /* ENABLE_SCLK_G3D */
3331         GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
3332                         ENABLE_SCLK_G3D, 0, 0, 0),
3333 };
3334
3335 static const struct samsung_cmu_info g3d_cmu_info __initconst = {
3336         .pll_clks               = g3d_pll_clks,
3337         .nr_pll_clks            = ARRAY_SIZE(g3d_pll_clks),
3338         .mux_clks               = g3d_mux_clks,
3339         .nr_mux_clks            = ARRAY_SIZE(g3d_mux_clks),
3340         .div_clks               = g3d_div_clks,
3341         .nr_div_clks            = ARRAY_SIZE(g3d_div_clks),
3342         .gate_clks              = g3d_gate_clks,
3343         .nr_gate_clks           = ARRAY_SIZE(g3d_gate_clks),
3344         .nr_clk_ids             = G3D_NR_CLK,
3345         .clk_regs               = g3d_clk_regs,
3346         .nr_clk_regs            = ARRAY_SIZE(g3d_clk_regs),
3347         .suspend_regs           = g3d_suspend_regs,
3348         .nr_suspend_regs        = ARRAY_SIZE(g3d_suspend_regs),
3349         .clk_name               = "aclk_g3d_400",
3350 };
3351
3352 /*
3353  * Register offset definitions for CMU_GSCL
3354  */
3355 #define MUX_SEL_GSCL                            0x0200
3356 #define MUX_ENABLE_GSCL                         0x0300
3357 #define MUX_STAT_GSCL                           0x0400
3358 #define ENABLE_ACLK_GSCL                        0x0800
3359 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0      0x0804
3360 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1      0x0808
3361 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2      0x080c
3362 #define ENABLE_PCLK_GSCL                        0x0900
3363 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0      0x0904
3364 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1      0x0908
3365 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2      0x090c
3366 #define ENABLE_IP_GSCL0                         0x0b00
3367 #define ENABLE_IP_GSCL1                         0x0b04
3368 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0        0x0b08
3369 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1        0x0b0c
3370 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2        0x0b10
3371
3372 static const unsigned long gscl_clk_regs[] __initconst = {
3373         MUX_SEL_GSCL,
3374         MUX_ENABLE_GSCL,
3375         ENABLE_ACLK_GSCL,
3376         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
3377         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
3378         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
3379         ENABLE_PCLK_GSCL,
3380         ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
3381         ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
3382         ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
3383         ENABLE_IP_GSCL0,
3384         ENABLE_IP_GSCL1,
3385         ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
3386         ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
3387         ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
3388 };
3389
3390 static const struct samsung_clk_reg_dump gscl_suspend_regs[] = {
3391         { MUX_SEL_GSCL, 0 },
3392         { ENABLE_ACLK_GSCL, 0xfff },
3393         { ENABLE_PCLK_GSCL, 0xff },
3394 };
3395
3396 /* list of all parent clock list */
3397 PNAME(aclk_gscl_111_user_p)     = { "oscclk", "aclk_gscl_111", };
3398 PNAME(aclk_gscl_333_user_p)     = { "oscclk", "aclk_gscl_333", };
3399
3400 static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
3401         /* MUX_SEL_GSCL */
3402         MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3403                         aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
3404         MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
3405                         aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3406 };
3407
3408 static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
3409         /* ENABLE_ACLK_GSCL */
3410         GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3411                         ENABLE_ACLK_GSCL, 11, 0, 0),
3412         GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
3413                         ENABLE_ACLK_GSCL, 10, 0, 0),
3414         GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
3415                         ENABLE_ACLK_GSCL, 9, 0, 0),
3416         GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
3417                         "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
3418                         8, CLK_IGNORE_UNUSED, 0),
3419         GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
3420                         ENABLE_ACLK_GSCL, 7, 0, 0),
3421         GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3422                         ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3423         GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3424                         "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5,
3425                         CLK_IGNORE_UNUSED, 0),
3426         GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3427                         "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4,
3428                         CLK_IGNORE_UNUSED, 0),
3429         GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3430                         ENABLE_ACLK_GSCL, 3, 0, 0),
3431         GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
3432                         ENABLE_ACLK_GSCL, 2, 0, 0),
3433         GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
3434                         ENABLE_ACLK_GSCL, 1, 0, 0),
3435         GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
3436                         ENABLE_ACLK_GSCL, 0, 0, 0),
3437
3438         /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
3439         GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
3440                         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3441
3442         /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
3443         GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
3444                         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3445
3446         /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
3447         GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
3448                         ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3449
3450         /* ENABLE_PCLK_GSCL */
3451         GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
3452                         ENABLE_PCLK_GSCL, 7, 0, 0),
3453         GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
3454                         ENABLE_PCLK_GSCL, 6, 0, 0),
3455         GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
3456                         ENABLE_PCLK_GSCL, 5, 0, 0),
3457         GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
3458                         ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3459         GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
3460                         "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
3461                         3, CLK_IGNORE_UNUSED, 0),
3462         GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
3463                         ENABLE_PCLK_GSCL, 2, 0, 0),
3464         GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
3465                         ENABLE_PCLK_GSCL, 1, 0, 0),
3466         GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
3467                         ENABLE_PCLK_GSCL, 0, 0, 0),
3468
3469         /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
3470         GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
3471                 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3472
3473         /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
3474         GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
3475                 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3476
3477         /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
3478         GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
3479                 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3480 };
3481
3482 static const struct samsung_cmu_info gscl_cmu_info __initconst = {
3483         .mux_clks               = gscl_mux_clks,
3484         .nr_mux_clks            = ARRAY_SIZE(gscl_mux_clks),
3485         .gate_clks              = gscl_gate_clks,
3486         .nr_gate_clks           = ARRAY_SIZE(gscl_gate_clks),
3487         .nr_clk_ids             = GSCL_NR_CLK,
3488         .clk_regs               = gscl_clk_regs,
3489         .nr_clk_regs            = ARRAY_SIZE(gscl_clk_regs),
3490         .suspend_regs           = gscl_suspend_regs,
3491         .nr_suspend_regs        = ARRAY_SIZE(gscl_suspend_regs),
3492         .clk_name               = "aclk_gscl_111",
3493 };
3494
3495 /*
3496  * Register offset definitions for CMU_APOLLO
3497  */
3498 #define APOLLO_PLL_LOCK                         0x0000
3499 #define APOLLO_PLL_CON0                         0x0100
3500 #define APOLLO_PLL_CON1                         0x0104
3501 #define APOLLO_PLL_FREQ_DET                     0x010c
3502 #define MUX_SEL_APOLLO0                         0x0200
3503 #define MUX_SEL_APOLLO1                         0x0204
3504 #define MUX_SEL_APOLLO2                         0x0208
3505 #define MUX_ENABLE_APOLLO0                      0x0300
3506 #define MUX_ENABLE_APOLLO1                      0x0304
3507 #define MUX_ENABLE_APOLLO2                      0x0308
3508 #define MUX_STAT_APOLLO0                        0x0400
3509 #define MUX_STAT_APOLLO1                        0x0404
3510 #define MUX_STAT_APOLLO2                        0x0408
3511 #define DIV_APOLLO0                             0x0600
3512 #define DIV_APOLLO1                             0x0604
3513 #define DIV_APOLLO_PLL_FREQ_DET                 0x0608
3514 #define DIV_STAT_APOLLO0                        0x0700
3515 #define DIV_STAT_APOLLO1                        0x0704
3516 #define DIV_STAT_APOLLO_PLL_FREQ_DET            0x0708
3517 #define ENABLE_ACLK_APOLLO                      0x0800
3518 #define ENABLE_PCLK_APOLLO                      0x0900
3519 #define ENABLE_SCLK_APOLLO                      0x0a00
3520 #define ENABLE_IP_APOLLO0                       0x0b00
3521 #define ENABLE_IP_APOLLO1                       0x0b04
3522 #define CLKOUT_CMU_APOLLO                       0x0c00
3523 #define CLKOUT_CMU_APOLLO_DIV_STAT              0x0c04
3524 #define ARMCLK_STOPCTRL                         0x1000
3525 #define APOLLO_PWR_CTRL                         0x1020
3526 #define APOLLO_PWR_CTRL2                        0x1024
3527 #define APOLLO_INTR_SPREAD_ENABLE               0x1080
3528 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI       0x1084
3529 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION    0x1088
3530
3531 static const unsigned long apollo_clk_regs[] __initconst = {
3532         APOLLO_PLL_LOCK,
3533         APOLLO_PLL_CON0,
3534         APOLLO_PLL_CON1,
3535         APOLLO_PLL_FREQ_DET,
3536         MUX_SEL_APOLLO0,
3537         MUX_SEL_APOLLO1,
3538         MUX_SEL_APOLLO2,
3539         MUX_ENABLE_APOLLO0,
3540         MUX_ENABLE_APOLLO1,
3541         MUX_ENABLE_APOLLO2,
3542         DIV_APOLLO0,
3543         DIV_APOLLO1,
3544         DIV_APOLLO_PLL_FREQ_DET,
3545         ENABLE_ACLK_APOLLO,
3546         ENABLE_PCLK_APOLLO,
3547         ENABLE_SCLK_APOLLO,
3548         ENABLE_IP_APOLLO0,
3549         ENABLE_IP_APOLLO1,
3550         CLKOUT_CMU_APOLLO,
3551         CLKOUT_CMU_APOLLO_DIV_STAT,
3552         ARMCLK_STOPCTRL,
3553         APOLLO_PWR_CTRL,
3554         APOLLO_PWR_CTRL2,
3555         APOLLO_INTR_SPREAD_ENABLE,
3556         APOLLO_INTR_SPREAD_USE_STANDBYWFI,
3557         APOLLO_INTR_SPREAD_BLOCKING_DURATION,
3558 };
3559
3560 /* list of all parent clock list */
3561 PNAME(mout_apollo_pll_p)                = { "oscclk", "fout_apollo_pll", };
3562 PNAME(mout_bus_pll_apollo_user_p)       = { "oscclk", "sclk_bus_pll_apollo", };
3563 PNAME(mout_apollo_p)                    = { "mout_apollo_pll",
3564                                             "mout_bus_pll_apollo_user", };
3565
3566 static const struct samsung_pll_clock apollo_pll_clks[] __initconst = {
3567         PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3568                 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5433_pll_rates),
3569 };
3570
3571 static const struct samsung_mux_clock apollo_mux_clks[] __initconst = {
3572         /* MUX_SEL_APOLLO0 */
3573         MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3574                         MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT |
3575                         CLK_RECALC_NEW_RATES, 0),
3576
3577         /* MUX_SEL_APOLLO1 */
3578         MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
3579                         mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3580
3581         /* MUX_SEL_APOLLO2 */
3582         MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
3583                         0, 1, CLK_SET_RATE_PARENT, 0),
3584 };
3585
3586 static const struct samsung_div_clock apollo_div_clks[] __initconst = {
3587         /* DIV_APOLLO0 */
3588         DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3589                         DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
3590                         CLK_DIVIDER_READ_ONLY),
3591         DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
3592                         DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
3593                         CLK_DIVIDER_READ_ONLY),
3594         DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
3595                         DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
3596                         CLK_DIVIDER_READ_ONLY),
3597         DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
3598                         DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
3599                         CLK_DIVIDER_READ_ONLY),
3600         DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
3601                         DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
3602                         CLK_DIVIDER_READ_ONLY),
3603         DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
3604                         DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0),
3605         DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
3606                         DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0),
3607
3608         /* DIV_APOLLO1 */
3609         DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
3610                         DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
3611                         CLK_DIVIDER_READ_ONLY),
3612         DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
3613                         DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3614                         CLK_DIVIDER_READ_ONLY),
3615 };
3616
3617 static const struct samsung_gate_clock apollo_gate_clks[] __initconst = {
3618         /* ENABLE_ACLK_APOLLO */
3619         GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3620                         "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3621                         6, CLK_IGNORE_UNUSED, 0),
3622         GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
3623                         "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3624                         5, CLK_IGNORE_UNUSED, 0),
3625         GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
3626                         "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3627                         4, CLK_IGNORE_UNUSED, 0),
3628         GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
3629                         "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3630                         3, CLK_IGNORE_UNUSED, 0),
3631         GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
3632                         "div_aclk_apollo", ENABLE_ACLK_APOLLO,
3633                         2, CLK_IGNORE_UNUSED, 0),
3634         GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
3635                         "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3636                         1, CLK_IGNORE_UNUSED, 0),
3637         GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
3638                         "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3639                         0, CLK_IGNORE_UNUSED, 0),
3640
3641         /* ENABLE_PCLK_APOLLO */
3642         GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
3643                         "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
3644                         2, CLK_IGNORE_UNUSED, 0),
3645         GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
3646                         ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3647         GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
3648                         "div_pclk_apollo", ENABLE_PCLK_APOLLO,
3649                         0, CLK_IGNORE_UNUSED, 0),
3650
3651         /* ENABLE_SCLK_APOLLO */
3652         GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
3653                         ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3654         GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3655                         ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3656 };
3657
3658 #define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3659                 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3660                  ((pclk) << 12) | ((aclk) << 8))
3661
3662 #define E5433_APOLLO_DIV1(hpm, copy) \
3663                 (((hpm) << 4) | ((copy) << 0))
3664
3665 static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = {
3666         { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3667         { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3668         { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3669         { 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3670         {  900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3671         {  800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3672         {  700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3673         {  600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3674         {  500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3675         {  400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3676         {  0 },
3677 };
3678
3679 static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3680 {
3681         void __iomem *reg_base;
3682         struct samsung_clk_provider *ctx;
3683
3684         reg_base = of_iomap(np, 0);
3685         if (!reg_base) {
3686                 panic("%s: failed to map registers\n", __func__);
3687                 return;
3688         }
3689
3690         ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK);
3691         if (!ctx) {
3692                 panic("%s: unable to allocate ctx\n", __func__);
3693                 return;
3694         }
3695
3696         samsung_clk_register_pll(ctx, apollo_pll_clks,
3697                                  ARRAY_SIZE(apollo_pll_clks), reg_base);
3698         samsung_clk_register_mux(ctx, apollo_mux_clks,
3699                                  ARRAY_SIZE(apollo_mux_clks));
3700         samsung_clk_register_div(ctx, apollo_div_clks,
3701                                  ARRAY_SIZE(apollo_div_clks));
3702         samsung_clk_register_gate(ctx, apollo_gate_clks,
3703                                   ARRAY_SIZE(apollo_gate_clks));
3704
3705         exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
3706                 mout_apollo_p[0], mout_apollo_p[1], 0x200,
3707                 exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
3708                 CLK_CPU_HAS_E5433_REGS_LAYOUT);
3709
3710         samsung_clk_sleep_init(reg_base, apollo_clk_regs,
3711                                ARRAY_SIZE(apollo_clk_regs));
3712
3713         samsung_clk_of_add_provider(np, ctx);
3714 }
3715 CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3716                 exynos5433_cmu_apollo_init);
3717
3718 /*
3719  * Register offset definitions for CMU_ATLAS
3720  */
3721 #define ATLAS_PLL_LOCK                          0x0000
3722 #define ATLAS_PLL_CON0                          0x0100
3723 #define ATLAS_PLL_CON1                          0x0104
3724 #define ATLAS_PLL_FREQ_DET                      0x010c
3725 #define MUX_SEL_ATLAS0                          0x0200
3726 #define MUX_SEL_ATLAS1                          0x0204
3727 #define MUX_SEL_ATLAS2                          0x0208
3728 #define MUX_ENABLE_ATLAS0                       0x0300
3729 #define MUX_ENABLE_ATLAS1                       0x0304
3730 #define MUX_ENABLE_ATLAS2                       0x0308
3731 #define MUX_STAT_ATLAS0                         0x0400
3732 #define MUX_STAT_ATLAS1                         0x0404
3733 #define MUX_STAT_ATLAS2                         0x0408
3734 #define DIV_ATLAS0                              0x0600
3735 #define DIV_ATLAS1                              0x0604
3736 #define DIV_ATLAS_PLL_FREQ_DET                  0x0608
3737 #define DIV_STAT_ATLAS0                         0x0700
3738 #define DIV_STAT_ATLAS1                         0x0704
3739 #define DIV_STAT_ATLAS_PLL_FREQ_DET             0x0708
3740 #define ENABLE_ACLK_ATLAS                       0x0800
3741 #define ENABLE_PCLK_ATLAS                       0x0900
3742 #define ENABLE_SCLK_ATLAS                       0x0a00
3743 #define ENABLE_IP_ATLAS0                        0x0b00
3744 #define ENABLE_IP_ATLAS1                        0x0b04
3745 #define CLKOUT_CMU_ATLAS                        0x0c00
3746 #define CLKOUT_CMU_ATLAS_DIV_STAT               0x0c04
3747 #define ARMCLK_STOPCTRL                         0x1000
3748 #define ATLAS_PWR_CTRL                          0x1020
3749 #define ATLAS_PWR_CTRL2                         0x1024
3750 #define ATLAS_INTR_SPREAD_ENABLE                0x1080
3751 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI        0x1084
3752 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION     0x1088
3753
3754 static const unsigned long atlas_clk_regs[] __initconst = {
3755         ATLAS_PLL_LOCK,
3756         ATLAS_PLL_CON0,
3757         ATLAS_PLL_CON1,
3758         ATLAS_PLL_FREQ_DET,
3759         MUX_SEL_ATLAS0,
3760         MUX_SEL_ATLAS1,
3761         MUX_SEL_ATLAS2,
3762         MUX_ENABLE_ATLAS0,
3763         MUX_ENABLE_ATLAS1,
3764         MUX_ENABLE_ATLAS2,
3765         DIV_ATLAS0,
3766         DIV_ATLAS1,
3767         DIV_ATLAS_PLL_FREQ_DET,
3768         ENABLE_ACLK_ATLAS,
3769         ENABLE_PCLK_ATLAS,
3770         ENABLE_SCLK_ATLAS,
3771         ENABLE_IP_ATLAS0,
3772         ENABLE_IP_ATLAS1,
3773         CLKOUT_CMU_ATLAS,
3774         CLKOUT_CMU_ATLAS_DIV_STAT,
3775         ARMCLK_STOPCTRL,
3776         ATLAS_PWR_CTRL,
3777         ATLAS_PWR_CTRL2,
3778         ATLAS_INTR_SPREAD_ENABLE,
3779         ATLAS_INTR_SPREAD_USE_STANDBYWFI,
3780         ATLAS_INTR_SPREAD_BLOCKING_DURATION,
3781 };
3782
3783 /* list of all parent clock list */
3784 PNAME(mout_atlas_pll_p)                 = { "oscclk", "fout_atlas_pll", };
3785 PNAME(mout_bus_pll_atlas_user_p)        = { "oscclk", "sclk_bus_pll_atlas", };
3786 PNAME(mout_atlas_p)                     = { "mout_atlas_pll",
3787                                             "mout_bus_pll_atlas_user", };
3788
3789 static const struct samsung_pll_clock atlas_pll_clks[] __initconst = {
3790         PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3791                 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5433_pll_rates),
3792 };
3793
3794 static const struct samsung_mux_clock atlas_mux_clks[] __initconst = {
3795         /* MUX_SEL_ATLAS0 */
3796         MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3797                         MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT |
3798                         CLK_RECALC_NEW_RATES, 0),
3799
3800         /* MUX_SEL_ATLAS1 */
3801         MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
3802                         mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3803
3804         /* MUX_SEL_ATLAS2 */
3805         MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
3806                         0, 1, CLK_SET_RATE_PARENT, 0),
3807 };
3808
3809 static const struct samsung_div_clock atlas_div_clks[] __initconst = {
3810         /* DIV_ATLAS0 */
3811         DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3812                         DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
3813                         CLK_DIVIDER_READ_ONLY),
3814         DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
3815                         DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
3816                         CLK_DIVIDER_READ_ONLY),
3817         DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
3818                         DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
3819                         CLK_DIVIDER_READ_ONLY),
3820         DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
3821                         DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
3822                         CLK_DIVIDER_READ_ONLY),
3823         DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
3824                         DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
3825                         CLK_DIVIDER_READ_ONLY),
3826         DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
3827                         DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0),
3828         DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
3829                         DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0),
3830
3831         /* DIV_ATLAS1 */
3832         DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
3833                         DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
3834                         CLK_DIVIDER_READ_ONLY),
3835         DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
3836                         DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3837                         CLK_DIVIDER_READ_ONLY),
3838 };
3839
3840 static const struct samsung_gate_clock atlas_gate_clks[] __initconst = {
3841         /* ENABLE_ACLK_ATLAS */
3842         GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3843                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3844                         9, CLK_IGNORE_UNUSED, 0),
3845         GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
3846                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3847                         8, CLK_IGNORE_UNUSED, 0),
3848         GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
3849                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3850                         7, CLK_IGNORE_UNUSED, 0),
3851         GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
3852                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3853                         6, CLK_IGNORE_UNUSED, 0),
3854         GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
3855                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3856                         5, CLK_IGNORE_UNUSED, 0),
3857         GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
3858                         "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3859                         4, CLK_IGNORE_UNUSED, 0),
3860         GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
3861                         "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
3862                         3, CLK_IGNORE_UNUSED, 0),
3863         GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
3864                         "div_aclk_atlas", ENABLE_ACLK_ATLAS,
3865                         2, CLK_IGNORE_UNUSED, 0),
3866         GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
3867                         ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3868         GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
3869                         ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3870
3871         /* ENABLE_PCLK_ATLAS */
3872         GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
3873                         "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3874                         5, CLK_IGNORE_UNUSED, 0),
3875         GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
3876                         "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3877                         4, CLK_IGNORE_UNUSED, 0),
3878         GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
3879                         "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3880                         3, CLK_IGNORE_UNUSED, 0),
3881         GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
3882                         ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3883         GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
3884                         ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3885         GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
3886                         ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3887
3888         /* ENABLE_SCLK_ATLAS */
3889         GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
3890                         ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3891         GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
3892                         ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3893         GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
3894                         ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3895         GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
3896                         ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3897         GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
3898                         ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3899         GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
3900                         ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3901         GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
3902                         ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3903         GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3904                         ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3905 };
3906
3907 #define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3908                 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3909                  ((pclk) << 12) | ((aclk) << 8))
3910
3911 #define E5433_ATLAS_DIV1(hpm, copy) \
3912                 (((hpm) << 4) | ((copy) << 0))
3913
3914 static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = {
3915         { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3916         { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3917         { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3918         { 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3919         { 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3920         { 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3921         { 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3922         { 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3923         { 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3924         { 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3925         {  900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3926         {  800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3927         {  700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3928         {  600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3929         {  500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3930         {  0 },
3931 };
3932
3933 static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3934 {
3935         void __iomem *reg_base;
3936         struct samsung_clk_provider *ctx;
3937
3938         reg_base = of_iomap(np, 0);
3939         if (!reg_base) {
3940                 panic("%s: failed to map registers\n", __func__);
3941                 return;
3942         }
3943
3944         ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK);
3945         if (!ctx) {
3946                 panic("%s: unable to allocate ctx\n", __func__);
3947                 return;
3948         }
3949
3950         samsung_clk_register_pll(ctx, atlas_pll_clks,
3951                                  ARRAY_SIZE(atlas_pll_clks), reg_base);
3952         samsung_clk_register_mux(ctx, atlas_mux_clks,
3953                                  ARRAY_SIZE(atlas_mux_clks));
3954         samsung_clk_register_div(ctx, atlas_div_clks,
3955                                  ARRAY_SIZE(atlas_div_clks));
3956         samsung_clk_register_gate(ctx, atlas_gate_clks,
3957                                   ARRAY_SIZE(atlas_gate_clks));
3958
3959         exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
3960                 mout_atlas_p[0], mout_atlas_p[1], 0x200,
3961                 exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
3962                 CLK_CPU_HAS_E5433_REGS_LAYOUT);
3963
3964         samsung_clk_sleep_init(reg_base, atlas_clk_regs,
3965                                ARRAY_SIZE(atlas_clk_regs));
3966
3967         samsung_clk_of_add_provider(np, ctx);
3968 }
3969 CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3970                 exynos5433_cmu_atlas_init);
3971
3972 /*
3973  * Register offset definitions for CMU_MSCL
3974  */
3975 #define MUX_SEL_MSCL0                                   0x0200
3976 #define MUX_SEL_MSCL1                                   0x0204
3977 #define MUX_ENABLE_MSCL0                                0x0300
3978 #define MUX_ENABLE_MSCL1                                0x0304
3979 #define MUX_STAT_MSCL0                                  0x0400
3980 #define MUX_STAT_MSCL1                                  0x0404
3981 #define DIV_MSCL                                        0x0600
3982 #define DIV_STAT_MSCL                                   0x0700
3983 #define ENABLE_ACLK_MSCL                                0x0800
3984 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0         0x0804
3985 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1         0x0808
3986 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG               0x080c
3987 #define ENABLE_PCLK_MSCL                                0x0900
3988 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0         0x0904
3989 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1         0x0908
3990 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG               0x090c
3991 #define ENABLE_SCLK_MSCL                                0x0a00
3992 #define ENABLE_IP_MSCL0                                 0x0b00
3993 #define ENABLE_IP_MSCL1                                 0x0b04
3994 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0           0x0b08
3995 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1           0x0b0c
3996 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG                 0x0b10
3997
3998 static const unsigned long mscl_clk_regs[] __initconst = {
3999         MUX_SEL_MSCL0,
4000         MUX_SEL_MSCL1,
4001         MUX_ENABLE_MSCL0,
4002         MUX_ENABLE_MSCL1,
4003         DIV_MSCL,
4004         ENABLE_ACLK_MSCL,
4005         ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
4006         ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
4007         ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
4008         ENABLE_PCLK_MSCL,
4009         ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
4010         ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
4011         ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
4012         ENABLE_SCLK_MSCL,
4013         ENABLE_IP_MSCL0,
4014         ENABLE_IP_MSCL1,
4015         ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
4016         ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
4017         ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
4018 };
4019
4020 static const struct samsung_clk_reg_dump mscl_suspend_regs[] = {
4021         { MUX_SEL_MSCL0, 0 },
4022         { MUX_SEL_MSCL1, 0 },
4023 };
4024
4025 /* list of all parent clock list */
4026 PNAME(mout_sclk_jpeg_user_p)            = { "oscclk", "sclk_jpeg_mscl", };
4027 PNAME(mout_aclk_mscl_400_user_p)        = { "oscclk", "aclk_mscl_400", };
4028 PNAME(mout_sclk_jpeg_p)                 = { "mout_sclk_jpeg_user",
4029                                         "mout_aclk_mscl_400_user", };
4030
4031 static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
4032         /* MUX_SEL_MSCL0 */
4033         MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
4034                         mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
4035         MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
4036                         mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
4037
4038         /* MUX_SEL_MSCL1 */
4039         MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
4040                         MUX_SEL_MSCL1, 0, 1),
4041 };
4042
4043 static const struct samsung_div_clock mscl_div_clks[] __initconst = {
4044         /* DIV_MSCL */
4045         DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
4046                         DIV_MSCL, 0, 3),
4047 };
4048
4049 static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
4050         /* ENABLE_ACLK_MSCL */
4051         GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
4052                         ENABLE_ACLK_MSCL, 9, 0, 0),
4053         GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
4054                         "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
4055         GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
4056                         "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
4057         GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
4058                         ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
4059         GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
4060                         ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
4061         GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
4062                         ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4063         GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
4064                         ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4065         GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
4066                         ENABLE_ACLK_MSCL, 2, 0, 0),
4067         GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
4068                         ENABLE_ACLK_MSCL, 1, 0, 0),
4069         GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
4070                         ENABLE_ACLK_MSCL, 0, 0, 0),
4071
4072         /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4073         GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
4074                         "mout_aclk_mscl_400_user",
4075                         ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
4076                         0, CLK_IGNORE_UNUSED, 0),
4077
4078         /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4079         GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
4080                         "mout_aclk_mscl_400_user",
4081                         ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
4082                         0, CLK_IGNORE_UNUSED, 0),
4083
4084         /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
4085         GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
4086                         ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
4087                         0, CLK_IGNORE_UNUSED, 0),
4088
4089         /* ENABLE_PCLK_MSCL */
4090         GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
4091                         ENABLE_PCLK_MSCL, 7, 0, 0),
4092         GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
4093                         ENABLE_PCLK_MSCL, 6, 0, 0),
4094         GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
4095                         ENABLE_PCLK_MSCL, 5, 0, 0),
4096         GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
4097                         ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4098         GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
4099                         ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4100         GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
4101                         ENABLE_PCLK_MSCL, 2, 0, 0),
4102         GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
4103                         ENABLE_PCLK_MSCL, 1, 0, 0),
4104         GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
4105                         ENABLE_PCLK_MSCL, 0, 0, 0),
4106
4107         /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4108         GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
4109                         ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
4110                         0, CLK_IGNORE_UNUSED, 0),
4111
4112         /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4113         GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
4114                         ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
4115                         0, CLK_IGNORE_UNUSED, 0),
4116
4117         /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
4118         GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
4119                         ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
4120                         0, CLK_IGNORE_UNUSED, 0),
4121
4122         /* ENABLE_SCLK_MSCL */
4123         GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
4124                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
4125 };
4126
4127 static const struct samsung_cmu_info mscl_cmu_info __initconst = {
4128         .mux_clks               = mscl_mux_clks,
4129         .nr_mux_clks            = ARRAY_SIZE(mscl_mux_clks),
4130         .div_clks               = mscl_div_clks,
4131         .nr_div_clks            = ARRAY_SIZE(mscl_div_clks),
4132         .gate_clks              = mscl_gate_clks,
4133         .nr_gate_clks           = ARRAY_SIZE(mscl_gate_clks),
4134         .nr_clk_ids             = MSCL_NR_CLK,
4135         .clk_regs               = mscl_clk_regs,
4136         .nr_clk_regs            = ARRAY_SIZE(mscl_clk_regs),
4137         .suspend_regs           = mscl_suspend_regs,
4138         .nr_suspend_regs        = ARRAY_SIZE(mscl_suspend_regs),
4139         .clk_name               = "aclk_mscl_400",
4140 };
4141
4142 /*
4143  * Register offset definitions for CMU_MFC
4144  */
4145 #define MUX_SEL_MFC                             0x0200
4146 #define MUX_ENABLE_MFC                          0x0300
4147 #define MUX_STAT_MFC                            0x0400
4148 #define DIV_MFC                                 0x0600
4149 #define DIV_STAT_MFC                            0x0700
4150 #define ENABLE_ACLK_MFC                         0x0800
4151 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC         0x0804
4152 #define ENABLE_PCLK_MFC                         0x0900
4153 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC         0x0904
4154 #define ENABLE_IP_MFC0                          0x0b00
4155 #define ENABLE_IP_MFC1                          0x0b04
4156 #define ENABLE_IP_MFC_SECURE_SMMU_MFC           0x0b08
4157
4158 static const unsigned long mfc_clk_regs[] __initconst = {
4159         MUX_SEL_MFC,
4160         MUX_ENABLE_MFC,
4161         DIV_MFC,
4162         ENABLE_ACLK_MFC,
4163         ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4164         ENABLE_PCLK_MFC,
4165         ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4166         ENABLE_IP_MFC0,
4167         ENABLE_IP_MFC1,
4168         ENABLE_IP_MFC_SECURE_SMMU_MFC,
4169 };
4170
4171 static const struct samsung_clk_reg_dump mfc_suspend_regs[] = {
4172         { MUX_SEL_MFC, 0 },
4173 };
4174
4175 PNAME(mout_aclk_mfc_400_user_p)         = { "oscclk", "aclk_mfc_400", };
4176
4177 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
4178         /* MUX_SEL_MFC */
4179         MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4180                         mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4181 };
4182
4183 static const struct samsung_div_clock mfc_div_clks[] __initconst = {
4184         /* DIV_MFC */
4185         DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4186                         DIV_MFC, 0, 2),
4187 };
4188
4189 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
4190         /* ENABLE_ACLK_MFC */
4191         GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4192                         ENABLE_ACLK_MFC, 6, 0, 0),
4193         GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
4194                         ENABLE_ACLK_MFC, 5, 0, 0),
4195         GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
4196                         ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4197         GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
4198                         ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4199         GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
4200                         ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4201         GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
4202                         ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4203         GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
4204                         ENABLE_ACLK_MFC, 0, 0, 0),
4205
4206         /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
4207         GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
4208                         ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4209                         1, CLK_IGNORE_UNUSED, 0),
4210         GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
4211                         ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4212                         0, CLK_IGNORE_UNUSED, 0),
4213
4214         /* ENABLE_PCLK_MFC */
4215         GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
4216                         ENABLE_PCLK_MFC, 4, 0, 0),
4217         GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
4218                         ENABLE_PCLK_MFC, 3, 0, 0),
4219         GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
4220                         ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4221         GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
4222                         ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4223         GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
4224                         ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4225
4226         /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
4227         GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
4228                         ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4229                         1, CLK_IGNORE_UNUSED, 0),
4230         GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
4231                         ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4232                         0, CLK_IGNORE_UNUSED, 0),
4233 };
4234
4235 static const struct samsung_cmu_info mfc_cmu_info __initconst = {
4236         .mux_clks               = mfc_mux_clks,
4237         .nr_mux_clks            = ARRAY_SIZE(mfc_mux_clks),
4238         .div_clks               = mfc_div_clks,
4239         .nr_div_clks            = ARRAY_SIZE(mfc_div_clks),
4240         .gate_clks              = mfc_gate_clks,
4241         .nr_gate_clks           = ARRAY_SIZE(mfc_gate_clks),
4242         .nr_clk_ids             = MFC_NR_CLK,
4243         .clk_regs               = mfc_clk_regs,
4244         .nr_clk_regs            = ARRAY_SIZE(mfc_clk_regs),
4245         .suspend_regs           = mfc_suspend_regs,
4246         .nr_suspend_regs        = ARRAY_SIZE(mfc_suspend_regs),
4247         .clk_name               = "aclk_mfc_400",
4248 };
4249
4250 /*
4251  * Register offset definitions for CMU_HEVC
4252  */
4253 #define MUX_SEL_HEVC                            0x0200
4254 #define MUX_ENABLE_HEVC                         0x0300
4255 #define MUX_STAT_HEVC                           0x0400
4256 #define DIV_HEVC                                0x0600
4257 #define DIV_STAT_HEVC                           0x0700
4258 #define ENABLE_ACLK_HEVC                        0x0800
4259 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC       0x0804
4260 #define ENABLE_PCLK_HEVC                        0x0900
4261 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC       0x0904
4262 #define ENABLE_IP_HEVC0                         0x0b00
4263 #define ENABLE_IP_HEVC1                         0x0b04
4264 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC         0x0b08
4265
4266 static const unsigned long hevc_clk_regs[] __initconst = {
4267         MUX_SEL_HEVC,
4268         MUX_ENABLE_HEVC,
4269         DIV_HEVC,
4270         ENABLE_ACLK_HEVC,
4271         ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4272         ENABLE_PCLK_HEVC,
4273         ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4274         ENABLE_IP_HEVC0,
4275         ENABLE_IP_HEVC1,
4276         ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
4277 };
4278
4279 static const struct samsung_clk_reg_dump hevc_suspend_regs[] = {
4280         { MUX_SEL_HEVC, 0 },
4281 };
4282
4283 PNAME(mout_aclk_hevc_400_user_p)        = { "oscclk", "aclk_hevc_400", };
4284
4285 static const struct samsung_mux_clock hevc_mux_clks[] __initconst = {
4286         /* MUX_SEL_HEVC */
4287         MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
4288                         mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4289 };
4290
4291 static const struct samsung_div_clock hevc_div_clks[] __initconst = {
4292         /* DIV_HEVC */
4293         DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4294                         DIV_HEVC, 0, 2),
4295 };
4296
4297 static const struct samsung_gate_clock hevc_gate_clks[] __initconst = {
4298         /* ENABLE_ACLK_HEVC */
4299         GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4300                         ENABLE_ACLK_HEVC, 6, 0, 0),
4301         GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
4302                         ENABLE_ACLK_HEVC, 5, 0, 0),
4303         GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
4304                         ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4305         GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
4306                         ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4307         GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
4308                         ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4309         GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
4310                         ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4311         GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
4312                         ENABLE_ACLK_HEVC, 0, 0, 0),
4313
4314         /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
4315         GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
4316                         "mout_aclk_hevc_400_user",
4317                         ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4318                         1, CLK_IGNORE_UNUSED, 0),
4319         GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
4320                         "mout_aclk_hevc_400_user",
4321                         ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4322                         0, CLK_IGNORE_UNUSED, 0),
4323
4324         /* ENABLE_PCLK_HEVC */
4325         GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
4326                         ENABLE_PCLK_HEVC, 4, 0, 0),
4327         GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
4328                         ENABLE_PCLK_HEVC, 3, 0, 0),
4329         GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
4330                         ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4331         GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
4332                         ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4333         GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
4334                         ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4335
4336         /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
4337         GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
4338                         ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4339                         1, CLK_IGNORE_UNUSED, 0),
4340         GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
4341                         ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4342                         0, CLK_IGNORE_UNUSED, 0),
4343 };
4344
4345 static const struct samsung_cmu_info hevc_cmu_info __initconst = {
4346         .mux_clks               = hevc_mux_clks,
4347         .nr_mux_clks            = ARRAY_SIZE(hevc_mux_clks),
4348         .div_clks               = hevc_div_clks,
4349         .nr_div_clks            = ARRAY_SIZE(hevc_div_clks),
4350         .gate_clks              = hevc_gate_clks,
4351         .nr_gate_clks           = ARRAY_SIZE(hevc_gate_clks),
4352         .nr_clk_ids             = HEVC_NR_CLK,
4353         .clk_regs               = hevc_clk_regs,
4354         .nr_clk_regs            = ARRAY_SIZE(hevc_clk_regs),
4355         .suspend_regs           = hevc_suspend_regs,
4356         .nr_suspend_regs        = ARRAY_SIZE(hevc_suspend_regs),
4357         .clk_name               = "aclk_hevc_400",
4358 };
4359
4360 /*
4361  * Register offset definitions for CMU_ISP
4362  */
4363 #define MUX_SEL_ISP                     0x0200
4364 #define MUX_ENABLE_ISP                  0x0300
4365 #define MUX_STAT_ISP                    0x0400
4366 #define DIV_ISP                         0x0600
4367 #define DIV_STAT_ISP                    0x0700
4368 #define ENABLE_ACLK_ISP0                0x0800
4369 #define ENABLE_ACLK_ISP1                0x0804
4370 #define ENABLE_ACLK_ISP2                0x0808
4371 #define ENABLE_PCLK_ISP                 0x0900
4372 #define ENABLE_SCLK_ISP                 0x0a00
4373 #define ENABLE_IP_ISP0                  0x0b00
4374 #define ENABLE_IP_ISP1                  0x0b04
4375 #define ENABLE_IP_ISP2                  0x0b08
4376 #define ENABLE_IP_ISP3                  0x0b0c
4377
4378 static const unsigned long isp_clk_regs[] __initconst = {
4379         MUX_SEL_ISP,
4380         MUX_ENABLE_ISP,
4381         DIV_ISP,
4382         ENABLE_ACLK_ISP0,
4383         ENABLE_ACLK_ISP1,
4384         ENABLE_ACLK_ISP2,
4385         ENABLE_PCLK_ISP,
4386         ENABLE_SCLK_ISP,
4387         ENABLE_IP_ISP0,
4388         ENABLE_IP_ISP1,
4389         ENABLE_IP_ISP2,
4390         ENABLE_IP_ISP3,
4391 };
4392
4393 static const struct samsung_clk_reg_dump isp_suspend_regs[] = {
4394         { MUX_SEL_ISP, 0 },
4395 };
4396
4397 PNAME(mout_aclk_isp_dis_400_user_p)     = { "oscclk", "aclk_isp_dis_400", };
4398 PNAME(mout_aclk_isp_400_user_p)         = { "oscclk", "aclk_isp_400", };
4399
4400 static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
4401         /* MUX_SEL_ISP */
4402         MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
4403                         mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
4404         MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
4405                         mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4406 };
4407
4408 static const struct samsung_div_clock isp_div_clks[] __initconst = {
4409         /* DIV_ISP */
4410         DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
4411                         "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
4412         DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
4413                         DIV_ISP, 8, 3),
4414         DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
4415                         "mout_aclk_isp_400_user", DIV_ISP, 4, 3),
4416         DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
4417                         "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4418 };
4419
4420 static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
4421         /* ENABLE_ACLK_ISP0 */
4422         GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
4423                         ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
4424         GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
4425                         ENABLE_ACLK_ISP0, 5, 0, 0),
4426         GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
4427                         ENABLE_ACLK_ISP0, 4, 0, 0),
4428         GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
4429                         ENABLE_ACLK_ISP0, 3, 0, 0),
4430         GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
4431                         ENABLE_ACLK_ISP0, 2, 0, 0),
4432         GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
4433                         ENABLE_ACLK_ISP0, 1, 0, 0),
4434         GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
4435                         ENABLE_ACLK_ISP0, 0, 0, 0),
4436
4437         /* ENABLE_ACLK_ISP1 */
4438         GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
4439                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4440                         17, CLK_IGNORE_UNUSED, 0),
4441         GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
4442                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4443                         16, CLK_IGNORE_UNUSED, 0),
4444         GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
4445                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4446                         15, CLK_IGNORE_UNUSED, 0),
4447         GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
4448                         "div_pclk_isp", ENABLE_ACLK_ISP1,
4449                         14, CLK_IGNORE_UNUSED, 0),
4450         GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
4451                         "div_pclk_isp", ENABLE_ACLK_ISP1,
4452                         13, CLK_IGNORE_UNUSED, 0),
4453         GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
4454                         "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4455                         12, CLK_IGNORE_UNUSED, 0),
4456         GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
4457                         "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4458                         11, CLK_IGNORE_UNUSED, 0),
4459         GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
4460                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4461                         10, CLK_IGNORE_UNUSED, 0),
4462         GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
4463                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4464                         9, CLK_IGNORE_UNUSED, 0),
4465         GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
4466                         "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4467                         8, CLK_IGNORE_UNUSED, 0),
4468         GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
4469                         "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4470                         7, CLK_IGNORE_UNUSED, 0),
4471         GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
4472                         ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
4473         GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
4474                         ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
4475         GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
4476                         "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4477                         4, CLK_IGNORE_UNUSED, 0),
4478         GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
4479                         "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4480                         3, CLK_IGNORE_UNUSED, 0),
4481         GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
4482                         ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
4483         GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
4484                         ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4485         GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
4486                         ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4487
4488         /* ENABLE_ACLK_ISP2 */
4489         GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
4490                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4491                         13, CLK_IGNORE_UNUSED, 0),
4492         GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
4493                         ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
4494         GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
4495                         ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
4496         GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
4497                         ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
4498         GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
4499                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4500                         9, CLK_IGNORE_UNUSED, 0),
4501         GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
4502                         ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
4503         GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
4504                         ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
4505         GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
4506                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4507                         6, CLK_IGNORE_UNUSED, 0),
4508         GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
4509                         ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4510         GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
4511                         ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4512         GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
4513                         ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4514         GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
4515                         "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4516                         2, CLK_IGNORE_UNUSED, 0),
4517         GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
4518                         ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4519         GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
4520                         ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4521
4522         /* ENABLE_PCLK_ISP */
4523         GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
4524                         ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
4525         GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
4526                         ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
4527         GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
4528                         ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
4529         GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
4530                         ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
4531         GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
4532                         ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
4533         GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
4534                         ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
4535         GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
4536                         ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
4537         GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
4538                         ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
4539         GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
4540                         ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
4541         GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
4542                         ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
4543         GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
4544                         ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
4545         GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
4546                         ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
4547         GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
4548                         ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
4549         GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
4550                         ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
4551         GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
4552                         ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
4553         GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
4554                         ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
4555         GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
4556                         ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
4557         GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
4558                         ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
4559         GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
4560                         "div_aclk_isp_c_200", ENABLE_PCLK_ISP,
4561                         7, CLK_IGNORE_UNUSED, 0),
4562         GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
4563                         ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
4564         GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
4565                         ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
4566         GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
4567                         ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
4568         GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
4569                         ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
4570         GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
4571                         ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
4572         GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
4573                         ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
4574         GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
4575                         ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
4576
4577         /* ENABLE_SCLK_ISP */
4578         GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
4579                         "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4580                         5, CLK_IGNORE_UNUSED, 0),
4581         GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
4582                         "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4583                         4, CLK_IGNORE_UNUSED, 0),
4584         GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
4585                         "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4586                         3, CLK_IGNORE_UNUSED, 0),
4587         GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
4588                         "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4589                         2, CLK_IGNORE_UNUSED, 0),
4590         GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
4591                         "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4592                         1, CLK_IGNORE_UNUSED, 0),
4593         GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
4594                         "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4595                         0, CLK_IGNORE_UNUSED, 0),
4596 };
4597
4598 static const struct samsung_cmu_info isp_cmu_info __initconst = {
4599         .mux_clks               = isp_mux_clks,
4600         .nr_mux_clks            = ARRAY_SIZE(isp_mux_clks),
4601         .div_clks               = isp_div_clks,
4602         .nr_div_clks            = ARRAY_SIZE(isp_div_clks),
4603         .gate_clks              = isp_gate_clks,
4604         .nr_gate_clks           = ARRAY_SIZE(isp_gate_clks),
4605         .nr_clk_ids             = ISP_NR_CLK,
4606         .clk_regs               = isp_clk_regs,
4607         .nr_clk_regs            = ARRAY_SIZE(isp_clk_regs),
4608         .suspend_regs           = isp_suspend_regs,
4609         .nr_suspend_regs        = ARRAY_SIZE(isp_suspend_regs),
4610         .clk_name               = "aclk_isp_400",
4611 };
4612
4613 /*
4614  * Register offset definitions for CMU_CAM0
4615  */
4616 #define MUX_SEL_CAM00                   0x0200
4617 #define MUX_SEL_CAM01                   0x0204
4618 #define MUX_SEL_CAM02                   0x0208
4619 #define MUX_SEL_CAM03                   0x020c
4620 #define MUX_SEL_CAM04                   0x0210
4621 #define MUX_ENABLE_CAM00                0x0300
4622 #define MUX_ENABLE_CAM01                0x0304
4623 #define MUX_ENABLE_CAM02                0x0308
4624 #define MUX_ENABLE_CAM03                0x030c
4625 #define MUX_ENABLE_CAM04                0x0310
4626 #define MUX_STAT_CAM00                  0x0400
4627 #define MUX_STAT_CAM01                  0x0404
4628 #define MUX_STAT_CAM02                  0x0408
4629 #define MUX_STAT_CAM03                  0x040c
4630 #define MUX_STAT_CAM04                  0x0410
4631 #define MUX_IGNORE_CAM01                0x0504
4632 #define DIV_CAM00                       0x0600
4633 #define DIV_CAM01                       0x0604
4634 #define DIV_CAM02                       0x0608
4635 #define DIV_CAM03                       0x060c
4636 #define DIV_STAT_CAM00                  0x0700
4637 #define DIV_STAT_CAM01                  0x0704
4638 #define DIV_STAT_CAM02                  0x0708
4639 #define DIV_STAT_CAM03                  0x070c
4640 #define ENABLE_ACLK_CAM00               0X0800
4641 #define ENABLE_ACLK_CAM01               0X0804
4642 #define ENABLE_ACLK_CAM02               0X0808
4643 #define ENABLE_PCLK_CAM0                0X0900
4644 #define ENABLE_SCLK_CAM0                0X0a00
4645 #define ENABLE_IP_CAM00                 0X0b00
4646 #define ENABLE_IP_CAM01                 0X0b04
4647 #define ENABLE_IP_CAM02                 0X0b08
4648 #define ENABLE_IP_CAM03                 0X0b0C
4649
4650 static const unsigned long cam0_clk_regs[] __initconst = {
4651         MUX_SEL_CAM00,
4652         MUX_SEL_CAM01,
4653         MUX_SEL_CAM02,
4654         MUX_SEL_CAM03,
4655         MUX_SEL_CAM04,
4656         MUX_ENABLE_CAM00,
4657         MUX_ENABLE_CAM01,
4658         MUX_ENABLE_CAM02,
4659         MUX_ENABLE_CAM03,
4660         MUX_ENABLE_CAM04,
4661         MUX_IGNORE_CAM01,
4662         DIV_CAM00,
4663         DIV_CAM01,
4664         DIV_CAM02,
4665         DIV_CAM03,
4666         ENABLE_ACLK_CAM00,
4667         ENABLE_ACLK_CAM01,
4668         ENABLE_ACLK_CAM02,
4669         ENABLE_PCLK_CAM0,
4670         ENABLE_SCLK_CAM0,
4671         ENABLE_IP_CAM00,
4672         ENABLE_IP_CAM01,
4673         ENABLE_IP_CAM02,
4674         ENABLE_IP_CAM03,
4675 };
4676
4677 static const struct samsung_clk_reg_dump cam0_suspend_regs[] = {
4678         { MUX_SEL_CAM00, 0 },
4679         { MUX_SEL_CAM01, 0 },
4680         { MUX_SEL_CAM02, 0 },
4681         { MUX_SEL_CAM03, 0 },
4682         { MUX_SEL_CAM04, 0 },
4683 };
4684
4685 PNAME(mout_aclk_cam0_333_user_p)        = { "oscclk", "aclk_cam0_333", };
4686 PNAME(mout_aclk_cam0_400_user_p)        = { "oscclk", "aclk_cam0_400", };
4687 PNAME(mout_aclk_cam0_552_user_p)        = { "oscclk", "aclk_cam0_552", };
4688
4689 PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk",
4690                                               "phyclk_rxbyteclkhs0_s4_phy", };
4691 PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk",
4692                                                "phyclk_rxbyteclkhs0_s2a_phy", };
4693
4694 PNAME(mout_aclk_lite_d_b_p)             = { "mout_aclk_lite_d_a",
4695                                             "mout_aclk_cam0_333_user", };
4696 PNAME(mout_aclk_lite_d_a_p)             = { "mout_aclk_cam0_552_user",
4697                                             "mout_aclk_cam0_400_user", };
4698 PNAME(mout_aclk_lite_b_b_p)             = { "mout_aclk_lite_b_a",
4699                                             "mout_aclk_cam0_333_user", };
4700 PNAME(mout_aclk_lite_b_a_p)             = { "mout_aclk_cam0_552_user",
4701                                             "mout_aclk_cam0_400_user", };
4702 PNAME(mout_aclk_lite_a_b_p)             = { "mout_aclk_lite_a_a",
4703                                             "mout_aclk_cam0_333_user", };
4704 PNAME(mout_aclk_lite_a_a_p)             = { "mout_aclk_cam0_552_user",
4705                                             "mout_aclk_cam0_400_user", };
4706 PNAME(mout_aclk_cam0_400_p)             = { "mout_aclk_cam0_400_user",
4707                                             "mout_aclk_cam0_333_user", };
4708
4709 PNAME(mout_aclk_csis1_b_p)              = { "mout_aclk_csis1_a",
4710                                             "mout_aclk_cam0_333_user" };
4711 PNAME(mout_aclk_csis1_a_p)              = { "mout_aclk_cam0_552_user",
4712                                             "mout_aclk_cam0_400_user", };
4713 PNAME(mout_aclk_csis0_b_p)              = { "mout_aclk_csis0_a",
4714                                             "mout_aclk_cam0_333_user", };
4715 PNAME(mout_aclk_csis0_a_p)              = { "mout_aclk_cam0_552_user",
4716                                             "mout_aclk-cam0_400_user", };
4717 PNAME(mout_aclk_3aa1_b_p)               = { "mout_aclk_3aa1_a",
4718                                             "mout_aclk_cam0_333_user", };
4719 PNAME(mout_aclk_3aa1_a_p)               = { "mout_aclk_cam0_552_user",
4720                                             "mout_aclk_cam0_400_user", };
4721 PNAME(mout_aclk_3aa0_b_p)               = { "mout_aclk_3aa0_a",
4722                                             "mout_aclk_cam0_333_user", };
4723 PNAME(mout_aclk_3aa0_a_p)               = { "mout_aclk_cam0_552_user",
4724                                             "mout_aclk_cam0_400_user", };
4725
4726 PNAME(mout_sclk_lite_freecnt_c_p)       = { "mout_sclk_lite_freecnt_b",
4727                                             "div_pclk_lite_d", };
4728 PNAME(mout_sclk_lite_freecnt_b_p)       = { "mout_sclk_lite_freecnt_a",
4729                                             "div_pclk_pixelasync_lite_c", };
4730 PNAME(mout_sclk_lite_freecnt_a_p)       = { "div_pclk_lite_a",
4731                                             "div_pclk_lite_b", };
4732 PNAME(mout_sclk_pixelasync_lite_c_b_p)  = { "mout_sclk_pixelasync_lite_c_a",
4733                                             "mout_aclk_cam0_333_user", };
4734 PNAME(mout_sclk_pixelasync_lite_c_a_p)  = { "mout_aclk_cam0_552_user",
4735                                             "mout_aclk_cam0_400_user", };
4736 PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = {
4737                                         "mout_sclk_pixelasync_lite_c_init_a",
4738                                         "mout_aclk_cam0_400_user", };
4739 PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
4740                                         "mout_aclk_cam0_552_user",
4741                                         "mout_aclk_cam0_400_user", };
4742
4743 static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = {
4744         FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
4745                         NULL, 0, 100000000),
4746         FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
4747                         NULL, 0, 100000000),
4748 };
4749
4750 static const struct samsung_mux_clock cam0_mux_clks[] __initconst = {
4751         /* MUX_SEL_CAM00 */
4752         MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
4753                         mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
4754         MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user",
4755                         mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1),
4756         MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user",
4757                         mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
4758
4759         /* MUX_SEL_CAM01 */
4760         MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
4761                         "mout_phyclk_rxbyteclkhs0_s4_user",
4762                         mout_phyclk_rxbyteclkhs0_s4_user_p,
4763                         MUX_SEL_CAM01, 4, 1),
4764         MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
4765                         "mout_phyclk_rxbyteclkhs0_s2a_user",
4766                         mout_phyclk_rxbyteclkhs0_s2a_user_p,
4767                         MUX_SEL_CAM01, 0, 1),
4768
4769         /* MUX_SEL_CAM02 */
4770         MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p,
4771                         MUX_SEL_CAM02, 24, 1),
4772         MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p,
4773                         MUX_SEL_CAM02, 20, 1),
4774         MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p,
4775                         MUX_SEL_CAM02, 16, 1),
4776         MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p,
4777                         MUX_SEL_CAM02, 12, 1),
4778         MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p,
4779                         MUX_SEL_CAM02, 8, 1),
4780         MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p,
4781                         MUX_SEL_CAM02, 4, 1),
4782         MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p,
4783                         MUX_SEL_CAM02, 0, 1),
4784
4785         /* MUX_SEL_CAM03 */
4786         MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p,
4787                         MUX_SEL_CAM03, 28, 1),
4788         MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p,
4789                         MUX_SEL_CAM03, 24, 1),
4790         MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p,
4791                         MUX_SEL_CAM03, 20, 1),
4792         MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p,
4793                         MUX_SEL_CAM03, 16, 1),
4794         MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p,
4795                         MUX_SEL_CAM03, 12, 1),
4796         MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p,
4797                         MUX_SEL_CAM03, 8, 1),
4798         MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p,
4799                         MUX_SEL_CAM03, 4, 1),
4800         MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p,
4801                         MUX_SEL_CAM03, 0, 1),
4802
4803         /* MUX_SEL_CAM04 */
4804         MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
4805                         mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
4806         MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
4807                         mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1),
4808         MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
4809                         mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1),
4810         MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
4811                         mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1),
4812         MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
4813                         mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1),
4814         MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
4815                         "mout_sclk_pixelasync_lite_c_init_b",
4816                         mout_sclk_pixelasync_lite_c_init_b_p,
4817                         MUX_SEL_CAM04, 4, 1),
4818         MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
4819                         "mout_sclk_pixelasync_lite_c_init_a",
4820                         mout_sclk_pixelasync_lite_c_init_a_p,
4821                         MUX_SEL_CAM04, 0, 1),
4822 };
4823
4824 static const struct samsung_div_clock cam0_div_clks[] __initconst = {
4825         /* DIV_CAM00 */
4826         DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
4827                         DIV_CAM00, 8, 2),
4828         DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400",
4829                         DIV_CAM00, 4, 3),
4830         DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400",
4831                         "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
4832
4833         /* DIV_CAM01 */
4834         DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d",
4835                         DIV_CAM01, 20, 2),
4836         DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b",
4837                         DIV_CAM01, 16, 3),
4838         DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b",
4839                         DIV_CAM01, 12, 2),
4840         DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b",
4841                         DIV_CAM01, 8, 3),
4842         DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a",
4843                         DIV_CAM01, 4, 2),
4844         DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b",
4845                         DIV_CAM01, 0, 3),
4846
4847         /* DIV_CAM02 */
4848         DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b",
4849                         DIV_CAM02, 20, 3),
4850         DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b",
4851                         DIV_CAM02, 16, 3),
4852         DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1",
4853                         DIV_CAM02, 12, 2),
4854         DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b",
4855                         DIV_CAM02, 8, 3),
4856         DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0",
4857                         DIV_CAM02, 4, 2),
4858         DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b",
4859                         DIV_CAM02, 0, 3),
4860
4861         /* DIV_CAM03 */
4862         DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c",
4863                         "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3),
4864         DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c",
4865                         "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2),
4866         DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT,
4867                         "div_sclk_pixelasync_lite_c_init",
4868                         "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4869 };
4870
4871 static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {
4872         /* ENABLE_ACLK_CAM00 */
4873         GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
4874                         6, 0, 0),
4875         GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
4876                         5, 0, 0),
4877         GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
4878                         4, 0, 0),
4879         GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
4880                         3, 0, 0),
4881         GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
4882                         ENABLE_ACLK_CAM00, 2, 0, 0),
4883         GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
4884                         ENABLE_ACLK_CAM00, 1, 0, 0),
4885         GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
4886                         ENABLE_ACLK_CAM00, 0, 0, 0),
4887
4888         /* ENABLE_ACLK_CAM01 */
4889         GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
4890                         ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
4891         GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
4892                         ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
4893         GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
4894                         ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
4895         GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
4896                         ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
4897         GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
4898                         ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
4899         GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
4900                         ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
4901         GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
4902                         ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
4903         GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
4904                         ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
4905         GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d",
4906                         "div_pclk_lite_d", ENABLE_ACLK_CAM01,
4907                         23, CLK_IGNORE_UNUSED, 0),
4908         GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d",
4909                         "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4910                         22, CLK_IGNORE_UNUSED, 0),
4911         GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b",
4912                         "div_pclk_lite_b", ENABLE_ACLK_CAM01,
4913                         21, CLK_IGNORE_UNUSED, 0),
4914         GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b",
4915                         "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4916                         20, CLK_IGNORE_UNUSED, 0),
4917         GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a",
4918                         "div_pclk_lite_a", ENABLE_ACLK_CAM01,
4919                         19, CLK_IGNORE_UNUSED, 0),
4920         GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a",
4921                         "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4922                         18, CLK_IGNORE_UNUSED, 0),
4923         GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p",
4924                         "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4925                         17, CLK_IGNORE_UNUSED, 0),
4926         GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1",
4927                         "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4928                         16, CLK_IGNORE_UNUSED, 0),
4929         GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1",
4930                         "div_aclk_3aa1", ENABLE_ACLK_CAM01,
4931                         15, CLK_IGNORE_UNUSED, 0),
4932         GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0",
4933                         "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4934                         14, CLK_IGNORE_UNUSED, 0),
4935         GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0",
4936                         "div_aclk_3aa0", ENABLE_ACLK_CAM01,
4937                         13, CLK_IGNORE_UNUSED, 0),
4938         GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d",
4939                         "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4940                         12, CLK_IGNORE_UNUSED, 0),
4941         GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d",
4942                         "div_aclk_lite_d", ENABLE_ACLK_CAM01,
4943                         11, CLK_IGNORE_UNUSED, 0),
4944         GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b",
4945                         "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4946                         10, CLK_IGNORE_UNUSED, 0),
4947         GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b",
4948                         "div_aclk_lite_b", ENABLE_ACLK_CAM01,
4949                         9, CLK_IGNORE_UNUSED, 0),
4950         GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a",
4951                         "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4952                         8, CLK_IGNORE_UNUSED, 0),
4953         GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a",
4954                         "div_aclk_lite_a", ENABLE_ACLK_CAM01,
4955                         7, CLK_IGNORE_UNUSED, 0),
4956         GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp",
4957                         "div_pclk_cam0_50", ENABLE_ACLK_CAM01,
4958                         6, CLK_IGNORE_UNUSED, 0),
4959         GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
4960                         ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
4961         GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
4962                         ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
4963         GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200",
4964                         ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
4965         GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
4966                         ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
4967         GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200",
4968                         ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
4969         GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
4970                         ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
4971
4972         /* ENABLE_ACLK_CAM02 */
4973         GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
4974                         ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
4975         GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
4976                         ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
4977         GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
4978                         ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
4979         GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
4980                         ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
4981         GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
4982                         ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
4983         GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
4984                         ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
4985         GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
4986                         ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
4987         GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
4988                         ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
4989         GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
4990                         ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
4991         GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
4992                         ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
4993
4994         /* ENABLE_PCLK_CAM0 */
4995         GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200",
4996                         ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
4997         GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200",
4998                         ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
4999         GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200",
5000                         ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
5001         GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200",
5002                         ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
5003         GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200",
5004                         ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
5005         GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50",
5006                         ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
5007         GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50",
5008                         ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
5009         GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50",
5010                         ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
5011         GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50",
5012                         ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
5013         GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50",
5014                         ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
5015         GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
5016                         ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
5017         GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
5018                         ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
5019         GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
5020                         ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
5021         GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d",
5022                         "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
5023                         12, CLK_IGNORE_UNUSED, 0),
5024         GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b",
5025                         "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
5026                         11, CLK_IGNORE_UNUSED, 0),
5027         GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a",
5028                         "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
5029                         10, CLK_IGNORE_UNUSED, 0),
5030         GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50",
5031                         ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
5032         GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50",
5033                         ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
5034         GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local",
5035                         "div_aclk_cam0_200", ENABLE_PCLK_CAM0,
5036                         7, CLK_IGNORE_UNUSED, 0),
5037         GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200",
5038                         ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
5039         GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200",
5040                         ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
5041         GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1",
5042                         ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
5043         GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0",
5044                         ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
5045         GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d",
5046                         ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
5047         GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b",
5048                         ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
5049         GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a",
5050                         ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
5051
5052         /* ENABLE_SCLK_CAM0 */
5053         GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
5054                         "mout_phyclk_rxbyteclkhs0_s4_user",
5055                         ENABLE_SCLK_CAM0, 8, 0, 0),
5056         GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
5057                         "mout_phyclk_rxbyteclkhs0_s2a_user",
5058                         ENABLE_SCLK_CAM0, 7, 0, 0),
5059         GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
5060                         "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
5061         GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
5062                         "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
5063         GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
5064                         "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
5065         GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
5066                         "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
5067         GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
5068                         "div_sclk_pixelasync_lite_c",
5069                         ENABLE_SCLK_CAM0, 2, 0, 0),
5070         GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
5071                         "div_sclk_pixelasync_lite_c_init",
5072                         ENABLE_SCLK_CAM0, 1, 0, 0),
5073         GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
5074                         "div_sclk_pixelasync_lite_c",
5075                         ENABLE_SCLK_CAM0, 0, 0, 0),
5076 };
5077
5078 static const struct samsung_cmu_info cam0_cmu_info __initconst = {
5079         .mux_clks               = cam0_mux_clks,
5080         .nr_mux_clks            = ARRAY_SIZE(cam0_mux_clks),
5081         .div_clks               = cam0_div_clks,
5082         .nr_div_clks            = ARRAY_SIZE(cam0_div_clks),
5083         .gate_clks              = cam0_gate_clks,
5084         .nr_gate_clks           = ARRAY_SIZE(cam0_gate_clks),
5085         .fixed_clks             = cam0_fixed_clks,
5086         .nr_fixed_clks          = ARRAY_SIZE(cam0_fixed_clks),
5087         .nr_clk_ids             = CAM0_NR_CLK,
5088         .clk_regs               = cam0_clk_regs,
5089         .nr_clk_regs            = ARRAY_SIZE(cam0_clk_regs),
5090         .suspend_regs           = cam0_suspend_regs,
5091         .nr_suspend_regs        = ARRAY_SIZE(cam0_suspend_regs),
5092         .clk_name               = "aclk_cam0_400",
5093 };
5094
5095 /*
5096  * Register offset definitions for CMU_CAM1
5097  */
5098 #define MUX_SEL_CAM10                   0x0200
5099 #define MUX_SEL_CAM11                   0x0204
5100 #define MUX_SEL_CAM12                   0x0208
5101 #define MUX_ENABLE_CAM10                0x0300
5102 #define MUX_ENABLE_CAM11                0x0304
5103 #define MUX_ENABLE_CAM12                0x0308
5104 #define MUX_STAT_CAM10                  0x0400
5105 #define MUX_STAT_CAM11                  0x0404
5106 #define MUX_STAT_CAM12                  0x0408
5107 #define MUX_IGNORE_CAM11                0x0504
5108 #define DIV_CAM10                       0x0600
5109 #define DIV_CAM11                       0x0604
5110 #define DIV_STAT_CAM10                  0x0700
5111 #define DIV_STAT_CAM11                  0x0704
5112 #define ENABLE_ACLK_CAM10               0X0800
5113 #define ENABLE_ACLK_CAM11               0X0804
5114 #define ENABLE_ACLK_CAM12               0X0808
5115 #define ENABLE_PCLK_CAM1                0X0900
5116 #define ENABLE_SCLK_CAM1                0X0a00
5117 #define ENABLE_IP_CAM10                 0X0b00
5118 #define ENABLE_IP_CAM11                 0X0b04
5119 #define ENABLE_IP_CAM12                 0X0b08
5120
5121 static const unsigned long cam1_clk_regs[] __initconst = {
5122         MUX_SEL_CAM10,
5123         MUX_SEL_CAM11,
5124         MUX_SEL_CAM12,
5125         MUX_ENABLE_CAM10,
5126         MUX_ENABLE_CAM11,
5127         MUX_ENABLE_CAM12,
5128         MUX_IGNORE_CAM11,
5129         DIV_CAM10,
5130         DIV_CAM11,
5131         ENABLE_ACLK_CAM10,
5132         ENABLE_ACLK_CAM11,
5133         ENABLE_ACLK_CAM12,
5134         ENABLE_PCLK_CAM1,
5135         ENABLE_SCLK_CAM1,
5136         ENABLE_IP_CAM10,
5137         ENABLE_IP_CAM11,
5138         ENABLE_IP_CAM12,
5139 };
5140
5141 static const struct samsung_clk_reg_dump cam1_suspend_regs[] = {
5142         { MUX_SEL_CAM10, 0 },
5143         { MUX_SEL_CAM11, 0 },
5144         { MUX_SEL_CAM12, 0 },
5145 };
5146
5147 PNAME(mout_sclk_isp_uart_user_p)        = { "oscclk", "sclk_isp_uart_cam1", };
5148 PNAME(mout_sclk_isp_spi1_user_p)        = { "oscclk", "sclk_isp_spi1_cam1", };
5149 PNAME(mout_sclk_isp_spi0_user_p)        = { "oscclk", "sclk_isp_spi0_cam1", };
5150
5151 PNAME(mout_aclk_cam1_333_user_p)        = { "oscclk", "aclk_cam1_333", };
5152 PNAME(mout_aclk_cam1_400_user_p)        = { "oscclk", "aclk_cam1_400", };
5153 PNAME(mout_aclk_cam1_552_user_p)        = { "oscclk", "aclk_cam1_552", };
5154
5155 PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk",
5156                                                "phyclk_rxbyteclkhs0_s2b_phy", };
5157
5158 PNAME(mout_aclk_csis2_b_p)              = { "mout_aclk_csis2_a",
5159                                             "mout_aclk_cam1_333_user", };
5160 PNAME(mout_aclk_csis2_a_p)              = { "mout_aclk_cam1_552_user",
5161                                             "mout_aclk_cam1_400_user", };
5162
5163 PNAME(mout_aclk_fd_b_p)                 = { "mout_aclk_fd_a",
5164                                             "mout_aclk_cam1_333_user", };
5165 PNAME(mout_aclk_fd_a_p)                 = { "mout_aclk_cam1_552_user",
5166                                             "mout_aclk_cam1_400_user", };
5167
5168 PNAME(mout_aclk_lite_c_b_p)             = { "mout_aclk_lite_c_a",
5169                                             "mout_aclk_cam1_333_user", };
5170 PNAME(mout_aclk_lite_c_a_p)             = { "mout_aclk_cam1_552_user",
5171                                             "mout_aclk_cam1_400_user", };
5172
5173 static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = {
5174         FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
5175                         0, 100000000),
5176 };
5177
5178 static const struct samsung_mux_clock cam1_mux_clks[] __initconst = {
5179         /* MUX_SEL_CAM10 */
5180         MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
5181                         mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
5182         MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user",
5183                         mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1),
5184         MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user",
5185                         mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1),
5186         MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
5187                         mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
5188         MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
5189                         mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1),
5190         MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
5191                         mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1),
5192
5193         /* MUX_SEL_CAM11 */
5194         MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
5195                         "mout_phyclk_rxbyteclkhs0_s2b_user",
5196                         mout_phyclk_rxbyteclkhs0_s2b_user_p,
5197                         MUX_SEL_CAM11, 0, 1),
5198
5199         /* MUX_SEL_CAM12 */
5200         MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p,
5201                         MUX_SEL_CAM12, 20, 1),
5202         MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p,
5203                         MUX_SEL_CAM12, 16, 1),
5204         MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p,
5205                         MUX_SEL_CAM12, 12, 1),
5206         MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p,
5207                         MUX_SEL_CAM12, 8, 1),
5208         MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p,
5209                         MUX_SEL_CAM12, 4, 1),
5210         MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p,
5211                         MUX_SEL_CAM12, 0, 1),
5212 };
5213
5214 static const struct samsung_div_clock cam1_div_clks[] __initconst = {
5215         /* DIV_CAM10 */
5216         DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm",
5217                         "div_pclk_cam1_83", DIV_CAM10, 16, 2),
5218         DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83",
5219                         "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2),
5220         DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166",
5221                         "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2),
5222         DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1",
5223                         "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3),
5224         DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user",
5225                         DIV_CAM10, 0, 3),
5226
5227         /* DIV_CAM11 */
5228         DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b",
5229                         DIV_CAM11, 16, 3),
5230         DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2),
5231         DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3),
5232         DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c",
5233                         DIV_CAM11, 4, 2),
5234         DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b",
5235                         DIV_CAM11, 0, 3),
5236 };
5237
5238 static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {
5239         /* ENABLE_ACLK_CAM10 */
5240         GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
5241                         ENABLE_ACLK_CAM10, 4, 0, 0),
5242         GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
5243                         ENABLE_ACLK_CAM10, 3, 0, 0),
5244         GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
5245                         ENABLE_ACLK_CAM10, 1, 0, 0),
5246         GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
5247                         ENABLE_ACLK_CAM10, 0, 0, 0),
5248
5249         /* ENABLE_ACLK_CAM11 */
5250         GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
5251                         ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
5252         GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
5253                         ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
5254         GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c",
5255                         "div_pclk_lite_c", ENABLE_ACLK_CAM11,
5256                         27, CLK_IGNORE_UNUSED, 0),
5257         GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c",
5258                         "div_pclk_cam1_166", ENABLE_ACLK_CAM11,
5259                         26, CLK_IGNORE_UNUSED, 0),
5260         GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2",
5261                         "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5262                         25, CLK_IGNORE_UNUSED, 0),
5263         GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1",
5264                         "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5265                         24, CLK_IGNORE_UNUSED, 0),
5266         GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5",
5267                         "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5268                         23, CLK_IGNORE_UNUSED, 0),
5269         GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5",
5270                         "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11,
5271                         22, CLK_IGNORE_UNUSED, 0),
5272         GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2",
5273                         "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5274                         21, CLK_IGNORE_UNUSED, 0),
5275         GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1",
5276                         "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5277                         20, CLK_IGNORE_UNUSED, 0),
5278         GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0",
5279                         "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5280                         19, CLK_IGNORE_UNUSED, 0),
5281         GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex",
5282                         "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5283                         18, CLK_IGNORE_UNUSED, 0),
5284         GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p",
5285                         "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5286                         17, CLK_IGNORE_UNUSED, 0),
5287         GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p",
5288                         "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5289                         16, CLK_IGNORE_UNUSED, 0),
5290         GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd",
5291                         "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5292                         15, CLK_IGNORE_UNUSED, 0),
5293         GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd",
5294                         ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
5295         GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c",
5296                         "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5297                         13, CLK_IGNORE_UNUSED, 0),
5298         GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c",
5299                         "div_aclk_lite_c", ENABLE_ACLK_CAM11,
5300                         12, CLK_IGNORE_UNUSED, 0),
5301         GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
5302                         ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
5303         GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
5304                         ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
5305         GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p",
5306                         "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5307                         9, CLK_IGNORE_UNUSED, 0),
5308         GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
5309                         ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
5310         GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
5311                         ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
5312         GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
5313                         ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
5314         GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
5315                         ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
5316         GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
5317                         ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
5318         GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
5319                         ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
5320         GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
5321                         ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
5322         GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
5323                         ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
5324         GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
5325                         ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
5326
5327         /* ENABLE_ACLK_CAM12 */
5328         GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu",
5329                         "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5330                         10, CLK_IGNORE_UNUSED, 0),
5331         GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
5332                         ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
5333         GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c",
5334                         "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5335                         8, CLK_IGNORE_UNUSED, 0),
5336         GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
5337                         ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
5338         GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user",
5339                         ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
5340         GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
5341                         ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
5342         GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h",
5343                         "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5344                         4, CLK_IGNORE_UNUSED, 0),
5345         GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p",
5346                         "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5347                         3, CLK_IGNORE_UNUSED, 0),
5348         GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p",
5349                         "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5350                         2, CLK_IGNORE_UNUSED, 0),
5351         GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user",
5352                         ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
5353         GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c",
5354                         "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5355                         0, CLK_IGNORE_UNUSED, 0),
5356
5357         /* ENABLE_PCLK_CAM1 */
5358         GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
5359                         ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
5360         GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166",
5361                         ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
5362         GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166",
5363                         ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
5364         GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83",
5365                         ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
5366         GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83",
5367                         ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
5368         GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83",
5369                         ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
5370         GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
5371                         ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
5372         GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex",
5373                         "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5374                         20, CLK_IGNORE_UNUSED, 0),
5375         GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p",
5376                         "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5377                         19, CLK_IGNORE_UNUSED, 0),
5378         GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
5379                         ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
5380         GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c",
5381                         "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5382                         17, CLK_IGNORE_UNUSED, 0),
5383         GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83",
5384                         ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
5385         GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83",
5386                         ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
5387         GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local",
5388                         "div_pclk_cam1_166", ENABLE_PCLK_CAM1,
5389                         14, CLK_IGNORE_UNUSED, 0),
5390         GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83",
5391                         ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
5392         GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83",
5393                         ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
5394         GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83",
5395                         ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
5396         GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83",
5397                         ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
5398         GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83",
5399                         ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
5400         GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83",
5401                         ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
5402         GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83",
5403                         ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
5404         GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83",
5405                         ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
5406         GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83",
5407                         ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
5408         GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83",
5409                         ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
5410         GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83",
5411                         ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5412         GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd",
5413                         ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5414         GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c",
5415                         ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
5416         GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166",
5417                         ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
5418
5419         /* ENABLE_SCLK_CAM1 */
5420         GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
5421                         15, 0, 0),
5422         GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
5423                         14, 0, 0),
5424         GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
5425                         13, 0, 0),
5426         GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
5427                         12, 0, 0),
5428         GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
5429                         "mout_phyclk_rxbyteclkhs0_s2b_user",
5430                         ENABLE_SCLK_CAM1, 11, 0, 0),
5431         GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
5432                         ENABLE_SCLK_CAM1, 10, 0, 0),
5433         GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
5434                         ENABLE_SCLK_CAM1, 9, 0, 0),
5435         GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
5436                         ENABLE_SCLK_CAM1, 7, 0, 0),
5437         GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
5438                         ENABLE_SCLK_CAM1, 6, 0, 0),
5439         GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
5440                         ENABLE_SCLK_CAM1, 5, 0, 0),
5441         GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
5442                         ENABLE_SCLK_CAM1, 4, 0, 0),
5443         GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm",
5444                         ENABLE_SCLK_CAM1, 3, 0, 0),
5445         GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
5446                         ENABLE_SCLK_CAM1, 2, 0, 0),
5447         GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
5448                         ENABLE_SCLK_CAM1, 1, 0, 0),
5449         GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
5450                         ENABLE_SCLK_CAM1, 0, 0, 0),
5451 };
5452
5453 static const struct samsung_cmu_info cam1_cmu_info __initconst = {
5454         .mux_clks               = cam1_mux_clks,
5455         .nr_mux_clks            = ARRAY_SIZE(cam1_mux_clks),
5456         .div_clks               = cam1_div_clks,
5457         .nr_div_clks            = ARRAY_SIZE(cam1_div_clks),
5458         .gate_clks              = cam1_gate_clks,
5459         .nr_gate_clks           = ARRAY_SIZE(cam1_gate_clks),
5460         .fixed_clks             = cam1_fixed_clks,
5461         .nr_fixed_clks          = ARRAY_SIZE(cam1_fixed_clks),
5462         .nr_clk_ids             = CAM1_NR_CLK,
5463         .clk_regs               = cam1_clk_regs,
5464         .nr_clk_regs            = ARRAY_SIZE(cam1_clk_regs),
5465         .suspend_regs           = cam1_suspend_regs,
5466         .nr_suspend_regs        = ARRAY_SIZE(cam1_suspend_regs),
5467         .clk_name               = "aclk_cam1_400",
5468 };
5469
5470 /*
5471  * Register offset definitions for CMU_IMEM
5472  */
5473 #define ENABLE_ACLK_IMEM_SLIMSSS                0x080c
5474 #define ENABLE_PCLK_IMEM_SLIMSSS                0x0908
5475
5476 static const unsigned long imem_clk_regs[] __initconst = {
5477         ENABLE_ACLK_IMEM_SLIMSSS,
5478         ENABLE_PCLK_IMEM_SLIMSSS,
5479 };
5480
5481 static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
5482         /* ENABLE_ACLK_IMEM_SLIMSSS */
5483         GATE(CLK_ACLK_SLIMSSS, "aclk_slimsss", "aclk_imem_sssx_266",
5484                         ENABLE_ACLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
5485
5486         /* ENABLE_PCLK_IMEM_SLIMSSS */
5487         GATE(CLK_PCLK_SLIMSSS, "pclk_slimsss", "aclk_imem_200",
5488                         ENABLE_PCLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
5489 };
5490
5491 static const struct samsung_cmu_info imem_cmu_info __initconst = {
5492         .gate_clks              = imem_gate_clks,
5493         .nr_gate_clks           = ARRAY_SIZE(imem_gate_clks),
5494         .nr_clk_ids             = IMEM_NR_CLK,
5495         .clk_regs               = imem_clk_regs,
5496         .nr_clk_regs            = ARRAY_SIZE(imem_clk_regs),
5497         .clk_name               = "aclk_imem_200",
5498 };
5499
5500 struct exynos5433_cmu_data {
5501         struct samsung_clk_reg_dump *clk_save;
5502         unsigned int nr_clk_save;
5503         const struct samsung_clk_reg_dump *clk_suspend;
5504         unsigned int nr_clk_suspend;
5505
5506         struct clk *clk;
5507         struct clk **pclks;
5508         int nr_pclks;
5509
5510         /* must be the last entry */
5511         struct samsung_clk_provider ctx;
5512 };
5513
5514 static int __maybe_unused exynos5433_cmu_suspend(struct device *dev)
5515 {
5516         struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
5517         int i;
5518
5519         samsung_clk_save(data->ctx.reg_base, data->clk_save,
5520                          data->nr_clk_save);
5521
5522         for (i = 0; i < data->nr_pclks; i++)
5523                 clk_prepare_enable(data->pclks[i]);
5524
5525         /* for suspend some registers have to be set to certain values */
5526         samsung_clk_restore(data->ctx.reg_base, data->clk_suspend,
5527                             data->nr_clk_suspend);
5528
5529         for (i = 0; i < data->nr_pclks; i++)
5530                 clk_disable_unprepare(data->pclks[i]);
5531
5532         clk_disable_unprepare(data->clk);
5533
5534         return 0;
5535 }
5536
5537 static int __maybe_unused exynos5433_cmu_resume(struct device *dev)
5538 {
5539         struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
5540         int i;
5541
5542         clk_prepare_enable(data->clk);
5543
5544         for (i = 0; i < data->nr_pclks; i++)
5545                 clk_prepare_enable(data->pclks[i]);
5546
5547         samsung_clk_restore(data->ctx.reg_base, data->clk_save,
5548                             data->nr_clk_save);
5549
5550         for (i = 0; i < data->nr_pclks; i++)
5551                 clk_disable_unprepare(data->pclks[i]);
5552
5553         return 0;
5554 }
5555
5556 static int __init exynos5433_cmu_probe(struct platform_device *pdev)
5557 {
5558         const struct samsung_cmu_info *info;
5559         struct exynos5433_cmu_data *data;
5560         struct samsung_clk_provider *ctx;
5561         struct device *dev = &pdev->dev;
5562         struct resource *res;
5563         void __iomem *reg_base;
5564         int i;
5565
5566         info = of_device_get_match_data(dev);
5567
5568         data = devm_kzalloc(dev,
5569                             struct_size(data, ctx.clk_data.hws, info->nr_clk_ids),
5570                             GFP_KERNEL);
5571         if (!data)
5572                 return -ENOMEM;
5573         ctx = &data->ctx;
5574
5575         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5576         reg_base = devm_ioremap_resource(dev, res);
5577         if (IS_ERR(reg_base))
5578                 return PTR_ERR(reg_base);
5579
5580         for (i = 0; i < info->nr_clk_ids; ++i)
5581                 ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
5582
5583         ctx->clk_data.num = info->nr_clk_ids;
5584         ctx->reg_base = reg_base;
5585         ctx->dev = dev;
5586         spin_lock_init(&ctx->lock);
5587
5588         data->clk_save = samsung_clk_alloc_reg_dump(info->clk_regs,
5589                                                     info->nr_clk_regs);
5590         data->nr_clk_save = info->nr_clk_regs;
5591         data->clk_suspend = info->suspend_regs;
5592         data->nr_clk_suspend = info->nr_suspend_regs;
5593         data->nr_pclks = of_count_phandle_with_args(dev->of_node, "clocks",
5594                                                     "#clock-cells");
5595         if (data->nr_pclks > 0) {
5596                 data->pclks = devm_kcalloc(dev, sizeof(struct clk *),
5597                                            data->nr_pclks, GFP_KERNEL);
5598
5599                 for (i = 0; i < data->nr_pclks; i++) {
5600                         struct clk *clk = of_clk_get(dev->of_node, i);
5601
5602                         if (IS_ERR(clk))
5603                                 return PTR_ERR(clk);
5604                         data->pclks[i] = clk;
5605                 }
5606         }
5607
5608         if (info->clk_name)
5609                 data->clk = clk_get(dev, info->clk_name);
5610         clk_prepare_enable(data->clk);
5611
5612         platform_set_drvdata(pdev, data);
5613
5614         /*
5615          * Enable runtime PM here to allow the clock core using runtime PM
5616          * for the registered clocks. Additionally, we increase the runtime
5617          * PM usage count before registering the clocks, to prevent the
5618          * clock core from runtime suspending the device.
5619          */
5620         pm_runtime_get_noresume(dev);
5621         pm_runtime_set_active(dev);
5622         pm_runtime_enable(dev);
5623
5624         if (info->pll_clks)
5625                 samsung_clk_register_pll(ctx, info->pll_clks, info->nr_pll_clks,
5626                                          reg_base);
5627         if (info->mux_clks)
5628                 samsung_clk_register_mux(ctx, info->mux_clks,
5629                                          info->nr_mux_clks);
5630         if (info->div_clks)
5631                 samsung_clk_register_div(ctx, info->div_clks,
5632                                          info->nr_div_clks);
5633         if (info->gate_clks)
5634                 samsung_clk_register_gate(ctx, info->gate_clks,
5635                                           info->nr_gate_clks);
5636         if (info->fixed_clks)
5637                 samsung_clk_register_fixed_rate(ctx, info->fixed_clks,
5638                                                 info->nr_fixed_clks);
5639         if (info->fixed_factor_clks)
5640                 samsung_clk_register_fixed_factor(ctx, info->fixed_factor_clks,
5641                                                   info->nr_fixed_factor_clks);
5642
5643         samsung_clk_of_add_provider(dev->of_node, ctx);
5644         pm_runtime_put_sync(dev);
5645
5646         return 0;
5647 }
5648
5649 static const struct of_device_id exynos5433_cmu_of_match[] = {
5650         {
5651                 .compatible = "samsung,exynos5433-cmu-aud",
5652                 .data = &aud_cmu_info,
5653         }, {
5654                 .compatible = "samsung,exynos5433-cmu-cam0",
5655                 .data = &cam0_cmu_info,
5656         }, {
5657                 .compatible = "samsung,exynos5433-cmu-cam1",
5658                 .data = &cam1_cmu_info,
5659         }, {
5660                 .compatible = "samsung,exynos5433-cmu-disp",
5661                 .data = &disp_cmu_info,
5662         }, {
5663                 .compatible = "samsung,exynos5433-cmu-g2d",
5664                 .data = &g2d_cmu_info,
5665         }, {
5666                 .compatible = "samsung,exynos5433-cmu-g3d",
5667                 .data = &g3d_cmu_info,
5668         }, {
5669                 .compatible = "samsung,exynos5433-cmu-fsys",
5670                 .data = &fsys_cmu_info,
5671         }, {
5672                 .compatible = "samsung,exynos5433-cmu-gscl",
5673                 .data = &gscl_cmu_info,
5674         }, {
5675                 .compatible = "samsung,exynos5433-cmu-mfc",
5676                 .data = &mfc_cmu_info,
5677         }, {
5678                 .compatible = "samsung,exynos5433-cmu-hevc",
5679                 .data = &hevc_cmu_info,
5680         }, {
5681                 .compatible = "samsung,exynos5433-cmu-isp",
5682                 .data = &isp_cmu_info,
5683         }, {
5684                 .compatible = "samsung,exynos5433-cmu-mscl",
5685                 .data = &mscl_cmu_info,
5686         }, {
5687                 .compatible = "samsung,exynos5433-cmu-imem",
5688                 .data = &imem_cmu_info,
5689         }, {
5690         },
5691 };
5692
5693 static const struct dev_pm_ops exynos5433_cmu_pm_ops = {
5694         SET_RUNTIME_PM_OPS(exynos5433_cmu_suspend, exynos5433_cmu_resume,
5695                            NULL)
5696         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
5697                                      pm_runtime_force_resume)
5698 };
5699
5700 static struct platform_driver exynos5433_cmu_driver __refdata = {
5701         .driver = {
5702                 .name = "exynos5433-cmu",
5703                 .of_match_table = exynos5433_cmu_of_match,
5704                 .suppress_bind_attrs = true,
5705                 .pm = &exynos5433_cmu_pm_ops,
5706         },
5707         .probe = exynos5433_cmu_probe,
5708 };
5709
5710 static int __init exynos5433_cmu_init(void)
5711 {
5712         return platform_driver_register(&exynos5433_cmu_driver);
5713 }
5714 core_initcall(exynos5433_cmu_init);