drivers/clk/samsung/clk-exynos5420.c

   1 /*
   2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   3  * Authors: Thomas Abraham <thomas.ab@samsung.com>
   4  *          Chander Kashyap <k.chander@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Common Clock Framework support for Exynos5420 SoC.
  11 */
  12
  13 #include <dt-bindings/clock/exynos5420.h>
  14 #include <linux/slab.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18
  19 #include "clk.h"
  20 #include "clk-cpu.h"
  21 #include "clk-exynos5-subcmu.h"
  22
  23 #define APLL_LOCK               0x0
  24 #define APLL_CON0               0x100
  25 #define SRC_CPU                 0x200
  26 #define DIV_CPU0                0x500
  27 #define DIV_CPU1                0x504
  28 #define GATE_BUS_CPU            0x700
  29 #define GATE_SCLK_CPU           0x800
  30 #define CLKOUT_CMU_CPU          0xa00
  31 #define SRC_MASK_CPERI          0x4300
  32 #define GATE_IP_G2D             0x8800
  33 #define CPLL_LOCK               0x10020
  34 #define DPLL_LOCK               0x10030
  35 #define EPLL_LOCK               0x10040
  36 #define RPLL_LOCK               0x10050
  37 #define IPLL_LOCK               0x10060
  38 #define SPLL_LOCK               0x10070
  39 #define VPLL_LOCK               0x10080
  40 #define MPLL_LOCK               0x10090
  41 #define CPLL_CON0               0x10120
  42 #define DPLL_CON0               0x10128
  43 #define EPLL_CON0               0x10130
  44 #define EPLL_CON1               0x10134
  45 #define EPLL_CON2               0x10138
  46 #define RPLL_CON0               0x10140
  47 #define RPLL_CON1               0x10144
  48 #define RPLL_CON2               0x10148
  49 #define IPLL_CON0               0x10150
  50 #define SPLL_CON0               0x10160
  51 #define VPLL_CON0               0x10170
  52 #define MPLL_CON0               0x10180
  53 #define SRC_TOP0                0x10200
  54 #define SRC_TOP1                0x10204
  55 #define SRC_TOP2                0x10208
  56 #define SRC_TOP3                0x1020c
  57 #define SRC_TOP4                0x10210
  58 #define SRC_TOP5                0x10214
  59 #define SRC_TOP6                0x10218
  60 #define SRC_TOP7                0x1021c
  61 #define SRC_TOP8                0x10220 /* 5800 specific */
  62 #define SRC_TOP9                0x10224 /* 5800 specific */
  63 #define SRC_DISP10              0x1022c
  64 #define SRC_MAU                 0x10240
  65 #define SRC_FSYS                0x10244
  66 #define SRC_PERIC0              0x10250
  67 #define SRC_PERIC1              0x10254
  68 #define SRC_ISP                 0x10270
  69 #define SRC_CAM                 0x10274 /* 5800 specific */
  70 #define SRC_TOP10               0x10280
  71 #define SRC_TOP11               0x10284
  72 #define SRC_TOP12               0x10288
  73 #define SRC_TOP13               0x1028c /* 5800 specific */
  74 #define SRC_MASK_TOP0           0x10300
  75 #define SRC_MASK_TOP1           0x10304
  76 #define SRC_MASK_TOP2           0x10308
  77 #define SRC_MASK_TOP7           0x1031c
  78 #define SRC_MASK_DISP10         0x1032c
  79 #define SRC_MASK_MAU            0x10334
  80 #define SRC_MASK_FSYS           0x10340
  81 #define SRC_MASK_PERIC0         0x10350
  82 #define SRC_MASK_PERIC1         0x10354
  83 #define SRC_MASK_ISP            0x10370
  84 #define DIV_TOP0                0x10500
  85 #define DIV_TOP1                0x10504
  86 #define DIV_TOP2                0x10508
  87 #define DIV_TOP8                0x10520 /* 5800 specific */
  88 #define DIV_TOP9                0x10524 /* 5800 specific */
  89 #define DIV_DISP10              0x1052c
  90 #define DIV_MAU                 0x10544
  91 #define DIV_FSYS0               0x10548
  92 #define DIV_FSYS1               0x1054c
  93 #define DIV_FSYS2               0x10550
  94 #define DIV_PERIC0              0x10558
  95 #define DIV_PERIC1              0x1055c
  96 #define DIV_PERIC2              0x10560
  97 #define DIV_PERIC3              0x10564
  98 #define DIV_PERIC4              0x10568
  99 #define DIV_CAM                 0x10574 /* 5800 specific */
 100 #define SCLK_DIV_ISP0           0x10580
 101 #define SCLK_DIV_ISP1           0x10584
 102 #define DIV2_RATIO0             0x10590
 103 #define DIV4_RATIO              0x105a0
 104 #define GATE_BUS_TOP            0x10700
 105 #define GATE_BUS_DISP1          0x10728
 106 #define GATE_BUS_GEN            0x1073c
 107 #define GATE_BUS_FSYS0          0x10740
 108 #define GATE_BUS_FSYS2          0x10748
 109 #define GATE_BUS_PERIC          0x10750
 110 #define GATE_BUS_PERIC1         0x10754
 111 #define GATE_BUS_PERIS0         0x10760
 112 #define GATE_BUS_PERIS1         0x10764
 113 #define GATE_BUS_NOC            0x10770
 114 #define GATE_TOP_SCLK_ISP       0x10870
 115 #define GATE_IP_GSCL0           0x10910
 116 #define GATE_IP_GSCL1           0x10920
 117 #define GATE_IP_CAM             0x10924 /* 5800 specific */
 118 #define GATE_IP_MFC             0x1092c
 119 #define GATE_IP_DISP1           0x10928
 120 #define GATE_IP_G3D             0x10930
 121 #define GATE_IP_GEN             0x10934
 122 #define GATE_IP_FSYS            0x10944
 123 #define GATE_IP_PERIC           0x10950
 124 #define GATE_IP_PERIS           0x10960
 125 #define GATE_IP_MSCL            0x10970
 126 #define GATE_TOP_SCLK_GSCL      0x10820
 127 #define GATE_TOP_SCLK_DISP1     0x10828
 128 #define GATE_TOP_SCLK_MAU       0x1083c
 129 #define GATE_TOP_SCLK_FSYS      0x10840
 130 #define GATE_TOP_SCLK_PERIC     0x10850
 131 #define TOP_SPARE2              0x10b08
 132 #define BPLL_LOCK               0x20010
 133 #define BPLL_CON0               0x20110
 134 #define SRC_CDREX               0x20200
 135 #define DIV_CDREX0              0x20500
 136 #define DIV_CDREX1              0x20504
 137 #define KPLL_LOCK               0x28000
 138 #define KPLL_CON0               0x28100
 139 #define SRC_KFC                 0x28200
 140 #define DIV_KFC0                0x28500
 141
 142 /* Exynos5x SoC type */
 143 enum exynos5x_soc {
 144         EXYNOS5420,
 145         EXYNOS5800,
 146 };
 147
 148 /* list of PLLs */
 149 enum exynos5x_plls {
 150         apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
 151         bpll, kpll,
 152         nr_plls                 /* number of PLLs */
 153 };
 154
 155 static void __iomem *reg_base;
 156 static enum exynos5x_soc exynos5x_soc;
 157
 158 /*
 159  * list of controller registers to be saved and restored during a
 160  * suspend/resume cycle.
 161  */
 162 static const unsigned long exynos5x_clk_regs[] __initconst = {
 163         SRC_CPU,
 164         DIV_CPU0,
 165         DIV_CPU1,
 166         GATE_BUS_CPU,
 167         GATE_SCLK_CPU,
 168         CLKOUT_CMU_CPU,
 169         EPLL_CON0,
 170         EPLL_CON1,
 171         EPLL_CON2,
 172         RPLL_CON0,
 173         RPLL_CON1,
 174         RPLL_CON2,
 175         SRC_TOP0,
 176         SRC_TOP1,
 177         SRC_TOP2,
 178         SRC_TOP3,
 179         SRC_TOP4,
 180         SRC_TOP5,
 181         SRC_TOP6,
 182         SRC_TOP7,
 183         SRC_DISP10,
 184         SRC_MAU,
 185         SRC_FSYS,
 186         SRC_PERIC0,
 187         SRC_PERIC1,
 188         SRC_TOP10,
 189         SRC_TOP11,
 190         SRC_TOP12,
 191         SRC_MASK_TOP2,
 192         SRC_MASK_TOP7,
 193         SRC_MASK_DISP10,
 194         SRC_MASK_FSYS,
 195         SRC_MASK_PERIC0,
 196         SRC_MASK_PERIC1,
 197         SRC_MASK_TOP0,
 198         SRC_MASK_TOP1,
 199         SRC_MASK_MAU,
 200         SRC_MASK_ISP,
 201         SRC_ISP,
 202         DIV_TOP0,
 203         DIV_TOP1,
 204         DIV_TOP2,
 205         DIV_DISP10,
 206         DIV_MAU,
 207         DIV_FSYS0,
 208         DIV_FSYS1,
 209         DIV_FSYS2,
 210         DIV_PERIC0,
 211         DIV_PERIC1,
 212         DIV_PERIC2,
 213         DIV_PERIC3,
 214         DIV_PERIC4,
 215         SCLK_DIV_ISP0,
 216         SCLK_DIV_ISP1,
 217         DIV2_RATIO0,
 218         DIV4_RATIO,
 219         GATE_BUS_DISP1,
 220         GATE_BUS_TOP,
 221         GATE_BUS_GEN,
 222         GATE_BUS_FSYS0,
 223         GATE_BUS_FSYS2,
 224         GATE_BUS_PERIC,
 225         GATE_BUS_PERIC1,
 226         GATE_BUS_PERIS0,
 227         GATE_BUS_PERIS1,
 228         GATE_BUS_NOC,
 229         GATE_TOP_SCLK_ISP,
 230         GATE_IP_GSCL0,
 231         GATE_IP_GSCL1,
 232         GATE_IP_MFC,
 233         GATE_IP_DISP1,
 234         GATE_IP_G3D,
 235         GATE_IP_GEN,
 236         GATE_IP_FSYS,
 237         GATE_IP_PERIC,
 238         GATE_IP_PERIS,
 239         GATE_IP_MSCL,
 240         GATE_TOP_SCLK_GSCL,
 241         GATE_TOP_SCLK_DISP1,
 242         GATE_TOP_SCLK_MAU,
 243         GATE_TOP_SCLK_FSYS,
 244         GATE_TOP_SCLK_PERIC,
 245         TOP_SPARE2,
 246         SRC_CDREX,
 247         DIV_CDREX0,
 248         DIV_CDREX1,
 249         SRC_KFC,
 250         DIV_KFC0,
 251 };
 252
 253 static const unsigned long exynos5800_clk_regs[] __initconst = {
 254         SRC_TOP8,
 255         SRC_TOP9,
 256         SRC_CAM,
 257         SRC_TOP1,
 258         DIV_TOP8,
 259         DIV_TOP9,
 260         DIV_CAM,
 261         GATE_IP_CAM,
 262 };
 263
 264 static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
 265         { .offset = SRC_MASK_CPERI,             .value = 0xffffffff, },
 266         { .offset = SRC_MASK_TOP0,              .value = 0x11111111, },
 267         { .offset = SRC_MASK_TOP1,              .value = 0x11101111, },
 268         { .offset = SRC_MASK_TOP2,              .value = 0x11111110, },
 269         { .offset = SRC_MASK_TOP7,              .value = 0x00111100, },
 270         { .offset = SRC_MASK_DISP10,            .value = 0x11111110, },
 271         { .offset = SRC_MASK_MAU,               .value = 0x10000000, },
 272         { .offset = SRC_MASK_FSYS,              .value = 0x11111110, },
 273         { .offset = SRC_MASK_PERIC0,            .value = 0x11111110, },
 274         { .offset = SRC_MASK_PERIC1,            .value = 0x11111100, },
 275         { .offset = SRC_MASK_ISP,               .value = 0x11111000, },
 276         { .offset = GATE_BUS_TOP,               .value = 0xffffffff, },
 277         { .offset = GATE_BUS_DISP1,             .value = 0xffffffff, },
 278         { .offset = GATE_IP_PERIC,              .value = 0xffffffff, },
 279         { .offset = GATE_IP_PERIS,              .value = 0xffffffff, },
 280 };
 281
 282 /* list of all parent clocks */
 283 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
 284                                 "mout_sclk_mpll", "mout_sclk_spll"};
 285 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
 286 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
 287 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
 288 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
 289 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
 290 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
 291 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
 292 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
 293 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
 294 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
 295 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
 296 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
 297 PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
 298
 299 PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
 300                                         "mout_sclk_mpll"};
 301 PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
 302                         "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
 303                         "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
 304 PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
 305 PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
 306 PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
 307
 308 PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
 309 PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
 310 PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
 311 PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
 312
 313 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
 314 PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
 315 PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
 316 PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
 317
 318 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
 319 PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
 320 PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
 321 PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
 322
 323 PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
 324 PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
 325 PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
 326
 327 PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
 328 PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
 329
 330 PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
 331                                         "mout_sclk_spll"};
 332 PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
 333
 334 PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
 335 PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
 336
 337 PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
 338 PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
 339
 340 PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
 341 PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
 342
 343 PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
 344 PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
 345
 346 PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
 347 PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
 348
 349 PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
 350 PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
 351 PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
 352
 353 PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
 354 PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
 355
 356 PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
 357 PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
 358
 359 PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
 360 PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
 361 PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
 362 PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
 363
 364 PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
 365 PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
 366
 367 PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
 368 PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
 369
 370 PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
 371 PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
 372
 373 PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
 374 PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
 375
 376 PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
 377                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 378                         "mout_sclk_epll", "mout_sclk_rpll"};
 379 PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
 380                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 381                         "mout_sclk_epll", "mout_sclk_rpll"};
 382 PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
 383                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 384                         "mout_sclk_epll", "mout_sclk_rpll"};
 385 PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
 386                         "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
 387                         "mout_sclk_epll", "mout_sclk_rpll"};
 388 PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
 389 PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
 390                          "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 391                          "mout_sclk_epll", "mout_sclk_rpll"};
 392 PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
 393                                 "mout_sclk_mpll", "mout_sclk_spll"};
 394 PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"};
 395
 396 /* List of parents specific to exynos5800 */
 397 PNAME(mout_epll2_5800_p)        = { "mout_sclk_epll", "ff_dout_epll2" };
 398 PNAME(mout_group1_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
 399                                 "mout_sclk_mpll", "ff_dout_spll2" };
 400 PNAME(mout_group2_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
 401                                         "mout_sclk_mpll", "ff_dout_spll2",
 402                                         "mout_epll2", "mout_sclk_ipll" };
 403 PNAME(mout_group3_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
 404                                         "mout_sclk_mpll", "ff_dout_spll2",
 405                                         "mout_epll2" };
 406 PNAME(mout_group5_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
 407                                         "mout_sclk_mpll", "mout_sclk_spll" };
 408 PNAME(mout_group6_5800_p)       = { "mout_sclk_ipll", "mout_sclk_dpll",
 409                                 "mout_sclk_mpll", "ff_dout_spll2" };
 410 PNAME(mout_group7_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
 411                                         "mout_sclk_mpll", "mout_sclk_spll",
 412                                         "mout_epll2", "mout_sclk_ipll" };
 413 PNAME(mout_mx_mspll_ccore_p)    = {"sclk_bpll", "mout_sclk_dpll",
 414                                         "mout_sclk_mpll", "ff_dout_spll2",
 415                                         "mout_sclk_spll", "mout_sclk_epll"};
 416 PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll",
 417                                         "mout_sclk_mpll",
 418                                         "ff_dout_spll2" };
 419 PNAME(mout_group8_5800_p)       = { "dout_aclk432_scaler", "dout_sclk_sw" };
 420 PNAME(mout_group9_5800_p)       = { "dout_osc_div", "mout_sw_aclk432_scaler" };
 421 PNAME(mout_group10_5800_p)      = { "dout_aclk432_cam", "dout_sclk_sw" };
 422 PNAME(mout_group11_5800_p)      = { "dout_osc_div", "mout_sw_aclk432_cam" };
 423 PNAME(mout_group12_5800_p)      = { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
 424 PNAME(mout_group13_5800_p)      = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
 425 PNAME(mout_group14_5800_p)      = { "dout_aclk550_cam", "dout_sclk_sw" };
 426 PNAME(mout_group15_5800_p)      = { "dout_osc_div", "mout_sw_aclk550_cam" };
 427 PNAME(mout_group16_5800_p)      = { "dout_osc_div", "mout_mau_epll_clk" };
 428
 429 /* fixed rate clocks generated outside the soc */
 430 static struct samsung_fixed_rate_clock
 431                 exynos5x_fixed_rate_ext_clks[] __initdata = {
 432         FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
 433 };
 434
 435 /* fixed rate clocks generated inside the soc */
 436 static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = {
 437         FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
 438         FRATE(0, "sclk_pwi", NULL, 0, 24000000),
 439         FRATE(0, "sclk_usbh20", NULL, 0, 48000000),
 440         FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000),
 441         FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000),
 442 };
 443
 444 static const struct samsung_fixed_factor_clock
 445                 exynos5x_fixed_factor_clks[] __initconst = {
 446         FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
 447         FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
 448 };
 449
 450 static const struct samsung_fixed_factor_clock
 451                 exynos5800_fixed_factor_clks[] __initconst = {
 452         FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
 453         FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
 454 };
 455
 456 static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
 457         MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
 458         MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
 459         MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
 460         MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
 461
 462         MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
 463         MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
 464         MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
 465         MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
 466         MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
 467
 468         MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
 469         MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
 470         MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
 471         MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
 472         MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
 473         MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
 474
 475         MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
 476                         mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2),
 477         MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
 478                         SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
 479         MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
 480         MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
 481
 482         MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
 483         MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
 484         MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
 485         MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
 486
 487         MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
 488                         SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
 489         MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
 490                                                         SRC_TOP9, 16, 1),
 491         MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
 492                                                         SRC_TOP9, 20, 1),
 493         MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
 494                                                         SRC_TOP9, 24, 1),
 495         MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
 496                                                         SRC_TOP9, 28, 1),
 497
 498         MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
 499         MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
 500                                                         SRC_TOP13, 20, 1),
 501         MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
 502                                                         SRC_TOP13, 24, 1),
 503         MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
 504                                                         SRC_TOP13, 28, 1),
 505
 506         MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
 507 };
 508
 509 static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
 510         DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
 511                         "mout_aclk400_wcore", DIV_TOP0, 16, 3),
 512         DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
 513                                 DIV_TOP8, 16, 3),
 514         DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
 515                                 DIV_TOP8, 20, 3),
 516         DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
 517                                 DIV_TOP8, 24, 3),
 518         DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
 519                                 DIV_TOP8, 28, 3),
 520
 521         DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
 522         DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
 523 };
 524
 525 static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
 526         GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
 527                                 GATE_BUS_TOP, 24, 0, 0),
 528         GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
 529                                 GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
 530         GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",
 531                         SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
 532 };
 533
 534 static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
 535         MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
 536         MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
 537                                 TOP_SPARE2, 4, 1),
 538
 539         MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
 540         MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
 541         MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
 542         MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
 543
 544         MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
 545         MUX(0, "mout_aclk333_432_isp", mout_group4_p,
 546                                 SRC_TOP1, 4, 2),
 547         MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
 548         MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
 549         MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
 550
 551         MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
 552         MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
 553         MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
 554         MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
 555         MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
 556         MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
 557
 558         MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
 559                         mout_group5_5800_p, SRC_TOP7, 16, 2),
 560         MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
 561               CLK_SET_RATE_PARENT, 0),
 562
 563         MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
 564 };
 565
 566 static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
 567         DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
 568                         "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
 569 };
 570
 571 static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
 572         GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
 573         GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
 574                         SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
 575 };
 576
 577 static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 578         MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
 579                         SRC_TOP7, 4, 1),
 580         MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
 581         MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
 582
 583         MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
 584               CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
 585         MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
 586         MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
 587               CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
 588         MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
 589
 590         MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
 591         MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
 592         MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
 593         MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
 594
 595         MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
 596         MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
 597
 598         MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
 599
 600         MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
 601                         SRC_TOP3, 0, 1),
 602         MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
 603                         SRC_TOP3, 4, 1),
 604         MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
 605                         mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
 606         MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
 607                         SRC_TOP3, 12, 1),
 608         MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
 609                         SRC_TOP3, 16, 1),
 610         MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
 611                         SRC_TOP3, 20, 1),
 612         MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
 613                         SRC_TOP3, 24, 1),
 614         MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
 615                         SRC_TOP3, 28, 1),
 616
 617         MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
 618                         SRC_TOP4, 0, 1),
 619         MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
 620                         SRC_TOP4, 4, 1),
 621         MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
 622                         SRC_TOP4, 8, 1),
 623         MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
 624                         SRC_TOP4, 12, 1),
 625         MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
 626                         SRC_TOP4, 16, 1),
 627         MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
 628         MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
 629         MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
 630                         SRC_TOP4, 28, 1),
 631
 632         MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
 633                         mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
 634         MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
 635                         SRC_TOP5, 4, 1),
 636         MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
 637                         SRC_TOP5, 8, 1),
 638         MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
 639                         SRC_TOP5, 12, 1),
 640         MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
 641                         SRC_TOP5, 16, 1),
 642         MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
 643                         SRC_TOP5, 20, 1),
 644         MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
 645                         mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
 646         MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
 647                         mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
 648
 649         MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
 650         MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
 651         MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
 652         MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
 653         MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
 654         MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
 655                         CLK_SET_RATE_PARENT, 0),
 656         MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
 657         MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
 658
 659         MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
 660                         SRC_TOP10, 0, 1),
 661         MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
 662                         SRC_TOP10, 4, 1),
 663         MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
 664                         SRC_TOP10, 8, 1),
 665         MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
 666                         SRC_TOP10, 12, 1),
 667         MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
 668                         SRC_TOP10, 16, 1),
 669         MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
 670                         SRC_TOP10, 20, 1),
 671         MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
 672                         SRC_TOP10, 24, 1),
 673         MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
 674                         SRC_TOP10, 28, 1),
 675
 676         MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
 677                         SRC_TOP11, 0, 1),
 678         MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
 679                         SRC_TOP11, 4, 1),
 680         MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
 681         MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
 682                         SRC_TOP11, 12, 1),
 683         MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
 684         MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
 685         MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
 686                         SRC_TOP11, 28, 1),
 687
 688         MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
 689                         mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
 690         MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
 691                         SRC_TOP12, 8, 1),
 692         MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
 693                         SRC_TOP12, 12, 1),
 694         MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
 695         MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
 696                         SRC_TOP12, 20, 1),
 697         MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
 698                         mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
 699         MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",
 700                         mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
 701
 702         /* DISP1 Block */
 703         MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
 704         MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
 705         MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
 706         MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
 707         MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
 708
 709         MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
 710
 711         /* CDREX block */
 712         MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p,
 713                         SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0),
 714         MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1,
 715                         CLK_SET_RATE_PARENT, 0),
 716
 717         /* MAU Block */
 718         MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
 719
 720         /* FSYS Block */
 721         MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
 722         MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
 723         MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
 724         MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
 725         MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
 726         MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
 727         MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
 728
 729         /* PERIC Block */
 730         MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
 731         MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
 732         MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
 733         MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
 734         MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
 735         MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
 736         MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
 737         MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
 738         MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
 739         MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
 740         MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
 741         MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
 742
 743         /* ISP Block */
 744         MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
 745         MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
 746         MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
 747         MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
 748         MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
 749 };
 750
 751 static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
 752         DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
 753         DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
 754         DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
 755         DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
 756         DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
 757
 758         DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp",
 759                         DIV_TOP0, 0, 3),
 760         DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl",
 761                         DIV_TOP0, 4, 3),
 762         DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200",
 763                         DIV_TOP0, 8, 3),
 764         DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
 765                         DIV_TOP0, 12, 3),
 766         DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
 767                         DIV_TOP0, 20, 3),
 768         DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
 769                         DIV_TOP0, 24, 3),
 770         DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
 771                         DIV_TOP0, 28, 3),
 772         DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl",
 773                         "mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
 774         DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp",
 775                         "mout_aclk333_432_isp", DIV_TOP1, 4, 3),
 776         DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66",
 777                         DIV_TOP1, 8, 6),
 778         DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0",
 779                         "mout_aclk333_432_isp0", DIV_TOP1, 16, 3),
 780         DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266",
 781                         DIV_TOP1, 20, 3),
 782         DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166",
 783                         DIV_TOP1, 24, 3),
 784         DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333",
 785                         DIV_TOP1, 28, 3),
 786
 787         DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d",
 788                         DIV_TOP2, 8, 3),
 789         DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
 790                         DIV_TOP2, 12, 3),
 791         DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
 792                         16, 3),
 793         DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
 794                         DIV_TOP2, 20, 3),
 795         DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
 796                         "mout_aclk300_disp1", DIV_TOP2, 24, 3),
 797         DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl",
 798                         DIV_TOP2, 28, 3),
 799
 800         /* DISP1 Block */
 801         DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
 802         DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
 803         DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
 804         DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
 805         DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1",
 806                         "mout_aclk400_disp1", DIV_TOP2, 4, 3),
 807
 808         /* CDREX Block */
 809         DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
 810                         DIV_CDREX0, 28, 3),
 811         DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex",
 812                         DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0),
 813         DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0",
 814                         DIV_CDREX0, 16, 3),
 815         DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0",
 816                         DIV_CDREX0, 8, 3),
 817         DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex",
 818                         DIV_CDREX0, 3, 5),
 819
 820         DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex",
 821                         DIV_CDREX1, 8, 3),
 822
 823         /* Audio Block */
 824         DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
 825         DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
 826
 827         /* USB3.0 */
 828         DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
 829         DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
 830         DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
 831         DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
 832
 833         /* MMC */
 834         DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
 835         DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
 836         DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
 837
 838         DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
 839         DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
 840
 841         /* UART and PWM */
 842         DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
 843         DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
 844         DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
 845         DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
 846         DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
 847
 848         /* SPI */
 849         DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
 850         DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
 851         DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
 852
 853
 854         /* PCM */
 855         DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
 856         DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
 857
 858         /* Audio - I2S */
 859         DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
 860         DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
 861         DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
 862         DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
 863         DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
 864
 865         /* SPI Pre-Ratio */
 866         DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
 867         DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
 868         DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
 869
 870         /* GSCL Block */
 871         DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
 872
 873         /* MSCL Block */
 874         DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
 875
 876         /* PSGEN */
 877         DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
 878         DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
 879
 880         /* ISP Block */
 881         DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
 882         DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
 883         DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
 884         DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
 885         DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
 886         DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
 887         DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
 888         DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
 889                         CLK_SET_RATE_PARENT, 0),
 890         DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
 891                         CLK_SET_RATE_PARENT, 0),
 892 };
 893
 894 static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
 895         /* G2D */
 896         GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
 897         GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
 898         GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
 899         GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
 900         GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
 901
 902         GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
 903                         GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0),
 904         GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
 905                         GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
 906
 907         GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
 908                         GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
 909         GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
 910                         GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0),
 911         GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
 912                         GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
 913         GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
 914                         GATE_BUS_TOP, 5, 0, 0),
 915         GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
 916                         GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0),
 917         GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
 918                         GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
 919         GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
 920                         GATE_BUS_TOP, 8, 0, 0),
 921         GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
 922                         GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
 923         GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
 924                         GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
 925         GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
 926                         GATE_BUS_TOP, 13, 0, 0),
 927         GATE(0, "aclk166", "mout_user_aclk166",
 928                         GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
 929         GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
 930                         GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0),
 931         GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
 932                         GATE_BUS_TOP, 16, 0, 0),
 933         GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
 934                         GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
 935         GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
 936                         GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
 937         GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
 938                         GATE_BUS_TOP, 28, 0, 0),
 939         GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
 940                         GATE_BUS_TOP, 29, 0, 0),
 941
 942         GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
 943                         SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0),
 944
 945         /* sclk */
 946         GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
 947                 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
 948         GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
 949                 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
 950         GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
 951                 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
 952         GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
 953                 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
 954         GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
 955                 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
 956         GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
 957                 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
 958         GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
 959                 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
 960         GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
 961                 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
 962         GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
 963                 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
 964         GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
 965                 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
 966         GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
 967                 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
 968         GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
 969                 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
 970         GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
 971                 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
 972
 973         GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
 974                 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
 975         GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
 976                 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
 977         GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
 978                 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
 979         GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
 980                 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
 981         GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
 982                 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
 983         GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
 984                 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
 985         GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
 986                 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
 987
 988         /* Display */
 989         GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
 990                         GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
 991         GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
 992                         GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
 993         GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
 994                         GATE_TOP_SCLK_DISP1, 9, 0, 0),
 995         GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
 996                         GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
 997         GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
 998                         GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
 999
1000         /* Maudio Block */
1001         GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
1002                 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
1003         GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
1004                 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
1005
1006         /* FSYS Block */
1007         GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
1008         GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
1009         GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
1010         GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
1011         GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
1012         GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
1013         GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
1014         GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
1015         GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
1016                         GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
1017         GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
1018         GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
1019         GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
1020         GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
1021                         SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1022
1023         /* PERIC Block */
1024         GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
1025                         GATE_IP_PERIC, 0, 0, 0),
1026         GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
1027                         GATE_IP_PERIC, 1, 0, 0),
1028         GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
1029                         GATE_IP_PERIC, 2, 0, 0),
1030         GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
1031                         GATE_IP_PERIC, 3, 0, 0),
1032         GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
1033                         GATE_IP_PERIC, 6, 0, 0),
1034         GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
1035                         GATE_IP_PERIC, 7, 0, 0),
1036         GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",
1037                         GATE_IP_PERIC, 8, 0, 0),
1038         GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",
1039                         GATE_IP_PERIC, 9, 0, 0),
1040         GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",
1041                         GATE_IP_PERIC, 10, 0, 0),
1042         GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",
1043                         GATE_IP_PERIC, 11, 0, 0),
1044         GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",
1045                         GATE_IP_PERIC, 12, 0, 0),
1046         GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",
1047                         GATE_IP_PERIC, 13, 0, 0),
1048         GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",
1049                         GATE_IP_PERIC, 14, 0, 0),
1050         GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
1051                         GATE_IP_PERIC, 15, 0, 0),
1052         GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
1053                         GATE_IP_PERIC, 16, 0, 0),
1054         GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
1055                         GATE_IP_PERIC, 17, 0, 0),
1056         GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",
1057                         GATE_IP_PERIC, 18, 0, 0),
1058         GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",
1059                         GATE_IP_PERIC, 20, 0, 0),
1060         GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
1061                         GATE_IP_PERIC, 21, 0, 0),
1062         GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",
1063                         GATE_IP_PERIC, 22, 0, 0),
1064         GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",
1065                         GATE_IP_PERIC, 23, 0, 0),
1066         GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
1067                         GATE_IP_PERIC, 24, 0, 0),
1068         GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",
1069                         GATE_IP_PERIC, 26, 0, 0),
1070         GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",
1071                         GATE_IP_PERIC, 28, 0, 0),
1072         GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",
1073                         GATE_IP_PERIC, 30, 0, 0),
1074         GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",
1075                         GATE_IP_PERIC, 31, 0, 0),
1076
1077         GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",
1078                         GATE_BUS_PERIC, 22, 0, 0),
1079
1080         /* PERIS Block */
1081         GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
1082                         GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1083         GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
1084                         GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1085         GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
1086         GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
1087         GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
1088         GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
1089         GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
1090         GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
1091         GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
1092         GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
1093         GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
1094         GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
1095         GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
1096         GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
1097         GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
1098         GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
1099         GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
1100         GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
1101
1102         /* GEN Block */
1103         GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
1104         GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
1105         GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
1106         GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
1107         GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
1108         GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
1109                         GATE_IP_GEN, 6, 0, 0),
1110         GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
1111         GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
1112                         GATE_IP_GEN, 9, 0, 0),
1113
1114         /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
1115         GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
1116                         GATE_BUS_GEN, 28, 0, 0),
1117         GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
1118
1119         /* GSCL Block */
1120         GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
1121                         GATE_TOP_SCLK_GSCL, 6, 0, 0),
1122         GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
1123                         GATE_TOP_SCLK_GSCL, 7, 0, 0),
1124
1125         GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
1126                         GATE_IP_GSCL0, 4, 0, 0),
1127         GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
1128                         GATE_IP_GSCL0, 5, 0, 0),
1129         GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
1130                         GATE_IP_GSCL0, 6, 0, 0),
1131
1132         GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
1133                         GATE_IP_GSCL1, 2, 0, 0),
1134         GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
1135                         GATE_IP_GSCL1, 3, 0, 0),
1136         GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
1137                         GATE_IP_GSCL1, 4, 0, 0),
1138         GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0),
1139         GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0),
1140         GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
1141                         GATE_IP_GSCL1, 16, 0, 0),
1142         GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
1143                         GATE_IP_GSCL1, 17, 0, 0),
1144
1145         /* MSCL Block */
1146         GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
1147         GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
1148         GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
1149         GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
1150                         GATE_IP_MSCL, 8, 0, 0),
1151         GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
1152                         GATE_IP_MSCL, 9, 0, 0),
1153         GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
1154                         GATE_IP_MSCL, 10, 0, 0),
1155
1156         /* ISP */
1157         GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
1158                         GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
1159         GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
1160                         GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
1161         GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
1162                         GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
1163         GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
1164                         GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
1165         GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
1166                         GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
1167         GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
1168                         GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1169         GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
1170                         GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
1171
1172         GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
1173 };
1174
1175 static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = {
1176         DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
1177 };
1178
1179 static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = {
1180         GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
1181         GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
1182         GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
1183         GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
1184         GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
1185         GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
1186                         GATE_IP_DISP1, 7, 0, 0),
1187         GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
1188                         GATE_IP_DISP1, 8, 0, 0),
1189         GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
1190                         GATE_IP_DISP1, 9, 0, 0),
1191 };
1192
1193 static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = {
1194         { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
1195         { SRC_TOP5, 0, BIT(0) },        /* MUX mout_user_aclk400_disp1 */
1196         { SRC_TOP5, 0, BIT(24) },       /* MUX mout_user_aclk300_disp1 */
1197         { SRC_TOP3, 0, BIT(8) },        /* MUX mout_user_aclk200_disp1 */
1198         { DIV2_RATIO0, 0, 0x30000 },            /* DIV dout_disp1_blk */
1199 };
1200
1201 static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = {
1202         DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
1203                         DIV2_RATIO0, 4, 2),
1204 };
1205
1206 static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = {
1207         GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
1208         GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
1209         GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
1210                         GATE_IP_GSCL1, 6, 0, 0),
1211         GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
1212                         GATE_IP_GSCL1, 7, 0, 0),
1213 };
1214
1215 static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
1216         { GATE_IP_GSCL0, 0x3, 0x3 },    /* GSC gates */
1217         { GATE_IP_GSCL1, 0xc0, 0xc0 },  /* GSC gates */
1218         { SRC_TOP5, 0, BIT(28) },       /* MUX mout_user_aclk300_gscl */
1219         { DIV2_RATIO0, 0, 0x30 },       /* DIV dout_gscl_blk_300 */
1220 };
1221
1222 static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = {
1223         DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
1224 };
1225
1226 static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = {
1227         GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
1228         GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
1229         GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
1230 };
1231
1232 static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = {
1233         { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */
1234         { SRC_TOP4, 0, BIT(28) },               /* MUX mout_user_aclk333 */
1235         { DIV4_RATIO, 0, 0x3 },                 /* DIV dout_mfc_blk */
1236 };
1237
1238 static const struct exynos5_subcmu_info exynos5x_subcmus[] = {
1239         {
1240                 .div_clks       = exynos5x_disp_div_clks,
1241                 .nr_div_clks    = ARRAY_SIZE(exynos5x_disp_div_clks),
1242                 .gate_clks      = exynos5x_disp_gate_clks,
1243                 .nr_gate_clks   = ARRAY_SIZE(exynos5x_disp_gate_clks),
1244                 .suspend_regs   = exynos5x_disp_suspend_regs,
1245                 .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs),
1246                 .pd_name        = "DISP",
1247         }, {
1248                 .div_clks       = exynos5x_gsc_div_clks,
1249                 .nr_div_clks    = ARRAY_SIZE(exynos5x_gsc_div_clks),
1250                 .gate_clks      = exynos5x_gsc_gate_clks,
1251                 .nr_gate_clks   = ARRAY_SIZE(exynos5x_gsc_gate_clks),
1252                 .suspend_regs   = exynos5x_gsc_suspend_regs,
1253                 .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs),
1254                 .pd_name        = "GSC",
1255         }, {
1256                 .div_clks       = exynos5x_mfc_div_clks,
1257                 .nr_div_clks    = ARRAY_SIZE(exynos5x_mfc_div_clks),
1258                 .gate_clks      = exynos5x_mfc_gate_clks,
1259                 .nr_gate_clks   = ARRAY_SIZE(exynos5x_mfc_gate_clks),
1260                 .suspend_regs   = exynos5x_mfc_suspend_regs,
1261                 .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs),
1262                 .pd_name        = "MFC",
1263         },
1264 };
1265
1266 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
1267         PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1268         PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1269         PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1270         PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1271         PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1272         PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1273         PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1274         PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1275         PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
1276         PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
1277         PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
1278         PLL_35XX_RATE(24 * MHZ, 900000000,  150, 2, 1),
1279         PLL_35XX_RATE(24 * MHZ, 800000000,  200, 3, 1),
1280         PLL_35XX_RATE(24 * MHZ, 700000000,  175, 3, 1),
1281         PLL_35XX_RATE(24 * MHZ, 600000000,  200, 2, 2),
1282         PLL_35XX_RATE(24 * MHZ, 500000000,  250, 3, 2),
1283         PLL_35XX_RATE(24 * MHZ, 400000000,  200, 3, 2),
1284         PLL_35XX_RATE(24 * MHZ, 300000000,  200, 2, 3),
1285         PLL_35XX_RATE(24 * MHZ, 200000000,  200, 3, 3),
1286 };
1287
1288 static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
1289         PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
1290         PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
1291         PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
1292         PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671),
1293         PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
1294         PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
1295         PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671),
1296         PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719),
1297         PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
1298         PLL_36XX_RATE(24 * MHZ,  73728000U, 98, 2, 4, 19923),
1299         PLL_36XX_RATE(24 * MHZ,  67737602U, 90, 2, 4, 20762),
1300         PLL_36XX_RATE(24 * MHZ,  65536003U, 131, 3, 4, 4719),
1301         PLL_36XX_RATE(24 * MHZ,  49152000U, 197, 3, 5, -25690),
1302         PLL_36XX_RATE(24 * MHZ,  45158401U, 90, 3, 4, 20762),
1303         PLL_36XX_RATE(24 * MHZ,  32768001U, 131, 3, 5, 4719),
1304 };
1305
1306 static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
1307         [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
1308                 APLL_CON0, NULL),
1309         [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
1310                 CPLL_CON0, NULL),
1311         [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
1312                 DPLL_CON0, NULL),
1313         [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
1314                 EPLL_CON0, NULL),
1315         [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
1316                 RPLL_CON0, NULL),
1317         [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
1318                 IPLL_CON0, NULL),
1319         [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
1320                 SPLL_CON0, NULL),
1321         [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
1322                 VPLL_CON0, NULL),
1323         [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
1324                 MPLL_CON0, NULL),
1325         [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
1326                 BPLL_CON0, NULL),
1327         [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
1328                 KPLL_CON0, NULL),
1329 };
1330
1331 #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud)                       \
1332                 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
1333                  ((cpud) << 4)))
1334
1335 static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
1336         { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
1337         { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
1338         { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
1339         { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
1340         { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
1341         { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
1342         { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
1343         { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
1344         { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
1345         {  900000, E5420_EGL_DIV0(3, 6, 6, 2), },
1346         {  800000, E5420_EGL_DIV0(3, 5, 5, 2), },
1347         {  700000, E5420_EGL_DIV0(3, 5, 5, 2), },
1348         {  600000, E5420_EGL_DIV0(3, 4, 4, 2), },
1349         {  500000, E5420_EGL_DIV0(3, 3, 3, 2), },
1350         {  400000, E5420_EGL_DIV0(3, 3, 3, 2), },
1351         {  300000, E5420_EGL_DIV0(3, 3, 3, 2), },
1352         {  200000, E5420_EGL_DIV0(3, 3, 3, 2), },
1353         {  0 },
1354 };
1355
1356 static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
1357         { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
1358         { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
1359         { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
1360         { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
1361         { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
1362         { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
1363         { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
1364         { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
1365         { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
1366         { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
1367         { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
1368         {  900000, E5420_EGL_DIV0(3, 7, 6, 2), },
1369         {  800000, E5420_EGL_DIV0(3, 7, 5, 2), },
1370         {  700000, E5420_EGL_DIV0(3, 7, 5, 2), },
1371         {  600000, E5420_EGL_DIV0(3, 7, 4, 2), },
1372         {  500000, E5420_EGL_DIV0(3, 7, 3, 2), },
1373         {  400000, E5420_EGL_DIV0(3, 7, 3, 2), },
1374         {  300000, E5420_EGL_DIV0(3, 7, 3, 2), },
1375         {  200000, E5420_EGL_DIV0(3, 7, 3, 2), },
1376         {  0 },
1377 };
1378
1379 #define E5420_KFC_DIV(kpll, pclk, aclk)                                 \
1380                 ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
1381
1382 static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
1383         { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
1384         { 1300000, E5420_KFC_DIV(3, 5, 2), },
1385         { 1200000, E5420_KFC_DIV(3, 5, 2), },
1386         { 1100000, E5420_KFC_DIV(3, 5, 2), },
1387         { 1000000, E5420_KFC_DIV(3, 5, 2), },
1388         {  900000, E5420_KFC_DIV(3, 5, 2), },
1389         {  800000, E5420_KFC_DIV(3, 5, 2), },
1390         {  700000, E5420_KFC_DIV(3, 4, 2), },
1391         {  600000, E5420_KFC_DIV(3, 4, 2), },
1392         {  500000, E5420_KFC_DIV(3, 4, 2), },
1393         {  400000, E5420_KFC_DIV(3, 3, 2), },
1394         {  300000, E5420_KFC_DIV(3, 3, 2), },
1395         {  200000, E5420_KFC_DIV(3, 3, 2), },
1396         {  0 },
1397 };
1398
1399 static const struct of_device_id ext_clk_match[] __initconst = {
1400         { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
1401         { },
1402 };
1403
1404 /* register exynos5420 clocks */
1405 static void __init exynos5x_clk_init(struct device_node *np,
1406                 enum exynos5x_soc soc)
1407 {
1408         struct samsung_clk_provider *ctx;
1409
1410         if (np) {
1411                 reg_base = of_iomap(np, 0);
1412                 if (!reg_base)
1413                         panic("%s: failed to map registers\n", __func__);
1414         } else {
1415                 panic("%s: unable to determine soc\n", __func__);
1416         }
1417
1418         exynos5x_soc = soc;
1419
1420         ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1421
1422         samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1423                         ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
1424                         ext_clk_match);
1425
1426         if (_get_rate("fin_pll") == 24 * MHZ) {
1427                 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1428                 exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
1429                 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1430                 exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1431         }
1432
1433         samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
1434                                         reg_base);
1435         samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
1436                         ARRAY_SIZE(exynos5x_fixed_rate_clks));
1437         samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
1438                         ARRAY_SIZE(exynos5x_fixed_factor_clks));
1439         samsung_clk_register_mux(ctx, exynos5x_mux_clks,
1440                         ARRAY_SIZE(exynos5x_mux_clks));
1441         samsung_clk_register_div(ctx, exynos5x_div_clks,
1442                         ARRAY_SIZE(exynos5x_div_clks));
1443         samsung_clk_register_gate(ctx, exynos5x_gate_clks,
1444                         ARRAY_SIZE(exynos5x_gate_clks));
1445
1446         if (soc == EXYNOS5420) {
1447                 samsung_clk_register_mux(ctx, exynos5420_mux_clks,
1448                                 ARRAY_SIZE(exynos5420_mux_clks));
1449                 samsung_clk_register_div(ctx, exynos5420_div_clks,
1450                                 ARRAY_SIZE(exynos5420_div_clks));
1451                 samsung_clk_register_gate(ctx, exynos5420_gate_clks,
1452                                 ARRAY_SIZE(exynos5420_gate_clks));
1453         } else {
1454                 samsung_clk_register_fixed_factor(
1455                                 ctx, exynos5800_fixed_factor_clks,
1456                                 ARRAY_SIZE(exynos5800_fixed_factor_clks));
1457                 samsung_clk_register_mux(ctx, exynos5800_mux_clks,
1458                                 ARRAY_SIZE(exynos5800_mux_clks));
1459                 samsung_clk_register_div(ctx, exynos5800_div_clks,
1460                                 ARRAY_SIZE(exynos5800_div_clks));
1461                 samsung_clk_register_gate(ctx, exynos5800_gate_clks,
1462                                 ARRAY_SIZE(exynos5800_gate_clks));
1463         }
1464
1465         if (soc == EXYNOS5420) {
1466                 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1467                         mout_cpu_p[0], mout_cpu_p[1], 0x200,
1468                         exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
1469         } else {
1470                 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1471                         mout_cpu_p[0], mout_cpu_p[1], 0x200,
1472                         exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
1473         }
1474         exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
1475                 mout_kfc_p[0], mout_kfc_p[1], 0x28200,
1476                 exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
1477
1478         samsung_clk_extended_sleep_init(reg_base,
1479                 exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs),
1480                 exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc));
1481         if (soc == EXYNOS5800)
1482                 samsung_clk_sleep_init(reg_base, exynos5800_clk_regs,
1483                                        ARRAY_SIZE(exynos5800_clk_regs));
1484         exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
1485                              exynos5x_subcmus);
1486
1487         samsung_clk_of_add_provider(np, ctx);
1488 }
1489
1490 static void __init exynos5420_clk_init(struct device_node *np)
1491 {
1492         exynos5x_clk_init(np, EXYNOS5420);
1493 }
1494 CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock",
1495                       exynos5420_clk_init);
1496
1497 static void __init exynos5800_clk_init(struct device_node *np)
1498 {
1499         exynos5x_clk_init(np, EXYNOS5800);
1500 }
1501 CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock",
1502                       exynos5800_clk_init);