drivers/clk/samsung/clk-exynos5420.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   4  * Authors: Thomas Abraham <thomas.ab@samsung.com>
   5  *          Chander Kashyap <k.chander@samsung.com>
   6  *
   7  * Common Clock Framework support for Exynos5420 SoC.
   8 */
   9
  10 #include <dt-bindings/clock/exynos5420.h>
  11 #include <linux/slab.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/of.h>
  14 #include <linux/of_address.h>
  15
  16 #include "clk.h"
  17 #include "clk-cpu.h"
  18 #include "clk-exynos5-subcmu.h"
  19
  20 #define APLL_LOCK               0x0
  21 #define APLL_CON0               0x100
  22 #define SRC_CPU                 0x200
  23 #define DIV_CPU0                0x500
  24 #define DIV_CPU1                0x504
  25 #define GATE_BUS_CPU            0x700
  26 #define GATE_SCLK_CPU           0x800
  27 #define CLKOUT_CMU_CPU          0xa00
  28 #define SRC_MASK_CPERI          0x4300
  29 #define GATE_IP_G2D             0x8800
  30 #define CPLL_LOCK               0x10020
  31 #define DPLL_LOCK               0x10030
  32 #define EPLL_LOCK               0x10040
  33 #define RPLL_LOCK               0x10050
  34 #define IPLL_LOCK               0x10060
  35 #define SPLL_LOCK               0x10070
  36 #define VPLL_LOCK               0x10080
  37 #define MPLL_LOCK               0x10090
  38 #define CPLL_CON0               0x10120
  39 #define DPLL_CON0               0x10128
  40 #define EPLL_CON0               0x10130
  41 #define EPLL_CON1               0x10134
  42 #define EPLL_CON2               0x10138
  43 #define RPLL_CON0               0x10140
  44 #define RPLL_CON1               0x10144
  45 #define RPLL_CON2               0x10148
  46 #define IPLL_CON0               0x10150
  47 #define SPLL_CON0               0x10160
  48 #define VPLL_CON0               0x10170
  49 #define MPLL_CON0               0x10180
  50 #define SRC_TOP0                0x10200
  51 #define SRC_TOP1                0x10204
  52 #define SRC_TOP2                0x10208
  53 #define SRC_TOP3                0x1020c
  54 #define SRC_TOP4                0x10210
  55 #define SRC_TOP5                0x10214
  56 #define SRC_TOP6                0x10218
  57 #define SRC_TOP7                0x1021c
  58 #define SRC_TOP8                0x10220 /* 5800 specific */
  59 #define SRC_TOP9                0x10224 /* 5800 specific */
  60 #define SRC_DISP10              0x1022c
  61 #define SRC_MAU                 0x10240
  62 #define SRC_FSYS                0x10244
  63 #define SRC_PERIC0              0x10250
  64 #define SRC_PERIC1              0x10254
  65 #define SRC_ISP                 0x10270
  66 #define SRC_CAM                 0x10274 /* 5800 specific */
  67 #define SRC_TOP10               0x10280
  68 #define SRC_TOP11               0x10284
  69 #define SRC_TOP12               0x10288
  70 #define SRC_TOP13               0x1028c /* 5800 specific */
  71 #define SRC_MASK_TOP0           0x10300
  72 #define SRC_MASK_TOP1           0x10304
  73 #define SRC_MASK_TOP2           0x10308
  74 #define SRC_MASK_TOP7           0x1031c
  75 #define SRC_MASK_DISP10         0x1032c
  76 #define SRC_MASK_MAU            0x10334
  77 #define SRC_MASK_FSYS           0x10340
  78 #define SRC_MASK_PERIC0         0x10350
  79 #define SRC_MASK_PERIC1         0x10354
  80 #define SRC_MASK_ISP            0x10370
  81 #define DIV_TOP0                0x10500
  82 #define DIV_TOP1                0x10504
  83 #define DIV_TOP2                0x10508
  84 #define DIV_TOP8                0x10520 /* 5800 specific */
  85 #define DIV_TOP9                0x10524 /* 5800 specific */
  86 #define DIV_DISP10              0x1052c
  87 #define DIV_MAU                 0x10544
  88 #define DIV_FSYS0               0x10548
  89 #define DIV_FSYS1               0x1054c
  90 #define DIV_FSYS2               0x10550
  91 #define DIV_PERIC0              0x10558
  92 #define DIV_PERIC1              0x1055c
  93 #define DIV_PERIC2              0x10560
  94 #define DIV_PERIC3              0x10564
  95 #define DIV_PERIC4              0x10568
  96 #define DIV_CAM                 0x10574 /* 5800 specific */
  97 #define SCLK_DIV_ISP0           0x10580
  98 #define SCLK_DIV_ISP1           0x10584
  99 #define DIV2_RATIO0             0x10590
 100 #define DIV4_RATIO              0x105a0
 101 #define GATE_BUS_TOP            0x10700
 102 #define GATE_BUS_DISP1          0x10728
 103 #define GATE_BUS_GEN            0x1073c
 104 #define GATE_BUS_FSYS0          0x10740
 105 #define GATE_BUS_FSYS2          0x10748
 106 #define GATE_BUS_PERIC          0x10750
 107 #define GATE_BUS_PERIC1         0x10754
 108 #define GATE_BUS_PERIS0         0x10760
 109 #define GATE_BUS_PERIS1         0x10764
 110 #define GATE_BUS_NOC            0x10770
 111 #define GATE_TOP_SCLK_ISP       0x10870
 112 #define GATE_IP_GSCL0           0x10910
 113 #define GATE_IP_GSCL1           0x10920
 114 #define GATE_IP_CAM             0x10924 /* 5800 specific */
 115 #define GATE_IP_MFC             0x1092c
 116 #define GATE_IP_DISP1           0x10928
 117 #define GATE_IP_G3D             0x10930
 118 #define GATE_IP_GEN             0x10934
 119 #define GATE_IP_FSYS            0x10944
 120 #define GATE_IP_PERIC           0x10950
 121 #define GATE_IP_PERIS           0x10960
 122 #define GATE_IP_MSCL            0x10970
 123 #define GATE_TOP_SCLK_GSCL      0x10820
 124 #define GATE_TOP_SCLK_DISP1     0x10828
 125 #define GATE_TOP_SCLK_MAU       0x1083c
 126 #define GATE_TOP_SCLK_FSYS      0x10840
 127 #define GATE_TOP_SCLK_PERIC     0x10850
 128 #define TOP_SPARE2              0x10b08
 129 #define BPLL_LOCK               0x20010
 130 #define BPLL_CON0               0x20110
 131 #define SRC_CDREX               0x20200
 132 #define DIV_CDREX0              0x20500
 133 #define DIV_CDREX1              0x20504
 134 #define GATE_BUS_CDREX0         0x20700
 135 #define GATE_BUS_CDREX1         0x20704
 136 #define KPLL_LOCK               0x28000
 137 #define KPLL_CON0               0x28100
 138 #define SRC_KFC                 0x28200
 139 #define DIV_KFC0                0x28500
 140
 141 /* Exynos5x SoC type */
 142 enum exynos5x_soc {
 143         EXYNOS5420,
 144         EXYNOS5800,
 145 };
 146
 147 /* list of PLLs */
 148 enum exynos5x_plls {
 149         apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
 150         bpll, kpll,
 151         nr_plls                 /* number of PLLs */
 152 };
 153
 154 static void __iomem *reg_base;
 155 static enum exynos5x_soc exynos5x_soc;
 156
 157 /*
 158  * list of controller registers to be saved and restored during a
 159  * suspend/resume cycle.
 160  */
 161 static const unsigned long exynos5x_clk_regs[] __initconst = {
 162         SRC_CPU,
 163         DIV_CPU0,
 164         DIV_CPU1,
 165         GATE_BUS_CPU,
 166         GATE_SCLK_CPU,
 167         CLKOUT_CMU_CPU,
 168         EPLL_CON0,
 169         EPLL_CON1,
 170         EPLL_CON2,
 171         RPLL_CON0,
 172         RPLL_CON1,
 173         RPLL_CON2,
 174         SRC_TOP0,
 175         SRC_TOP1,
 176         SRC_TOP2,
 177         SRC_TOP3,
 178         SRC_TOP4,
 179         SRC_TOP5,
 180         SRC_TOP6,
 181         SRC_TOP7,
 182         SRC_DISP10,
 183         SRC_MAU,
 184         SRC_FSYS,
 185         SRC_PERIC0,
 186         SRC_PERIC1,
 187         SRC_TOP10,
 188         SRC_TOP11,
 189         SRC_TOP12,
 190         SRC_MASK_TOP2,
 191         SRC_MASK_TOP7,
 192         SRC_MASK_DISP10,
 193         SRC_MASK_FSYS,
 194         SRC_MASK_PERIC0,
 195         SRC_MASK_PERIC1,
 196         SRC_MASK_TOP0,
 197         SRC_MASK_TOP1,
 198         SRC_MASK_MAU,
 199         SRC_MASK_ISP,
 200         SRC_ISP,
 201         DIV_TOP0,
 202         DIV_TOP1,
 203         DIV_TOP2,
 204         DIV_DISP10,
 205         DIV_MAU,
 206         DIV_FSYS0,
 207         DIV_FSYS1,
 208         DIV_FSYS2,
 209         DIV_PERIC0,
 210         DIV_PERIC1,
 211         DIV_PERIC2,
 212         DIV_PERIC3,
 213         DIV_PERIC4,
 214         SCLK_DIV_ISP0,
 215         SCLK_DIV_ISP1,
 216         DIV2_RATIO0,
 217         DIV4_RATIO,
 218         GATE_BUS_DISP1,
 219         GATE_BUS_TOP,
 220         GATE_BUS_GEN,
 221         GATE_BUS_FSYS0,
 222         GATE_BUS_FSYS2,
 223         GATE_BUS_PERIC,
 224         GATE_BUS_PERIC1,
 225         GATE_BUS_PERIS0,
 226         GATE_BUS_PERIS1,
 227         GATE_BUS_NOC,
 228         GATE_TOP_SCLK_ISP,
 229         GATE_IP_GSCL0,
 230         GATE_IP_GSCL1,
 231         GATE_IP_MFC,
 232         GATE_IP_DISP1,
 233         GATE_IP_G3D,
 234         GATE_IP_GEN,
 235         GATE_IP_FSYS,
 236         GATE_IP_PERIC,
 237         GATE_IP_PERIS,
 238         GATE_IP_MSCL,
 239         GATE_TOP_SCLK_GSCL,
 240         GATE_TOP_SCLK_DISP1,
 241         GATE_TOP_SCLK_MAU,
 242         GATE_TOP_SCLK_FSYS,
 243         GATE_TOP_SCLK_PERIC,
 244         TOP_SPARE2,
 245         SRC_CDREX,
 246         DIV_CDREX0,
 247         DIV_CDREX1,
 248         SRC_KFC,
 249         DIV_KFC0,
 250         GATE_BUS_CDREX0,
 251         GATE_BUS_CDREX1,
 252 };
 253
 254 static const unsigned long exynos5800_clk_regs[] __initconst = {
 255         SRC_TOP8,
 256         SRC_TOP9,
 257         SRC_CAM,
 258         SRC_TOP1,
 259         DIV_TOP8,
 260         DIV_TOP9,
 261         DIV_CAM,
 262         GATE_IP_CAM,
 263 };
 264
 265 static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
 266         { .offset = SRC_MASK_CPERI,             .value = 0xffffffff, },
 267         { .offset = SRC_MASK_TOP0,              .value = 0x11111111, },
 268         { .offset = SRC_MASK_TOP1,              .value = 0x11101111, },
 269         { .offset = SRC_MASK_TOP2,              .value = 0x11111110, },
 270         { .offset = SRC_MASK_TOP7,              .value = 0x00111100, },
 271         { .offset = SRC_MASK_DISP10,            .value = 0x11111110, },
 272         { .offset = SRC_MASK_MAU,               .value = 0x10000000, },
 273         { .offset = SRC_MASK_FSYS,              .value = 0x11111110, },
 274         { .offset = SRC_MASK_PERIC0,            .value = 0x11111110, },
 275         { .offset = SRC_MASK_PERIC1,            .value = 0x11111100, },
 276         { .offset = SRC_MASK_ISP,               .value = 0x11111000, },
 277         { .offset = GATE_BUS_TOP,               .value = 0xffffffff, },
 278         { .offset = GATE_BUS_DISP1,             .value = 0xffffffff, },
 279         { .offset = GATE_IP_PERIC,              .value = 0xffffffff, },
 280         { .offset = GATE_IP_PERIS,              .value = 0xffffffff, },
 281 };
 282
 283 /* list of all parent clocks */
 284 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
 285                                 "mout_sclk_mpll", "mout_sclk_spll"};
 286 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
 287 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
 288 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
 289 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
 290 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
 291 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
 292 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
 293 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
 294 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
 295 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
 296 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
 297 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
 298 PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
 299
 300 PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
 301                                         "mout_sclk_mpll"};
 302 PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
 303                         "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
 304                         "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
 305 PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
 306 PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
 307 PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
 308
 309 PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
 310 PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
 311 PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
 312 PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
 313
 314 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
 315 PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
 316 PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
 317 PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
 318
 319 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
 320 PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
 321 PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
 322 PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
 323
 324 PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
 325 PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
 326 PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
 327
 328 PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
 329 PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
 330
 331 PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
 332                                         "mout_sclk_spll"};
 333 PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
 334
 335 PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
 336 PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
 337
 338 PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
 339 PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
 340
 341 PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
 342 PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
 343
 344 PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
 345 PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
 346
 347 PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
 348 PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
 349
 350 PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
 351 PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
 352 PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
 353
 354 PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
 355 PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
 356
 357 PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
 358 PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
 359
 360 PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
 361 PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
 362 PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
 363 PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
 364
 365 PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
 366 PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
 367
 368 PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
 369 PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
 370
 371 PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
 372 PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
 373
 374 PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
 375 PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
 376
 377 PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
 378                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 379                         "mout_sclk_epll", "mout_sclk_rpll"};
 380 PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
 381                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 382                         "mout_sclk_epll", "mout_sclk_rpll"};
 383 PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
 384                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 385                         "mout_sclk_epll", "mout_sclk_rpll"};
 386 PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
 387                         "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
 388                         "mout_sclk_epll", "mout_sclk_rpll"};
 389 PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
 390 PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
 391                          "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 392                          "mout_sclk_epll", "mout_sclk_rpll"};
 393 PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
 394                                 "mout_sclk_mpll", "mout_sclk_spll"};
 395 PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"};
 396
 397 /* List of parents specific to exynos5800 */
 398 PNAME(mout_epll2_5800_p)        = { "mout_sclk_epll", "ff_dout_epll2" };
 399 PNAME(mout_group1_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
 400                                 "mout_sclk_mpll", "ff_dout_spll2" };
 401 PNAME(mout_group2_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
 402                                         "mout_sclk_mpll", "ff_dout_spll2",
 403                                         "mout_epll2", "mout_sclk_ipll" };
 404 PNAME(mout_group3_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
 405                                         "mout_sclk_mpll", "ff_dout_spll2",
 406                                         "mout_epll2" };
 407 PNAME(mout_group5_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
 408                                         "mout_sclk_mpll", "mout_sclk_spll" };
 409 PNAME(mout_group6_5800_p)       = { "mout_sclk_ipll", "mout_sclk_dpll",
 410                                 "mout_sclk_mpll", "ff_dout_spll2" };
 411 PNAME(mout_group7_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
 412                                         "mout_sclk_mpll", "mout_sclk_spll",
 413                                         "mout_epll2", "mout_sclk_ipll" };
 414 PNAME(mout_mx_mspll_ccore_p)    = {"sclk_bpll", "mout_sclk_dpll",
 415                                         "mout_sclk_mpll", "ff_dout_spll2",
 416                                         "mout_sclk_spll", "mout_sclk_epll"};
 417 PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll",
 418                                         "mout_sclk_mpll",
 419                                         "ff_dout_spll2" };
 420 PNAME(mout_group8_5800_p)       = { "dout_aclk432_scaler", "dout_sclk_sw" };
 421 PNAME(mout_group9_5800_p)       = { "dout_osc_div", "mout_sw_aclk432_scaler" };
 422 PNAME(mout_group10_5800_p)      = { "dout_aclk432_cam", "dout_sclk_sw" };
 423 PNAME(mout_group11_5800_p)      = { "dout_osc_div", "mout_sw_aclk432_cam" };
 424 PNAME(mout_group12_5800_p)      = { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
 425 PNAME(mout_group13_5800_p)      = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
 426 PNAME(mout_group14_5800_p)      = { "dout_aclk550_cam", "dout_sclk_sw" };
 427 PNAME(mout_group15_5800_p)      = { "dout_osc_div", "mout_sw_aclk550_cam" };
 428 PNAME(mout_group16_5800_p)      = { "dout_osc_div", "mout_mau_epll_clk" };
 429 PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
 430                                         "mout_sclk_mpll", "ff_dout_spll2",
 431                                         "mout_sclk_spll", "mout_sclk_epll"};
 432
 433 /* fixed rate clocks generated outside the soc */
 434 static struct samsung_fixed_rate_clock
 435                 exynos5x_fixed_rate_ext_clks[] __initdata = {
 436         FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
 437 };
 438
 439 /* fixed rate clocks generated inside the soc */
 440 static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = {
 441         FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
 442         FRATE(0, "sclk_pwi", NULL, 0, 24000000),
 443         FRATE(0, "sclk_usbh20", NULL, 0, 48000000),
 444         FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000),
 445         FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000),
 446 };
 447
 448 static const struct samsung_fixed_factor_clock
 449                 exynos5x_fixed_factor_clks[] __initconst = {
 450         FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
 451         FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
 452 };
 453
 454 static const struct samsung_fixed_factor_clock
 455                 exynos5800_fixed_factor_clks[] __initconst = {
 456         FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
 457         FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
 458 };
 459
 460 static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
 461         MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
 462         MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
 463         MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
 464         MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
 465
 466         MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
 467         MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
 468         MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
 469         MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
 470         MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
 471
 472         MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
 473         MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
 474         MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
 475         MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
 476         MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
 477         MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
 478
 479         MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy",
 480                 mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),
 481
 482         MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
 483                         mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3),
 484         MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
 485                         SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
 486         MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
 487         MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
 488
 489         MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
 490         MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
 491         MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
 492         MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
 493
 494         MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
 495                         SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
 496         MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
 497                                                         SRC_TOP9, 16, 1),
 498         MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
 499                                                         SRC_TOP9, 20, 1),
 500         MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
 501                                                         SRC_TOP9, 24, 1),
 502         MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
 503                                                         SRC_TOP9, 28, 1),
 504
 505         MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
 506         MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
 507                                                         SRC_TOP13, 20, 1),
 508         MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
 509                                                         SRC_TOP13, 24, 1),
 510         MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
 511                                                         SRC_TOP13, 28, 1),
 512
 513         MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
 514 };
 515
 516 static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
 517         DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
 518                         "mout_aclk400_wcore", DIV_TOP0, 16, 3),
 519         DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
 520                                 DIV_TOP8, 16, 3),
 521         DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
 522                                 DIV_TOP8, 20, 3),
 523         DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
 524                                 DIV_TOP8, 24, 3),
 525         DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
 526                                 DIV_TOP8, 28, 3),
 527
 528         DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
 529         DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
 530 };
 531
 532 static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
 533         GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
 534                                 GATE_BUS_TOP, 24, 0, 0),
 535         GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
 536                                 GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
 537         GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",
 538                         SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
 539 };
 540
 541 static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
 542         MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
 543         MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
 544                                 TOP_SPARE2, 4, 1),
 545
 546         MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
 547         MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
 548         MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
 549         MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
 550
 551         MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
 552         MUX(0, "mout_aclk333_432_isp", mout_group4_p,
 553                                 SRC_TOP1, 4, 2),
 554         MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
 555         MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
 556         MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
 557
 558         MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
 559         MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
 560         MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
 561         MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
 562         MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
 563         MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
 564
 565         MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
 566                         mout_group5_5800_p, SRC_TOP7, 16, 2),
 567         MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
 568               CLK_SET_RATE_PARENT, 0),
 569
 570         MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
 571 };
 572
 573 static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
 574         DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
 575                         "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
 576 };
 577
 578 static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
 579         GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
 580         GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
 581                         SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
 582 };
 583
 584 static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 585         MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
 586                         SRC_TOP7, 4, 1),
 587         MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
 588         MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
 589
 590         MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
 591               CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
 592         MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
 593         MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
 594               CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
 595         MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
 596
 597         MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
 598         MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
 599         MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
 600         MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
 601
 602         MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
 603         MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
 604
 605         MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
 606
 607         MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
 608                         SRC_TOP3, 0, 1),
 609         MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
 610                         SRC_TOP3, 4, 1),
 611         MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
 612                         mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
 613         MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
 614                         SRC_TOP3, 12, 1),
 615         MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
 616                         SRC_TOP3, 16, 1),
 617         MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
 618                         SRC_TOP3, 20, 1),
 619         MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
 620                         SRC_TOP3, 24, 1),
 621         MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
 622                         SRC_TOP3, 28, 1),
 623
 624         MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
 625                         SRC_TOP4, 0, 1),
 626         MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
 627                         SRC_TOP4, 4, 1),
 628         MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
 629                         SRC_TOP4, 8, 1),
 630         MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
 631                         SRC_TOP4, 12, 1),
 632         MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
 633                         SRC_TOP4, 16, 1),
 634         MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
 635         MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
 636         MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
 637                         SRC_TOP4, 28, 1),
 638
 639         MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
 640                         mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
 641         MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
 642                         SRC_TOP5, 4, 1),
 643         MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
 644                         SRC_TOP5, 8, 1),
 645         MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
 646                         SRC_TOP5, 12, 1),
 647         MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
 648                         SRC_TOP5, 16, 1),
 649         MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
 650                         SRC_TOP5, 20, 1),
 651         MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
 652                         mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
 653         MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
 654                         mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
 655
 656         MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
 657         MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
 658         MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
 659         MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
 660         MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
 661         MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
 662                         CLK_SET_RATE_PARENT, 0),
 663         MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
 664         MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
 665
 666         MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
 667                         SRC_TOP10, 0, 1),
 668         MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
 669                         SRC_TOP10, 4, 1),
 670         MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
 671                         SRC_TOP10, 8, 1),
 672         MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
 673                         SRC_TOP10, 12, 1),
 674         MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
 675                         SRC_TOP10, 16, 1),
 676         MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
 677                         SRC_TOP10, 20, 1),
 678         MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
 679                         SRC_TOP10, 24, 1),
 680         MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
 681                         SRC_TOP10, 28, 1),
 682
 683         MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
 684                         SRC_TOP11, 0, 1),
 685         MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
 686                         SRC_TOP11, 4, 1),
 687         MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
 688         MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
 689                         SRC_TOP11, 12, 1),
 690         MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
 691         MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
 692         MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
 693                         SRC_TOP11, 28, 1),
 694
 695         MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
 696                         mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
 697         MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
 698                         SRC_TOP12, 8, 1),
 699         MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
 700                         SRC_TOP12, 12, 1),
 701         MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
 702         MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
 703                         SRC_TOP12, 20, 1),
 704         MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
 705                         mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
 706         MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",
 707                         mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
 708
 709         /* DISP1 Block */
 710         MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
 711         MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
 712         MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
 713         MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
 714         MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
 715
 716         MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
 717
 718         /* CDREX block */
 719         MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p,
 720                         SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0),
 721         MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1,
 722                         CLK_SET_RATE_PARENT, 0),
 723
 724         /* MAU Block */
 725         MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
 726
 727         /* FSYS Block */
 728         MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
 729         MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
 730         MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
 731         MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
 732         MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
 733         MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
 734         MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
 735
 736         /* PERIC Block */
 737         MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
 738         MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
 739         MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
 740         MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
 741         MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
 742         MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
 743         MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
 744         MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
 745         MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
 746         MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
 747         MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
 748         MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
 749
 750         /* ISP Block */
 751         MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
 752         MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
 753         MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
 754         MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
 755         MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
 756 };
 757
 758 static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
 759         DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
 760         DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
 761         DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
 762         DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
 763         DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
 764
 765         DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp",
 766                         DIV_TOP0, 0, 3),
 767         DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl",
 768                         DIV_TOP0, 4, 3),
 769         DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200",
 770                         DIV_TOP0, 8, 3),
 771         DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
 772                         DIV_TOP0, 12, 3),
 773         DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
 774                         DIV_TOP0, 20, 3),
 775         DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
 776                         DIV_TOP0, 24, 3),
 777         DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
 778                         DIV_TOP0, 28, 3),
 779         DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl",
 780                         "mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
 781         DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp",
 782                         "mout_aclk333_432_isp", DIV_TOP1, 4, 3),
 783         DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66",
 784                         DIV_TOP1, 8, 6),
 785         DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0",
 786                         "mout_aclk333_432_isp0", DIV_TOP1, 16, 3),
 787         DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266",
 788                         DIV_TOP1, 20, 3),
 789         DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166",
 790                         DIV_TOP1, 24, 3),
 791         DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333",
 792                         DIV_TOP1, 28, 3),
 793
 794         DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d",
 795                         DIV_TOP2, 8, 3),
 796         DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
 797                         DIV_TOP2, 12, 3),
 798         DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
 799                         16, 3),
 800         DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
 801                         DIV_TOP2, 20, 3),
 802         DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
 803                         "mout_aclk300_disp1", DIV_TOP2, 24, 3),
 804         DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl",
 805                         DIV_TOP2, 28, 3),
 806
 807         /* DISP1 Block */
 808         DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
 809         DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
 810         DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
 811         DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
 812         DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1",
 813                         "mout_aclk400_disp1", DIV_TOP2, 4, 3),
 814
 815         /* CDREX Block */
 816         /*
 817          * The three clocks below are controlled using the same register and
 818          * bits. They are put into one because there is a need of
 819          * synchronization between the BUS and DREXs (two external memory
 820          * interfaces).
 821          * They are put here to show this HW assumption and for clock
 822          * information summary completeness.
 823          */
 824         DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
 825                         DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
 826         DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0",
 827                         DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
 828         DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0",
 829                         DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
 830
 831         DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex",
 832                         DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0),
 833         DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0",
 834                         DIV_CDREX0, 16, 3),
 835         DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0",
 836                         DIV_CDREX0, 8, 3),
 837         DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex",
 838                         DIV_CDREX0, 3, 5),
 839
 840         DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex",
 841                         DIV_CDREX1, 8, 3),
 842
 843         /* Audio Block */
 844         DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
 845         DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
 846
 847         /* USB3.0 */
 848         DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
 849         DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
 850         DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
 851         DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
 852
 853         /* MMC */
 854         DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
 855         DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
 856         DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
 857
 858         DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
 859         DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
 860
 861         /* UART and PWM */
 862         DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
 863         DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
 864         DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
 865         DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
 866         DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
 867
 868         /* SPI */
 869         DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
 870         DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
 871         DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
 872
 873
 874         /* PCM */
 875         DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
 876         DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
 877
 878         /* Audio - I2S */
 879         DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
 880         DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
 881         DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
 882         DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
 883         DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
 884
 885         /* SPI Pre-Ratio */
 886         DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
 887         DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
 888         DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
 889
 890         /* GSCL Block */
 891         DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
 892
 893         /* MSCL Block */
 894         DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
 895
 896         /* PSGEN */
 897         DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
 898         DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
 899
 900         /* ISP Block */
 901         DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
 902         DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
 903         DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
 904         DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
 905         DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
 906         DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
 907         DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
 908         DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
 909                         CLK_SET_RATE_PARENT, 0),
 910         DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
 911                         CLK_SET_RATE_PARENT, 0),
 912 };
 913
 914 static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
 915         /* G2D */
 916         GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
 917         GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
 918         GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
 919         GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
 920         GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
 921
 922         GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
 923                         GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0),
 924         GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
 925                         GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
 926
 927         GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
 928                         GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
 929         GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
 930                         GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0),
 931         GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
 932                         GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
 933         GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
 934                         GATE_BUS_TOP, 5, 0, 0),
 935         GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
 936                         GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0),
 937         GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
 938                         GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
 939         GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
 940                         GATE_BUS_TOP, 8, 0, 0),
 941         GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
 942                         GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
 943         GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
 944                         GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
 945         GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
 946                         GATE_BUS_TOP, 13, 0, 0),
 947         GATE(0, "aclk166", "mout_user_aclk166",
 948                         GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
 949         GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
 950                         GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0),
 951         GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
 952                         GATE_BUS_TOP, 16, 0, 0),
 953         GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
 954                         GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
 955         GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
 956                         GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
 957         GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
 958                         GATE_BUS_TOP, 28, 0, 0),
 959         GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
 960                         GATE_BUS_TOP, 29, 0, 0),
 961
 962         GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
 963                         SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0),
 964
 965         /* sclk */
 966         GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
 967                 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
 968         GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
 969                 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
 970         GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
 971                 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
 972         GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
 973                 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
 974         GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
 975                 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
 976         GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
 977                 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
 978         GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
 979                 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
 980         GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
 981                 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
 982         GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
 983                 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
 984         GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
 985                 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
 986         GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
 987                 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
 988         GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
 989                 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
 990         GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
 991                 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
 992
 993         GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
 994                 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
 995         GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
 996                 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
 997         GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
 998                 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
 999         GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
1000                 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
1001         GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
1002                 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
1003         GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
1004                 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
1005         GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
1006                 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
1007
1008         /* Display */
1009         GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
1010                         GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
1011         GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
1012                         GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
1013         GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
1014                         GATE_TOP_SCLK_DISP1, 9, 0, 0),
1015         GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
1016                         GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
1017         GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
1018                         GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
1019
1020         /* Maudio Block */
1021         GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
1022                 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
1023         GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
1024                 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
1025
1026         /* FSYS Block */
1027         GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
1028         GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
1029         GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
1030         GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
1031         GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
1032         GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
1033         GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
1034         GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
1035         GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
1036                         GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
1037         GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
1038         GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
1039         GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
1040         GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
1041                         SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1042
1043         /* PERIC Block */
1044         GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
1045                         GATE_IP_PERIC, 0, 0, 0),
1046         GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
1047                         GATE_IP_PERIC, 1, 0, 0),
1048         GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
1049                         GATE_IP_PERIC, 2, 0, 0),
1050         GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
1051                         GATE_IP_PERIC, 3, 0, 0),
1052         GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
1053                         GATE_IP_PERIC, 6, 0, 0),
1054         GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
1055                         GATE_IP_PERIC, 7, 0, 0),
1056         GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",
1057                         GATE_IP_PERIC, 8, 0, 0),
1058         GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",
1059                         GATE_IP_PERIC, 9, 0, 0),
1060         GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",
1061                         GATE_IP_PERIC, 10, 0, 0),
1062         GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",
1063                         GATE_IP_PERIC, 11, 0, 0),
1064         GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",
1065                         GATE_IP_PERIC, 12, 0, 0),
1066         GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",
1067                         GATE_IP_PERIC, 13, 0, 0),
1068         GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",
1069                         GATE_IP_PERIC, 14, 0, 0),
1070         GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
1071                         GATE_IP_PERIC, 15, 0, 0),
1072         GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
1073                         GATE_IP_PERIC, 16, 0, 0),
1074         GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
1075                         GATE_IP_PERIC, 17, 0, 0),
1076         GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",
1077                         GATE_IP_PERIC, 18, 0, 0),
1078         GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",
1079                         GATE_IP_PERIC, 20, 0, 0),
1080         GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
1081                         GATE_IP_PERIC, 21, 0, 0),
1082         GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",
1083                         GATE_IP_PERIC, 22, 0, 0),
1084         GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",
1085                         GATE_IP_PERIC, 23, 0, 0),
1086         GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
1087                         GATE_IP_PERIC, 24, 0, 0),
1088         GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",
1089                         GATE_IP_PERIC, 26, 0, 0),
1090         GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",
1091                         GATE_IP_PERIC, 28, 0, 0),
1092         GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",
1093                         GATE_IP_PERIC, 30, 0, 0),
1094         GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",
1095                         GATE_IP_PERIC, 31, 0, 0),
1096
1097         GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",
1098                         GATE_BUS_PERIC, 22, 0, 0),
1099
1100         /* PERIS Block */
1101         GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
1102                         GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1103         GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
1104                         GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1105         GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
1106         GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
1107         GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
1108         GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
1109         GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
1110         GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
1111         GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
1112         GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
1113         GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
1114         GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
1115         GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
1116         GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
1117         GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
1118         GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
1119         GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
1120         GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
1121
1122         /* GEN Block */
1123         GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
1124         GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
1125         GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
1126         GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
1127         GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
1128         GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
1129                         GATE_IP_GEN, 6, 0, 0),
1130         GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
1131         GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
1132                         GATE_IP_GEN, 9, 0, 0),
1133
1134         /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
1135         GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
1136                         GATE_BUS_GEN, 28, 0, 0),
1137         GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
1138
1139         /* GSCL Block */
1140         GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
1141                         GATE_TOP_SCLK_GSCL, 6, 0, 0),
1142         GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
1143                         GATE_TOP_SCLK_GSCL, 7, 0, 0),
1144
1145         GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
1146                         GATE_IP_GSCL0, 4, 0, 0),
1147         GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
1148                         GATE_IP_GSCL0, 5, 0, 0),
1149         GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
1150                         GATE_IP_GSCL0, 6, 0, 0),
1151
1152         GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
1153                         GATE_IP_GSCL1, 2, 0, 0),
1154         GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
1155                         GATE_IP_GSCL1, 3, 0, 0),
1156         GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
1157                         GATE_IP_GSCL1, 4, 0, 0),
1158         GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0),
1159         GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0),
1160         GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
1161                         GATE_IP_GSCL1, 16, 0, 0),
1162         GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
1163                         GATE_IP_GSCL1, 17, 0, 0),
1164
1165         /* MSCL Block */
1166         GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
1167         GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
1168         GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
1169         GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
1170                         GATE_IP_MSCL, 8, 0, 0),
1171         GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
1172                         GATE_IP_MSCL, 9, 0, 0),
1173         GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
1174                         GATE_IP_MSCL, 10, 0, 0),
1175
1176         /* ISP */
1177         GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
1178                         GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
1179         GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
1180                         GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
1181         GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
1182                         GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
1183         GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
1184                         GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
1185         GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
1186                         GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
1187         GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
1188                         GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1189         GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
1190                         GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
1191
1192         GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
1193
1194         /* CDREX */
1195         GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",
1196                         GATE_BUS_CDREX0, 0, 0, 0),
1197         GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex",
1198                         GATE_BUS_CDREX0, 1, 0, 0),
1199         GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy",
1200                         SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0),
1201
1202         GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1",
1203                         GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0),
1204         GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1",
1205                         GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0),
1206         GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1",
1207                         GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0),
1208         GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1",
1209                         GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0),
1210
1211         GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex",
1212                         GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0),
1213         GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex",
1214                         GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0),
1215         GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex",
1216                         GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0),
1217         GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex",
1218                         GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0),
1219 };
1220
1221 static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = {
1222         DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
1223 };
1224
1225 static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = {
1226         GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
1227         GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
1228         GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
1229         GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
1230         GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
1231         GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
1232                         GATE_IP_DISP1, 7, 0, 0),
1233         GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
1234                         GATE_IP_DISP1, 8, 0, 0),
1235         GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
1236                         GATE_IP_DISP1, 9, 0, 0),
1237 };
1238
1239 static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = {
1240         { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
1241         { SRC_TOP5, 0, BIT(0) },        /* MUX mout_user_aclk400_disp1 */
1242         { SRC_TOP5, 0, BIT(24) },       /* MUX mout_user_aclk300_disp1 */
1243         { SRC_TOP3, 0, BIT(8) },        /* MUX mout_user_aclk200_disp1 */
1244         { DIV2_RATIO0, 0, 0x30000 },            /* DIV dout_disp1_blk */
1245 };
1246
1247 static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = {
1248         DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
1249                         DIV2_RATIO0, 4, 2),
1250 };
1251
1252 static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = {
1253         GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
1254         GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
1255         GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
1256                         GATE_IP_GSCL1, 6, 0, 0),
1257         GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
1258                         GATE_IP_GSCL1, 7, 0, 0),
1259 };
1260
1261 static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
1262         { GATE_IP_GSCL0, 0x3, 0x3 },    /* GSC gates */
1263         { GATE_IP_GSCL1, 0xc0, 0xc0 },  /* GSC gates */
1264         { SRC_TOP5, 0, BIT(28) },       /* MUX mout_user_aclk300_gscl */
1265         { DIV2_RATIO0, 0, 0x30 },       /* DIV dout_gscl_blk_300 */
1266 };
1267
1268 static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = {
1269         DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
1270 };
1271
1272 static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = {
1273         GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
1274         GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
1275         GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
1276 };
1277
1278 static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = {
1279         { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */
1280         { SRC_TOP4, 0, BIT(28) },               /* MUX mout_user_aclk333 */
1281         { DIV4_RATIO, 0, 0x3 },                 /* DIV dout_mfc_blk */
1282 };
1283
1284 static const struct exynos5_subcmu_info exynos5x_subcmus[] = {
1285         {
1286                 .div_clks       = exynos5x_disp_div_clks,
1287                 .nr_div_clks    = ARRAY_SIZE(exynos5x_disp_div_clks),
1288                 .gate_clks      = exynos5x_disp_gate_clks,
1289                 .nr_gate_clks   = ARRAY_SIZE(exynos5x_disp_gate_clks),
1290                 .suspend_regs   = exynos5x_disp_suspend_regs,
1291                 .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs),
1292                 .pd_name        = "DISP",
1293         }, {
1294                 .div_clks       = exynos5x_gsc_div_clks,
1295                 .nr_div_clks    = ARRAY_SIZE(exynos5x_gsc_div_clks),
1296                 .gate_clks      = exynos5x_gsc_gate_clks,
1297                 .nr_gate_clks   = ARRAY_SIZE(exynos5x_gsc_gate_clks),
1298                 .suspend_regs   = exynos5x_gsc_suspend_regs,
1299                 .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs),
1300                 .pd_name        = "GSC",
1301         }, {
1302                 .div_clks       = exynos5x_mfc_div_clks,
1303                 .nr_div_clks    = ARRAY_SIZE(exynos5x_mfc_div_clks),
1304                 .gate_clks      = exynos5x_mfc_gate_clks,
1305                 .nr_gate_clks   = ARRAY_SIZE(exynos5x_mfc_gate_clks),
1306                 .suspend_regs   = exynos5x_mfc_suspend_regs,
1307                 .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs),
1308                 .pd_name        = "MFC",
1309         },
1310 };
1311
1312 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
1313         PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1314         PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1315         PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1316         PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1317         PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1318         PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1319         PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1320         PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1321         PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
1322         PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
1323         PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
1324         PLL_35XX_RATE(24 * MHZ, 900000000,  150, 2, 1),
1325         PLL_35XX_RATE(24 * MHZ, 800000000,  200, 3, 1),
1326         PLL_35XX_RATE(24 * MHZ, 700000000,  175, 3, 1),
1327         PLL_35XX_RATE(24 * MHZ, 600000000,  200, 2, 2),
1328         PLL_35XX_RATE(24 * MHZ, 500000000,  250, 3, 2),
1329         PLL_35XX_RATE(24 * MHZ, 400000000,  200, 3, 2),
1330         PLL_35XX_RATE(24 * MHZ, 300000000,  200, 2, 3),
1331         PLL_35XX_RATE(24 * MHZ, 200000000,  200, 3, 3),
1332 };
1333
1334 static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = {
1335         PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
1336         PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
1337         PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
1338         PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
1339         PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
1340         PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
1341         PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
1342         PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),
1343 };
1344
1345 static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
1346         PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
1347         PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
1348         PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
1349         PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671),
1350         PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
1351         PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
1352         PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671),
1353         PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719),
1354         PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
1355         PLL_36XX_RATE(24 * MHZ,  73728000U, 98, 2, 4, 19923),
1356         PLL_36XX_RATE(24 * MHZ,  67737602U, 90, 2, 4, 20762),
1357         PLL_36XX_RATE(24 * MHZ,  65536003U, 131, 3, 4, 4719),
1358         PLL_36XX_RATE(24 * MHZ,  49152000U, 197, 3, 5, -25690),
1359         PLL_36XX_RATE(24 * MHZ,  45158401U, 90, 3, 4, 20762),
1360         PLL_36XX_RATE(24 * MHZ,  32768001U, 131, 3, 5, 4719),
1361 };
1362
1363 static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
1364         [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
1365                 APLL_CON0, NULL),
1366         [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
1367                 CPLL_CON0, NULL),
1368         [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
1369                 DPLL_CON0, NULL),
1370         [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
1371                 EPLL_CON0, NULL),
1372         [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
1373                 RPLL_CON0, NULL),
1374         [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
1375                 IPLL_CON0, NULL),
1376         [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
1377                 SPLL_CON0, NULL),
1378         [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
1379                 VPLL_CON0, NULL),
1380         [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
1381                 MPLL_CON0, NULL),
1382         [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
1383                 BPLL_CON0, NULL),
1384         [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
1385                 KPLL_CON0, NULL),
1386 };
1387
1388 #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud)                       \
1389                 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
1390                  ((cpud) << 4)))
1391
1392 static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
1393         { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
1394         { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
1395         { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
1396         { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
1397         { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
1398         { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
1399         { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
1400         { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
1401         { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
1402         {  900000, E5420_EGL_DIV0(3, 6, 6, 2), },
1403         {  800000, E5420_EGL_DIV0(3, 5, 5, 2), },
1404         {  700000, E5420_EGL_DIV0(3, 5, 5, 2), },
1405         {  600000, E5420_EGL_DIV0(3, 4, 4, 2), },
1406         {  500000, E5420_EGL_DIV0(3, 3, 3, 2), },
1407         {  400000, E5420_EGL_DIV0(3, 3, 3, 2), },
1408         {  300000, E5420_EGL_DIV0(3, 3, 3, 2), },
1409         {  200000, E5420_EGL_DIV0(3, 3, 3, 2), },
1410         {  0 },
1411 };
1412
1413 static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
1414         { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
1415         { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
1416         { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
1417         { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
1418         { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
1419         { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
1420         { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
1421         { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
1422         { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
1423         { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
1424         { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
1425         {  900000, E5420_EGL_DIV0(3, 7, 6, 2), },
1426         {  800000, E5420_EGL_DIV0(3, 7, 5, 2), },
1427         {  700000, E5420_EGL_DIV0(3, 7, 5, 2), },
1428         {  600000, E5420_EGL_DIV0(3, 7, 4, 2), },
1429         {  500000, E5420_EGL_DIV0(3, 7, 3, 2), },
1430         {  400000, E5420_EGL_DIV0(3, 7, 3, 2), },
1431         {  300000, E5420_EGL_DIV0(3, 7, 3, 2), },
1432         {  200000, E5420_EGL_DIV0(3, 7, 3, 2), },
1433         {  0 },
1434 };
1435
1436 #define E5420_KFC_DIV(kpll, pclk, aclk)                                 \
1437                 ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
1438
1439 static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
1440         { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
1441         { 1300000, E5420_KFC_DIV(3, 5, 2), },
1442         { 1200000, E5420_KFC_DIV(3, 5, 2), },
1443         { 1100000, E5420_KFC_DIV(3, 5, 2), },
1444         { 1000000, E5420_KFC_DIV(3, 5, 2), },
1445         {  900000, E5420_KFC_DIV(3, 5, 2), },
1446         {  800000, E5420_KFC_DIV(3, 5, 2), },
1447         {  700000, E5420_KFC_DIV(3, 4, 2), },
1448         {  600000, E5420_KFC_DIV(3, 4, 2), },
1449         {  500000, E5420_KFC_DIV(3, 4, 2), },
1450         {  400000, E5420_KFC_DIV(3, 3, 2), },
1451         {  300000, E5420_KFC_DIV(3, 3, 2), },
1452         {  200000, E5420_KFC_DIV(3, 3, 2), },
1453         {  0 },
1454 };
1455
1456 static const struct of_device_id ext_clk_match[] __initconst = {
1457         { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
1458         { },
1459 };
1460
1461 /* register exynos5420 clocks */
1462 static void __init exynos5x_clk_init(struct device_node *np,
1463                 enum exynos5x_soc soc)
1464 {
1465         struct samsung_clk_provider *ctx;
1466
1467         if (np) {
1468                 reg_base = of_iomap(np, 0);
1469                 if (!reg_base)
1470                         panic("%s: failed to map registers\n", __func__);
1471         } else {
1472                 panic("%s: unable to determine soc\n", __func__);
1473         }
1474
1475         exynos5x_soc = soc;
1476
1477         ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1478
1479         samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1480                         ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
1481                         ext_clk_match);
1482
1483         if (_get_rate("fin_pll") == 24 * MHZ) {
1484                 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1485                 exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
1486                 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1487         }
1488
1489         if (soc == EXYNOS5420)
1490                 exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1491         else
1492                 exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
1493
1494         samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
1495                                         reg_base);
1496         samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
1497                         ARRAY_SIZE(exynos5x_fixed_rate_clks));
1498         samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
1499                         ARRAY_SIZE(exynos5x_fixed_factor_clks));
1500         samsung_clk_register_mux(ctx, exynos5x_mux_clks,
1501                         ARRAY_SIZE(exynos5x_mux_clks));
1502         samsung_clk_register_div(ctx, exynos5x_div_clks,
1503                         ARRAY_SIZE(exynos5x_div_clks));
1504         samsung_clk_register_gate(ctx, exynos5x_gate_clks,
1505                         ARRAY_SIZE(exynos5x_gate_clks));
1506
1507         if (soc == EXYNOS5420) {
1508                 samsung_clk_register_mux(ctx, exynos5420_mux_clks,
1509                                 ARRAY_SIZE(exynos5420_mux_clks));
1510                 samsung_clk_register_div(ctx, exynos5420_div_clks,
1511                                 ARRAY_SIZE(exynos5420_div_clks));
1512                 samsung_clk_register_gate(ctx, exynos5420_gate_clks,
1513                                 ARRAY_SIZE(exynos5420_gate_clks));
1514         } else {
1515                 samsung_clk_register_fixed_factor(
1516                                 ctx, exynos5800_fixed_factor_clks,
1517                                 ARRAY_SIZE(exynos5800_fixed_factor_clks));
1518                 samsung_clk_register_mux(ctx, exynos5800_mux_clks,
1519                                 ARRAY_SIZE(exynos5800_mux_clks));
1520                 samsung_clk_register_div(ctx, exynos5800_div_clks,
1521                                 ARRAY_SIZE(exynos5800_div_clks));
1522                 samsung_clk_register_gate(ctx, exynos5800_gate_clks,
1523                                 ARRAY_SIZE(exynos5800_gate_clks));
1524         }
1525
1526         if (soc == EXYNOS5420) {
1527                 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1528                         mout_cpu_p[0], mout_cpu_p[1], 0x200,
1529                         exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
1530         } else {
1531                 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1532                         mout_cpu_p[0], mout_cpu_p[1], 0x200,
1533                         exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
1534         }
1535         exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
1536                 mout_kfc_p[0], mout_kfc_p[1], 0x28200,
1537                 exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
1538
1539         samsung_clk_extended_sleep_init(reg_base,
1540                 exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs),
1541                 exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc));
1542         if (soc == EXYNOS5800)
1543                 samsung_clk_sleep_init(reg_base, exynos5800_clk_regs,
1544                                        ARRAY_SIZE(exynos5800_clk_regs));
1545         exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
1546                              exynos5x_subcmus);
1547
1548         samsung_clk_of_add_provider(np, ctx);
1549 }
1550
1551 static void __init exynos5420_clk_init(struct device_node *np)
1552 {
1553         exynos5x_clk_init(np, EXYNOS5420);
1554 }
1555 CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock",
1556                       exynos5420_clk_init);
1557
1558 static void __init exynos5800_clk_init(struct device_node *np)
1559 {
1560         exynos5x_clk_init(np, EXYNOS5800);
1561 }
1562 CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock",
1563                       exynos5800_clk_init);