drivers/clk/samsung/clk-exynos5260.c

   1 /*
   2  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   3  * Author: Rahul Sharma <rahul.sharma@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * Common Clock Framework support for Exynos5260 SoC.
  10  */
  11
  12 #include <linux/of.h>
  13 #include <linux/of_address.h>
  14
  15 #include "clk-exynos5260.h"
  16 #include "clk.h"
  17 #include "clk-pll.h"
  18
  19 #include <dt-bindings/clock/exynos5260-clk.h>
  20
  21 /*
  22  * Applicable for all 2550 Type PLLS for Exynos5260, listed below
  23  * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
  24  */
  25 static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst = {
  26         PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
  27         PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
  28         PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
  29         PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
  30         PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
  31         PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
  32         PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
  33         PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
  34         PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
  35         PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
  36         PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
  37         PLL_35XX_RATE(24 * MHZ, 733000000, 733, 12, 1),
  38         PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
  39         PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
  40         PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
  41         PLL_35XX_RATE(24 * MHZ, 620000000, 310, 3, 2),
  42         PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2),
  43         PLL_35XX_RATE(24 * MHZ, 543000000, 362, 4, 2),
  44         PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2),
  45         PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
  46         PLL_35XX_RATE(24 * MHZ, 450000000, 300, 4, 2),
  47         PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
  48         PLL_35XX_RATE(24 * MHZ, 350000000, 175, 3, 2),
  49         PLL_35XX_RATE(24 * MHZ, 300000000, 400, 4, 3),
  50         PLL_35XX_RATE(24 * MHZ, 266000000, 266, 3, 3),
  51         PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
  52         PLL_35XX_RATE(24 * MHZ, 160000000, 160, 3, 3),
  53 };
  54
  55 /*
  56  * Applicable for 2650 Type PLL for AUD_PLL.
  57  */
  58 static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = {
  59         PLL_36XX_RATE(24 * MHZ, 1600000000, 200, 3, 0, 0),
  60         PLL_36XX_RATE(24 * MHZ, 1200000000, 100, 2, 0, 0),
  61         PLL_36XX_RATE(24 * MHZ, 1000000000, 250, 3, 1, 0),
  62         PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0),
  63         PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0),
  64         PLL_36XX_RATE(24 * MHZ, 532000000, 266, 3, 2, 0),
  65         PLL_36XX_RATE(24 * MHZ, 480000000, 160, 2, 2, 0),
  66         PLL_36XX_RATE(24 * MHZ, 432000000, 144, 2, 2, 0),
  67         PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0),
  68         PLL_36XX_RATE(24 * MHZ, 394073128, 459, 7, 2, 49282),
  69         PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0),
  70         PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0),
  71         PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
  72         PLL_36XX_RATE(24 * MHZ, 200000000, 200, 3, 3, 0),
  73         PLL_36XX_RATE(24 * MHZ, 166000000, 166, 3, 3, 0),
  74         PLL_36XX_RATE(24 * MHZ, 133000000, 266, 3, 4, 0),
  75         PLL_36XX_RATE(24 * MHZ, 100000000, 200, 3, 4, 0),
  76         PLL_36XX_RATE(24 * MHZ, 66000000, 176, 2, 5, 0),
  77 };
  78
  79 /* CMU_AUD */
  80
  81 static const unsigned long aud_clk_regs[] __initconst = {
  82         MUX_SEL_AUD,
  83         DIV_AUD0,
  84         DIV_AUD1,
  85         EN_ACLK_AUD,
  86         EN_PCLK_AUD,
  87         EN_SCLK_AUD,
  88         EN_IP_AUD,
  89 };
  90
  91 PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"};
  92 PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"};
  93 PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"};
  94
  95 static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
  96         MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p,
  97                         MUX_SEL_AUD, 0, 1),
  98         MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p,
  99                         MUX_SEL_AUD, 4, 1),
 100         MUX(AUD_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
 101                         MUX_SEL_AUD, 8, 1),
 102 };
 103
 104 static const struct samsung_div_clock aud_div_clks[] __initconst = {
 105         DIV(AUD_DOUT_ACLK_AUD_131, "dout_aclk_aud_131", "mout_aud_pll_user",
 106                         DIV_AUD0, 0, 4),
 107
 108         DIV(AUD_DOUT_SCLK_AUD_I2S, "dout_sclk_aud_i2s", "mout_sclk_aud_i2s",
 109                         DIV_AUD1, 0, 4),
 110         DIV(AUD_DOUT_SCLK_AUD_PCM, "dout_sclk_aud_pcm", "mout_sclk_aud_pcm",
 111                         DIV_AUD1, 4, 8),
 112         DIV(AUD_DOUT_SCLK_AUD_UART, "dout_sclk_aud_uart", "mout_aud_pll_user",
 113                         DIV_AUD1, 12, 4),
 114 };
 115
 116 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
 117         GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s",
 118                         EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0),
 119         GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm",
 120                         EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0),
 121         GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart",
 122                         EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0),
 123
 124         GATE(AUD_CLK_SRAMC, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD,
 125                         0, 0, 0),
 126         GATE(AUD_CLK_DMAC, "clk_dmac", "dout_aclk_aud_131",
 127                         EN_IP_AUD, 1, 0, 0),
 128         GATE(AUD_CLK_I2S, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD, 2, 0, 0),
 129         GATE(AUD_CLK_PCM, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD, 3, 0, 0),
 130         GATE(AUD_CLK_AUD_UART, "clk_aud_uart", "dout_aclk_aud_131",
 131                         EN_IP_AUD, 4, 0, 0),
 132 };
 133
 134 static const struct samsung_cmu_info aud_cmu __initconst = {
 135         .mux_clks       = aud_mux_clks,
 136         .nr_mux_clks    = ARRAY_SIZE(aud_mux_clks),
 137         .div_clks       = aud_div_clks,
 138         .nr_div_clks    = ARRAY_SIZE(aud_div_clks),
 139         .gate_clks      = aud_gate_clks,
 140         .nr_gate_clks   = ARRAY_SIZE(aud_gate_clks),
 141         .nr_clk_ids     = AUD_NR_CLK,
 142         .clk_regs       = aud_clk_regs,
 143         .nr_clk_regs    = ARRAY_SIZE(aud_clk_regs),
 144 };
 145
 146 static void __init exynos5260_clk_aud_init(struct device_node *np)
 147 {
 148         samsung_cmu_register_one(np, &aud_cmu);
 149 }
 150
 151 CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",
 152                 exynos5260_clk_aud_init);
 153
 154
 155 /* CMU_DISP */
 156
 157 static const unsigned long disp_clk_regs[] __initconst = {
 158         MUX_SEL_DISP0,
 159         MUX_SEL_DISP1,
 160         MUX_SEL_DISP2,
 161         MUX_SEL_DISP3,
 162         MUX_SEL_DISP4,
 163         DIV_DISP,
 164         EN_ACLK_DISP,
 165         EN_PCLK_DISP,
 166         EN_SCLK_DISP0,
 167         EN_SCLK_DISP1,
 168         EN_IP_DISP,
 169         EN_IP_DISP_BUS,
 170 };
 171
 172 PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll",
 173                         "phyclk_dptx_phy_ch3_txd_clk"};
 174 PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll",
 175                         "phyclk_dptx_phy_ch2_txd_clk"};
 176 PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll",
 177                         "phyclk_dptx_phy_ch1_txd_clk"};
 178 PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll",
 179                         "phyclk_dptx_phy_ch0_txd_clk"};
 180 PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"};
 181 PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"};
 182 PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"};
 183 PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll",
 184                         "phyclk_hdmi_phy_tmds_clko"};
 185 PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll",
 186                         "phyclk_hdmi_phy_ref_clko"};
 187 PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p) = {"fin_pll",
 188                         "phyclk_hdmi_phy_pixel_clko"};
 189 PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p) = {"fin_pll",
 190                         "phyclk_hdmi_link_o_tmds_clkhi"};
 191 PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p) = {"fin_pll",
 192                         "phyclk_mipi_dphy_4l_m_txbyte_clkhs"};
 193 PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p) = {"fin_pll",
 194                         "phyclk_dptx_phy_o_ref_clk_24m"};
 195 PNAME(mout_phyclk_dptx_phy_clk_div2_user_p) = {"fin_pll",
 196                         "phyclk_dptx_phy_clk_div2"};
 197 PNAME(mout_sclk_hdmi_pixel_p) = {"mout_sclk_disp_pixel_user",
 198                         "mout_aclk_disp_222_user"};
 199 PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll",
 200                         "phyclk_mipi_dphy_4l_m_rxclkesc0"};
 201 PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk",
 202                         "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
 203
 204 static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
 205         MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
 206                         mout_aclk_disp_333_user_p,
 207                         MUX_SEL_DISP0, 0, 1),
 208         MUX(DISP_MOUT_SCLK_DISP_PIXEL_USER, "mout_sclk_disp_pixel_user",
 209                         mout_sclk_disp_pixel_user_p,
 210                         MUX_SEL_DISP0, 4, 1),
 211         MUX(DISP_MOUT_ACLK_DISP_222_USER, "mout_aclk_disp_222_user",
 212                         mout_aclk_disp_222_user_p,
 213                         MUX_SEL_DISP0, 8, 1),
 214         MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER,
 215                         "mout_phyclk_dptx_phy_ch0_txd_clk_user",
 216                         mout_phyclk_dptx_phy_ch0_txd_clk_user_p,
 217                         MUX_SEL_DISP0, 16, 1),
 218         MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER,
 219                         "mout_phyclk_dptx_phy_ch1_txd_clk_user",
 220                         mout_phyclk_dptx_phy_ch1_txd_clk_user_p,
 221                         MUX_SEL_DISP0, 20, 1),
 222         MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER,
 223                         "mout_phyclk_dptx_phy_ch2_txd_clk_user",
 224                         mout_phyclk_dptx_phy_ch2_txd_clk_user_p,
 225                         MUX_SEL_DISP0, 24, 1),
 226         MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER,
 227                         "mout_phyclk_dptx_phy_ch3_txd_clk_user",
 228                         mout_phyclk_dptx_phy_ch3_txd_clk_user_p,
 229                         MUX_SEL_DISP0, 28, 1),
 230
 231         MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER,
 232                         "mout_phyclk_dptx_phy_clk_div2_user",
 233                         mout_phyclk_dptx_phy_clk_div2_user_p,
 234                         MUX_SEL_DISP1, 0, 1),
 235         MUX(DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER,
 236                         "mout_phyclk_dptx_phy_o_ref_clk_24m_user",
 237                         mout_phyclk_dptx_phy_o_ref_clk_24m_user_p,
 238                         MUX_SEL_DISP1, 4, 1),
 239         MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS,
 240                         "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs",
 241                         mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p,
 242                         MUX_SEL_DISP1, 8, 1),
 243         MUX(DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER,
 244                         "mout_phyclk_hdmi_link_o_tmds_clkhi_user",
 245                         mout_phyclk_hdmi_link_o_tmds_clkhi_user_p,
 246                         MUX_SEL_DISP1, 16, 1),
 247         MUX(DISP_MOUT_HDMI_PHY_PIXEL,
 248                         "mout_phyclk_hdmi_phy_pixel_clko_user",
 249                         mout_phyclk_hdmi_phy_pixel_clko_user_p,
 250                         MUX_SEL_DISP1, 20, 1),
 251         MUX(DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER,
 252                         "mout_phyclk_hdmi_phy_ref_clko_user",
 253                         mout_phyclk_hdmi_phy_ref_clko_user_p,
 254                         MUX_SEL_DISP1, 24, 1),
 255         MUX(DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER,
 256                         "mout_phyclk_hdmi_phy_tmds_clko_user",
 257                         mout_phyclk_hdmi_phy_tmds_clko_user_p,
 258                         MUX_SEL_DISP1, 28, 1),
 259
 260         MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER,
 261                         "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user",
 262                         mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p,
 263                         MUX_SEL_DISP2, 0, 1),
 264         MUX(DISP_MOUT_SCLK_HDMI_PIXEL, "mout_sclk_hdmi_pixel",
 265                         mout_sclk_hdmi_pixel_p,
 266                         MUX_SEL_DISP2, 4, 1),
 267
 268         MUX(DISP_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
 269                         mout_sclk_hdmi_spdif_p,
 270                         MUX_SEL_DISP4, 4, 2),
 271 };
 272
 273 static const struct samsung_div_clock disp_div_clks[] __initconst = {
 274         DIV(DISP_DOUT_PCLK_DISP_111, "dout_pclk_disp_111",
 275                         "mout_aclk_disp_222_user",
 276                         DIV_DISP, 8, 4),
 277         DIV(DISP_DOUT_SCLK_FIMD1_EXTCLKPLL, "dout_sclk_fimd1_extclkpll",
 278                         "mout_sclk_disp_pixel_user",
 279                         DIV_DISP, 12, 4),
 280         DIV(DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI,
 281                         "dout_sclk_hdmi_phy_pixel_clki",
 282                         "mout_sclk_hdmi_pixel",
 283                         DIV_DISP, 16, 4),
 284 };
 285
 286 static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
 287         GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel",
 288                         "mout_phyclk_hdmi_phy_pixel_clko_user",
 289                         EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0),
 290         GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki",
 291                         "dout_sclk_hdmi_phy_pixel_clki",
 292                         EN_SCLK_DISP0, 29, CLK_SET_RATE_PARENT, 0),
 293
 294         GATE(DISP_CLK_DP, "clk_dptx_link", "mout_aclk_disp_222_user",
 295                         EN_IP_DISP, 4, 0, 0),
 296         GATE(DISP_CLK_DPPHY, "clk_dptx_phy", "mout_aclk_disp_222_user",
 297                         EN_IP_DISP, 5, 0, 0),
 298         GATE(DISP_CLK_DSIM1, "clk_dsim1", "mout_aclk_disp_222_user",
 299                         EN_IP_DISP, 6, 0, 0),
 300         GATE(DISP_CLK_FIMD1, "clk_fimd1", "mout_aclk_disp_222_user",
 301                         EN_IP_DISP, 7, 0, 0),
 302         GATE(DISP_CLK_HDMI, "clk_hdmi", "mout_aclk_disp_222_user",
 303                         EN_IP_DISP, 8, 0, 0),
 304         GATE(DISP_CLK_HDMIPHY, "clk_hdmiphy", "mout_aclk_disp_222_user",
 305                         EN_IP_DISP, 9, 0, 0),
 306         GATE(DISP_CLK_MIPIPHY, "clk_mipi_dphy", "mout_aclk_disp_222_user",
 307                         EN_IP_DISP, 10, 0, 0),
 308         GATE(DISP_CLK_MIXER, "clk_mixer", "mout_aclk_disp_222_user",
 309                         EN_IP_DISP, 11, 0, 0),
 310         GATE(DISP_CLK_PIXEL_DISP, "clk_pixel_disp", "mout_aclk_disp_222_user",
 311                         EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0),
 312         GATE(DISP_CLK_PIXEL_MIXER, "clk_pixel_mixer", "mout_aclk_disp_222_user",
 313                         EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0),
 314         GATE(DISP_CLK_SMMU_FIMD1M0, "clk_smmu3_fimd1m0",
 315                         "mout_aclk_disp_222_user",
 316                         EN_IP_DISP, 22, 0, 0),
 317         GATE(DISP_CLK_SMMU_FIMD1M1, "clk_smmu3_fimd1m1",
 318                         "mout_aclk_disp_222_user",
 319                         EN_IP_DISP, 23, 0, 0),
 320         GATE(DISP_CLK_SMMU_TV, "clk_smmu3_tv", "mout_aclk_disp_222_user",
 321                         EN_IP_DISP, 25, 0, 0),
 322 };
 323
 324 static const struct samsung_cmu_info disp_cmu __initconst = {
 325         .mux_clks       = disp_mux_clks,
 326         .nr_mux_clks    = ARRAY_SIZE(disp_mux_clks),
 327         .div_clks       = disp_div_clks,
 328         .nr_div_clks    = ARRAY_SIZE(disp_div_clks),
 329         .gate_clks      = disp_gate_clks,
 330         .nr_gate_clks   = ARRAY_SIZE(disp_gate_clks),
 331         .nr_clk_ids     = DISP_NR_CLK,
 332         .clk_regs       = disp_clk_regs,
 333         .nr_clk_regs    = ARRAY_SIZE(disp_clk_regs),
 334 };
 335
 336 static void __init exynos5260_clk_disp_init(struct device_node *np)
 337 {
 338         samsung_cmu_register_one(np, &disp_cmu);
 339 }
 340
 341 CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",
 342                 exynos5260_clk_disp_init);
 343
 344
 345 /* CMU_EGL */
 346
 347 static const unsigned long egl_clk_regs[] __initconst = {
 348         EGL_PLL_LOCK,
 349         EGL_PLL_CON0,
 350         EGL_PLL_CON1,
 351         EGL_PLL_FREQ_DET,
 352         MUX_SEL_EGL,
 353         MUX_ENABLE_EGL,
 354         DIV_EGL,
 355         DIV_EGL_PLL_FDET,
 356         EN_ACLK_EGL,
 357         EN_PCLK_EGL,
 358         EN_SCLK_EGL,
 359 };
 360
 361 PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"};
 362 PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"};
 363
 364 static const struct samsung_mux_clock egl_mux_clks[] __initconst = {
 365         MUX(EGL_MOUT_EGL_PLL, "mout_egl_pll", mout_egl_pll_p,
 366                         MUX_SEL_EGL, 4, 1),
 367         MUX(EGL_MOUT_EGL_B, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1),
 368 };
 369
 370 static const struct samsung_div_clock egl_div_clks[] __initconst = {
 371         DIV(EGL_DOUT_EGL1, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3),
 372         DIV(EGL_DOUT_EGL2, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3),
 373         DIV(EGL_DOUT_ACLK_EGL, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3),
 374         DIV(EGL_DOUT_PCLK_EGL, "dout_pclk_egl", "dout_egl_atclk",
 375                         DIV_EGL, 12, 3),
 376         DIV(EGL_DOUT_EGL_ATCLK, "dout_egl_atclk", "dout_egl2", DIV_EGL, 16, 3),
 377         DIV(EGL_DOUT_EGL_PCLK_DBG, "dout_egl_pclk_dbg", "dout_egl_atclk",
 378                         DIV_EGL, 20, 3),
 379         DIV(EGL_DOUT_EGL_PLL, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3),
 380 };
 381
 382 static const struct samsung_pll_clock egl_pll_clks[] __initconst = {
 383         PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll",
 384                 EGL_PLL_LOCK, EGL_PLL_CON0,
 385                 pll2550_24mhz_tbl),
 386 };
 387
 388 static const struct samsung_cmu_info egl_cmu __initconst = {
 389         .pll_clks       = egl_pll_clks,
 390         .nr_pll_clks    = ARRAY_SIZE(egl_pll_clks),
 391         .mux_clks       = egl_mux_clks,
 392         .nr_mux_clks    = ARRAY_SIZE(egl_mux_clks),
 393         .div_clks       = egl_div_clks,
 394         .nr_div_clks    = ARRAY_SIZE(egl_div_clks),
 395         .nr_clk_ids     = EGL_NR_CLK,
 396         .clk_regs       = egl_clk_regs,
 397         .nr_clk_regs    = ARRAY_SIZE(egl_clk_regs),
 398 };
 399
 400 static void __init exynos5260_clk_egl_init(struct device_node *np)
 401 {
 402         samsung_cmu_register_one(np, &egl_cmu);
 403 }
 404
 405 CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",
 406                 exynos5260_clk_egl_init);
 407
 408
 409 /* CMU_FSYS */
 410
 411 static const unsigned long fsys_clk_regs[] __initconst = {
 412         MUX_SEL_FSYS0,
 413         MUX_SEL_FSYS1,
 414         EN_ACLK_FSYS,
 415         EN_ACLK_FSYS_SECURE_RTIC,
 416         EN_ACLK_FSYS_SECURE_SMMU_RTIC,
 417         EN_SCLK_FSYS,
 418         EN_IP_FSYS,
 419         EN_IP_FSYS_SECURE_RTIC,
 420         EN_IP_FSYS_SECURE_SMMU_RTIC,
 421 };
 422
 423 PNAME(mout_phyclk_usbhost20_phyclk_user_p) = {"fin_pll",
 424                         "phyclk_usbhost20_phy_phyclock"};
 425 PNAME(mout_phyclk_usbhost20_freeclk_user_p) = {"fin_pll",
 426                         "phyclk_usbhost20_phy_freeclk"};
 427 PNAME(mout_phyclk_usbhost20_clk48mohci_user_p) = {"fin_pll",
 428                         "phyclk_usbhost20_phy_clk48mohci"};
 429 PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll",
 430                         "phyclk_usbdrd30_udrd30_pipe_pclk"};
 431 PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll",
 432                         "phyclk_usbdrd30_udrd30_phyclock"};
 433
 434 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
 435         MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER,
 436                         "mout_phyclk_usbdrd30_phyclock_user",
 437                         mout_phyclk_usbdrd30_phyclock_user_p,
 438                         MUX_SEL_FSYS1, 0, 1),
 439         MUX(FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER,
 440                         "mout_phyclk_usbdrd30_pipe_pclk_user",
 441                         mout_phyclk_usbdrd30_pipe_pclk_user_p,
 442                         MUX_SEL_FSYS1, 4, 1),
 443         MUX(FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER,
 444                         "mout_phyclk_usbhost20_clk48mohci_user",
 445                         mout_phyclk_usbhost20_clk48mohci_user_p,
 446                         MUX_SEL_FSYS1, 8, 1),
 447         MUX(FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER,
 448                         "mout_phyclk_usbhost20_freeclk_user",
 449                         mout_phyclk_usbhost20_freeclk_user_p,
 450                         MUX_SEL_FSYS1, 12, 1),
 451         MUX(FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER,
 452                         "mout_phyclk_usbhost20_phyclk_user",
 453                         mout_phyclk_usbhost20_phyclk_user_p,
 454                         MUX_SEL_FSYS1, 16, 1),
 455 };
 456
 457 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
 458         GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock",
 459                         "mout_phyclk_usbdrd30_phyclock_user",
 460                         EN_SCLK_FSYS, 1, 0, 0),
 461         GATE(FSYS_PHYCLK_USBDRD30, "phyclk_usbdrd30_udrd30_phyclock_g",
 462                         "mout_phyclk_usbdrd30_phyclock_user",
 463                         EN_SCLK_FSYS, 7, 0, 0),
 464
 465         GATE(FSYS_CLK_MMC0, "clk_mmc0", "dout_aclk_fsys_200",
 466                         EN_IP_FSYS, 6, 0, 0),
 467         GATE(FSYS_CLK_MMC1, "clk_mmc1", "dout_aclk_fsys_200",
 468                         EN_IP_FSYS, 7, 0, 0),
 469         GATE(FSYS_CLK_MMC2, "clk_mmc2", "dout_aclk_fsys_200",
 470                         EN_IP_FSYS, 8, 0, 0),
 471         GATE(FSYS_CLK_PDMA, "clk_pdma", "dout_aclk_fsys_200",
 472                         EN_IP_FSYS, 9, 0, 0),
 473         GATE(FSYS_CLK_SROMC, "clk_sromc", "dout_aclk_fsys_200",
 474                         EN_IP_FSYS, 13, 0, 0),
 475         GATE(FSYS_CLK_USBDRD30, "clk_usbdrd30", "dout_aclk_fsys_200",
 476                         EN_IP_FSYS, 14, 0, 0),
 477         GATE(FSYS_CLK_USBHOST20, "clk_usbhost20", "dout_aclk_fsys_200",
 478                         EN_IP_FSYS, 15, 0, 0),
 479         GATE(FSYS_CLK_USBLINK, "clk_usblink", "dout_aclk_fsys_200",
 480                         EN_IP_FSYS, 18, 0, 0),
 481         GATE(FSYS_CLK_TSI, "clk_tsi", "dout_aclk_fsys_200",
 482                         EN_IP_FSYS, 20, 0, 0),
 483
 484         GATE(FSYS_CLK_RTIC, "clk_rtic", "dout_aclk_fsys_200",
 485                         EN_IP_FSYS_SECURE_RTIC, 11, 0, 0),
 486         GATE(FSYS_CLK_SMMU_RTIC, "clk_smmu_rtic", "dout_aclk_fsys_200",
 487                         EN_IP_FSYS_SECURE_SMMU_RTIC, 12, 0, 0),
 488 };
 489
 490 static const struct samsung_cmu_info fsys_cmu __initconst = {
 491         .mux_clks       = fsys_mux_clks,
 492         .nr_mux_clks    = ARRAY_SIZE(fsys_mux_clks),
 493         .gate_clks      = fsys_gate_clks,
 494         .nr_gate_clks   = ARRAY_SIZE(fsys_gate_clks),
 495         .nr_clk_ids     = FSYS_NR_CLK,
 496         .clk_regs       = fsys_clk_regs,
 497         .nr_clk_regs    = ARRAY_SIZE(fsys_clk_regs),
 498 };
 499
 500 static void __init exynos5260_clk_fsys_init(struct device_node *np)
 501 {
 502         samsung_cmu_register_one(np, &fsys_cmu);
 503 }
 504
 505 CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",
 506                 exynos5260_clk_fsys_init);
 507
 508
 509 /* CMU_G2D */
 510
 511 static const unsigned long g2d_clk_regs[] __initconst = {
 512         MUX_SEL_G2D,
 513         MUX_STAT_G2D,
 514         DIV_G2D,
 515         EN_ACLK_G2D,
 516         EN_ACLK_G2D_SECURE_SSS,
 517         EN_ACLK_G2D_SECURE_SLIM_SSS,
 518         EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS,
 519         EN_ACLK_G2D_SECURE_SMMU_SSS,
 520         EN_ACLK_G2D_SECURE_SMMU_MDMA,
 521         EN_ACLK_G2D_SECURE_SMMU_G2D,
 522         EN_PCLK_G2D,
 523         EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS,
 524         EN_PCLK_G2D_SECURE_SMMU_SSS,
 525         EN_PCLK_G2D_SECURE_SMMU_MDMA,
 526         EN_PCLK_G2D_SECURE_SMMU_G2D,
 527         EN_IP_G2D,
 528         EN_IP_G2D_SECURE_SSS,
 529         EN_IP_G2D_SECURE_SLIM_SSS,
 530         EN_IP_G2D_SECURE_SMMU_SLIM_SSS,
 531         EN_IP_G2D_SECURE_SMMU_SSS,
 532         EN_IP_G2D_SECURE_SMMU_MDMA,
 533         EN_IP_G2D_SECURE_SMMU_G2D,
 534 };
 535
 536 PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"};
 537
 538 static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
 539         MUX(G2D_MOUT_ACLK_G2D_333_USER, "mout_aclk_g2d_333_user",
 540                         mout_aclk_g2d_333_user_p,
 541                         MUX_SEL_G2D, 0, 1),
 542 };
 543
 544 static const struct samsung_div_clock g2d_div_clks[] __initconst = {
 545         DIV(G2D_DOUT_PCLK_G2D_83, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user",
 546                         DIV_G2D, 0, 3),
 547 };
 548
 549 static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
 550         GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user",
 551                         EN_IP_G2D, 4, 0, 0),
 552         GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user",
 553                         EN_IP_G2D, 5, 0, 0),
 554         GATE(G2D_CLK_MDMA, "clk_mdma", "mout_aclk_g2d_333_user",
 555                         EN_IP_G2D, 6, 0, 0),
 556         GATE(G2D_CLK_SMMU3_JPEG, "clk_smmu3_jpeg", "mout_aclk_g2d_333_user",
 557                         EN_IP_G2D, 16, 0, 0),
 558
 559         GATE(G2D_CLK_SSS, "clk_sss", "mout_aclk_g2d_333_user",
 560                         EN_IP_G2D_SECURE_SSS, 17, 0, 0),
 561
 562         GATE(G2D_CLK_SLIM_SSS, "clk_slim_sss", "mout_aclk_g2d_333_user",
 563                         EN_IP_G2D_SECURE_SLIM_SSS, 11, 0, 0),
 564
 565         GATE(G2D_CLK_SMMU_SLIM_SSS, "clk_smmu_slim_sss",
 566                         "mout_aclk_g2d_333_user",
 567                         EN_IP_G2D_SECURE_SMMU_SLIM_SSS, 13, 0, 0),
 568
 569         GATE(G2D_CLK_SMMU_SSS, "clk_smmu_sss", "mout_aclk_g2d_333_user",
 570                         EN_IP_G2D_SECURE_SMMU_SSS, 14, 0, 0),
 571
 572         GATE(G2D_CLK_SMMU_MDMA, "clk_smmu_mdma", "mout_aclk_g2d_333_user",
 573                         EN_IP_G2D_SECURE_SMMU_MDMA, 12, 0, 0),
 574
 575         GATE(G2D_CLK_SMMU3_G2D, "clk_smmu3_g2d", "mout_aclk_g2d_333_user",
 576                         EN_IP_G2D_SECURE_SMMU_G2D, 15, 0, 0),
 577 };
 578
 579 static const struct samsung_cmu_info g2d_cmu __initconst = {
 580         .mux_clks       = g2d_mux_clks,
 581         .nr_mux_clks    = ARRAY_SIZE(g2d_mux_clks),
 582         .div_clks       = g2d_div_clks,
 583         .nr_div_clks    = ARRAY_SIZE(g2d_div_clks),
 584         .gate_clks      = g2d_gate_clks,
 585         .nr_gate_clks   = ARRAY_SIZE(g2d_gate_clks),
 586         .nr_clk_ids     = G2D_NR_CLK,
 587         .clk_regs       = g2d_clk_regs,
 588         .nr_clk_regs    = ARRAY_SIZE(g2d_clk_regs),
 589 };
 590
 591 static void __init exynos5260_clk_g2d_init(struct device_node *np)
 592 {
 593         samsung_cmu_register_one(np, &g2d_cmu);
 594 }
 595
 596 CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",
 597                 exynos5260_clk_g2d_init);
 598
 599
 600 /* CMU_G3D */
 601
 602 static const unsigned long g3d_clk_regs[] __initconst = {
 603         G3D_PLL_LOCK,
 604         G3D_PLL_CON0,
 605         G3D_PLL_CON1,
 606         G3D_PLL_FDET,
 607         MUX_SEL_G3D,
 608         DIV_G3D,
 609         DIV_G3D_PLL_FDET,
 610         EN_ACLK_G3D,
 611         EN_PCLK_G3D,
 612         EN_SCLK_G3D,
 613         EN_IP_G3D,
 614 };
 615
 616 PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"};
 617
 618 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
 619         MUX(G3D_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
 620                         MUX_SEL_G3D, 0, 1),
 621 };
 622
 623 static const struct samsung_div_clock g3d_div_clks[] __initconst = {
 624         DIV(G3D_DOUT_PCLK_G3D, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3),
 625         DIV(G3D_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3),
 626 };
 627
 628 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
 629         GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0),
 630         GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d",
 631                         EN_IP_G3D, 3, 0, 0),
 632 };
 633
 634 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
 635         PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll",
 636                 G3D_PLL_LOCK, G3D_PLL_CON0,
 637                 pll2550_24mhz_tbl),
 638 };
 639
 640 static const struct samsung_cmu_info g3d_cmu __initconst = {
 641         .pll_clks       = g3d_pll_clks,
 642         .nr_pll_clks    = ARRAY_SIZE(g3d_pll_clks),
 643         .mux_clks       = g3d_mux_clks,
 644         .nr_mux_clks    = ARRAY_SIZE(g3d_mux_clks),
 645         .div_clks       = g3d_div_clks,
 646         .nr_div_clks    = ARRAY_SIZE(g3d_div_clks),
 647         .gate_clks      = g3d_gate_clks,
 648         .nr_gate_clks   = ARRAY_SIZE(g3d_gate_clks),
 649         .nr_clk_ids     = G3D_NR_CLK,
 650         .clk_regs       = g3d_clk_regs,
 651         .nr_clk_regs    = ARRAY_SIZE(g3d_clk_regs),
 652 };
 653
 654 static void __init exynos5260_clk_g3d_init(struct device_node *np)
 655 {
 656         samsung_cmu_register_one(np, &g3d_cmu);
 657 }
 658
 659 CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",
 660                 exynos5260_clk_g3d_init);
 661
 662
 663 /* CMU_GSCL */
 664
 665 static const unsigned long gscl_clk_regs[] __initconst = {
 666         MUX_SEL_GSCL,
 667         DIV_GSCL,
 668         EN_ACLK_GSCL,
 669         EN_ACLK_GSCL_FIMC,
 670         EN_ACLK_GSCL_SECURE_SMMU_GSCL0,
 671         EN_ACLK_GSCL_SECURE_SMMU_GSCL1,
 672         EN_ACLK_GSCL_SECURE_SMMU_MSCL0,
 673         EN_ACLK_GSCL_SECURE_SMMU_MSCL1,
 674         EN_PCLK_GSCL,
 675         EN_PCLK_GSCL_FIMC,
 676         EN_PCLK_GSCL_SECURE_SMMU_GSCL0,
 677         EN_PCLK_GSCL_SECURE_SMMU_GSCL1,
 678         EN_PCLK_GSCL_SECURE_SMMU_MSCL0,
 679         EN_PCLK_GSCL_SECURE_SMMU_MSCL1,
 680         EN_SCLK_GSCL,
 681         EN_SCLK_GSCL_FIMC,
 682         EN_IP_GSCL,
 683         EN_IP_GSCL_FIMC,
 684         EN_IP_GSCL_SECURE_SMMU_GSCL0,
 685         EN_IP_GSCL_SECURE_SMMU_GSCL1,
 686         EN_IP_GSCL_SECURE_SMMU_MSCL0,
 687         EN_IP_GSCL_SECURE_SMMU_MSCL1,
 688 };
 689
 690 PNAME(mout_aclk_gscl_333_user_p) = {"fin_pll", "dout_aclk_gscl_333"};
 691 PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
 692 PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
 693 PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"};
 694
 695 static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
 696         MUX(GSCL_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
 697                         mout_aclk_gscl_333_user_p,
 698                         MUX_SEL_GSCL, 0, 1),
 699         MUX(GSCL_MOUT_ACLK_M2M_400_USER, "mout_aclk_m2m_400_user",
 700                         mout_aclk_m2m_400_user_p,
 701                         MUX_SEL_GSCL, 4, 1),
 702         MUX(GSCL_MOUT_ACLK_GSCL_FIMC_USER, "mout_aclk_gscl_fimc_user",
 703                         mout_aclk_gscl_fimc_user_p,
 704                         MUX_SEL_GSCL, 8, 1),
 705         MUX(GSCL_MOUT_ACLK_CSIS, "mout_aclk_csis", mout_aclk_csis_p,
 706                         MUX_SEL_GSCL, 24, 1),
 707 };
 708
 709 static const struct samsung_div_clock gscl_div_clks[] __initconst = {
 710         DIV(GSCL_DOUT_PCLK_M2M_100, "dout_pclk_m2m_100",
 711                         "mout_aclk_m2m_400_user",
 712                         DIV_GSCL, 0, 3),
 713         DIV(GSCL_DOUT_ACLK_CSIS_200, "dout_aclk_csis_200",
 714                         "mout_aclk_m2m_400_user",
 715                         DIV_GSCL, 4, 3),
 716 };
 717
 718 static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
 719         GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200",
 720                         EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0),
 721         GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200",
 722                         EN_SCLK_GSCL_FIMC, 1, CLK_SET_RATE_PARENT, 0),
 723
 724         GATE(GSCL_CLK_GSCL0, "clk_gscl0", "mout_aclk_gscl_333_user",
 725                         EN_IP_GSCL, 2, 0, 0),
 726         GATE(GSCL_CLK_GSCL1, "clk_gscl1", "mout_aclk_gscl_333_user",
 727                         EN_IP_GSCL, 3, 0, 0),
 728         GATE(GSCL_CLK_MSCL0, "clk_mscl0", "mout_aclk_gscl_333_user",
 729                         EN_IP_GSCL, 4, 0, 0),
 730         GATE(GSCL_CLK_MSCL1, "clk_mscl1", "mout_aclk_gscl_333_user",
 731                         EN_IP_GSCL, 5, 0, 0),
 732         GATE(GSCL_CLK_PIXEL_GSCL0, "clk_pixel_gscl0",
 733                         "mout_aclk_gscl_333_user",
 734                         EN_IP_GSCL, 8, 0, 0),
 735         GATE(GSCL_CLK_PIXEL_GSCL1, "clk_pixel_gscl1",
 736                         "mout_aclk_gscl_333_user",
 737                         EN_IP_GSCL, 9, 0, 0),
 738
 739         GATE(GSCL_CLK_SMMU3_LITE_A, "clk_smmu3_lite_a",
 740                         "mout_aclk_gscl_fimc_user",
 741                         EN_IP_GSCL_FIMC, 5, 0, 0),
 742         GATE(GSCL_CLK_SMMU3_LITE_B, "clk_smmu3_lite_b",
 743                         "mout_aclk_gscl_fimc_user",
 744                         EN_IP_GSCL_FIMC, 6, 0, 0),
 745         GATE(GSCL_CLK_SMMU3_LITE_D, "clk_smmu3_lite_d",
 746                         "mout_aclk_gscl_fimc_user",
 747                         EN_IP_GSCL_FIMC, 7, 0, 0),
 748         GATE(GSCL_CLK_CSIS0, "clk_csis0", "mout_aclk_gscl_fimc_user",
 749                         EN_IP_GSCL_FIMC, 8, 0, 0),
 750         GATE(GSCL_CLK_CSIS1, "clk_csis1", "mout_aclk_gscl_fimc_user",
 751                         EN_IP_GSCL_FIMC, 9, 0, 0),
 752         GATE(GSCL_CLK_FIMC_LITE_A, "clk_fimc_lite_a",
 753                         "mout_aclk_gscl_fimc_user",
 754                         EN_IP_GSCL_FIMC, 10, 0, 0),
 755         GATE(GSCL_CLK_FIMC_LITE_B, "clk_fimc_lite_b",
 756                         "mout_aclk_gscl_fimc_user",
 757                         EN_IP_GSCL_FIMC, 11, 0, 0),
 758         GATE(GSCL_CLK_FIMC_LITE_D, "clk_fimc_lite_d",
 759                         "mout_aclk_gscl_fimc_user",
 760                         EN_IP_GSCL_FIMC, 12, 0, 0),
 761
 762         GATE(GSCL_CLK_SMMU3_GSCL0, "clk_smmu3_gscl0",
 763                         "mout_aclk_gscl_333_user",
 764                         EN_IP_GSCL_SECURE_SMMU_GSCL0, 17, 0, 0),
 765         GATE(GSCL_CLK_SMMU3_GSCL1, "clk_smmu3_gscl1", "mout_aclk_gscl_333_user",
 766                         EN_IP_GSCL_SECURE_SMMU_GSCL1, 18, 0, 0),
 767         GATE(GSCL_CLK_SMMU3_MSCL0, "clk_smmu3_mscl0",
 768                         "mout_aclk_m2m_400_user",
 769                         EN_IP_GSCL_SECURE_SMMU_MSCL0, 19, 0, 0),
 770         GATE(GSCL_CLK_SMMU3_MSCL1, "clk_smmu3_mscl1",
 771                         "mout_aclk_m2m_400_user",
 772                         EN_IP_GSCL_SECURE_SMMU_MSCL1, 20, 0, 0),
 773 };
 774
 775 static const struct samsung_cmu_info gscl_cmu __initconst = {
 776         .mux_clks       = gscl_mux_clks,
 777         .nr_mux_clks    = ARRAY_SIZE(gscl_mux_clks),
 778         .div_clks       = gscl_div_clks,
 779         .nr_div_clks    = ARRAY_SIZE(gscl_div_clks),
 780         .gate_clks      = gscl_gate_clks,
 781         .nr_gate_clks   = ARRAY_SIZE(gscl_gate_clks),
 782         .nr_clk_ids     = GSCL_NR_CLK,
 783         .clk_regs       = gscl_clk_regs,
 784         .nr_clk_regs    = ARRAY_SIZE(gscl_clk_regs),
 785 };
 786
 787 static void __init exynos5260_clk_gscl_init(struct device_node *np)
 788 {
 789         samsung_cmu_register_one(np, &gscl_cmu);
 790 }
 791
 792 CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",
 793                 exynos5260_clk_gscl_init);
 794
 795
 796 /* CMU_ISP */
 797
 798 static const unsigned long isp_clk_regs[] __initconst = {
 799         MUX_SEL_ISP0,
 800         MUX_SEL_ISP1,
 801         DIV_ISP,
 802         EN_ACLK_ISP0,
 803         EN_ACLK_ISP1,
 804         EN_PCLK_ISP0,
 805         EN_PCLK_ISP1,
 806         EN_SCLK_ISP,
 807         EN_IP_ISP0,
 808         EN_IP_ISP1,
 809 };
 810
 811 PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"};
 812 PNAME(mout_isp_266_user_p)       = {"fin_pll", "dout_aclk_isp1_266"};
 813
 814 static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
 815         MUX(ISP_MOUT_ISP_266_USER, "mout_isp_266_user", mout_isp_266_user_p,
 816                         MUX_SEL_ISP0, 0, 1),
 817         MUX(ISP_MOUT_ISP_400_USER, "mout_isp_400_user", mout_isp_400_user_p,
 818                         MUX_SEL_ISP0, 4, 1),
 819 };
 820
 821 static const struct samsung_div_clock isp_div_clks[] __initconst = {
 822         DIV(ISP_DOUT_PCLK_ISP_66, "dout_pclk_isp_66", "mout_kfc",
 823                         DIV_ISP, 0, 3),
 824         DIV(ISP_DOUT_PCLK_ISP_133, "dout_pclk_isp_133", "mout_kfc",
 825                         DIV_ISP, 4, 4),
 826         DIV(ISP_DOUT_CA5_ATCLKIN, "dout_ca5_atclkin", "mout_kfc",
 827                         DIV_ISP, 12, 3),
 828         DIV(ISP_DOUT_CA5_PCLKDBG, "dout_ca5_pclkdbg", "mout_kfc",
 829                         DIV_ISP, 16, 4),
 830         DIV(ISP_DOUT_SCLK_MPWM, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2),
 831 };
 832
 833 static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
 834         GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266",
 835                         EN_IP_ISP0, 15, 0, 0),
 836
 837         GATE(ISP_CLK_CA5, "clk_isp_ca5", "mout_aclk_isp1_266",
 838                         EN_IP_ISP1, 1, 0, 0),
 839         GATE(ISP_CLK_FIMC_DRC, "clk_isp_fimc_drc", "mout_aclk_isp1_266",
 840                         EN_IP_ISP1, 2, 0, 0),
 841         GATE(ISP_CLK_FIMC_FD, "clk_isp_fimc_fd", "mout_aclk_isp1_266",
 842                         EN_IP_ISP1, 3, 0, 0),
 843         GATE(ISP_CLK_FIMC, "clk_isp_fimc", "mout_aclk_isp1_266",
 844                         EN_IP_ISP1, 4, 0, 0),
 845         GATE(ISP_CLK_FIMC_SCALERC, "clk_isp_fimc_scalerc",
 846                         "mout_aclk_isp1_266",
 847                         EN_IP_ISP1, 5, 0, 0),
 848         GATE(ISP_CLK_FIMC_SCALERP, "clk_isp_fimc_scalerp",
 849                         "mout_aclk_isp1_266",
 850                         EN_IP_ISP1, 6, 0, 0),
 851         GATE(ISP_CLK_I2C0, "clk_isp_i2c0", "mout_aclk_isp1_266",
 852                         EN_IP_ISP1, 7, 0, 0),
 853         GATE(ISP_CLK_I2C1, "clk_isp_i2c1", "mout_aclk_isp1_266",
 854                         EN_IP_ISP1, 8, 0, 0),
 855         GATE(ISP_CLK_MCUCTL, "clk_isp_mcuctl", "mout_aclk_isp1_266",
 856                         EN_IP_ISP1, 9, 0, 0),
 857         GATE(ISP_CLK_MPWM, "clk_isp_mpwm", "mout_aclk_isp1_266",
 858                         EN_IP_ISP1, 10, 0, 0),
 859         GATE(ISP_CLK_MTCADC, "clk_isp_mtcadc", "mout_aclk_isp1_266",
 860                         EN_IP_ISP1, 11, 0, 0),
 861         GATE(ISP_CLK_PWM, "clk_isp_pwm", "mout_aclk_isp1_266",
 862                         EN_IP_ISP1, 14, 0, 0),
 863         GATE(ISP_CLK_SMMU_DRC, "clk_smmu_drc", "mout_aclk_isp1_266",
 864                         EN_IP_ISP1, 21, 0, 0),
 865         GATE(ISP_CLK_SMMU_FD, "clk_smmu_fd", "mout_aclk_isp1_266",
 866                         EN_IP_ISP1, 22, 0, 0),
 867         GATE(ISP_CLK_SMMU_ISP, "clk_smmu_isp", "mout_aclk_isp1_266",
 868                         EN_IP_ISP1, 23, 0, 0),
 869         GATE(ISP_CLK_SMMU_ISPCX, "clk_smmu_ispcx", "mout_aclk_isp1_266",
 870                         EN_IP_ISP1, 24, 0, 0),
 871         GATE(ISP_CLK_SMMU_SCALERC, "clk_isp_smmu_scalerc",
 872                         "mout_aclk_isp1_266",
 873                         EN_IP_ISP1, 25, 0, 0),
 874         GATE(ISP_CLK_SMMU_SCALERP, "clk_isp_smmu_scalerp",
 875                         "mout_aclk_isp1_266",
 876                         EN_IP_ISP1, 26, 0, 0),
 877         GATE(ISP_CLK_SPI0, "clk_isp_spi0", "mout_aclk_isp1_266",
 878                         EN_IP_ISP1, 27, 0, 0),
 879         GATE(ISP_CLK_SPI1, "clk_isp_spi1", "mout_aclk_isp1_266",
 880                         EN_IP_ISP1, 28, 0, 0),
 881         GATE(ISP_CLK_WDT, "clk_isp_wdt", "mout_aclk_isp1_266",
 882                         EN_IP_ISP1, 31, 0, 0),
 883         GATE(ISP_CLK_UART, "clk_isp_uart", "mout_aclk_isp1_266",
 884                         EN_IP_ISP1, 30, 0, 0),
 885
 886         GATE(ISP_SCLK_UART_EXT, "sclk_isp_uart_ext", "fin_pll",
 887                         EN_SCLK_ISP, 7, CLK_SET_RATE_PARENT, 0),
 888         GATE(ISP_SCLK_SPI1_EXT, "sclk_isp_spi1_ext", "fin_pll",
 889                         EN_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
 890         GATE(ISP_SCLK_SPI0_EXT, "sclk_isp_spi0_ext", "fin_pll",
 891                         EN_SCLK_ISP, 9, CLK_SET_RATE_PARENT, 0),
 892 };
 893
 894 static const struct samsung_cmu_info isp_cmu __initconst = {
 895         .mux_clks       = isp_mux_clks,
 896         .nr_mux_clks    = ARRAY_SIZE(isp_mux_clks),
 897         .div_clks       = isp_div_clks,
 898         .nr_div_clks    = ARRAY_SIZE(isp_div_clks),
 899         .gate_clks      = isp_gate_clks,
 900         .nr_gate_clks   = ARRAY_SIZE(isp_gate_clks),
 901         .nr_clk_ids     = ISP_NR_CLK,
 902         .clk_regs       = isp_clk_regs,
 903         .nr_clk_regs    = ARRAY_SIZE(isp_clk_regs),
 904 };
 905
 906 static void __init exynos5260_clk_isp_init(struct device_node *np)
 907 {
 908         samsung_cmu_register_one(np, &isp_cmu);
 909 }
 910
 911 CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",
 912                 exynos5260_clk_isp_init);
 913
 914
 915 /* CMU_KFC */
 916
 917 static const unsigned long kfc_clk_regs[] __initconst = {
 918         KFC_PLL_LOCK,
 919         KFC_PLL_CON0,
 920         KFC_PLL_CON1,
 921         KFC_PLL_FDET,
 922         MUX_SEL_KFC0,
 923         MUX_SEL_KFC2,
 924         DIV_KFC,
 925         DIV_KFC_PLL_FDET,
 926         EN_ACLK_KFC,
 927         EN_PCLK_KFC,
 928         EN_SCLK_KFC,
 929         EN_IP_KFC,
 930 };
 931
 932 PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"};
 933 PNAME(mout_kfc_p)        = {"mout_kfc_pll", "dout_media_pll"};
 934
 935 static const struct samsung_mux_clock kfc_mux_clks[] __initconst = {
 936         MUX(KFC_MOUT_KFC_PLL, "mout_kfc_pll", mout_kfc_pll_p,
 937                         MUX_SEL_KFC0, 0, 1),
 938         MUX(KFC_MOUT_KFC, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1),
 939 };
 940
 941 static const struct samsung_div_clock kfc_div_clks[] __initconst = {
 942         DIV(KFC_DOUT_KFC1, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3),
 943         DIV(KFC_DOUT_KFC2, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3),
 944         DIV(KFC_DOUT_KFC_ATCLK, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3),
 945         DIV(KFC_DOUT_KFC_PCLK_DBG, "dout_kfc_pclk_dbg", "dout_kfc2",
 946                         DIV_KFC, 12, 3),
 947         DIV(KFC_DOUT_ACLK_KFC, "dout_aclk_kfc", "dout_kfc2", DIV_KFC, 16, 3),
 948         DIV(KFC_DOUT_PCLK_KFC, "dout_pclk_kfc", "dout_kfc2", DIV_KFC, 20, 3),
 949         DIV(KFC_DOUT_KFC_PLL, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3),
 950 };
 951
 952 static const struct samsung_pll_clock kfc_pll_clks[] __initconst = {
 953         PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll",
 954                 KFC_PLL_LOCK, KFC_PLL_CON0,
 955                 pll2550_24mhz_tbl),
 956 };
 957
 958 static const struct samsung_cmu_info kfc_cmu __initconst = {
 959         .pll_clks       = kfc_pll_clks,
 960         .nr_pll_clks    = ARRAY_SIZE(kfc_pll_clks),
 961         .mux_clks       = kfc_mux_clks,
 962         .nr_mux_clks    = ARRAY_SIZE(kfc_mux_clks),
 963         .div_clks       = kfc_div_clks,
 964         .nr_div_clks    = ARRAY_SIZE(kfc_div_clks),
 965         .nr_clk_ids     = KFC_NR_CLK,
 966         .clk_regs       = kfc_clk_regs,
 967         .nr_clk_regs    = ARRAY_SIZE(kfc_clk_regs),
 968 };
 969
 970 static void __init exynos5260_clk_kfc_init(struct device_node *np)
 971 {
 972         samsung_cmu_register_one(np, &kfc_cmu);
 973 }
 974
 975 CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",
 976                 exynos5260_clk_kfc_init);
 977
 978
 979 /* CMU_MFC */
 980
 981 static const unsigned long mfc_clk_regs[] __initconst = {
 982         MUX_SEL_MFC,
 983         DIV_MFC,
 984         EN_ACLK_MFC,
 985         EN_ACLK_SECURE_SMMU2_MFC,
 986         EN_PCLK_MFC,
 987         EN_PCLK_SECURE_SMMU2_MFC,
 988         EN_IP_MFC,
 989         EN_IP_MFC_SECURE_SMMU2_MFC,
 990 };
 991
 992 PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"};
 993
 994 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
 995         MUX(MFC_MOUT_ACLK_MFC_333_USER, "mout_aclk_mfc_333_user",
 996                         mout_aclk_mfc_333_user_p,
 997                         MUX_SEL_MFC, 0, 1),
 998 };
 999
1000 static const struct samsung_div_clock mfc_div_clks[] __initconst = {
1001         DIV(MFC_DOUT_PCLK_MFC_83, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user",
1002                         DIV_MFC, 0, 3),
1003 };
1004
1005 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
1006         GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user",
1007                         EN_IP_MFC, 1, 0, 0),
1008         GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user",
1009                         EN_IP_MFC_SECURE_SMMU2_MFC, 6, 0, 0),
1010         GATE(MFC_CLK_SMMU2_MFCM1, "clk_smmu2_mfcm1", "mout_aclk_mfc_333_user",
1011                         EN_IP_MFC_SECURE_SMMU2_MFC, 7, 0, 0),
1012 };
1013
1014 static const struct samsung_cmu_info mfc_cmu __initconst = {
1015         .mux_clks       = mfc_mux_clks,
1016         .nr_mux_clks    = ARRAY_SIZE(mfc_mux_clks),
1017         .div_clks       = mfc_div_clks,
1018         .nr_div_clks    = ARRAY_SIZE(mfc_div_clks),
1019         .gate_clks      = mfc_gate_clks,
1020         .nr_gate_clks   = ARRAY_SIZE(mfc_gate_clks),
1021         .nr_clk_ids     = MFC_NR_CLK,
1022         .clk_regs       = mfc_clk_regs,
1023         .nr_clk_regs    = ARRAY_SIZE(mfc_clk_regs),
1024 };
1025
1026 static void __init exynos5260_clk_mfc_init(struct device_node *np)
1027 {
1028         samsung_cmu_register_one(np, &mfc_cmu);
1029 }
1030
1031 CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",
1032                 exynos5260_clk_mfc_init);
1033
1034
1035 /* CMU_MIF */
1036
1037 static const unsigned long mif_clk_regs[] __initconst = {
1038         MEM_PLL_LOCK,
1039         BUS_PLL_LOCK,
1040         MEDIA_PLL_LOCK,
1041         MEM_PLL_CON0,
1042         MEM_PLL_CON1,
1043         MEM_PLL_FDET,
1044         BUS_PLL_CON0,
1045         BUS_PLL_CON1,
1046         BUS_PLL_FDET,
1047         MEDIA_PLL_CON0,
1048         MEDIA_PLL_CON1,
1049         MEDIA_PLL_FDET,
1050         MUX_SEL_MIF,
1051         DIV_MIF,
1052         DIV_MIF_PLL_FDET,
1053         EN_ACLK_MIF,
1054         EN_ACLK_MIF_SECURE_DREX1_TZ,
1055         EN_ACLK_MIF_SECURE_DREX0_TZ,
1056         EN_ACLK_MIF_SECURE_INTMEM,
1057         EN_PCLK_MIF,
1058         EN_PCLK_MIF_SECURE_MONOCNT,
1059         EN_PCLK_MIF_SECURE_RTC_APBIF,
1060         EN_PCLK_MIF_SECURE_DREX1_TZ,
1061         EN_PCLK_MIF_SECURE_DREX0_TZ,
1062         EN_SCLK_MIF,
1063         EN_IP_MIF,
1064         EN_IP_MIF_SECURE_MONOCNT,
1065         EN_IP_MIF_SECURE_RTC_APBIF,
1066         EN_IP_MIF_SECURE_DREX1_TZ,
1067         EN_IP_MIF_SECURE_DREX0_TZ,
1068         EN_IP_MIF_SECURE_INTEMEM,
1069 };
1070
1071 PNAME(mout_mem_pll_p) = {"fin_pll", "fout_mem_pll"};
1072 PNAME(mout_bus_pll_p) = {"fin_pll", "fout_bus_pll"};
1073 PNAME(mout_media_pll_p) = {"fin_pll", "fout_media_pll"};
1074 PNAME(mout_mif_drex_p) = {"dout_mem_pll", "dout_bus_pll"};
1075 PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"};
1076 PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"};
1077 PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"};
1078
1079 static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
1080         MUX(MIF_MOUT_MEM_PLL, "mout_mem_pll", mout_mem_pll_p,
1081                         MUX_SEL_MIF, 0, 1),
1082         MUX(MIF_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p,
1083                         MUX_SEL_MIF, 4, 1),
1084         MUX(MIF_MOUT_MEDIA_PLL, "mout_media_pll", mout_media_pll_p,
1085                         MUX_SEL_MIF, 8, 1),
1086         MUX(MIF_MOUT_MIF_DREX, "mout_mif_drex", mout_mif_drex_p,
1087                         MUX_SEL_MIF, 12, 1),
1088         MUX(MIF_MOUT_CLKM_PHY, "mout_clkm_phy", mout_clkm_phy_p,
1089                         MUX_SEL_MIF, 16, 1),
1090         MUX(MIF_MOUT_MIF_DREX2X, "mout_mif_drex2x", mout_mif_drex2x_p,
1091                         MUX_SEL_MIF, 20, 1),
1092         MUX(MIF_MOUT_CLK2X_PHY, "mout_clk2x_phy", mout_clk2x_phy_p,
1093                         MUX_SEL_MIF, 24, 1),
1094 };
1095
1096 static const struct samsung_div_clock mif_div_clks[] __initconst = {
1097         DIV(MIF_DOUT_MEDIA_PLL, "dout_media_pll", "mout_media_pll",
1098                         DIV_MIF, 0, 3),
1099         DIV(MIF_DOUT_MEM_PLL, "dout_mem_pll", "mout_mem_pll",
1100                         DIV_MIF, 4, 3),
1101         DIV(MIF_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll",
1102                         DIV_MIF, 8, 3),
1103         DIV(MIF_DOUT_CLKM_PHY, "dout_clkm_phy", "mout_clkm_phy",
1104                         DIV_MIF, 12, 3),
1105         DIV(MIF_DOUT_CLK2X_PHY, "dout_clk2x_phy", "mout_clk2x_phy",
1106                         DIV_MIF, 16, 4),
1107         DIV(MIF_DOUT_ACLK_MIF_466, "dout_aclk_mif_466", "dout_clk2x_phy",
1108                         DIV_MIF, 20, 3),
1109         DIV(MIF_DOUT_ACLK_BUS_200, "dout_aclk_bus_200", "dout_bus_pll",
1110                         DIV_MIF, 24, 3),
1111         DIV(MIF_DOUT_ACLK_BUS_100, "dout_aclk_bus_100", "dout_bus_pll",
1112                         DIV_MIF, 28, 4),
1113 };
1114
1115 static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
1116         GATE(MIF_CLK_LPDDR3PHY_WRAP0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy",
1117                         EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0),
1118         GATE(MIF_CLK_LPDDR3PHY_WRAP1, "clk_lpddr3phy_wrap1", "dout_clk2x_phy",
1119                         EN_IP_MIF, 13, CLK_IGNORE_UNUSED, 0),
1120
1121         GATE(MIF_CLK_MONOCNT, "clk_monocnt", "dout_aclk_bus_100",
1122                         EN_IP_MIF_SECURE_MONOCNT, 22,
1123                         CLK_IGNORE_UNUSED, 0),
1124
1125         GATE(MIF_CLK_MIF_RTC, "clk_mif_rtc", "dout_aclk_bus_100",
1126                         EN_IP_MIF_SECURE_RTC_APBIF, 23,
1127                         CLK_IGNORE_UNUSED, 0),
1128
1129         GATE(MIF_CLK_DREX1, "clk_drex1", "dout_aclk_mif_466",
1130                         EN_IP_MIF_SECURE_DREX1_TZ, 9,
1131                         CLK_IGNORE_UNUSED, 0),
1132
1133         GATE(MIF_CLK_DREX0, "clk_drex0", "dout_aclk_mif_466",
1134                         EN_IP_MIF_SECURE_DREX0_TZ, 9,
1135                         CLK_IGNORE_UNUSED, 0),
1136
1137         GATE(MIF_CLK_INTMEM, "clk_intmem", "dout_aclk_bus_200",
1138                         EN_IP_MIF_SECURE_INTEMEM, 11,
1139                         CLK_IGNORE_UNUSED, 0),
1140
1141         GATE(MIF_SCLK_LPDDR3PHY_WRAP_U0, "sclk_lpddr3phy_wrap_u0",
1142                         "dout_clkm_phy", EN_SCLK_MIF, 0,
1143                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1144         GATE(MIF_SCLK_LPDDR3PHY_WRAP_U1, "sclk_lpddr3phy_wrap_u1",
1145                         "dout_clkm_phy", EN_SCLK_MIF, 1,
1146                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1147 };
1148
1149 static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
1150         PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll",
1151                 MEM_PLL_LOCK, MEM_PLL_CON0,
1152                 pll2550_24mhz_tbl),
1153         PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll",
1154                 BUS_PLL_LOCK, BUS_PLL_CON0,
1155                 pll2550_24mhz_tbl),
1156         PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll",
1157                 MEDIA_PLL_LOCK, MEDIA_PLL_CON0,
1158                 pll2550_24mhz_tbl),
1159 };
1160
1161 static const struct samsung_cmu_info mif_cmu __initconst = {
1162         .pll_clks       = mif_pll_clks,
1163         .nr_pll_clks    = ARRAY_SIZE(mif_pll_clks),
1164         .mux_clks       = mif_mux_clks,
1165         .nr_mux_clks    = ARRAY_SIZE(mif_mux_clks),
1166         .div_clks       = mif_div_clks,
1167         .nr_div_clks    = ARRAY_SIZE(mif_div_clks),
1168         .gate_clks      = mif_gate_clks,
1169         .nr_gate_clks   = ARRAY_SIZE(mif_gate_clks),
1170         .nr_clk_ids     = MIF_NR_CLK,
1171         .clk_regs       = mif_clk_regs,
1172         .nr_clk_regs    = ARRAY_SIZE(mif_clk_regs),
1173 };
1174
1175 static void __init exynos5260_clk_mif_init(struct device_node *np)
1176 {
1177         samsung_cmu_register_one(np, &mif_cmu);
1178 }
1179
1180 CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif",
1181                 exynos5260_clk_mif_init);
1182
1183
1184 /* CMU_PERI */
1185
1186 static const unsigned long peri_clk_regs[] __initconst = {
1187         MUX_SEL_PERI,
1188         MUX_SEL_PERI1,
1189         DIV_PERI,
1190         EN_PCLK_PERI0,
1191         EN_PCLK_PERI1,
1192         EN_PCLK_PERI2,
1193         EN_PCLK_PERI3,
1194         EN_PCLK_PERI_SECURE_CHIPID,
1195         EN_PCLK_PERI_SECURE_PROVKEY0,
1196         EN_PCLK_PERI_SECURE_PROVKEY1,
1197         EN_PCLK_PERI_SECURE_SECKEY,
1198         EN_PCLK_PERI_SECURE_ANTIRBKCNT,
1199         EN_PCLK_PERI_SECURE_TOP_RTC,
1200         EN_PCLK_PERI_SECURE_TZPC,
1201         EN_SCLK_PERI,
1202         EN_SCLK_PERI_SECURE_TOP_RTC,
1203         EN_IP_PERI0,
1204         EN_IP_PERI1,
1205         EN_IP_PERI2,
1206         EN_IP_PERI_SECURE_CHIPID,
1207         EN_IP_PERI_SECURE_PROVKEY0,
1208         EN_IP_PERI_SECURE_PROVKEY1,
1209         EN_IP_PERI_SECURE_SECKEY,
1210         EN_IP_PERI_SECURE_ANTIRBKCNT,
1211         EN_IP_PERI_SECURE_TOP_RTC,
1212         EN_IP_PERI_SECURE_TZPC,
1213 };
1214
1215 PNAME(mout_sclk_pcm_p) = {"ioclk_pcm_extclk", "fin_pll", "dout_aclk_peri_aud",
1216                         "phyclk_hdmi_phy_ref_cko"};
1217 PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud",
1218                         "phyclk_hdmi_phy_ref_cko"};
1219 PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extclk", "fin_pll",
1220                         "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
1221
1222 static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
1223         MUX(PERI_MOUT_SCLK_PCM, "mout_sclk_pcm", mout_sclk_pcm_p,
1224                         MUX_SEL_PERI1, 4, 2),
1225         MUX(PERI_MOUT_SCLK_I2SCOD, "mout_sclk_i2scod", mout_sclk_i2scod_p,
1226                         MUX_SEL_PERI1, 12, 2),
1227         MUX(PERI_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
1228                         MUX_SEL_PERI1, 20, 2),
1229 };
1230
1231 static const struct samsung_div_clock peri_div_clks[] __initconst = {
1232         DIV(PERI_DOUT_PCM, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8),
1233         DIV(PERI_DOUT_I2S, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 8, 6),
1234 };
1235
1236 static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
1237         GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0,
1238                         CLK_SET_RATE_PARENT, 0),
1239         GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1,
1240                         CLK_SET_RATE_PARENT, 0),
1241         GATE(PERI_SCLK_SPDIF, "sclk_spdif", "dout_sclk_peri_spi0_b",
1242                         EN_SCLK_PERI, 2, CLK_SET_RATE_PARENT, 0),
1243         GATE(PERI_SCLK_SPI0, "sclk_spi0", "dout_sclk_peri_spi0_b",
1244                         EN_SCLK_PERI, 7, CLK_SET_RATE_PARENT, 0),
1245         GATE(PERI_SCLK_SPI1, "sclk_spi1", "dout_sclk_peri_spi1_b",
1246                         EN_SCLK_PERI, 8, CLK_SET_RATE_PARENT, 0),
1247         GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b",
1248                         EN_SCLK_PERI, 9, CLK_SET_RATE_PARENT, 0),
1249         GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0",
1250                         EN_SCLK_PERI, 10, CLK_SET_RATE_PARENT, 0),
1251         GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1",
1252                         EN_SCLK_PERI, 11, CLK_SET_RATE_PARENT, 0),
1253         GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2",
1254                         EN_SCLK_PERI, 12, CLK_SET_RATE_PARENT, 0),
1255
1256         GATE(PERI_CLK_ABB, "clk_abb", "dout_aclk_peri_66",
1257                 EN_IP_PERI0, 1, 0, 0),
1258         GATE(PERI_CLK_EFUSE_WRITER, "clk_efuse_writer", "dout_aclk_peri_66",
1259                 EN_IP_PERI0, 5, 0, 0),
1260         GATE(PERI_CLK_HDMICEC, "clk_hdmicec", "dout_aclk_peri_66",
1261                 EN_IP_PERI0, 6, 0, 0),
1262         GATE(PERI_CLK_I2C10, "clk_i2c10", "dout_aclk_peri_66",
1263                 EN_IP_PERI0, 7, 0, 0),
1264         GATE(PERI_CLK_I2C11, "clk_i2c11", "dout_aclk_peri_66",
1265                 EN_IP_PERI0, 8, 0, 0),
1266         GATE(PERI_CLK_I2C8, "clk_i2c8", "dout_aclk_peri_66",
1267                 EN_IP_PERI0, 9, 0, 0),
1268         GATE(PERI_CLK_I2C9, "clk_i2c9", "dout_aclk_peri_66",
1269                 EN_IP_PERI0, 10, 0, 0),
1270         GATE(PERI_CLK_I2C4, "clk_i2c4", "dout_aclk_peri_66",
1271                 EN_IP_PERI0, 11, 0, 0),
1272         GATE(PERI_CLK_I2C5, "clk_i2c5", "dout_aclk_peri_66",
1273                 EN_IP_PERI0, 12, 0, 0),
1274         GATE(PERI_CLK_I2C6, "clk_i2c6", "dout_aclk_peri_66",
1275                 EN_IP_PERI0, 13, 0, 0),
1276         GATE(PERI_CLK_I2C7, "clk_i2c7", "dout_aclk_peri_66",
1277                 EN_IP_PERI0, 14, 0, 0),
1278         GATE(PERI_CLK_I2CHDMI, "clk_i2chdmi", "dout_aclk_peri_66",
1279                 EN_IP_PERI0, 15, 0, 0),
1280         GATE(PERI_CLK_I2S, "clk_peri_i2s", "dout_aclk_peri_66",
1281                 EN_IP_PERI0, 16, 0, 0),
1282         GATE(PERI_CLK_MCT, "clk_mct", "dout_aclk_peri_66",
1283                 EN_IP_PERI0, 17, 0, 0),
1284         GATE(PERI_CLK_PCM, "clk_peri_pcm", "dout_aclk_peri_66",
1285                 EN_IP_PERI0, 18, 0, 0),
1286         GATE(PERI_CLK_HSIC0, "clk_hsic0", "dout_aclk_peri_66",
1287                 EN_IP_PERI0, 20, 0, 0),
1288         GATE(PERI_CLK_HSIC1, "clk_hsic1", "dout_aclk_peri_66",
1289                 EN_IP_PERI0, 21, 0, 0),
1290         GATE(PERI_CLK_HSIC2, "clk_hsic2", "dout_aclk_peri_66",
1291                 EN_IP_PERI0, 22, 0, 0),
1292         GATE(PERI_CLK_HSIC3, "clk_hsic3", "dout_aclk_peri_66",
1293                 EN_IP_PERI0, 23, 0, 0),
1294         GATE(PERI_CLK_WDT_EGL, "clk_wdt_egl", "dout_aclk_peri_66",
1295                 EN_IP_PERI0, 24, 0, 0),
1296         GATE(PERI_CLK_WDT_KFC, "clk_wdt_kfc", "dout_aclk_peri_66",
1297                 EN_IP_PERI0, 25, 0, 0),
1298
1299         GATE(PERI_CLK_UART4, "clk_uart4", "dout_aclk_peri_66",
1300                 EN_IP_PERI2, 0, 0, 0),
1301         GATE(PERI_CLK_PWM, "clk_pwm", "dout_aclk_peri_66",
1302                 EN_IP_PERI2, 3, 0, 0),
1303         GATE(PERI_CLK_SPDIF, "clk_spdif", "dout_aclk_peri_66",
1304                 EN_IP_PERI2, 6, 0, 0),
1305         GATE(PERI_CLK_SPI0, "clk_spi0", "dout_aclk_peri_66",
1306                 EN_IP_PERI2, 7, 0, 0),
1307         GATE(PERI_CLK_SPI1, "clk_spi1", "dout_aclk_peri_66",
1308                 EN_IP_PERI2, 8, 0, 0),
1309         GATE(PERI_CLK_SPI2, "clk_spi2", "dout_aclk_peri_66",
1310                 EN_IP_PERI2, 9, 0, 0),
1311         GATE(PERI_CLK_TMU0, "clk_tmu0", "dout_aclk_peri_66",
1312                 EN_IP_PERI2, 10, 0, 0),
1313         GATE(PERI_CLK_TMU1, "clk_tmu1", "dout_aclk_peri_66",
1314                 EN_IP_PERI2, 11, 0, 0),
1315         GATE(PERI_CLK_TMU2, "clk_tmu2", "dout_aclk_peri_66",
1316                 EN_IP_PERI2, 12, 0, 0),
1317         GATE(PERI_CLK_TMU3, "clk_tmu3", "dout_aclk_peri_66",
1318                 EN_IP_PERI2, 13, 0, 0),
1319         GATE(PERI_CLK_TMU4, "clk_tmu4", "dout_aclk_peri_66",
1320                 EN_IP_PERI2, 14, 0, 0),
1321         GATE(PERI_CLK_ADC, "clk_adc", "dout_aclk_peri_66",
1322                 EN_IP_PERI2, 18, 0, 0),
1323         GATE(PERI_CLK_UART0, "clk_uart0", "dout_aclk_peri_66",
1324                 EN_IP_PERI2, 19, 0, 0),
1325         GATE(PERI_CLK_UART1, "clk_uart1", "dout_aclk_peri_66",
1326                 EN_IP_PERI2, 20, 0, 0),
1327         GATE(PERI_CLK_UART2, "clk_uart2", "dout_aclk_peri_66",
1328                 EN_IP_PERI2, 21, 0, 0),
1329
1330         GATE(PERI_CLK_CHIPID, "clk_chipid", "dout_aclk_peri_66",
1331                 EN_IP_PERI_SECURE_CHIPID, 2, 0, 0),
1332
1333         GATE(PERI_CLK_PROVKEY0, "clk_provkey0", "dout_aclk_peri_66",
1334                 EN_IP_PERI_SECURE_PROVKEY0, 1, 0, 0),
1335
1336         GATE(PERI_CLK_PROVKEY1, "clk_provkey1", "dout_aclk_peri_66",
1337                 EN_IP_PERI_SECURE_PROVKEY1, 2, 0, 0),
1338
1339         GATE(PERI_CLK_SECKEY, "clk_seckey", "dout_aclk_peri_66",
1340                 EN_IP_PERI_SECURE_SECKEY, 5, 0, 0),
1341
1342         GATE(PERI_CLK_TOP_RTC, "clk_top_rtc", "dout_aclk_peri_66",
1343                 EN_IP_PERI_SECURE_TOP_RTC, 5, 0, 0),
1344
1345         GATE(PERI_CLK_TZPC0, "clk_tzpc0", "dout_aclk_peri_66",
1346                 EN_IP_PERI_SECURE_TZPC, 10, 0, 0),
1347         GATE(PERI_CLK_TZPC1, "clk_tzpc1", "dout_aclk_peri_66",
1348                 EN_IP_PERI_SECURE_TZPC, 11, 0, 0),
1349         GATE(PERI_CLK_TZPC2, "clk_tzpc2", "dout_aclk_peri_66",
1350                 EN_IP_PERI_SECURE_TZPC, 12, 0, 0),
1351         GATE(PERI_CLK_TZPC3, "clk_tzpc3", "dout_aclk_peri_66",
1352                 EN_IP_PERI_SECURE_TZPC, 13, 0, 0),
1353         GATE(PERI_CLK_TZPC4, "clk_tzpc4", "dout_aclk_peri_66",
1354                 EN_IP_PERI_SECURE_TZPC, 14, 0, 0),
1355         GATE(PERI_CLK_TZPC5, "clk_tzpc5", "dout_aclk_peri_66",
1356                 EN_IP_PERI_SECURE_TZPC, 15, 0, 0),
1357         GATE(PERI_CLK_TZPC6, "clk_tzpc6", "dout_aclk_peri_66",
1358                 EN_IP_PERI_SECURE_TZPC, 16, 0, 0),
1359         GATE(PERI_CLK_TZPC7, "clk_tzpc7", "dout_aclk_peri_66",
1360                 EN_IP_PERI_SECURE_TZPC, 17, 0, 0),
1361         GATE(PERI_CLK_TZPC8, "clk_tzpc8", "dout_aclk_peri_66",
1362                 EN_IP_PERI_SECURE_TZPC, 18, 0, 0),
1363         GATE(PERI_CLK_TZPC9, "clk_tzpc9", "dout_aclk_peri_66",
1364                 EN_IP_PERI_SECURE_TZPC, 19, 0, 0),
1365         GATE(PERI_CLK_TZPC10, "clk_tzpc10", "dout_aclk_peri_66",
1366                 EN_IP_PERI_SECURE_TZPC, 20, 0, 0),
1367 };
1368
1369 static const struct samsung_cmu_info peri_cmu __initconst = {
1370         .mux_clks       = peri_mux_clks,
1371         .nr_mux_clks    = ARRAY_SIZE(peri_mux_clks),
1372         .div_clks       = peri_div_clks,
1373         .nr_div_clks    = ARRAY_SIZE(peri_div_clks),
1374         .gate_clks      = peri_gate_clks,
1375         .nr_gate_clks   = ARRAY_SIZE(peri_gate_clks),
1376         .nr_clk_ids     = PERI_NR_CLK,
1377         .clk_regs       = peri_clk_regs,
1378         .nr_clk_regs    = ARRAY_SIZE(peri_clk_regs),
1379 };
1380
1381 static void __init exynos5260_clk_peri_init(struct device_node *np)
1382 {
1383         samsung_cmu_register_one(np, &peri_cmu);
1384 }
1385
1386 CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri",
1387                 exynos5260_clk_peri_init);
1388
1389
1390 /* CMU_TOP */
1391
1392 static const unsigned long top_clk_regs[] __initconst = {
1393         DISP_PLL_LOCK,
1394         AUD_PLL_LOCK,
1395         DISP_PLL_CON0,
1396         DISP_PLL_CON1,
1397         DISP_PLL_FDET,
1398         AUD_PLL_CON0,
1399         AUD_PLL_CON1,
1400         AUD_PLL_CON2,
1401         AUD_PLL_FDET,
1402         MUX_SEL_TOP_PLL0,
1403         MUX_SEL_TOP_MFC,
1404         MUX_SEL_TOP_G2D,
1405         MUX_SEL_TOP_GSCL,
1406         MUX_SEL_TOP_ISP10,
1407         MUX_SEL_TOP_ISP11,
1408         MUX_SEL_TOP_DISP0,
1409         MUX_SEL_TOP_DISP1,
1410         MUX_SEL_TOP_BUS,
1411         MUX_SEL_TOP_PERI0,
1412         MUX_SEL_TOP_PERI1,
1413         MUX_SEL_TOP_FSYS,
1414         DIV_TOP_G2D_MFC,
1415         DIV_TOP_GSCL_ISP0,
1416         DIV_TOP_ISP10,
1417         DIV_TOP_ISP11,
1418         DIV_TOP_DISP,
1419         DIV_TOP_BUS,
1420         DIV_TOP_PERI0,
1421         DIV_TOP_PERI1,
1422         DIV_TOP_PERI2,
1423         DIV_TOP_FSYS0,
1424         DIV_TOP_FSYS1,
1425         DIV_TOP_HPM,
1426         DIV_TOP_PLL_FDET,
1427         EN_ACLK_TOP,
1428         EN_SCLK_TOP,
1429         EN_IP_TOP,
1430 };
1431
1432 /* fixed rate clocks generated inside the soc */
1433 static const struct samsung_fixed_rate_clock fixed_rate_clks[] __initconst = {
1434         FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL,
1435                         0, 270000000),
1436         FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL,
1437                         0, 270000000),
1438         FRATE(PHYCLK_DPTX_PHY_CH1_TXD_CLK, "phyclk_dptx_phy_ch1_txd_clk", NULL,
1439                         0, 270000000),
1440         FRATE(PHYCLK_DPTX_PHY_CH0_TXD_CLK, "phyclk_dptx_phy_ch0_txd_clk", NULL,
1441                         0, 270000000),
1442         FRATE(phyclk_hdmi_phy_tmds_clko, "phyclk_hdmi_phy_tmds_clko", NULL,
1443                         0, 250000000),
1444         FRATE(PHYCLK_HDMI_PHY_PIXEL_CLKO, "phyclk_hdmi_phy_pixel_clko", NULL,
1445                         0, 1660000000),
1446         FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",
1447                         NULL, 0, 125000000),
1448         FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,
1449                         "phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL,
1450                         0, 187500000),
1451         FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",
1452                         NULL, 0, 24000000),
1453         FRATE(PHYCLK_DPTX_PHY_CLK_DIV2, "phyclk_dptx_phy_clk_div2", NULL,
1454                         0, 135000000),
1455         FRATE(PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0,
1456                         "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL, 0, 20000000),
1457         FRATE(PHYCLK_USBHOST20_PHY_PHYCLOCK, "phyclk_usbhost20_phy_phyclock",
1458                         NULL, 0, 60000000),
1459         FRATE(PHYCLK_USBHOST20_PHY_FREECLK, "phyclk_usbhost20_phy_freeclk",
1460                         NULL, 0, 60000000),
1461         FRATE(PHYCLK_USBHOST20_PHY_CLK48MOHCI,
1462                         "phyclk_usbhost20_phy_clk48mohci", NULL, 0, 48000000),
1463         FRATE(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
1464                         "phyclk_usbdrd30_udrd30_pipe_pclk", NULL, 0, 125000000),
1465         FRATE(PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
1466                         "phyclk_usbdrd30_udrd30_phyclock", NULL, 0, 60000000),
1467 };
1468
1469 PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"};
1470 PNAME(mout_bustop_pll_user_p) = {"fin_pll", "dout_bus_pll"};
1471 PNAME(mout_mediatop_pll_user_p) = {"fin_pll", "dout_media_pll"};
1472 PNAME(mout_audtop_pll_user_p) = {"fin_pll", "mout_aud_pll"};
1473 PNAME(mout_aud_pll_p) = {"fin_pll", "fout_aud_pll"};
1474 PNAME(mout_disp_pll_p) = {"fin_pll", "fout_disp_pll"};
1475 PNAME(mout_mfc_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
1476 PNAME(mout_aclk_mfc_333_p) = {"mout_mediatop_pll_user", "mout_mfc_bustop_333"};
1477 PNAME(mout_g2d_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
1478 PNAME(mout_aclk_g2d_333_p) = {"mout_mediatop_pll_user", "mout_g2d_bustop_333"};
1479 PNAME(mout_gscl_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
1480 PNAME(mout_aclk_gscl_333_p) = {"mout_mediatop_pll_user",
1481                         "mout_gscl_bustop_333"};
1482 PNAME(mout_m2m_mediatop_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
1483 PNAME(mout_aclk_gscl_400_p) = {"mout_bustop_pll_user",
1484                         "mout_m2m_mediatop_400"};
1485 PNAME(mout_gscl_bustop_fimc_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
1486 PNAME(mout_aclk_gscl_fimc_p) = {"mout_mediatop_pll_user",
1487                         "mout_gscl_bustop_fimc"};
1488 PNAME(mout_isp1_media_266_p) = {"mout_mediatop_pll_user",
1489                         "mout_memtop_pll_user"};
1490 PNAME(mout_aclk_isp1_266_p) = {"mout_bustop_pll_user", "mout_isp1_media_266"};
1491 PNAME(mout_isp1_media_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
1492 PNAME(mout_aclk_isp1_400_p) = {"mout_bustop_pll_user", "mout_isp1_media_400"};
1493 PNAME(mout_sclk_isp_spi_p) = {"fin_pll", "mout_bustop_pll_user"};
1494 PNAME(mout_sclk_isp_uart_p) = {"fin_pll", "mout_bustop_pll_user"};
1495 PNAME(mout_sclk_isp_sensor_p) = {"fin_pll", "mout_bustop_pll_user"};
1496 PNAME(mout_disp_disp_333_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
1497 PNAME(mout_aclk_disp_333_p) = {"mout_mediatop_pll_user", "mout_disp_disp_333"};
1498 PNAME(mout_disp_disp_222_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
1499 PNAME(mout_aclk_disp_222_p) = {"mout_mediatop_pll_user", "mout_disp_disp_222"};
1500 PNAME(mout_disp_media_pixel_p) = {"mout_mediatop_pll_user",
1501                         "mout_bustop_pll_user"};
1502 PNAME(mout_sclk_disp_pixel_p) = {"mout_disp_pll", "mout_disp_media_pixel"};
1503 PNAME(mout_bus_bustop_400_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
1504 PNAME(mout_bus_bustop_100_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
1505 PNAME(mout_sclk_peri_spi_clk_p) = {"fin_pll", "mout_bustop_pll_user"};
1506 PNAME(mout_sclk_peri_uart_uclk_p) = {"fin_pll", "mout_bustop_pll_user"};
1507 PNAME(mout_sclk_fsys_usb_p) = {"fin_pll", "mout_bustop_pll_user"};
1508 PNAME(mout_sclk_fsys_mmc_sdclkin_a_p) = {"fin_pll", "mout_bustop_pll_user"};
1509 PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p) = {"mout_sclk_fsys_mmc0_sdclkin_a",
1510                         "mout_mediatop_pll_user"};
1511 PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a",
1512                         "mout_mediatop_pll_user"};
1513 PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a",
1514                         "mout_mediatop_pll_user"};
1515
1516 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
1517         MUX(TOP_MOUT_MEDIATOP_PLL_USER, "mout_mediatop_pll_user",
1518                         mout_mediatop_pll_user_p,
1519                         MUX_SEL_TOP_PLL0, 0, 1),
1520         MUX(TOP_MOUT_MEMTOP_PLL_USER, "mout_memtop_pll_user",
1521                         mout_memtop_pll_user_p,
1522                         MUX_SEL_TOP_PLL0, 4, 1),
1523         MUX(TOP_MOUT_BUSTOP_PLL_USER, "mout_bustop_pll_user",
1524                         mout_bustop_pll_user_p,
1525                         MUX_SEL_TOP_PLL0, 8, 1),
1526         MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
1527                         MUX_SEL_TOP_PLL0, 12, 1),
1528         MUX(TOP_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
1529                         MUX_SEL_TOP_PLL0, 16, 1),
1530         MUX(TOP_MOUT_AUDTOP_PLL_USER, "mout_audtop_pll_user",
1531                         mout_audtop_pll_user_p,
1532                         MUX_SEL_TOP_PLL0, 24, 1),
1533
1534         MUX(TOP_MOUT_DISP_DISP_333, "mout_disp_disp_333", mout_disp_disp_333_p,
1535                         MUX_SEL_TOP_DISP0, 0, 1),
1536         MUX(TOP_MOUT_ACLK_DISP_333, "mout_aclk_disp_333", mout_aclk_disp_333_p,
1537                         MUX_SEL_TOP_DISP0, 8, 1),
1538         MUX(TOP_MOUT_DISP_DISP_222, "mout_disp_disp_222", mout_disp_disp_222_p,
1539                         MUX_SEL_TOP_DISP0, 12, 1),
1540         MUX(TOP_MOUT_ACLK_DISP_222, "mout_aclk_disp_222", mout_aclk_disp_222_p,
1541                         MUX_SEL_TOP_DISP0, 20, 1),
1542
1543         MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p,
1544                         MUX_SEL_TOP_DISP1, 0, 1),
1545         MUX(TOP_MOUT_DISP_MEDIA_PIXEL, "mout_disp_media_pixel",
1546                         mout_disp_media_pixel_p,
1547                         MUX_SEL_TOP_DISP1, 8, 1),
1548
1549         MUX(TOP_MOUT_SCLK_PERI_SPI2_CLK, "mout_sclk_peri_spi2_clk",
1550                         mout_sclk_peri_spi_clk_p,
1551                         MUX_SEL_TOP_PERI1, 0, 1),
1552         MUX(TOP_MOUT_SCLK_PERI_SPI1_CLK, "mout_sclk_peri_spi1_clk",
1553                         mout_sclk_peri_spi_clk_p,
1554                         MUX_SEL_TOP_PERI1, 4, 1),
1555         MUX(TOP_MOUT_SCLK_PERI_SPI0_CLK, "mout_sclk_peri_spi0_clk",
1556                         mout_sclk_peri_spi_clk_p,
1557                         MUX_SEL_TOP_PERI1, 8, 1),
1558         MUX(TOP_MOUT_SCLK_PERI_UART1_UCLK, "mout_sclk_peri_uart1_uclk",
1559                         mout_sclk_peri_uart_uclk_p,
1560                         MUX_SEL_TOP_PERI1, 12, 1),
1561         MUX(TOP_MOUT_SCLK_PERI_UART2_UCLK, "mout_sclk_peri_uart2_uclk",
1562                         mout_sclk_peri_uart_uclk_p,
1563                         MUX_SEL_TOP_PERI1, 16, 1),
1564         MUX(TOP_MOUT_SCLK_PERI_UART0_UCLK, "mout_sclk_peri_uart0_uclk",
1565                         mout_sclk_peri_uart_uclk_p,
1566                         MUX_SEL_TOP_PERI1, 20, 1),
1567
1568
1569         MUX(TOP_MOUT_BUS1_BUSTOP_400, "mout_bus1_bustop_400",
1570                         mout_bus_bustop_400_p,
1571                         MUX_SEL_TOP_BUS, 0, 1),
1572         MUX(TOP_MOUT_BUS1_BUSTOP_100, "mout_bus1_bustop_100",
1573                         mout_bus_bustop_100_p,
1574                         MUX_SEL_TOP_BUS, 4, 1),
1575         MUX(TOP_MOUT_BUS2_BUSTOP_100, "mout_bus2_bustop_100",
1576                         mout_bus_bustop_100_p,
1577                         MUX_SEL_TOP_BUS, 8, 1),
1578         MUX(TOP_MOUT_BUS2_BUSTOP_400, "mout_bus2_bustop_400",
1579                         mout_bus_bustop_400_p,
1580                         MUX_SEL_TOP_BUS, 12, 1),
1581         MUX(TOP_MOUT_BUS3_BUSTOP_400, "mout_bus3_bustop_400",
1582                         mout_bus_bustop_400_p,
1583                         MUX_SEL_TOP_BUS, 16, 1),
1584         MUX(TOP_MOUT_BUS3_BUSTOP_100, "mout_bus3_bustop_100",
1585                         mout_bus_bustop_100_p,
1586                         MUX_SEL_TOP_BUS, 20, 1),
1587         MUX(TOP_MOUT_BUS4_BUSTOP_400, "mout_bus4_bustop_400",
1588                         mout_bus_bustop_400_p,
1589                         MUX_SEL_TOP_BUS, 24, 1),
1590         MUX(TOP_MOUT_BUS4_BUSTOP_100, "mout_bus4_bustop_100",
1591                         mout_bus_bustop_100_p,
1592                         MUX_SEL_TOP_BUS, 28, 1),
1593
1594         MUX(TOP_MOUT_SCLK_FSYS_USB, "mout_sclk_fsys_usb",
1595                         mout_sclk_fsys_usb_p,
1596                         MUX_SEL_TOP_FSYS, 0, 1),
1597         MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "mout_sclk_fsys_mmc2_sdclkin_a",
1598                         mout_sclk_fsys_mmc_sdclkin_a_p,
1599                         MUX_SEL_TOP_FSYS, 4, 1),
1600         MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "mout_sclk_fsys_mmc2_sdclkin_b",
1601                         mout_sclk_fsys_mmc2_sdclkin_b_p,
1602                         MUX_SEL_TOP_FSYS, 8, 1),
1603         MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "mout_sclk_fsys_mmc1_sdclkin_a",
1604                         mout_sclk_fsys_mmc_sdclkin_a_p,
1605                         MUX_SEL_TOP_FSYS, 12, 1),
1606         MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "mout_sclk_fsys_mmc1_sdclkin_b",
1607                         mout_sclk_fsys_mmc1_sdclkin_b_p,
1608                         MUX_SEL_TOP_FSYS, 16, 1),
1609         MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "mout_sclk_fsys_mmc0_sdclkin_a",
1610                         mout_sclk_fsys_mmc_sdclkin_a_p,
1611                         MUX_SEL_TOP_FSYS, 20, 1),
1612         MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "mout_sclk_fsys_mmc0_sdclkin_b",
1613                         mout_sclk_fsys_mmc0_sdclkin_b_p,
1614                         MUX_SEL_TOP_FSYS, 24, 1),
1615
1616         MUX(TOP_MOUT_ISP1_MEDIA_400, "mout_isp1_media_400",
1617                         mout_isp1_media_400_p,
1618                         MUX_SEL_TOP_ISP10, 4, 1),
1619         MUX(TOP_MOUT_ACLK_ISP1_400, "mout_aclk_isp1_400", mout_aclk_isp1_400_p,
1620                         MUX_SEL_TOP_ISP10, 8 , 1),
1621         MUX(TOP_MOUT_ISP1_MEDIA_266, "mout_isp1_media_266",
1622                         mout_isp1_media_266_p,
1623                         MUX_SEL_TOP_ISP10, 16, 1),
1624         MUX(TOP_MOUT_ACLK_ISP1_266, "mout_aclk_isp1_266", mout_aclk_isp1_266_p,
1625                         MUX_SEL_TOP_ISP10, 20, 1),
1626
1627         MUX(TOP_MOUT_SCLK_ISP1_SPI0, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p,
1628                         MUX_SEL_TOP_ISP11, 4, 1),
1629         MUX(TOP_MOUT_SCLK_ISP1_SPI1, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p,
1630                         MUX_SEL_TOP_ISP11, 8, 1),
1631         MUX(TOP_MOUT_SCLK_ISP1_UART, "mout_sclk_isp1_uart",
1632                         mout_sclk_isp_uart_p,
1633                         MUX_SEL_TOP_ISP11, 12, 1),
1634         MUX(TOP_MOUT_SCLK_ISP1_SENSOR0, "mout_sclk_isp1_sensor0",
1635                         mout_sclk_isp_sensor_p,
1636                         MUX_SEL_TOP_ISP11, 16, 1),
1637         MUX(TOP_MOUT_SCLK_ISP1_SENSOR1, "mout_sclk_isp1_sensor1",
1638                         mout_sclk_isp_sensor_p,
1639                         MUX_SEL_TOP_ISP11, 20, 1),
1640         MUX(TOP_MOUT_SCLK_ISP1_SENSOR2, "mout_sclk_isp1_sensor2",
1641                         mout_sclk_isp_sensor_p,
1642                         MUX_SEL_TOP_ISP11, 24, 1),
1643
1644         MUX(TOP_MOUT_MFC_BUSTOP_333, "mout_mfc_bustop_333",
1645                         mout_mfc_bustop_333_p,
1646                         MUX_SEL_TOP_MFC, 4, 1),
1647         MUX(TOP_MOUT_ACLK_MFC_333, "mout_aclk_mfc_333", mout_aclk_mfc_333_p,
1648                         MUX_SEL_TOP_MFC, 8, 1),
1649
1650         MUX(TOP_MOUT_G2D_BUSTOP_333, "mout_g2d_bustop_333",
1651                         mout_g2d_bustop_333_p,
1652                         MUX_SEL_TOP_G2D, 4, 1),
1653         MUX(TOP_MOUT_ACLK_G2D_333, "mout_aclk_g2d_333", mout_aclk_g2d_333_p,
1654                         MUX_SEL_TOP_G2D, 8, 1),
1655
1656         MUX(TOP_MOUT_M2M_MEDIATOP_400, "mout_m2m_mediatop_400",
1657                         mout_m2m_mediatop_400_p,
1658                         MUX_SEL_TOP_GSCL, 0, 1),
1659         MUX(TOP_MOUT_ACLK_GSCL_400, "mout_aclk_gscl_400",
1660                         mout_aclk_gscl_400_p,
1661                         MUX_SEL_TOP_GSCL, 4, 1),
1662         MUX(TOP_MOUT_GSCL_BUSTOP_333, "mout_gscl_bustop_333",
1663                         mout_gscl_bustop_333_p,
1664                         MUX_SEL_TOP_GSCL, 8, 1),
1665         MUX(TOP_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
1666                         mout_aclk_gscl_333_p,
1667                         MUX_SEL_TOP_GSCL, 12, 1),
1668         MUX(TOP_MOUT_GSCL_BUSTOP_FIMC, "mout_gscl_bustop_fimc",
1669                         mout_gscl_bustop_fimc_p,
1670                         MUX_SEL_TOP_GSCL, 16, 1),
1671         MUX(TOP_MOUT_ACLK_GSCL_FIMC, "mout_aclk_gscl_fimc",
1672                         mout_aclk_gscl_fimc_p,
1673                         MUX_SEL_TOP_GSCL, 20, 1),
1674 };
1675
1676 static const struct samsung_div_clock top_div_clks[] __initconst = {
1677         DIV(TOP_DOUT_ACLK_G2D_333, "dout_aclk_g2d_333", "mout_aclk_g2d_333",
1678                         DIV_TOP_G2D_MFC, 0, 3),
1679         DIV(TOP_DOUT_ACLK_MFC_333, "dout_aclk_mfc_333", "mout_aclk_mfc_333",
1680                         DIV_TOP_G2D_MFC, 4, 3),
1681
1682         DIV(TOP_DOUT_ACLK_GSCL_333, "dout_aclk_gscl_333", "mout_aclk_gscl_333",
1683                         DIV_TOP_GSCL_ISP0, 0, 3),
1684         DIV(TOP_DOUT_ACLK_GSCL_400, "dout_aclk_gscl_400", "mout_aclk_gscl_400",
1685                         DIV_TOP_GSCL_ISP0, 4, 3),
1686         DIV(TOP_DOUT_ACLK_GSCL_FIMC, "dout_aclk_gscl_fimc",
1687                         "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 8, 3),
1688         DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_A, "dout_sclk_isp1_sensor0_a",
1689                         "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 16, 4),
1690         DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_A, "dout_sclk_isp1_sensor1_a",
1691                         "mout_aclk_gscl_400", DIV_TOP_GSCL_ISP0, 20, 4),
1692         DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_A, "dout_sclk_isp1_sensor2_a",
1693                         "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 24, 4),
1694
1695         DIV(TOP_DOUT_ACLK_ISP1_266, "dout_aclk_isp1_266", "mout_aclk_isp1_266",
1696                         DIV_TOP_ISP10, 0, 3),
1697         DIV(TOP_DOUT_ACLK_ISP1_400, "dout_aclk_isp1_400", "mout_aclk_isp1_400",
1698                         DIV_TOP_ISP10, 4, 3),
1699         DIV(TOP_DOUT_SCLK_ISP1_SPI0_A, "dout_sclk_isp1_spi0_a",
1700                         "mout_sclk_isp1_spi0", DIV_TOP_ISP10, 12, 4),
1701         DIV(TOP_DOUT_SCLK_ISP1_SPI0_B, "dout_sclk_isp1_spi0_b",
1702                         "dout_sclk_isp1_spi0_a", DIV_TOP_ISP10, 16, 8),
1703
1704         DIV(TOP_DOUT_SCLK_ISP1_SPI1_A, "dout_sclk_isp1_spi1_a",
1705                         "mout_sclk_isp1_spi1", DIV_TOP_ISP11, 0, 4),
1706         DIV(TOP_DOUT_SCLK_ISP1_SPI1_B, "dout_sclk_isp1_spi1_b",
1707                         "dout_sclk_isp1_spi1_a", DIV_TOP_ISP11, 4, 8),
1708         DIV(TOP_DOUT_SCLK_ISP1_UART, "dout_sclk_isp1_uart",
1709                         "mout_sclk_isp1_uart", DIV_TOP_ISP11, 12, 4),
1710         DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_B, "dout_sclk_isp1_sensor0_b",
1711                         "dout_sclk_isp1_sensor0_a", DIV_TOP_ISP11, 16, 4),
1712         DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_B, "dout_sclk_isp1_sensor1_b",
1713                         "dout_sclk_isp1_sensor1_a", DIV_TOP_ISP11, 20, 4),
1714         DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_B, "dout_sclk_isp1_sensor2_b",
1715                         "dout_sclk_isp1_sensor2_a", DIV_TOP_ISP11, 24, 4),
1716
1717         DIV(TOP_DOUTTOP__SCLK_HPM_TARGETCLK, "dout_sclk_hpm_targetclk",
1718                         "mout_bustop_pll_user", DIV_TOP_HPM, 0, 3),
1719
1720         DIV(TOP_DOUT_ACLK_DISP_333, "dout_aclk_disp_333", "mout_aclk_disp_333",
1721                         DIV_TOP_DISP, 0, 3),
1722         DIV(TOP_DOUT_ACLK_DISP_222, "dout_aclk_disp_222", "mout_aclk_disp_222",
1723                         DIV_TOP_DISP, 4, 3),
1724         DIV(TOP_DOUT_SCLK_DISP_PIXEL, "dout_sclk_disp_pixel",
1725                         "mout_sclk_disp_pixel", DIV_TOP_DISP, 8, 3),
1726
1727         DIV(TOP_DOUT_ACLK_BUS1_400, "dout_aclk_bus1_400",
1728                         "mout_bus1_bustop_400", DIV_TOP_BUS, 0, 3),
1729         DIV(TOP_DOUT_ACLK_BUS1_100, "dout_aclk_bus1_100",
1730                         "mout_bus1_bustop_100", DIV_TOP_BUS, 4, 4),
1731         DIV(TOP_DOUT_ACLK_BUS2_400, "dout_aclk_bus2_400",
1732                         "mout_bus2_bustop_400", DIV_TOP_BUS, 8, 3),
1733         DIV(TOP_DOUT_ACLK_BUS2_100, "dout_aclk_bus2_100",
1734                         "mout_bus2_bustop_100", DIV_TOP_BUS, 12, 4),
1735         DIV(TOP_DOUT_ACLK_BUS3_400, "dout_aclk_bus3_400",
1736                         "mout_bus3_bustop_400", DIV_TOP_BUS, 16, 3),
1737         DIV(TOP_DOUT_ACLK_BUS3_100, "dout_aclk_bus3_100",
1738                         "mout_bus3_bustop_100", DIV_TOP_BUS, 20, 4),
1739         DIV(TOP_DOUT_ACLK_BUS4_400, "dout_aclk_bus4_400",
1740                         "mout_bus4_bustop_400", DIV_TOP_BUS, 24, 3),
1741         DIV(TOP_DOUT_ACLK_BUS4_100, "dout_aclk_bus4_100",
1742                         "mout_bus4_bustop_100", DIV_TOP_BUS, 28, 4),
1743
1744         DIV(TOP_DOUT_SCLK_PERI_SPI0_A, "dout_sclk_peri_spi0_a",
1745                         "mout_sclk_peri_spi0_clk", DIV_TOP_PERI0, 4, 4),
1746         DIV(TOP_DOUT_SCLK_PERI_SPI0_B, "dout_sclk_peri_spi0_b",
1747                         "dout_sclk_peri_spi0_a", DIV_TOP_PERI0, 8, 8),
1748         DIV(TOP_DOUT_SCLK_PERI_SPI1_A, "dout_sclk_peri_spi1_a",
1749                         "mout_sclk_peri_spi1_clk", DIV_TOP_PERI0, 16, 4),
1750         DIV(TOP_DOUT_SCLK_PERI_SPI1_B, "dout_sclk_peri_spi1_b",
1751                         "dout_sclk_peri_spi1_a", DIV_TOP_PERI0, 20, 8),
1752
1753         DIV(TOP_DOUT_SCLK_PERI_SPI2_A, "dout_sclk_peri_spi2_a",
1754                         "mout_sclk_peri_spi2_clk", DIV_TOP_PERI1, 0, 4),
1755         DIV(TOP_DOUT_SCLK_PERI_SPI2_B, "dout_sclk_peri_spi2_b",
1756                         "dout_sclk_peri_spi2_a", DIV_TOP_PERI1, 4, 8),
1757         DIV(TOP_DOUT_SCLK_PERI_UART1, "dout_sclk_peri_uart1",
1758                         "mout_sclk_peri_uart1_uclk", DIV_TOP_PERI1, 16, 4),
1759         DIV(TOP_DOUT_SCLK_PERI_UART2, "dout_sclk_peri_uart2",
1760                         "mout_sclk_peri_uart2_uclk", DIV_TOP_PERI1, 20, 4),
1761         DIV(TOP_DOUT_SCLK_PERI_UART0, "dout_sclk_peri_uart0",
1762                         "mout_sclk_peri_uart0_uclk", DIV_TOP_PERI1, 24, 4),
1763
1764         DIV(TOP_DOUT_ACLK_PERI_66, "dout_aclk_peri_66", "mout_bustop_pll_user",
1765                         DIV_TOP_PERI2, 20, 4),
1766         DIV(TOP_DOUT_ACLK_PERI_AUD, "dout_aclk_peri_aud",
1767                         "mout_audtop_pll_user", DIV_TOP_PERI2, 24, 3),
1768
1769         DIV(TOP_DOUT_ACLK_FSYS_200, "dout_aclk_fsys_200",
1770                         "mout_bustop_pll_user", DIV_TOP_FSYS0, 0, 3),
1771         DIV(TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK,
1772                         "dout_sclk_fsys_usbdrd30_suspend_clk",
1773                         "mout_sclk_fsys_usb", DIV_TOP_FSYS0, 4, 4),
1774         DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "dout_sclk_fsys_mmc0_sdclkin_a",
1775                         "mout_sclk_fsys_mmc0_sdclkin_b",
1776                         DIV_TOP_FSYS0, 12, 4),
1777         DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "dout_sclk_fsys_mmc0_sdclkin_b",
1778                         "dout_sclk_fsys_mmc0_sdclkin_a",
1779                         DIV_TOP_FSYS0, 16, 8),
1780
1781
1782         DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "dout_sclk_fsys_mmc1_sdclkin_a",
1783                         "mout_sclk_fsys_mmc1_sdclkin_b",
1784                         DIV_TOP_FSYS1, 0, 4),
1785         DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "dout_sclk_fsys_mmc1_sdclkin_b",
1786                         "dout_sclk_fsys_mmc1_sdclkin_a",
1787                         DIV_TOP_FSYS1, 4, 8),
1788         DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "dout_sclk_fsys_mmc2_sdclkin_a",
1789                         "mout_sclk_fsys_mmc2_sdclkin_b",
1790                         DIV_TOP_FSYS1, 12, 4),
1791         DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "dout_sclk_fsys_mmc2_sdclkin_b",
1792                         "dout_sclk_fsys_mmc2_sdclkin_a",
1793                         DIV_TOP_FSYS1, 16, 8),
1794
1795 };
1796
1797 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
1798         GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin",
1799                         "dout_sclk_fsys_mmc0_sdclkin_b",
1800                         EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0),
1801         GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin",
1802                         "dout_sclk_fsys_mmc1_sdclkin_b",
1803                         EN_SCLK_TOP, 8, CLK_SET_RATE_PARENT, 0),
1804         GATE(TOP_SCLK_MMC2, "sclk_fsys_mmc2_sdclkin",
1805                         "dout_sclk_fsys_mmc2_sdclkin_b",
1806                         EN_SCLK_TOP, 9, CLK_SET_RATE_PARENT, 0),
1807         GATE(TOP_SCLK_FIMD1, "sclk_disp_pixel", "dout_sclk_disp_pixel",
1808                         EN_ACLK_TOP, 10, CLK_IGNORE_UNUSED |
1809                         CLK_SET_RATE_PARENT, 0),
1810 };
1811
1812 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
1813         PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll",
1814                 DISP_PLL_LOCK, DISP_PLL_CON0,
1815                 pll2550_24mhz_tbl),
1816         PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll",
1817                 AUD_PLL_LOCK, AUD_PLL_CON0,
1818                 pll2650_24mhz_tbl),
1819 };
1820
1821 static const struct samsung_cmu_info top_cmu __initconst = {
1822         .pll_clks       = top_pll_clks,
1823         .nr_pll_clks    = ARRAY_SIZE(top_pll_clks),
1824         .mux_clks       = top_mux_clks,
1825         .nr_mux_clks    = ARRAY_SIZE(top_mux_clks),
1826         .div_clks       = top_div_clks,
1827         .nr_div_clks    = ARRAY_SIZE(top_div_clks),
1828         .gate_clks      = top_gate_clks,
1829         .nr_gate_clks   = ARRAY_SIZE(top_gate_clks),
1830         .fixed_clks     = fixed_rate_clks,
1831         .nr_fixed_clks  = ARRAY_SIZE(fixed_rate_clks),
1832         .nr_clk_ids     = TOP_NR_CLK,
1833         .clk_regs       = top_clk_regs,
1834         .nr_clk_regs    = ARRAY_SIZE(top_clk_regs),
1835 };
1836
1837 static void __init exynos5260_clk_top_init(struct device_node *np)
1838 {
1839         samsung_cmu_register_one(np, &top_cmu);
1840 }
1841
1842 CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top",
1843                 exynos5260_clk_top_init);