drivers/clk/rockchip/clk-rk3288.c

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk-provider.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <dt-bindings/clock/rk3288-cru.h>
  20 #include "clk.h"
  21
  22 #define RK3288_GRF_SOC_CON(x)   (0x244 + x * 4)
  23 #define RK3288_GRF_SOC_STATUS1  0x284
  24
  25 enum rk3288_plls {
  26         apll, dpll, cpll, gpll, npll,
  27 };
  28
  29 struct rockchip_pll_rate_table rk3288_pll_rates[] = {
  30         RK3066_PLL_RATE(2208000000, 1, 92, 1),
  31         RK3066_PLL_RATE(2184000000, 1, 91, 1),
  32         RK3066_PLL_RATE(2160000000, 1, 90, 1),
  33         RK3066_PLL_RATE(2136000000, 1, 89, 1),
  34         RK3066_PLL_RATE(2112000000, 1, 88, 1),
  35         RK3066_PLL_RATE(2088000000, 1, 87, 1),
  36         RK3066_PLL_RATE(2064000000, 1, 86, 1),
  37         RK3066_PLL_RATE(2040000000, 1, 85, 1),
  38         RK3066_PLL_RATE(2016000000, 1, 84, 1),
  39         RK3066_PLL_RATE(1992000000, 1, 83, 1),
  40         RK3066_PLL_RATE(1968000000, 1, 82, 1),
  41         RK3066_PLL_RATE(1944000000, 1, 81, 1),
  42         RK3066_PLL_RATE(1920000000, 1, 80, 1),
  43         RK3066_PLL_RATE(1896000000, 1, 79, 1),
  44         RK3066_PLL_RATE(1872000000, 1, 78, 1),
  45         RK3066_PLL_RATE(1848000000, 1, 77, 1),
  46         RK3066_PLL_RATE(1824000000, 1, 76, 1),
  47         RK3066_PLL_RATE(1800000000, 1, 75, 1),
  48         RK3066_PLL_RATE(1776000000, 1, 74, 1),
  49         RK3066_PLL_RATE(1752000000, 1, 73, 1),
  50         RK3066_PLL_RATE(1728000000, 1, 72, 1),
  51         RK3066_PLL_RATE(1704000000, 1, 71, 1),
  52         RK3066_PLL_RATE(1680000000, 1, 70, 1),
  53         RK3066_PLL_RATE(1656000000, 1, 69, 1),
  54         RK3066_PLL_RATE(1632000000, 1, 68, 1),
  55         RK3066_PLL_RATE(1608000000, 1, 67, 1),
  56         RK3066_PLL_RATE(1560000000, 1, 65, 1),
  57         RK3066_PLL_RATE(1512000000, 1, 63, 1),
  58         RK3066_PLL_RATE(1488000000, 1, 62, 1),
  59         RK3066_PLL_RATE(1464000000, 1, 61, 1),
  60         RK3066_PLL_RATE(1440000000, 1, 60, 1),
  61         RK3066_PLL_RATE(1416000000, 1, 59, 1),
  62         RK3066_PLL_RATE(1392000000, 1, 58, 1),
  63         RK3066_PLL_RATE(1368000000, 1, 57, 1),
  64         RK3066_PLL_RATE(1344000000, 1, 56, 1),
  65         RK3066_PLL_RATE(1320000000, 1, 55, 1),
  66         RK3066_PLL_RATE(1296000000, 1, 54, 1),
  67         RK3066_PLL_RATE(1272000000, 1, 53, 1),
  68         RK3066_PLL_RATE(1248000000, 1, 52, 1),
  69         RK3066_PLL_RATE(1224000000, 1, 51, 1),
  70         RK3066_PLL_RATE(1200000000, 1, 50, 1),
  71         RK3066_PLL_RATE(1188000000, 2, 99, 1),
  72         RK3066_PLL_RATE(1176000000, 1, 49, 1),
  73         RK3066_PLL_RATE(1128000000, 1, 47, 1),
  74         RK3066_PLL_RATE(1104000000, 1, 46, 1),
  75         RK3066_PLL_RATE(1008000000, 1, 84, 2),
  76         RK3066_PLL_RATE( 912000000, 1, 76, 2),
  77         RK3066_PLL_RATE( 891000000, 8, 594, 2),
  78         RK3066_PLL_RATE( 888000000, 1, 74, 2),
  79         RK3066_PLL_RATE( 816000000, 1, 68, 2),
  80         RK3066_PLL_RATE( 798000000, 2, 133, 2),
  81         RK3066_PLL_RATE( 792000000, 1, 66, 2),
  82         RK3066_PLL_RATE( 768000000, 1, 64, 2),
  83         RK3066_PLL_RATE( 742500000, 8, 495, 2),
  84         RK3066_PLL_RATE( 696000000, 1, 58, 2),
  85         RK3066_PLL_RATE( 600000000, 1, 50, 2),
  86         RK3066_PLL_RATE( 594000000, 2, 198, 4),
  87         RK3066_PLL_RATE( 552000000, 1, 46, 2),
  88         RK3066_PLL_RATE( 504000000, 1, 84, 4),
  89         RK3066_PLL_RATE( 456000000, 1, 76, 4),
  90         RK3066_PLL_RATE( 408000000, 1, 68, 4),
  91         RK3066_PLL_RATE( 384000000, 2, 128, 4),
  92         RK3066_PLL_RATE( 360000000, 1, 60, 4),
  93         RK3066_PLL_RATE( 312000000, 1, 52, 4),
  94         RK3066_PLL_RATE( 300000000, 1, 50, 4),
  95         RK3066_PLL_RATE( 297000000, 2, 198, 8),
  96         RK3066_PLL_RATE( 252000000, 1, 84, 8),
  97         RK3066_PLL_RATE( 216000000, 1, 72, 8),
  98         RK3066_PLL_RATE( 148500000, 2, 99, 8),
  99         RK3066_PLL_RATE( 126000000, 1, 84, 16),
 100         RK3066_PLL_RATE(  48000000, 1, 64, 32),
 101         { /* sentinel */ },
 102 };
 103
 104 #define RK3288_DIV_ACLK_CORE_M0_MASK    0xf
 105 #define RK3288_DIV_ACLK_CORE_M0_SHIFT   0
 106 #define RK3288_DIV_ACLK_CORE_MP_MASK    0xf
 107 #define RK3288_DIV_ACLK_CORE_MP_SHIFT   4
 108 #define RK3288_DIV_L2RAM_MASK           0x7
 109 #define RK3288_DIV_L2RAM_SHIFT          0
 110 #define RK3288_DIV_ATCLK_MASK           0x1f
 111 #define RK3288_DIV_ATCLK_SHIFT          4
 112 #define RK3288_DIV_PCLK_DBGPRE_MASK     0x1f
 113 #define RK3288_DIV_PCLK_DBGPRE_SHIFT    9
 114
 115 #define RK3288_CLKSEL0(_core_m0, _core_mp)                              \
 116         {                                                               \
 117                 .reg = RK3288_CLKSEL_CON(0),                            \
 118                 .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
 119                                 RK3288_DIV_ACLK_CORE_M0_SHIFT) |        \
 120                        HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
 121                                 RK3288_DIV_ACLK_CORE_MP_SHIFT),         \
 122         }
 123 #define RK3288_CLKSEL37(_l2ram, _atclk, _pclk_dbg_pre)                  \
 124         {                                                               \
 125                 .reg = RK3288_CLKSEL_CON(37),                           \
 126                 .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK,     \
 127                                 RK3288_DIV_L2RAM_SHIFT) |               \
 128                        HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK,     \
 129                                 RK3288_DIV_ATCLK_SHIFT) |               \
 130                        HIWORD_UPDATE(_pclk_dbg_pre,                     \
 131                                 RK3288_DIV_PCLK_DBGPRE_MASK,            \
 132                                 RK3288_DIV_PCLK_DBGPRE_SHIFT),          \
 133         }
 134
 135 #define RK3288_CPUCLK_RATE(_prate, _core_m0, _core_mp, _l2ram, _atclk, _pdbg) \
 136         {                                                               \
 137                 .prate = _prate,                                        \
 138                 .divs = {                                               \
 139                         RK3288_CLKSEL0(_core_m0, _core_mp),             \
 140                         RK3288_CLKSEL37(_l2ram, _atclk, _pdbg),         \
 141                 },                                                      \
 142         }
 143
 144 static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
 145         RK3288_CPUCLK_RATE(1800000000, 2, 4, 2, 4, 4),
 146         RK3288_CPUCLK_RATE(1704000000, 2, 4, 2, 4, 4),
 147         RK3288_CPUCLK_RATE(1608000000, 2, 4, 2, 4, 4),
 148         RK3288_CPUCLK_RATE(1512000000, 2, 4, 2, 4, 4),
 149         RK3288_CPUCLK_RATE(1416000000, 2, 4, 2, 4, 4),
 150         RK3288_CPUCLK_RATE(1200000000, 2, 4, 2, 4, 4),
 151         RK3288_CPUCLK_RATE(1008000000, 2, 4, 2, 4, 4),
 152         RK3288_CPUCLK_RATE( 816000000, 2, 4, 2, 4, 4),
 153         RK3288_CPUCLK_RATE( 696000000, 2, 4, 2, 4, 4),
 154         RK3288_CPUCLK_RATE( 600000000, 2, 4, 2, 4, 4),
 155         RK3288_CPUCLK_RATE( 408000000, 2, 4, 2, 4, 4),
 156         RK3288_CPUCLK_RATE( 312000000, 2, 4, 2, 4, 4),
 157         RK3288_CPUCLK_RATE( 216000000, 2, 4, 2, 4, 4),
 158         RK3288_CPUCLK_RATE( 126000000, 2, 4, 2, 4, 4),
 159 };
 160
 161 static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
 162         .core_reg = RK3288_CLKSEL_CON(0),
 163         .div_core_shift = 8,
 164         .div_core_mask = 0x1f,
 165         .mux_core_shift = 15,
 166 };
 167
 168 PNAME(mux_pll_p)                = { "xin24m", "xin32k" };
 169 PNAME(mux_armclk_p)             = { "apll_core", "gpll_core" };
 170 PNAME(mux_ddrphy_p)             = { "dpll_ddr", "gpll_ddr" };
 171 PNAME(mux_aclk_cpu_src_p)       = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
 172
 173 PNAME(mux_pll_src_cpll_gpll_p)          = { "cpll", "gpll" };
 174 PNAME(mux_pll_src_npll_cpll_gpll_p)     = { "npll", "cpll", "gpll" };
 175 PNAME(mux_pll_src_cpll_gpll_npll_p)     = { "cpll", "gpll", "npll" };
 176 PNAME(mux_pll_src_cpll_gpll_usb480m_p)  = { "cpll", "gpll", "usb480m" };
 177
 178 PNAME(mux_mmc_src_p)    = { "cpll", "gpll", "xin24m", "xin24m" };
 179 PNAME(mux_i2s_pre_p)    = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
 180 PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
 181 PNAME(mux_spdif_p)      = { "spdif_pre", "spdif_frac", "xin12m" };
 182 PNAME(mux_spdif_8ch_p)  = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };
 183 PNAME(mux_uart0_pll_p)  = { "cpll", "gpll", "usbphy_480m_src", "npll" };
 184 PNAME(mux_uart0_p)      = { "uart0_src", "uart0_frac", "xin24m" };
 185 PNAME(mux_uart1_p)      = { "uart1_src", "uart1_frac", "xin24m" };
 186 PNAME(mux_uart2_p)      = { "uart2_src", "uart2_frac", "xin24m" };
 187 PNAME(mux_uart3_p)      = { "uart3_src", "uart3_frac", "xin24m" };
 188 PNAME(mux_uart4_p)      = { "uart4_src", "uart4_frac", "xin24m" };
 189 PNAME(mux_cif_out_p)    = { "cif_src", "xin24m" };
 190 PNAME(mux_macref_p)     = { "mac_src", "ext_gmac" };
 191 PNAME(mux_hsadcout_p)   = { "hsadc_src", "ext_hsadc" };
 192 PNAME(mux_edp_24m_p)    = { "ext_edp_24m", "xin24m" };
 193 PNAME(mux_tspout_p)     = { "cpll", "gpll", "npll", "xin27m" };
 194
 195 PNAME(mux_usbphy480m_p)         = { "sclk_otgphy0", "sclk_otgphy1",
 196                                     "sclk_otgphy2" };
 197 PNAME(mux_hsicphy480m_p)        = { "cpll", "gpll", "usbphy480m_src" };
 198 PNAME(mux_hsicphy12m_p)         = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
 199
 200 static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
 201         [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
 202                      RK3288_MODE_CON, 0, 6, rk3288_pll_rates),
 203         [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
 204                      RK3288_MODE_CON, 4, 5, NULL),
 205         [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
 206                      RK3288_MODE_CON, 8, 7, rk3288_pll_rates),
 207         [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
 208                      RK3288_MODE_CON, 12, 8, rk3288_pll_rates),
 209         [npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3288_PLL_CON(16),
 210                      RK3288_MODE_CON, 14, 9, rk3288_pll_rates),
 211 };
 212
 213 static struct clk_div_table div_hclk_cpu_t[] = {
 214         { .val = 0, .div = 1 },
 215         { .val = 1, .div = 2 },
 216         { .val = 3, .div = 4 },
 217         { /* sentinel */},
 218 };
 219
 220 #define MFLAGS CLK_MUX_HIWORD_MASK
 221 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
 222 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
 223
 224 static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 225         /*
 226          * Clock-Architecture Diagram 1
 227          */
 228
 229         GATE(0, "apll_core", "apll", 0,
 230                         RK3288_CLKGATE_CON(0), 1, GFLAGS),
 231         GATE(0, "gpll_core", "gpll", 0,
 232                         RK3288_CLKGATE_CON(0), 2, GFLAGS),
 233
 234         COMPOSITE_NOMUX(0, "armcore0", "armclk", 0,
 235                         RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 236                         RK3288_CLKGATE_CON(12), 0, GFLAGS),
 237         COMPOSITE_NOMUX(0, "armcore1", "armclk", 0,
 238                         RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 239                         RK3288_CLKGATE_CON(12), 1, GFLAGS),
 240         COMPOSITE_NOMUX(0, "armcore2", "armclk", 0,
 241                         RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 242                         RK3288_CLKGATE_CON(12), 2, GFLAGS),
 243         COMPOSITE_NOMUX(0, "armcore3", "armclk", 0,
 244                         RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 245                         RK3288_CLKGATE_CON(12), 3, GFLAGS),
 246         COMPOSITE_NOMUX(0, "l2ram", "armclk", 0,
 247                         RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 248                         RK3288_CLKGATE_CON(12), 4, GFLAGS),
 249         COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", 0,
 250                         RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
 251                         RK3288_CLKGATE_CON(12), 5, GFLAGS),
 252         COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", 0,
 253                         RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
 254                         RK3288_CLKGATE_CON(12), 6, GFLAGS),
 255         COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
 256                         RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 257                         RK3288_CLKGATE_CON(12), 7, GFLAGS),
 258         COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", 0,
 259                         RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 260                         RK3288_CLKGATE_CON(12), 8, GFLAGS),
 261         GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
 262                         RK3288_CLKGATE_CON(12), 9, GFLAGS),
 263         GATE(0, "cs_dbg", "pclk_dbg_pre", 0,
 264                         RK3288_CLKGATE_CON(12), 10, GFLAGS),
 265         GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
 266                         RK3288_CLKGATE_CON(12), 11, GFLAGS),
 267
 268         GATE(0, "dpll_ddr", "dpll", 0,
 269                         RK3288_CLKGATE_CON(0), 8, GFLAGS),
 270         GATE(0, "gpll_ddr", "gpll", 0,
 271                         RK3288_CLKGATE_CON(0), 9, GFLAGS),
 272         COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, 0,
 273                         RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
 274                                         DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
 275
 276         GATE(0, "gpll_aclk_cpu", "gpll", 0,
 277                         RK3288_CLKGATE_CON(0), 10, GFLAGS),
 278         GATE(0, "cpll_aclk_cpu", "cpll", 0,
 279                         RK3288_CLKGATE_CON(0), 11, GFLAGS),
 280         COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
 281                         RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
 282         DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,
 283                         RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
 284         GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
 285                         RK3288_CLKGATE_CON(0), 3, GFLAGS),
 286         COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", 0,
 287                         RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
 288                         RK3288_CLKGATE_CON(0), 5, GFLAGS),
 289         COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", 0,
 290                         RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
 291                         RK3288_CLKGATE_CON(0), 4, GFLAGS),
 292         GATE(0, "c2c_host", "aclk_cpu_src", 0,
 293                         RK3288_CLKGATE_CON(13), 8, GFLAGS),
 294         COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0,
 295                         RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
 296                         RK3288_CLKGATE_CON(5), 4, GFLAGS),
 297         GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", 0,
 298                         RK3288_CLKGATE_CON(0), 7, GFLAGS),
 299
 300         COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
 301                         RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
 302                         RK3288_CLKGATE_CON(4), 1, GFLAGS),
 303         COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
 304                         RK3288_CLKSEL_CON(8), 0,
 305                         RK3288_CLKGATE_CON(4), 2, GFLAGS),
 306         MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
 307                         RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
 308         COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, CLK_SET_RATE_PARENT,
 309                         RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
 310                         RK3288_CLKGATE_CON(4), 0, GFLAGS),
 311         GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
 312                         RK3288_CLKGATE_CON(4), 3, GFLAGS),
 313
 314         MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
 315                         RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
 316         COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", 0,
 317                         RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
 318                         RK3288_CLKGATE_CON(4), 4, GFLAGS),
 319         COMPOSITE_FRAC(0, "spdif_frac", "spdif_src", 0,
 320                         RK3288_CLKSEL_CON(9), 0,
 321                         RK3288_CLKGATE_CON(4), 5, GFLAGS),
 322         COMPOSITE_NODIV(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
 323                         RK3288_CLKSEL_CON(5), 8, 2, MFLAGS,
 324                         RK3288_CLKGATE_CON(4), 6, GFLAGS),
 325         COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", 0,
 326                         RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
 327                         RK3288_CLKGATE_CON(4), 7, GFLAGS),
 328         COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", 0,
 329                         RK3288_CLKSEL_CON(41), 0,
 330                         RK3288_CLKGATE_CON(4), 8, GFLAGS),
 331         COMPOSITE_NODIV(SCLK_SPDIF8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, 0,
 332                         RK3288_CLKSEL_CON(40), 8, 2, MFLAGS,
 333                         RK3288_CLKGATE_CON(4), 9, GFLAGS),
 334
 335         GATE(0, "sclk_acc_efuse", "xin24m", 0,
 336                         RK3288_CLKGATE_CON(0), 12, GFLAGS),
 337
 338         GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
 339                         RK3288_CLKGATE_CON(1), 0, GFLAGS),
 340         GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
 341                         RK3288_CLKGATE_CON(1), 1, GFLAGS),
 342         GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
 343                         RK3288_CLKGATE_CON(1), 2, GFLAGS),
 344         GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
 345                         RK3288_CLKGATE_CON(1), 3, GFLAGS),
 346         GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
 347                         RK3288_CLKGATE_CON(1), 4, GFLAGS),
 348         GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
 349                         RK3288_CLKGATE_CON(1), 5, GFLAGS),
 350
 351         /*
 352          * Clock-Architecture Diagram 2
 353          */
 354
 355         COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb480m_p, 0,
 356                         RK3288_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 5, DFLAGS,
 357                         RK3288_CLKGATE_CON(3), 9, GFLAGS),
 358         COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
 359                         RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
 360                         RK3288_CLKGATE_CON(3), 11, GFLAGS),
 361         /*
 362          * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system,
 363          * so we ignore the mux and make clocks nodes as following,
 364          */
 365         GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0,
 366                 RK3288_CLKGATE_CON(9), 0, GFLAGS),
 367         /*
 368          * We introduce a virtul node of hclk_vodec_pre_v to split one clock
 369          * struct with a gate and a fix divider into two node in software.
 370          */
 371         GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0,
 372                 RK3288_CLKGATE_CON(3), 10, GFLAGS),
 373         GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
 374                 RK3288_CLKGATE_CON(9), 1, GFLAGS),
 375
 376         COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0,
 377                         RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
 378                         RK3288_CLKGATE_CON(3), 0, GFLAGS),
 379         DIV(0, "hclk_vio", "aclk_vio0", 0,
 380                         RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
 381         COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, 0,
 382                         RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
 383                         RK3288_CLKGATE_CON(3), 2, GFLAGS),
 384
 385         COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,
 386                         RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,
 387                         RK3288_CLKGATE_CON(3), 5, GFLAGS),
 388         COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
 389                         RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
 390                         RK3288_CLKGATE_CON(3), 4, GFLAGS),
 391
 392         COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
 393                         RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
 394                         RK3288_CLKGATE_CON(3), 1, GFLAGS),
 395         COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
 396                         RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
 397                         RK3288_CLKGATE_CON(3), 3, GFLAGS),
 398
 399         COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
 400                         RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
 401                         RK3288_CLKGATE_CON(3), 12, GFLAGS),
 402         COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
 403                         RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
 404                         RK3288_CLKGATE_CON(3), 13, GFLAGS),
 405
 406         COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
 407                         RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
 408                         RK3288_CLKGATE_CON(3), 14, GFLAGS),
 409         COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
 410                         RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
 411                         RK3288_CLKGATE_CON(3), 15, GFLAGS),
 412
 413         GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
 414                         RK3288_CLKGATE_CON(5), 12, GFLAGS),
 415         GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
 416                         RK3288_CLKGATE_CON(5), 11, GFLAGS),
 417
 418         COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
 419                         RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
 420                         RK3288_CLKGATE_CON(13), 13, GFLAGS),
 421         DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
 422                         RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
 423
 424         COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
 425                         RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
 426                         RK3288_CLKGATE_CON(13), 14, GFLAGS),
 427         COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
 428                         RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
 429                         RK3288_CLKGATE_CON(13), 15, GFLAGS),
 430
 431         COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
 432                         RK3288_CLKSEL_CON(26), 8, 1, MFLAGS,
 433                         RK3288_CLKGATE_CON(3), 7, GFLAGS),
 434         COMPOSITE_NOGATE(0, "sclk_vip_out", mux_cif_out_p, 0,
 435                         RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS),
 436
 437         DIV(0, "pclk_pd_alive", "gpll", 0,
 438                         RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
 439         COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", 0,
 440                         RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
 441                         RK3288_CLKGATE_CON(5), 8, GFLAGS),
 442
 443         COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
 444                         RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
 445                         RK3288_CLKGATE_CON(5), 7, GFLAGS),
 446
 447         COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, 0,
 448                         RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
 449                         RK3288_CLKGATE_CON(2), 0, GFLAGS),
 450         COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
 451                         RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 452                         RK3288_CLKGATE_CON(2), 3, GFLAGS),
 453         COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
 454                         RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 455                         RK3288_CLKGATE_CON(2), 2, GFLAGS),
 456         GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
 457                         RK3288_CLKGATE_CON(2), 1, GFLAGS),
 458
 459         /*
 460          * Clock-Architecture Diagram 3
 461          */
 462
 463         COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
 464                         RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
 465                         RK3288_CLKGATE_CON(2), 9, GFLAGS),
 466         COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
 467                         RK3288_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
 468                         RK3288_CLKGATE_CON(2), 10, GFLAGS),
 469         COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
 470                         RK3288_CLKSEL_CON(39), 7, 1, MFLAGS, 0, 7, DFLAGS,
 471                         RK3288_CLKGATE_CON(2), 11, GFLAGS),
 472
 473         COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
 474                         RK3288_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
 475                         RK3288_CLKGATE_CON(13), 0, GFLAGS),
 476         COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
 477                         RK3288_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
 478                         RK3288_CLKGATE_CON(13), 1, GFLAGS),
 479         COMPOSITE(SCLK_SDIO1, "sclk_sdio1", mux_mmc_src_p, 0,
 480                         RK3288_CLKSEL_CON(34), 14, 2, MFLAGS, 8, 6, DFLAGS,
 481                         RK3288_CLKGATE_CON(13), 2, GFLAGS),
 482         COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
 483                         RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
 484                         RK3288_CLKGATE_CON(13), 3, GFLAGS),
 485
 486         COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
 487                         RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
 488                         RK3288_CLKGATE_CON(4), 11, GFLAGS),
 489         COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
 490                         RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
 491                         RK3288_CLKGATE_CON(4), 10, GFLAGS),
 492
 493         GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
 494                         RK3288_CLKGATE_CON(13), 4, GFLAGS),
 495         GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
 496                         RK3288_CLKGATE_CON(13), 5, GFLAGS),
 497         GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", 0,
 498                         RK3288_CLKGATE_CON(13), 6, GFLAGS),
 499         GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", 0,
 500                         RK3288_CLKGATE_CON(13), 7, GFLAGS),
 501
 502         COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
 503                         RK3288_CLKSEL_CON(2), 0, 6, DFLAGS,
 504                         RK3288_CLKGATE_CON(2), 7, GFLAGS),
 505
 506         COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
 507                         RK3288_CLKSEL_CON(24), 8, 8, DFLAGS,
 508                         RK3288_CLKGATE_CON(2), 8, GFLAGS),
 509
 510         GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0,
 511                         RK3288_CLKGATE_CON(5), 13, GFLAGS),
 512
 513         COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
 514                         RK3288_CLKSEL_CON(38), 7, 1, MFLAGS, 0, 5, DFLAGS,
 515                         RK3288_CLKGATE_CON(5), 5, GFLAGS),
 516         COMPOSITE(SCLK_NANDC1, "sclk_nandc1", mux_pll_src_cpll_gpll_p, 0,
 517                         RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
 518                         RK3288_CLKGATE_CON(5), 6, GFLAGS),
 519
 520         COMPOSITE(0, "uart0_src", mux_uart0_pll_p, 0,
 521                         RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
 522                         RK3288_CLKGATE_CON(1), 8, GFLAGS),
 523         COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", 0,
 524                         RK3288_CLKSEL_CON(17), 0,
 525                         RK3288_CLKGATE_CON(1), 9, GFLAGS),
 526         MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, 0,
 527                         RK3288_CLKSEL_CON(13), 8, 2, MFLAGS),
 528         MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
 529                         RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
 530         COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
 531                         RK3288_CLKSEL_CON(14), 0, 7, DFLAGS,
 532                         RK3288_CLKGATE_CON(1), 10, GFLAGS),
 533         COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", 0,
 534                         RK3288_CLKSEL_CON(18), 0,
 535                         RK3288_CLKGATE_CON(1), 11, GFLAGS),
 536         MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, 0,
 537                         RK3288_CLKSEL_CON(14), 8, 2, MFLAGS),
 538         COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
 539                         RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
 540                         RK3288_CLKGATE_CON(1), 12, GFLAGS),
 541         COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", 0,
 542                         RK3288_CLKSEL_CON(19), 0,
 543                         RK3288_CLKGATE_CON(1), 13, GFLAGS),
 544         MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, 0,
 545                         RK3288_CLKSEL_CON(15), 8, 2, MFLAGS),
 546         COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
 547                         RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
 548                         RK3288_CLKGATE_CON(1), 14, GFLAGS),
 549         COMPOSITE_FRAC(0, "uart3_frac", "uart3_src", 0,
 550                         RK3288_CLKSEL_CON(20), 0,
 551                         RK3288_CLKGATE_CON(1), 15, GFLAGS),
 552         MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, 0,
 553                         RK3288_CLKSEL_CON(16), 8, 2, MFLAGS),
 554         COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
 555                         RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
 556                         RK3288_CLKGATE_CON(2), 12, GFLAGS),
 557         COMPOSITE_FRAC(0, "uart4_frac", "uart4_src", 0,
 558                         RK3288_CLKSEL_CON(7), 0,
 559                         RK3288_CLKGATE_CON(2), 13, GFLAGS),
 560         MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, 0,
 561                         RK3288_CLKSEL_CON(3), 8, 2, MFLAGS),
 562
 563         COMPOSITE(0, "mac_src", mux_pll_src_npll_cpll_gpll_p, 0,
 564                         RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
 565                         RK3288_CLKGATE_CON(2), 5, GFLAGS),
 566         MUX(0, "macref", mux_macref_p, 0,
 567                         RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),
 568         GATE(0, "sclk_macref_out", "macref", 0,
 569                         RK3288_CLKGATE_CON(5), 3, GFLAGS),
 570         GATE(SCLK_MACREF, "sclk_macref", "macref", 0,
 571                         RK3288_CLKGATE_CON(5), 2, GFLAGS),
 572         GATE(SCLK_MAC_RX, "sclk_mac_rx", "macref", 0,
 573                         RK3288_CLKGATE_CON(5), 0, GFLAGS),
 574         GATE(SCLK_MAC_TX, "sclk_mac_tx", "macref", 0,
 575                         RK3288_CLKGATE_CON(5), 1, GFLAGS),
 576
 577         COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,
 578                         RK3288_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
 579                         RK3288_CLKGATE_CON(2), 6, GFLAGS),
 580         MUX(SCLK_HSADC, "sclk_hsadc_out", mux_hsadcout_p, 0,
 581                         RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
 582
 583         GATE(0, "jtag", "ext_jtag", 0,
 584                         RK3288_CLKGATE_CON(4), 14, GFLAGS),
 585
 586         COMPOSITE_NODIV(0, "usbphy480m_src", mux_usbphy480m_p, 0,
 587                         RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
 588                         RK3288_CLKGATE_CON(5), 15, GFLAGS),
 589         COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
 590                         RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
 591                         RK3288_CLKGATE_CON(3), 6, GFLAGS),
 592         GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
 593                         RK3288_CLKGATE_CON(13), 9, GFLAGS),
 594         DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
 595                         RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
 596         MUX(SCLK_HSICPHY12M, "sclk_hsicphy12m", mux_hsicphy12m_p, 0,
 597                         RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
 598
 599         /*
 600          * Clock-Architecture Diagram 4
 601          */
 602
 603         /* aclk_cpu gates */
 604         GATE(0, "sclk_intmem0", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 5, GFLAGS),
 605         GATE(0, "sclk_intmem1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 6, GFLAGS),
 606         GATE(0, "sclk_intmem2", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 7, GFLAGS),
 607         GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 12, GFLAGS),
 608         GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 13, GFLAGS),
 609         GATE(0, "aclk_intmem", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 4, GFLAGS),
 610         GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS),
 611         GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS),
 612
 613         /* hclk_cpu gates */
 614         GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS),
 615         GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),
 616         GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 9, GFLAGS),
 617         GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS),
 618         GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS),
 619
 620         /* pclk_cpu gates */
 621         GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS),
 622         GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS),
 623         GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),
 624         GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),
 625         GATE(0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
 626         GATE(0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
 627         GATE(0, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
 628         GATE(0, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
 629         GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
 630         GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
 631         GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
 632         GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
 633         GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS),
 634
 635         /* ddrctrl [DDR Controller PHY clock] gates */
 636         GATE(0, "nclk_ddrupctl0", "ddrphy", 0, RK3288_CLKGATE_CON(11), 4, GFLAGS),
 637         GATE(0, "nclk_ddrupctl1", "ddrphy", 0, RK3288_CLKGATE_CON(11), 5, GFLAGS),
 638
 639         /* ddrphy gates */
 640         GATE(0, "sclk_ddrphy0", "ddrphy", 0, RK3288_CLKGATE_CON(4), 12, GFLAGS),
 641         GATE(0, "sclk_ddrphy1", "ddrphy", 0, RK3288_CLKGATE_CON(4), 13, GFLAGS),
 642
 643         /* aclk_peri gates */
 644         GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 2, GFLAGS),
 645         GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
 646         GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS),
 647         GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 12, GFLAGS),
 648         GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
 649         GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
 650
 651         /* hclk_peri gates */
 652         GATE(0, "hclk_peri_matrix", "hclk_peri", 0, RK3288_CLKGATE_CON(6), 0, GFLAGS),
 653         GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 4, GFLAGS),
 654         GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS),
 655         GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 7, GFLAGS),
 656         GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS),
 657         GATE(0, "hclk_usb_peri", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 9, GFLAGS),
 658         GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 10, GFLAGS),
 659         GATE(0, "hclk_emem", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 12, GFLAGS),
 660         GATE(0, "hclk_mem", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 13, GFLAGS),
 661         GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS),
 662         GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS),
 663         GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS),
 664         GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 3, GFLAGS),
 665         GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 4, GFLAGS),
 666         GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 5, GFLAGS),
 667         GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 6, GFLAGS),
 668         GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 7, GFLAGS),
 669         GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, GFLAGS),
 670
 671         /* pclk_peri gates */
 672         GATE(0, "pclk_peri_matrix", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 1, GFLAGS),
 673         GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),
 674         GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),
 675         GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS),
 676         GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 7, GFLAGS),
 677         GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 8, GFLAGS),
 678         GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 9, GFLAGS),
 679         GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 15, GFLAGS),
 680         GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS),
 681         GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 12, GFLAGS),
 682         GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS),
 683         GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 14, GFLAGS),
 684         GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 1, GFLAGS),
 685         GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 2, GFLAGS),
 686         GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 3, GFLAGS),
 687         GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 0, GFLAGS),
 688         GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3288_CLKGATE_CON(8), 1, GFLAGS),
 689
 690         GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS),
 691         GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
 692         GATE(0, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
 693         GATE(0, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
 694         GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
 695
 696         /* sclk_gpu gates */
 697         GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),
 698
 699         /* pclk_pd_alive gates */
 700         GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 8, GFLAGS),
 701         GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 7, GFLAGS),
 702         GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 1, GFLAGS),
 703         GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 2, GFLAGS),
 704         GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 3, GFLAGS),
 705         GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS),
 706         GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),
 707         GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),
 708         GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 11, GFLAGS),
 709         GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS),
 710
 711         /* pclk_pd_pmu gates */
 712         GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 0, GFLAGS),
 713         GATE(0, "pclk_intmem1", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 1, GFLAGS),
 714         GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 2, GFLAGS),
 715         GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 3, GFLAGS),
 716         GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
 717
 718         /* hclk_vio gates */
 719         GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
 720         GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
 721         GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
 722         GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS),
 723         GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
 724         GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
 725         GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
 726         GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
 727         GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS),
 728         GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
 729         GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
 730         GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
 731         GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
 732         GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS),
 733         GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
 734         GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS),
 735
 736         /* aclk_vio0 gates */
 737         GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
 738         GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
 739         GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
 740         GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
 741
 742         /* aclk_vio1 gates */
 743         GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
 744         GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
 745         GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
 746
 747         /* aclk_rga_pre gates */
 748         GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
 749         GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
 750
 751         /*
 752          * Other ungrouped clocks.
 753          */
 754
 755         GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),
 756         GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
 757 };
 758
 759 static const char *rk3288_critical_clocks[] __initconst = {
 760         "aclk_cpu",
 761         "aclk_peri",
 762         "hclk_peri",
 763 };
 764
 765 static void __init rk3288_clk_init(struct device_node *np)
 766 {
 767         void __iomem *reg_base;
 768         struct clk *clk;
 769
 770         reg_base = of_iomap(np, 0);
 771         if (!reg_base) {
 772                 pr_err("%s: could not map cru region\n", __func__);
 773                 return;
 774         }
 775
 776         rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
 777
 778         /* xin12m is created by an cru-internal divider */
 779         clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
 780         if (IS_ERR(clk))
 781                 pr_warn("%s: could not register clock xin12m: %ld\n",
 782                         __func__, PTR_ERR(clk));
 783
 784
 785         clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
 786         if (IS_ERR(clk))
 787                 pr_warn("%s: could not register clock usb480m: %ld\n",
 788                         __func__, PTR_ERR(clk));
 789
 790         clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre",
 791                                         "hclk_vcodec_pre_v", 0, 1, 4);
 792         if (IS_ERR(clk))
 793                 pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
 794                         __func__, PTR_ERR(clk));
 795
 796         rockchip_clk_register_plls(rk3288_pll_clks,
 797                                    ARRAY_SIZE(rk3288_pll_clks),
 798                                    RK3288_GRF_SOC_STATUS1);
 799         rockchip_clk_register_branches(rk3288_clk_branches,
 800                                   ARRAY_SIZE(rk3288_clk_branches));
 801         rockchip_clk_protect_critical(rk3288_critical_clocks,
 802                                       ARRAY_SIZE(rk3288_critical_clocks));
 803
 804         rockchip_clk_register_armclk(ARMCLK, "armclk",
 805                         mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
 806                         &rk3288_cpuclk_data, rk3288_cpuclk_rates,
 807                         ARRAY_SIZE(rk3288_cpuclk_rates));
 808
 809         rockchip_register_softrst(np, 12, reg_base + RK3288_SOFTRST_CON(0),
 810                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
 811
 812         rockchip_register_restart_notifier(RK3288_GLB_SRST_FST);
 813 }
 814 CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);