2 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
4 * Jeffy Chen <jeffy.chen@rock-chips.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
20 #include <linux/of_address.h>
21 #include <linux/syscore_ops.h>
22 #include <dt-bindings/clock/rk3228-cru.h>
25 #define RK3228_GRF_SOC_STATUS0 0x480
28 apll, dpll, cpll, gpll,
31 static struct rockchip_pll_rate_table rk3228_pll_rates[] = {
32 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
33 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
34 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
54 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
55 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
56 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
57 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
58 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
59 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
60 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
61 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
62 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
63 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
64 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
65 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
66 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
67 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
68 RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
69 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
70 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
71 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
72 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
73 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
74 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
78 #define RK3228_DIV_CPU_MASK 0x1f
79 #define RK3228_DIV_CPU_SHIFT 8
81 #define RK3228_DIV_PERI_MASK 0xf
82 #define RK3228_DIV_PERI_SHIFT 0
83 #define RK3228_DIV_ACLK_MASK 0x7
84 #define RK3228_DIV_ACLK_SHIFT 4
85 #define RK3228_DIV_HCLK_MASK 0x3
86 #define RK3228_DIV_HCLK_SHIFT 8
87 #define RK3228_DIV_PCLK_MASK 0x7
88 #define RK3228_DIV_PCLK_SHIFT 12
90 #define RK3228_CLKSEL1(_core_aclk_div, _core_peri_div) \
92 .reg = RK2928_CLKSEL_CON(1), \
93 .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \
94 RK3228_DIV_PERI_SHIFT) | \
95 HIWORD_UPDATE(_core_aclk_div, RK3228_DIV_ACLK_MASK, \
96 RK3228_DIV_ACLK_SHIFT), \
99 #define RK3228_CPUCLK_RATE(_prate, _core_aclk_div, _core_peri_div) \
103 RK3228_CLKSEL1(_core_aclk_div, _core_peri_div), \
107 static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = {
108 RK3228_CPUCLK_RATE(1800000000, 1, 7),
109 RK3228_CPUCLK_RATE(1704000000, 1, 7),
110 RK3228_CPUCLK_RATE(1608000000, 1, 7),
111 RK3228_CPUCLK_RATE(1512000000, 1, 7),
112 RK3228_CPUCLK_RATE(1488000000, 1, 5),
113 RK3228_CPUCLK_RATE(1416000000, 1, 5),
114 RK3228_CPUCLK_RATE(1392000000, 1, 5),
115 RK3228_CPUCLK_RATE(1296000000, 1, 5),
116 RK3228_CPUCLK_RATE(1200000000, 1, 5),
117 RK3228_CPUCLK_RATE(1104000000, 1, 5),
118 RK3228_CPUCLK_RATE(1008000000, 1, 5),
119 RK3228_CPUCLK_RATE(912000000, 1, 5),
120 RK3228_CPUCLK_RATE(816000000, 1, 3),
121 RK3228_CPUCLK_RATE(696000000, 1, 3),
122 RK3228_CPUCLK_RATE(600000000, 1, 3),
123 RK3228_CPUCLK_RATE(408000000, 1, 1),
124 RK3228_CPUCLK_RATE(312000000, 1, 1),
125 RK3228_CPUCLK_RATE(216000000, 1, 1),
126 RK3228_CPUCLK_RATE(96000000, 1, 1),
129 static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
130 .core_reg = RK2928_CLKSEL_CON(0),
132 .div_core_mask = 0x1f,
136 .mux_core_mask = 0x1,
139 PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
141 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
142 PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
143 PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" };
144 PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
145 PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" };
146 PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
148 PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" };
149 PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" };
150 PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" };
151 PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" };
152 PNAME(mux_aclk_peri_src_p) = { "cpll_peri", "gpll_peri", "hdmiphy_peri" };
153 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" };
154 PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
156 PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" };
158 PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" };
159 PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" };
161 PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
162 PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" };
163 PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" };
164 PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" };
165 PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" };
167 PNAME(mux_aclk_gpu_pre_p) = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" };
169 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
170 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
171 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
173 PNAME(mux_sclk_mac_extclk_p) = { "ext_gmac", "phy_50m_out" };
174 PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_mac_extclk" };
175 PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" };
177 static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
178 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
179 RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates),
180 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3),
181 RK2928_MODE_CON, 4, 6, 0, NULL),
182 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
183 RK2928_MODE_CON, 8, 8, 0, NULL),
184 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
185 RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates),
188 #define MFLAGS CLK_MUX_HIWORD_MASK
189 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
190 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
192 static struct rockchip_clk_branch rk3228_i2s0_fracmux __initdata =
193 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
194 RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
196 static struct rockchip_clk_branch rk3228_i2s1_fracmux __initdata =
197 MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT,
198 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
200 static struct rockchip_clk_branch rk3228_i2s2_fracmux __initdata =
201 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
202 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
204 static struct rockchip_clk_branch rk3228_spdif_fracmux __initdata =
205 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
206 RK2928_CLKSEL_CON(6), 8, 2, MFLAGS);
208 static struct rockchip_clk_branch rk3228_uart0_fracmux __initdata =
209 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
210 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
212 static struct rockchip_clk_branch rk3228_uart1_fracmux __initdata =
213 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
214 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
216 static struct rockchip_clk_branch rk3228_uart2_fracmux __initdata =
217 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
218 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
220 static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
222 * Clock-Architecture Diagram 1
225 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
226 RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
229 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
230 RK2928_CLKGATE_CON(0), 2, GFLAGS),
231 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
232 RK2928_CLKGATE_CON(0), 2, GFLAGS),
233 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
234 RK2928_CLKGATE_CON(0), 2, GFLAGS),
235 COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
236 RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
237 RK2928_CLKGATE_CON(7), 1, GFLAGS),
238 GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
239 RK2928_CLKGATE_CON(8), 5, GFLAGS),
240 FACTOR_GATE(0, "ddrphy", "ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
241 RK2928_CLKGATE_CON(7), 0, GFLAGS),
244 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
245 RK2928_CLKGATE_CON(0), 6, GFLAGS),
246 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
247 RK2928_CLKGATE_CON(0), 6, GFLAGS),
248 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
249 RK2928_CLKGATE_CON(0), 6, GFLAGS),
250 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
251 RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
252 RK2928_CLKGATE_CON(4), 1, GFLAGS),
253 COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED,
254 RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
255 RK2928_CLKGATE_CON(4), 0, GFLAGS),
258 MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
259 RK2928_MISC_CON, 13, 1, MFLAGS),
260 MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
261 RK2928_MISC_CON, 14, 1, MFLAGS),
262 MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
263 RK2928_MISC_CON, 15, 1, MFLAGS),
266 GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED,
267 RK2928_CLKGATE_CON(0), 1, GFLAGS),
268 GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
269 RK2928_CLKGATE_CON(0), 1, GFLAGS),
270 GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
271 RK2928_CLKGATE_CON(0), 1, GFLAGS),
272 COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
273 RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
274 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
275 RK2928_CLKGATE_CON(6), 0, GFLAGS),
276 COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0,
277 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
278 RK2928_CLKGATE_CON(6), 1, GFLAGS),
279 COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0,
280 RK2928_CLKSEL_CON(1), 12, 3, DFLAGS,
281 RK2928_CLKGATE_CON(6), 2, GFLAGS),
282 GATE(PCLK_CPU, "pclk_cpu", "pclk_bus_src", 0,
283 RK2928_CLKGATE_CON(6), 3, GFLAGS),
284 GATE(0, "pclk_phy_pre", "pclk_bus_src", 0,
285 RK2928_CLKGATE_CON(6), 4, GFLAGS),
286 GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0,
287 RK2928_CLKGATE_CON(6), 13, GFLAGS),
290 COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
291 RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS,
292 RK2928_CLKGATE_CON(3), 11, GFLAGS),
293 FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
294 RK2928_CLKGATE_CON(4), 4, GFLAGS),
296 COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
297 RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
298 RK2928_CLKGATE_CON(3), 2, GFLAGS),
299 FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
300 RK2928_CLKGATE_CON(4), 5, GFLAGS),
302 COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
303 RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
304 RK2928_CLKGATE_CON(3), 3, GFLAGS),
306 COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_pll_src_4plls_p, 0,
307 RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, 8, 5, DFLAGS,
308 RK2928_CLKGATE_CON(3), 4, GFLAGS),
311 COMPOSITE(ACLK_IEP_PRE, "aclk_iep_pre", mux_pll_src_4plls_p, 0,
312 RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, 0, 5, DFLAGS,
313 RK2928_CLKGATE_CON(3), 0, GFLAGS),
314 DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_iep_pre", 0,
315 RK2928_CLKSEL_CON(2), 0, 5, DFLAGS),
317 COMPOSITE(ACLK_HDCP_PRE, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0,
318 RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, 8, 5, DFLAGS,
319 RK2928_CLKGATE_CON(1), 4, GFLAGS),
321 MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0,
322 RK2928_CLKSEL_CON(33), 13, 2, MFLAGS),
323 COMPOSITE_NOMUX(ACLK_RGA_PRE, "aclk_rga_pre", "sclk_rga_src", 0,
324 RK2928_CLKSEL_CON(33), 8, 5, DFLAGS,
325 RK2928_CLKGATE_CON(1), 2, GFLAGS),
326 COMPOSITE(SCLK_RGA, "sclk_rga", mux_sclk_rga_p, 0,
327 RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS,
328 RK2928_CLKGATE_CON(3), 6, GFLAGS),
330 COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_pll_src_4plls_p, 0,
331 RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, 0, 5, DFLAGS,
332 RK2928_CLKGATE_CON(1), 1, GFLAGS),
334 COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_3plls_p, 0,
335 RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS,
336 RK2928_CLKGATE_CON(3), 5, GFLAGS),
338 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
339 RK2928_CLKGATE_CON(3), 7, GFLAGS),
341 COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
342 RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, 0, 14, DFLAGS,
343 RK2928_CLKGATE_CON(3), 8, GFLAGS),
346 GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
347 RK2928_CLKGATE_CON(2), 0, GFLAGS),
348 GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
349 RK2928_CLKGATE_CON(2), 0, GFLAGS),
350 GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
351 RK2928_CLKGATE_CON(2), 0, GFLAGS),
352 COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
353 RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS),
354 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
355 RK2928_CLKSEL_CON(10), 12, 3, DFLAGS,
356 RK2928_CLKGATE_CON(5), 2, GFLAGS),
357 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
358 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS,
359 RK2928_CLKGATE_CON(5), 1, GFLAGS),
360 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
361 RK2928_CLKGATE_CON(5), 0, GFLAGS),
363 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
364 RK2928_CLKGATE_CON(6), 5, GFLAGS),
365 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
366 RK2928_CLKGATE_CON(6), 6, GFLAGS),
367 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
368 RK2928_CLKGATE_CON(6), 7, GFLAGS),
369 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
370 RK2928_CLKGATE_CON(6), 8, GFLAGS),
371 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
372 RK2928_CLKGATE_CON(6), 9, GFLAGS),
373 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
374 RK2928_CLKGATE_CON(6), 10, GFLAGS),
376 COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0,
377 RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, 0, 5, DFLAGS,
378 RK2928_CLKGATE_CON(2), 7, GFLAGS),
380 COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_2plls_p, 0,
381 RK2928_CLKSEL_CON(22), 15, 1, MFLAGS, 8, 5, DFLAGS,
382 RK2928_CLKGATE_CON(2), 6, GFLAGS),
384 GATE(SCLK_HSADC, "sclk_hsadc", "ext_hsadc", 0,
385 RK2928_CLKGATE_CON(10), 12, GFLAGS),
387 COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
388 RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
389 RK2928_CLKGATE_CON(2), 15, GFLAGS),
391 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
392 RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
393 RK2928_CLKGATE_CON(2), 11, GFLAGS),
395 COMPOSITE_NODIV(SCLK_SDIO_SRC, "sclk_sdio_src", mux_mmc_src_p, 0,
396 RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
397 RK2928_CLKGATE_CON(2), 13, GFLAGS),
398 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
399 RK2928_CLKSEL_CON(12), 0, 8, DFLAGS),
401 COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
402 RK2928_CLKSEL_CON(11), 12, 2, MFLAGS,
403 RK2928_CLKGATE_CON(2), 14, GFLAGS),
404 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
405 RK2928_CLKSEL_CON(12), 8, 8, DFLAGS),
408 * Clock-Architecture Diagram 2
411 GATE(0, "gpll_vop", "gpll", 0,
412 RK2928_CLKGATE_CON(3), 1, GFLAGS),
413 GATE(0, "cpll_vop", "cpll", 0,
414 RK2928_CLKGATE_CON(3), 1, GFLAGS),
415 MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
416 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS),
417 DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0,
418 RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
419 DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
420 RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
421 MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,
422 RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
424 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
426 COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
427 RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS,
428 RK2928_CLKGATE_CON(0), 3, GFLAGS),
429 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
430 RK2928_CLKSEL_CON(8), 0,
431 RK2928_CLKGATE_CON(0), 4, GFLAGS,
432 &rk3228_i2s0_fracmux),
433 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
434 RK2928_CLKGATE_CON(0), 5, GFLAGS),
436 COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
437 RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS,
438 RK2928_CLKGATE_CON(0), 10, GFLAGS),
439 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
440 RK2928_CLKSEL_CON(7), 0,
441 RK2928_CLKGATE_CON(0), 11, GFLAGS,
442 &rk3228_i2s1_fracmux),
443 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
444 RK2928_CLKGATE_CON(0), 14, GFLAGS),
445 COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
446 RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
447 RK2928_CLKGATE_CON(0), 13, GFLAGS),
449 COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
450 RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS,
451 RK2928_CLKGATE_CON(0), 7, GFLAGS),
452 COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
453 RK2928_CLKSEL_CON(30), 0,
454 RK2928_CLKGATE_CON(0), 8, GFLAGS,
455 &rk3228_i2s2_fracmux),
456 GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
457 RK2928_CLKGATE_CON(0), 9, GFLAGS),
459 COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0,
460 RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
461 RK2928_CLKGATE_CON(2), 10, GFLAGS),
462 COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
463 RK2928_CLKSEL_CON(20), 0,
464 RK2928_CLKGATE_CON(2), 12, GFLAGS,
465 &rk3228_spdif_fracmux),
467 GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
468 RK2928_CLKGATE_CON(1), 3, GFLAGS),
470 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0,
471 RK2928_CLKGATE_CON(1), 5, GFLAGS),
472 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", 0,
473 RK2928_CLKGATE_CON(1), 6, GFLAGS),
475 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
476 RK2928_CLKSEL_CON(24), 6, 10, DFLAGS,
477 RK2928_CLKGATE_CON(2), 8, GFLAGS),
479 GATE(0, "cpll_gpu", "cpll", 0,
480 RK2928_CLKGATE_CON(3), 13, GFLAGS),
481 GATE(0, "gpll_gpu", "gpll", 0,
482 RK2928_CLKGATE_CON(3), 13, GFLAGS),
483 GATE(0, "hdmiphy_gpu", "hdmiphy", 0,
484 RK2928_CLKGATE_CON(3), 13, GFLAGS),
485 GATE(0, "usb480m_gpu", "usb480m", 0,
486 RK2928_CLKGATE_CON(3), 13, GFLAGS),
487 COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0,
488 RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS),
490 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0,
491 RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS,
492 RK2928_CLKGATE_CON(2), 9, GFLAGS),
495 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
496 RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
497 RK2928_CLKGATE_CON(1), 8, GFLAGS),
498 COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
499 RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
500 RK2928_CLKGATE_CON(1), 10, GFLAGS),
501 COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p,
502 0, RK2928_CLKSEL_CON(15), 12, 2,
503 MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS),
504 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
505 RK2928_CLKSEL_CON(17), 0,
506 RK2928_CLKGATE_CON(1), 9, GFLAGS,
507 &rk3228_uart0_fracmux),
508 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
509 RK2928_CLKSEL_CON(18), 0,
510 RK2928_CLKGATE_CON(1), 11, GFLAGS,
511 &rk3228_uart1_fracmux),
512 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
513 RK2928_CLKSEL_CON(19), 0,
514 RK2928_CLKGATE_CON(1), 13, GFLAGS,
515 &rk3228_uart2_fracmux),
517 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
518 RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS,
519 RK2928_CLKGATE_CON(1), 0, GFLAGS),
521 COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_2plls_p, 0,
522 RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS,
523 RK2928_CLKGATE_CON(1), 7, GFLAGS),
524 MUX(SCLK_MAC_EXTCLK, "sclk_mac_extclk", mux_sclk_mac_extclk_p, 0,
525 RK2928_CLKSEL_CON(29), 10, 1, MFLAGS),
526 MUX(SCLK_MAC, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0,
527 RK2928_CLKSEL_CON(5), 5, 1, MFLAGS),
528 GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac_pre", 0,
529 RK2928_CLKGATE_CON(5), 4, GFLAGS),
530 GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac_pre", 0,
531 RK2928_CLKGATE_CON(5), 3, GFLAGS),
532 GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac_pre", 0,
533 RK2928_CLKGATE_CON(5), 5, GFLAGS),
534 GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac_pre", 0,
535 RK2928_CLKGATE_CON(5), 6, GFLAGS),
536 COMPOSITE(SCLK_MAC_PHY, "sclk_macphy", mux_sclk_macphy_p, 0,
537 RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS,
538 RK2928_CLKGATE_CON(5), 7, GFLAGS),
539 COMPOSITE(SCLK_MAC_OUT, "sclk_gmac_out", mux_pll_src_2plls_p, 0,
540 RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS,
541 RK2928_CLKGATE_CON(2), 2, GFLAGS),
544 * Clock-Architecture Diagram 3
548 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
549 GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS),
550 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
551 GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),
553 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
554 GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),
556 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
557 GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),
559 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
560 GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
561 GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
562 GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),
563 GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),
564 GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),
565 GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
566 GATE(HCLK_HDCP_MMU, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
567 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
568 GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
569 GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
572 GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS),
573 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS),
575 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 0, GFLAGS),
576 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS),
577 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),
578 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
579 GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
580 GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS),
581 GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
582 GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS),
583 GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
584 GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
585 GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS),
586 GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),
587 GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
589 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
590 GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS),
593 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),
594 GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS),
597 GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
598 GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
599 GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
600 GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
602 GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
603 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
604 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
605 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
606 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
607 GATE(HCLK_TSP, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
608 GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
609 GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
611 GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
612 GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
613 GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
615 GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
616 GATE(PCLK_EFUSE_256, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
617 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
618 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
619 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
620 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
621 GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS),
622 GATE(0, "pclk_stimer", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
623 GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
624 GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
625 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
626 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS),
627 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 10, GFLAGS),
628 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 11, GFLAGS),
629 GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS),
630 GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS),
631 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS),
632 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS),
633 GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS),
634 GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
635 GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
636 GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
638 GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
639 GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
640 GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
641 GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
642 GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
644 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
645 GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS),
646 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
647 GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS),
648 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
649 GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS),
650 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
651 GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS),
654 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
655 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0),
657 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1),
658 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0),
660 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1),
661 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0),
664 static const char *const rk3228_critical_clocks[] __initconst = {
683 "sclk_initmem_mbist",
699 static void __init rk3228_clk_init(struct device_node *np)
701 struct rockchip_clk_provider *ctx;
702 void __iomem *reg_base;
704 reg_base = of_iomap(np, 0);
706 pr_err("%s: could not map cru region\n", __func__);
710 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
712 pr_err("%s: rockchip clk init failed\n", __func__);
717 rockchip_clk_register_plls(ctx, rk3228_pll_clks,
718 ARRAY_SIZE(rk3228_pll_clks),
719 RK3228_GRF_SOC_STATUS0);
720 rockchip_clk_register_branches(ctx, rk3228_clk_branches,
721 ARRAY_SIZE(rk3228_clk_branches));
722 rockchip_clk_protect_critical(rk3228_critical_clocks,
723 ARRAY_SIZE(rk3228_critical_clocks));
725 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
726 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
727 &rk3228_cpuclk_data, rk3228_cpuclk_rates,
728 ARRAY_SIZE(rk3228_cpuclk_rates));
730 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
731 ROCKCHIP_SOFTRST_HIWORD_MASK);
733 rockchip_register_restart_notifier(ctx, RK3228_GLB_SRST_FST, NULL);
735 rockchip_clk_of_add_provider(np, ctx);
737 CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init);