2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
20 #include <linux/of_address.h>
21 #include <dt-bindings/clock/rk3188-cru-common.h>
24 #define RK3066_GRF_SOC_STATUS 0x15c
25 #define RK3188_GRF_SOC_STATUS 0xac
28 apll, cpll, dpll, gpll,
31 static struct rockchip_pll_rate_table rk3188_pll_rates[] = {
32 RK3066_PLL_RATE(2208000000, 1, 92, 1),
33 RK3066_PLL_RATE(2184000000, 1, 91, 1),
34 RK3066_PLL_RATE(2160000000, 1, 90, 1),
35 RK3066_PLL_RATE(2136000000, 1, 89, 1),
36 RK3066_PLL_RATE(2112000000, 1, 88, 1),
37 RK3066_PLL_RATE(2088000000, 1, 87, 1),
38 RK3066_PLL_RATE(2064000000, 1, 86, 1),
39 RK3066_PLL_RATE(2040000000, 1, 85, 1),
40 RK3066_PLL_RATE(2016000000, 1, 84, 1),
41 RK3066_PLL_RATE(1992000000, 1, 83, 1),
42 RK3066_PLL_RATE(1968000000, 1, 82, 1),
43 RK3066_PLL_RATE(1944000000, 1, 81, 1),
44 RK3066_PLL_RATE(1920000000, 1, 80, 1),
45 RK3066_PLL_RATE(1896000000, 1, 79, 1),
46 RK3066_PLL_RATE(1872000000, 1, 78, 1),
47 RK3066_PLL_RATE(1848000000, 1, 77, 1),
48 RK3066_PLL_RATE(1824000000, 1, 76, 1),
49 RK3066_PLL_RATE(1800000000, 1, 75, 1),
50 RK3066_PLL_RATE(1776000000, 1, 74, 1),
51 RK3066_PLL_RATE(1752000000, 1, 73, 1),
52 RK3066_PLL_RATE(1728000000, 1, 72, 1),
53 RK3066_PLL_RATE(1704000000, 1, 71, 1),
54 RK3066_PLL_RATE(1680000000, 1, 70, 1),
55 RK3066_PLL_RATE(1656000000, 1, 69, 1),
56 RK3066_PLL_RATE(1632000000, 1, 68, 1),
57 RK3066_PLL_RATE(1608000000, 1, 67, 1),
58 RK3066_PLL_RATE(1560000000, 1, 65, 1),
59 RK3066_PLL_RATE(1512000000, 1, 63, 1),
60 RK3066_PLL_RATE(1488000000, 1, 62, 1),
61 RK3066_PLL_RATE(1464000000, 1, 61, 1),
62 RK3066_PLL_RATE(1440000000, 1, 60, 1),
63 RK3066_PLL_RATE(1416000000, 1, 59, 1),
64 RK3066_PLL_RATE(1392000000, 1, 58, 1),
65 RK3066_PLL_RATE(1368000000, 1, 57, 1),
66 RK3066_PLL_RATE(1344000000, 1, 56, 1),
67 RK3066_PLL_RATE(1320000000, 1, 55, 1),
68 RK3066_PLL_RATE(1296000000, 1, 54, 1),
69 RK3066_PLL_RATE(1272000000, 1, 53, 1),
70 RK3066_PLL_RATE(1248000000, 1, 52, 1),
71 RK3066_PLL_RATE(1224000000, 1, 51, 1),
72 RK3066_PLL_RATE(1200000000, 1, 50, 1),
73 RK3066_PLL_RATE(1188000000, 2, 99, 1),
74 RK3066_PLL_RATE(1176000000, 1, 49, 1),
75 RK3066_PLL_RATE(1128000000, 1, 47, 1),
76 RK3066_PLL_RATE(1104000000, 1, 46, 1),
77 RK3066_PLL_RATE(1008000000, 1, 84, 2),
78 RK3066_PLL_RATE( 912000000, 1, 76, 2),
79 RK3066_PLL_RATE( 891000000, 8, 594, 2),
80 RK3066_PLL_RATE( 888000000, 1, 74, 2),
81 RK3066_PLL_RATE( 816000000, 1, 68, 2),
82 RK3066_PLL_RATE( 798000000, 2, 133, 2),
83 RK3066_PLL_RATE( 792000000, 1, 66, 2),
84 RK3066_PLL_RATE( 768000000, 1, 64, 2),
85 RK3066_PLL_RATE( 742500000, 8, 495, 2),
86 RK3066_PLL_RATE( 696000000, 1, 58, 2),
87 RK3066_PLL_RATE( 600000000, 1, 50, 2),
88 RK3066_PLL_RATE( 594000000, 2, 198, 4),
89 RK3066_PLL_RATE( 552000000, 1, 46, 2),
90 RK3066_PLL_RATE( 504000000, 1, 84, 4),
91 RK3066_PLL_RATE( 456000000, 1, 76, 4),
92 RK3066_PLL_RATE( 408000000, 1, 68, 4),
93 RK3066_PLL_RATE( 400000000, 3, 100, 2),
94 RK3066_PLL_RATE( 384000000, 2, 128, 4),
95 RK3066_PLL_RATE( 360000000, 1, 60, 4),
96 RK3066_PLL_RATE( 312000000, 1, 52, 4),
97 RK3066_PLL_RATE( 300000000, 1, 50, 4),
98 RK3066_PLL_RATE( 297000000, 2, 198, 8),
99 RK3066_PLL_RATE( 252000000, 1, 84, 8),
100 RK3066_PLL_RATE( 216000000, 1, 72, 8),
101 RK3066_PLL_RATE( 148500000, 2, 99, 8),
102 RK3066_PLL_RATE( 126000000, 1, 84, 16),
103 RK3066_PLL_RATE( 48000000, 1, 64, 32),
107 #define RK3066_DIV_CORE_PERIPH_MASK 0x3
108 #define RK3066_DIV_CORE_PERIPH_SHIFT 6
109 #define RK3066_DIV_ACLK_CORE_MASK 0x7
110 #define RK3066_DIV_ACLK_CORE_SHIFT 0
111 #define RK3066_DIV_ACLK_HCLK_MASK 0x3
112 #define RK3066_DIV_ACLK_HCLK_SHIFT 8
113 #define RK3066_DIV_ACLK_PCLK_MASK 0x3
114 #define RK3066_DIV_ACLK_PCLK_SHIFT 12
115 #define RK3066_DIV_AHB2APB_MASK 0x3
116 #define RK3066_DIV_AHB2APB_SHIFT 14
118 #define RK3066_CLKSEL0(_core_peri) \
120 .reg = RK2928_CLKSEL_CON(0), \
121 .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \
122 RK3066_DIV_CORE_PERIPH_SHIFT) \
124 #define RK3066_CLKSEL1(_aclk_core, _aclk_hclk, _aclk_pclk, _ahb2apb) \
126 .reg = RK2928_CLKSEL_CON(1), \
127 .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
128 RK3066_DIV_ACLK_CORE_SHIFT) | \
129 HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \
130 RK3066_DIV_ACLK_HCLK_SHIFT) | \
131 HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \
132 RK3066_DIV_ACLK_PCLK_SHIFT) | \
133 HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \
134 RK3066_DIV_AHB2APB_SHIFT), \
137 #define RK3066_CPUCLK_RATE(_prate, _core_peri, _acore, _ahclk, _apclk, _h2p) \
141 RK3066_CLKSEL0(_core_peri), \
142 RK3066_CLKSEL1(_acore, _ahclk, _apclk, _h2p), \
146 static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = {
147 RK3066_CPUCLK_RATE(1416000000, 2, 3, 1, 2, 1),
148 RK3066_CPUCLK_RATE(1200000000, 2, 3, 1, 2, 1),
149 RK3066_CPUCLK_RATE(1008000000, 2, 2, 1, 2, 1),
150 RK3066_CPUCLK_RATE( 816000000, 2, 2, 1, 2, 1),
151 RK3066_CPUCLK_RATE( 600000000, 1, 2, 1, 2, 1),
152 RK3066_CPUCLK_RATE( 504000000, 1, 1, 1, 2, 1),
153 RK3066_CPUCLK_RATE( 312000000, 0, 1, 1, 1, 0),
156 static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = {
157 .core_reg = RK2928_CLKSEL_CON(0),
159 .div_core_mask = 0x1f,
163 .mux_core_mask = 0x1,
166 #define RK3188_DIV_ACLK_CORE_MASK 0x7
167 #define RK3188_DIV_ACLK_CORE_SHIFT 3
169 #define RK3188_CLKSEL1(_aclk_core) \
171 .reg = RK2928_CLKSEL_CON(1), \
172 .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
173 RK3188_DIV_ACLK_CORE_SHIFT) \
175 #define RK3188_CPUCLK_RATE(_prate, _core_peri, _aclk_core) \
179 RK3066_CLKSEL0(_core_peri), \
180 RK3188_CLKSEL1(_aclk_core), \
184 static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = {
185 RK3188_CPUCLK_RATE(1608000000, 2, 3),
186 RK3188_CPUCLK_RATE(1416000000, 2, 3),
187 RK3188_CPUCLK_RATE(1200000000, 2, 3),
188 RK3188_CPUCLK_RATE(1008000000, 2, 3),
189 RK3188_CPUCLK_RATE( 816000000, 2, 3),
190 RK3188_CPUCLK_RATE( 600000000, 1, 3),
191 RK3188_CPUCLK_RATE( 504000000, 1, 3),
192 RK3188_CPUCLK_RATE( 312000000, 0, 1),
195 static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = {
196 .core_reg = RK2928_CLKSEL_CON(0),
198 .div_core_mask = 0x1f,
202 .mux_core_mask = 0x1,
205 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
206 PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
207 PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" };
208 PNAME(mux_pll_src_gpll_cpll_p) = { "gpll", "cpll" };
209 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
210 PNAME(mux_aclk_cpu_p) = { "apll", "gpll" };
211 PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" };
212 PNAME(mux_sclk_i2s0_p) = { "i2s0_pre", "i2s0_frac", "xin12m" };
213 PNAME(mux_sclk_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" };
214 PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" };
215 PNAME(mux_sclk_uart1_p) = { "uart1_pre", "uart1_frac", "xin24m" };
216 PNAME(mux_sclk_uart2_p) = { "uart2_pre", "uart2_frac", "xin24m" };
217 PNAME(mux_sclk_uart3_p) = { "uart3_pre", "uart3_frac", "xin24m" };
218 PNAME(mux_sclk_hsadc_p) = { "hsadc_src", "hsadc_frac", "ext_hsadc" };
219 PNAME(mux_mac_p) = { "gpll", "dpll" };
220 PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" };
222 static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = {
223 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
224 RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates),
225 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
226 RK2928_MODE_CON, 4, 4, 0, NULL),
227 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
228 RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
229 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
230 RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
233 static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
234 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
235 RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates),
236 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
237 RK2928_MODE_CON, 4, 5, 0, NULL),
238 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
239 RK2928_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
240 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
241 RK2928_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
244 #define MFLAGS CLK_MUX_HIWORD_MASK
245 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
246 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
247 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
250 static struct clk_div_table div_core_peri_t[] = {
251 { .val = 0, .div = 2 },
252 { .val = 1, .div = 4 },
253 { .val = 2, .div = 8 },
254 { .val = 3, .div = 16 },
258 static struct rockchip_clk_branch common_hsadc_out_fracmux __initdata =
259 MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0,
260 RK2928_CLKSEL_CON(22), 4, 2, MFLAGS);
262 static struct rockchip_clk_branch common_spdif_fracmux __initdata =
263 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
264 RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
266 static struct rockchip_clk_branch common_uart0_fracmux __initdata =
267 MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
268 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
270 static struct rockchip_clk_branch common_uart1_fracmux __initdata =
271 MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
272 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
274 static struct rockchip_clk_branch common_uart2_fracmux __initdata =
275 MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0,
276 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
278 static struct rockchip_clk_branch common_uart3_fracmux __initdata =
279 MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0,
280 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
282 static struct rockchip_clk_branch common_clk_branches[] __initdata = {
284 * Clock-Architecture Diagram 2
287 GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
289 /* these two are set by the cpuclk and should not be changed */
290 COMPOSITE_NOMUX_DIVTBL(CORE_PERI, "core_peri", "armclk", 0,
291 RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
292 div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS),
294 COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
295 RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
296 RK2928_CLKGATE_CON(3), 9, GFLAGS),
297 GATE(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0,
298 RK2928_CLKGATE_CON(3), 10, GFLAGS),
299 COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
300 RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
301 RK2928_CLKGATE_CON(3), 11, GFLAGS),
302 GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0,
303 RK2928_CLKGATE_CON(3), 12, GFLAGS),
305 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
306 RK2928_CLKGATE_CON(1), 7, GFLAGS),
307 COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
308 RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
309 RK2928_CLKGATE_CON(0), 2, GFLAGS),
311 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
312 RK2928_CLKGATE_CON(0), 3, GFLAGS),
314 GATE(0, "atclk_cpu", "pclk_cpu_pre", 0,
315 RK2928_CLKGATE_CON(0), 6, GFLAGS),
316 GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_pre", 0,
317 RK2928_CLKGATE_CON(0), 5, GFLAGS),
318 GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,
319 RK2928_CLKGATE_CON(0), 4, GFLAGS),
321 COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
322 RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
323 RK2928_CLKGATE_CON(3), 0, GFLAGS),
324 COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
325 RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS,
326 RK2928_CLKGATE_CON(1), 4, GFLAGS),
328 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0,
329 RK2928_CLKGATE_CON(2), 1, GFLAGS),
330 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", 0,
331 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
332 RK2928_CLKGATE_CON(2), 2, GFLAGS),
333 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", 0,
334 RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
335 RK2928_CLKGATE_CON(2), 3, GFLAGS),
337 MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
338 RK2928_CLKSEL_CON(29), 0, 1, MFLAGS),
339 COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0,
340 RK2928_CLKSEL_CON(29), 1, 5, DFLAGS,
341 RK2928_CLKGATE_CON(3), 7, GFLAGS),
342 MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0,
343 RK2928_CLKSEL_CON(29), 7, 1, MFLAGS),
345 GATE(0, "pclkin_cif0", "ext_cif0", 0,
346 RK2928_CLKGATE_CON(3), 3, GFLAGS),
347 INVERTER(0, "pclk_cif0", "pclkin_cif0",
348 RK2928_CLKSEL_CON(30), 8, IFLAGS),
350 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
353 * the 480m are generated inside the usb block from these clocks,
354 * but they are also a source for the hsicphy clock.
356 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
357 RK2928_CLKGATE_CON(1), 5, GFLAGS),
358 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
359 RK2928_CLKGATE_CON(1), 6, GFLAGS),
361 COMPOSITE(0, "mac_src", mux_mac_p, 0,
362 RK2928_CLKSEL_CON(21), 0, 1, MFLAGS, 8, 5, DFLAGS,
363 RK2928_CLKGATE_CON(2), 5, GFLAGS),
364 MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
365 RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),
366 GATE(0, "sclk_mac_lbtest", "sclk_macref", 0,
367 RK2928_CLKGATE_CON(2), 12, GFLAGS),
369 COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
370 RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
371 RK2928_CLKGATE_CON(2), 6, GFLAGS),
372 COMPOSITE_FRACMUX(0, "hsadc_frac", "hsadc_src", 0,
373 RK2928_CLKSEL_CON(23), 0,
374 RK2928_CLKGATE_CON(2), 7, GFLAGS,
375 &common_hsadc_out_fracmux),
376 INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
377 RK2928_CLKSEL_CON(22), 7, IFLAGS),
379 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
380 RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
381 RK2928_CLKGATE_CON(2), 8, GFLAGS),
383 COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
384 RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
385 RK2928_CLKGATE_CON(0), 13, GFLAGS),
386 COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT,
387 RK2928_CLKSEL_CON(9), 0,
388 RK2928_CLKGATE_CON(0), 14, GFLAGS,
389 &common_spdif_fracmux),
392 * Clock-Architecture Diagram 4
395 GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0,
396 RK2928_CLKGATE_CON(2), 4, GFLAGS),
398 COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
399 RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,
400 RK2928_CLKGATE_CON(2), 9, GFLAGS),
401 COMPOSITE_NOMUX(SCLK_SPI1, "sclk_spi1", "pclk_peri", 0,
402 RK2928_CLKSEL_CON(25), 8, 7, DFLAGS,
403 RK2928_CLKGATE_CON(2), 10, GFLAGS),
405 COMPOSITE_NOMUX(SCLK_SDMMC, "sclk_sdmmc", "hclk_peri", 0,
406 RK2928_CLKSEL_CON(11), 0, 6, DFLAGS,
407 RK2928_CLKGATE_CON(2), 11, GFLAGS),
408 COMPOSITE_NOMUX(SCLK_SDIO, "sclk_sdio", "hclk_peri", 0,
409 RK2928_CLKSEL_CON(12), 0, 6, DFLAGS,
410 RK2928_CLKGATE_CON(2), 13, GFLAGS),
411 COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc", "hclk_peri", 0,
412 RK2928_CLKSEL_CON(12), 8, 6, DFLAGS,
413 RK2928_CLKGATE_CON(2), 14, GFLAGS),
415 MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0,
416 RK2928_CLKSEL_CON(12), 15, 1, MFLAGS),
417 COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0,
418 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
419 RK2928_CLKGATE_CON(1), 8, GFLAGS),
420 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", 0,
421 RK2928_CLKSEL_CON(17), 0,
422 RK2928_CLKGATE_CON(1), 9, GFLAGS,
423 &common_uart0_fracmux),
424 COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
425 RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
426 RK2928_CLKGATE_CON(1), 10, GFLAGS),
427 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", 0,
428 RK2928_CLKSEL_CON(18), 0,
429 RK2928_CLKGATE_CON(1), 11, GFLAGS,
430 &common_uart1_fracmux),
431 COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
432 RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
433 RK2928_CLKGATE_CON(1), 12, GFLAGS),
434 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", 0,
435 RK2928_CLKSEL_CON(19), 0,
436 RK2928_CLKGATE_CON(1), 13, GFLAGS,
437 &common_uart2_fracmux),
438 COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
439 RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
440 RK2928_CLKGATE_CON(1), 14, GFLAGS),
441 COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", 0,
442 RK2928_CLKSEL_CON(20), 0,
443 RK2928_CLKGATE_CON(1), 15, GFLAGS,
444 &common_uart3_fracmux),
446 GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS),
448 GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS),
449 GATE(SCLK_TIMER1, "timer1", "xin24m", 0, RK2928_CLKGATE_CON(1), 1, GFLAGS),
451 /* clk_core_pre gates */
452 GATE(0, "core_dbg", "armclk", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
455 GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
456 GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
457 GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
460 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
461 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
462 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
463 GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS),
464 /* hclk_ahb2apb is part of a clk branch */
465 GATE(0, "hclk_vio_bus", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
466 GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
467 GATE(HCLK_LCDC1, "hclk_lcdc1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
468 GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
469 GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS),
470 GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
472 /* hclk_peri gates */
473 GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
474 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS),
475 GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 7, GFLAGS),
476 GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
477 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
478 GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 5, GFLAGS),
479 GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
480 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS),
481 GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS),
482 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
483 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
484 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 12, GFLAGS),
486 /* aclk_lcdc0_pre gates */
487 GATE(0, "aclk_vio0", "aclk_lcdc0_pre", 0, RK2928_CLKGATE_CON(6), 13, GFLAGS),
488 GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS),
489 GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS),
490 GATE(ACLK_IPP, "aclk_ipp", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 8, GFLAGS),
492 /* aclk_lcdc1_pre gates */
493 GATE(0, "aclk_vio1", "aclk_lcdc1_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
494 GATE(ACLK_LCDC1, "aclk_lcdc1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 3, GFLAGS),
495 GATE(ACLK_RGA, "aclk_rga", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS),
497 /* atclk_cpu gates */
498 GATE(0, "atclk", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 3, GFLAGS),
499 GATE(0, "trace", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
502 GATE(PCLK_PWM01, "pclk_pwm01", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
503 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
504 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
505 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
506 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
507 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
508 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
509 GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS),
510 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS),
511 GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
512 GATE(PCLK_PUBL, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
513 GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
514 GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
515 GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS),
518 GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
519 GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS),
520 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 4, GFLAGS),
521 GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
522 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
524 /* pclk_peri gates */
525 GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
526 GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS),
527 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
528 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
529 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 13, GFLAGS),
530 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
531 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
532 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
533 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
534 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
535 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
536 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
539 PNAME(mux_rk3066_lcdc0_p) = { "dclk_lcdc0_src", "xin27m" };
540 PNAME(mux_rk3066_lcdc1_p) = { "dclk_lcdc1_src", "xin27m" };
541 PNAME(mux_sclk_cif1_p) = { "cif1_pre", "xin24m" };
542 PNAME(mux_sclk_i2s1_p) = { "i2s1_pre", "i2s1_frac", "xin12m" };
543 PNAME(mux_sclk_i2s2_p) = { "i2s2_pre", "i2s2_frac", "xin12m" };
545 static struct clk_div_table div_aclk_cpu_t[] = {
546 { .val = 0, .div = 1 },
547 { .val = 1, .div = 2 },
548 { .val = 2, .div = 3 },
549 { .val = 3, .div = 4 },
550 { .val = 4, .div = 8 },
554 static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata =
555 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
556 RK2928_CLKSEL_CON(2), 8, 2, MFLAGS);
558 static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata =
559 MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0,
560 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
562 static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata =
563 MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
564 RK2928_CLKSEL_CON(4), 8, 2, MFLAGS);
566 static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
567 DIVTBL(0, "aclk_cpu_pre", "armclk", 0,
568 RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t),
569 DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
570 RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
571 | CLK_DIVIDER_READ_ONLY),
572 DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
573 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
574 | CLK_DIVIDER_READ_ONLY),
575 COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
576 RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
577 | CLK_DIVIDER_READ_ONLY,
578 RK2928_CLKGATE_CON(4), 9, GFLAGS),
580 GATE(CORE_L2C, "core_l2c", "aclk_cpu", CLK_IGNORE_UNUSED,
581 RK2928_CLKGATE_CON(9), 4, GFLAGS),
583 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0,
584 RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
585 RK2928_CLKGATE_CON(2), 0, GFLAGS),
587 COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,
588 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
589 RK2928_CLKGATE_CON(3), 1, GFLAGS),
590 MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, CLK_SET_RATE_PARENT,
591 RK2928_CLKSEL_CON(27), 4, 1, MFLAGS),
592 COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,
593 RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
594 RK2928_CLKGATE_CON(3), 2, GFLAGS),
595 MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, CLK_SET_RATE_PARENT,
596 RK2928_CLKSEL_CON(28), 4, 1, MFLAGS),
598 COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0,
599 RK2928_CLKSEL_CON(29), 8, 5, DFLAGS,
600 RK2928_CLKGATE_CON(3), 8, GFLAGS),
601 MUX(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_p, 0,
602 RK2928_CLKSEL_CON(29), 15, 1, MFLAGS),
604 GATE(0, "pclkin_cif1", "ext_cif1", 0,
605 RK2928_CLKGATE_CON(3), 4, GFLAGS),
606 INVERTER(0, "pclk_cif1", "pclkin_cif1",
607 RK2928_CLKSEL_CON(30), 12, IFLAGS),
609 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
610 RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS,
611 RK2928_CLKGATE_CON(3), 13, GFLAGS),
612 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
613 RK2928_CLKGATE_CON(5), 15, GFLAGS),
615 GATE(SCLK_TIMER2, "timer2", "xin24m", 0,
616 RK2928_CLKGATE_CON(3), 2, GFLAGS),
618 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
619 RK2928_CLKSEL_CON(34), 0, 16, DFLAGS,
620 RK2928_CLKGATE_CON(2), 15, GFLAGS),
622 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
623 RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
624 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
625 RK2928_CLKSEL_CON(2), 0, 7, DFLAGS,
626 RK2928_CLKGATE_CON(0), 7, GFLAGS),
627 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0,
628 RK2928_CLKSEL_CON(6), 0,
629 RK2928_CLKGATE_CON(0), 8, GFLAGS,
630 &rk3066a_i2s0_fracmux),
631 COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0,
632 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
633 RK2928_CLKGATE_CON(0), 9, GFLAGS),
634 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", 0,
635 RK2928_CLKSEL_CON(7), 0,
636 RK2928_CLKGATE_CON(0), 10, GFLAGS,
637 &rk3066a_i2s1_fracmux),
638 COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0,
639 RK2928_CLKSEL_CON(4), 0, 7, DFLAGS,
640 RK2928_CLKGATE_CON(0), 11, GFLAGS),
641 COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", 0,
642 RK2928_CLKSEL_CON(8), 0,
643 RK2928_CLKGATE_CON(0), 12, GFLAGS,
644 &rk3066a_i2s2_fracmux),
646 GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
647 GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
648 GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
649 GATE(HCLK_HDMI, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
651 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
652 RK2928_CLKGATE_CON(5), 14, GFLAGS),
654 GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
656 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS),
657 GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
658 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
659 GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
660 GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
662 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
663 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 13, GFLAGS),
666 static struct clk_div_table div_rk3188_aclk_core_t[] = {
667 { .val = 0, .div = 1 },
668 { .val = 1, .div = 2 },
669 { .val = 2, .div = 3 },
670 { .val = 3, .div = 4 },
671 { .val = 4, .div = 8 },
675 PNAME(mux_hsicphy_p) = { "sclk_otgphy0_480m", "sclk_otgphy1_480m",
678 static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata =
679 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
680 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
682 static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
683 COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
684 RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
685 div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
687 /* do not source aclk_cpu_pre from the apll, to keep complexity down */
688 COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT,
689 RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS),
690 DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
691 RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
692 DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
693 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
694 COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
695 RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
696 RK2928_CLKGATE_CON(4), 9, GFLAGS),
698 GATE(CORE_L2C, "core_l2c", "armclk", CLK_IGNORE_UNUSED,
699 RK2928_CLKGATE_CON(9), 4, GFLAGS),
701 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,
702 RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
703 RK2928_CLKGATE_CON(2), 0, GFLAGS),
705 COMPOSITE(DCLK_LCDC0, "dclk_lcdc0", mux_pll_src_cpll_gpll_p, 0,
706 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
707 RK2928_CLKGATE_CON(3), 1, GFLAGS),
708 COMPOSITE(DCLK_LCDC1, "dclk_lcdc1", mux_pll_src_cpll_gpll_p, 0,
709 RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
710 RK2928_CLKGATE_CON(3), 2, GFLAGS),
712 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
713 RK2928_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 5, DFLAGS,
714 RK2928_CLKGATE_CON(3), 15, GFLAGS),
715 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
716 RK2928_CLKGATE_CON(9), 7, GFLAGS),
718 GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS),
719 GATE(SCLK_TIMER3, "timer3", "xin24m", 0, RK2928_CLKGATE_CON(1), 2, GFLAGS),
720 GATE(SCLK_TIMER4, "timer4", "xin24m", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
721 GATE(SCLK_TIMER5, "timer5", "xin24m", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
722 GATE(SCLK_TIMER6, "timer6", "xin24m", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
724 COMPOSITE_NODIV(0, "sclk_hsicphy_480m", mux_hsicphy_p, 0,
725 RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
726 RK2928_CLKGATE_CON(3), 6, GFLAGS),
727 DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
728 RK2928_CLKSEL_CON(11), 8, 6, DFLAGS),
730 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
731 RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
732 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
733 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
734 RK2928_CLKGATE_CON(0), 9, GFLAGS),
735 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
736 RK2928_CLKSEL_CON(7), 0,
737 RK2928_CLKGATE_CON(0), 10, GFLAGS,
738 &rk3188_i2s0_fracmux),
740 GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
741 GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
743 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
744 RK2928_CLKGATE_CON(7), 3, GFLAGS),
745 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
747 GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
749 GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
750 GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
752 GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
755 static const char *const rk3188_critical_clocks[] __initconst = {
765 static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)
767 struct rockchip_clk_provider *ctx;
768 void __iomem *reg_base;
770 reg_base = of_iomap(np, 0);
772 pr_err("%s: could not map cru region\n", __func__);
773 return ERR_PTR(-ENOMEM);
776 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
778 pr_err("%s: rockchip clk init failed\n", __func__);
780 return ERR_PTR(-ENOMEM);
783 rockchip_clk_register_branches(ctx, common_clk_branches,
784 ARRAY_SIZE(common_clk_branches));
786 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
787 ROCKCHIP_SOFTRST_HIWORD_MASK);
789 rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
794 static void __init rk3066a_clk_init(struct device_node *np)
796 struct rockchip_clk_provider *ctx;
798 ctx = rk3188_common_clk_init(np);
802 rockchip_clk_register_plls(ctx, rk3066_pll_clks,
803 ARRAY_SIZE(rk3066_pll_clks),
804 RK3066_GRF_SOC_STATUS);
805 rockchip_clk_register_branches(ctx, rk3066a_clk_branches,
806 ARRAY_SIZE(rk3066a_clk_branches));
807 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
808 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
809 &rk3066_cpuclk_data, rk3066_cpuclk_rates,
810 ARRAY_SIZE(rk3066_cpuclk_rates));
811 rockchip_clk_protect_critical(rk3188_critical_clocks,
812 ARRAY_SIZE(rk3188_critical_clocks));
813 rockchip_clk_of_add_provider(np, ctx);
815 CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
817 static void __init rk3188a_clk_init(struct device_node *np)
819 struct rockchip_clk_provider *ctx;
820 struct clk *clk1, *clk2;
824 ctx = rk3188_common_clk_init(np);
828 rockchip_clk_register_plls(ctx, rk3188_pll_clks,
829 ARRAY_SIZE(rk3188_pll_clks),
830 RK3188_GRF_SOC_STATUS);
831 rockchip_clk_register_branches(ctx, rk3188_clk_branches,
832 ARRAY_SIZE(rk3188_clk_branches));
833 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
834 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
835 &rk3188_cpuclk_data, rk3188_cpuclk_rates,
836 ARRAY_SIZE(rk3188_cpuclk_rates));
838 /* reparent aclk_cpu_pre from apll */
839 clk1 = __clk_lookup("aclk_cpu_pre");
840 clk2 = __clk_lookup("gpll");
842 rate = clk_get_rate(clk1);
844 ret = clk_set_parent(clk1, clk2);
846 pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n",
849 clk_set_rate(clk1, rate);
851 pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n",
855 rockchip_clk_protect_critical(rk3188_critical_clocks,
856 ARRAY_SIZE(rk3188_critical_clocks));
857 rockchip_clk_of_add_provider(np, ctx);
859 CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init);
861 static void __init rk3188_clk_init(struct device_node *np)
865 for (i = 0; i < ARRAY_SIZE(rk3188_pll_clks); i++) {
866 struct rockchip_pll_clock *pll = &rk3188_pll_clks[i];
867 struct rockchip_pll_rate_table *rate;
869 if (!pll->rate_table)
872 rate = pll->rate_table;
873 while (rate->rate > 0) {
879 rk3188a_clk_init(np);
881 CLK_OF_DECLARE(rk3188_cru, "rockchip,rk3188-cru", rk3188_clk_init);