Merge tag 'v3.20-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[sfrench/cifs-2.6.git] / drivers / clk / rockchip / clk-rk3188.c
1 /*
2  * Copyright (c) 2014 MundoReader S.L.
3  * Author: Heiko Stuebner <heiko@sntech.de>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15
16 #include <linux/clk-provider.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <dt-bindings/clock/rk3188-cru-common.h>
20 #include "clk.h"
21
22 #define RK3066_GRF_SOC_STATUS   0x15c
23 #define RK3188_GRF_SOC_STATUS   0xac
24
25 enum rk3188_plls {
26         apll, cpll, dpll, gpll,
27 };
28
29 struct rockchip_pll_rate_table rk3188_pll_rates[] = {
30         RK3066_PLL_RATE(2208000000, 1, 92, 1),
31         RK3066_PLL_RATE(2184000000, 1, 91, 1),
32         RK3066_PLL_RATE(2160000000, 1, 90, 1),
33         RK3066_PLL_RATE(2136000000, 1, 89, 1),
34         RK3066_PLL_RATE(2112000000, 1, 88, 1),
35         RK3066_PLL_RATE(2088000000, 1, 87, 1),
36         RK3066_PLL_RATE(2064000000, 1, 86, 1),
37         RK3066_PLL_RATE(2040000000, 1, 85, 1),
38         RK3066_PLL_RATE(2016000000, 1, 84, 1),
39         RK3066_PLL_RATE(1992000000, 1, 83, 1),
40         RK3066_PLL_RATE(1968000000, 1, 82, 1),
41         RK3066_PLL_RATE(1944000000, 1, 81, 1),
42         RK3066_PLL_RATE(1920000000, 1, 80, 1),
43         RK3066_PLL_RATE(1896000000, 1, 79, 1),
44         RK3066_PLL_RATE(1872000000, 1, 78, 1),
45         RK3066_PLL_RATE(1848000000, 1, 77, 1),
46         RK3066_PLL_RATE(1824000000, 1, 76, 1),
47         RK3066_PLL_RATE(1800000000, 1, 75, 1),
48         RK3066_PLL_RATE(1776000000, 1, 74, 1),
49         RK3066_PLL_RATE(1752000000, 1, 73, 1),
50         RK3066_PLL_RATE(1728000000, 1, 72, 1),
51         RK3066_PLL_RATE(1704000000, 1, 71, 1),
52         RK3066_PLL_RATE(1680000000, 1, 70, 1),
53         RK3066_PLL_RATE(1656000000, 1, 69, 1),
54         RK3066_PLL_RATE(1632000000, 1, 68, 1),
55         RK3066_PLL_RATE(1608000000, 1, 67, 1),
56         RK3066_PLL_RATE(1560000000, 1, 65, 1),
57         RK3066_PLL_RATE(1512000000, 1, 63, 1),
58         RK3066_PLL_RATE(1488000000, 1, 62, 1),
59         RK3066_PLL_RATE(1464000000, 1, 61, 1),
60         RK3066_PLL_RATE(1440000000, 1, 60, 1),
61         RK3066_PLL_RATE(1416000000, 1, 59, 1),
62         RK3066_PLL_RATE(1392000000, 1, 58, 1),
63         RK3066_PLL_RATE(1368000000, 1, 57, 1),
64         RK3066_PLL_RATE(1344000000, 1, 56, 1),
65         RK3066_PLL_RATE(1320000000, 1, 55, 1),
66         RK3066_PLL_RATE(1296000000, 1, 54, 1),
67         RK3066_PLL_RATE(1272000000, 1, 53, 1),
68         RK3066_PLL_RATE(1248000000, 1, 52, 1),
69         RK3066_PLL_RATE(1224000000, 1, 51, 1),
70         RK3066_PLL_RATE(1200000000, 1, 50, 1),
71         RK3066_PLL_RATE(1188000000, 2, 99, 1),
72         RK3066_PLL_RATE(1176000000, 1, 49, 1),
73         RK3066_PLL_RATE(1128000000, 1, 47, 1),
74         RK3066_PLL_RATE(1104000000, 1, 46, 1),
75         RK3066_PLL_RATE(1008000000, 1, 84, 2),
76         RK3066_PLL_RATE( 912000000, 1, 76, 2),
77         RK3066_PLL_RATE( 891000000, 8, 594, 2),
78         RK3066_PLL_RATE( 888000000, 1, 74, 2),
79         RK3066_PLL_RATE( 816000000, 1, 68, 2),
80         RK3066_PLL_RATE( 798000000, 2, 133, 2),
81         RK3066_PLL_RATE( 792000000, 1, 66, 2),
82         RK3066_PLL_RATE( 768000000, 1, 64, 2),
83         RK3066_PLL_RATE( 742500000, 8, 495, 2),
84         RK3066_PLL_RATE( 696000000, 1, 58, 2),
85         RK3066_PLL_RATE( 600000000, 1, 50, 2),
86         RK3066_PLL_RATE( 594000000, 2, 198, 4),
87         RK3066_PLL_RATE( 552000000, 1, 46, 2),
88         RK3066_PLL_RATE( 504000000, 1, 84, 4),
89         RK3066_PLL_RATE( 456000000, 1, 76, 4),
90         RK3066_PLL_RATE( 408000000, 1, 68, 4),
91         RK3066_PLL_RATE( 384000000, 2, 128, 4),
92         RK3066_PLL_RATE( 360000000, 1, 60, 4),
93         RK3066_PLL_RATE( 312000000, 1, 52, 4),
94         RK3066_PLL_RATE( 300000000, 1, 50, 4),
95         RK3066_PLL_RATE( 297000000, 2, 198, 8),
96         RK3066_PLL_RATE( 252000000, 1, 84, 8),
97         RK3066_PLL_RATE( 216000000, 1, 72, 8),
98         RK3066_PLL_RATE( 148500000, 2, 99, 8),
99         RK3066_PLL_RATE( 126000000, 1, 84, 16),
100         RK3066_PLL_RATE(  48000000, 1, 64, 32),
101         { /* sentinel */ },
102 };
103
104 #define RK3066_DIV_CORE_PERIPH_MASK     0x3
105 #define RK3066_DIV_CORE_PERIPH_SHIFT    6
106 #define RK3066_DIV_ACLK_CORE_MASK       0x7
107 #define RK3066_DIV_ACLK_CORE_SHIFT      0
108 #define RK3066_DIV_ACLK_HCLK_MASK       0x3
109 #define RK3066_DIV_ACLK_HCLK_SHIFT      8
110 #define RK3066_DIV_ACLK_PCLK_MASK       0x3
111 #define RK3066_DIV_ACLK_PCLK_SHIFT      12
112 #define RK3066_DIV_AHB2APB_MASK         0x3
113 #define RK3066_DIV_AHB2APB_SHIFT        14
114
115 #define RK3066_CLKSEL0(_core_peri)                                      \
116         {                                                               \
117                 .reg = RK2928_CLKSEL_CON(0),                            \
118                 .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \
119                                 RK3066_DIV_CORE_PERIPH_SHIFT)           \
120         }
121 #define RK3066_CLKSEL1(_aclk_core, _aclk_hclk, _aclk_pclk, _ahb2apb)    \
122         {                                                               \
123                 .reg = RK2928_CLKSEL_CON(1),                            \
124                 .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
125                                 RK3066_DIV_ACLK_CORE_SHIFT) |           \
126                        HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \
127                                 RK3066_DIV_ACLK_HCLK_SHIFT) |           \
128                        HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \
129                                 RK3066_DIV_ACLK_PCLK_SHIFT) |           \
130                        HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \
131                                 RK3066_DIV_AHB2APB_SHIFT),              \
132         }
133
134 #define RK3066_CPUCLK_RATE(_prate, _core_peri, _acore, _ahclk, _apclk, _h2p) \
135         {                                                               \
136                 .prate = _prate,                                        \
137                 .divs = {                                               \
138                         RK3066_CLKSEL0(_core_peri),                     \
139                         RK3066_CLKSEL1(_acore, _ahclk, _apclk, _h2p),   \
140                 },                                                      \
141         }
142
143 static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = {
144         RK3066_CPUCLK_RATE(1416000000, 2, 3, 1, 2, 1),
145         RK3066_CPUCLK_RATE(1200000000, 2, 3, 1, 2, 1),
146         RK3066_CPUCLK_RATE(1008000000, 2, 2, 1, 2, 1),
147         RK3066_CPUCLK_RATE( 816000000, 2, 2, 1, 2, 1),
148         RK3066_CPUCLK_RATE( 600000000, 1, 2, 1, 2, 1),
149         RK3066_CPUCLK_RATE( 504000000, 1, 1, 1, 2, 1),
150         RK3066_CPUCLK_RATE( 312000000, 0, 1, 1, 1, 0),
151 };
152
153 static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = {
154         .core_reg = RK2928_CLKSEL_CON(0),
155         .div_core_shift = 0,
156         .div_core_mask = 0x1f,
157         .mux_core_shift = 8,
158 };
159
160 #define RK3188_DIV_ACLK_CORE_MASK       0x7
161 #define RK3188_DIV_ACLK_CORE_SHIFT      3
162
163 #define RK3188_CLKSEL1(_aclk_core)              \
164         {                                       \
165                 .reg = RK2928_CLKSEL_CON(1),    \
166                 .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
167                                  RK3188_DIV_ACLK_CORE_SHIFT) \
168         }
169 #define RK3188_CPUCLK_RATE(_prate, _core_peri, _aclk_core)      \
170         {                                                       \
171                 .prate = _prate,                                \
172                 .divs = {                                       \
173                         RK3066_CLKSEL0(_core_peri),             \
174                         RK3188_CLKSEL1(_aclk_core),             \
175                 },                                              \
176         }
177
178 static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = {
179         RK3188_CPUCLK_RATE(1608000000, 2, 3),
180         RK3188_CPUCLK_RATE(1416000000, 2, 3),
181         RK3188_CPUCLK_RATE(1200000000, 2, 3),
182         RK3188_CPUCLK_RATE(1008000000, 2, 3),
183         RK3188_CPUCLK_RATE( 816000000, 2, 3),
184         RK3188_CPUCLK_RATE( 600000000, 1, 3),
185         RK3188_CPUCLK_RATE( 504000000, 1, 3),
186         RK3188_CPUCLK_RATE( 312000000, 0, 1),
187 };
188
189 static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = {
190         .core_reg = RK2928_CLKSEL_CON(0),
191         .div_core_shift = 9,
192         .div_core_mask = 0x1f,
193         .mux_core_shift = 8,
194 };
195
196 PNAME(mux_pll_p)                = { "xin24m", "xin32k" };
197 PNAME(mux_armclk_p)             = { "apll", "gpll_armclk" };
198 PNAME(mux_ddrphy_p)             = { "dpll", "gpll_ddr" };
199 PNAME(mux_pll_src_gpll_cpll_p)  = { "gpll", "cpll" };
200 PNAME(mux_pll_src_cpll_gpll_p)  = { "cpll", "gpll" };
201 PNAME(mux_aclk_cpu_p)           = { "apll", "gpll" };
202 PNAME(mux_sclk_cif0_p)          = { "cif0_pre", "xin24m" };
203 PNAME(mux_sclk_i2s0_p)          = { "i2s0_pre", "i2s0_frac", "xin12m" };
204 PNAME(mux_sclk_spdif_p)         = { "spdif_src", "spdif_frac", "xin12m" };
205 PNAME(mux_sclk_uart0_p)         = { "uart0_pre", "uart0_frac", "xin24m" };
206 PNAME(mux_sclk_uart1_p)         = { "uart1_pre", "uart1_frac", "xin24m" };
207 PNAME(mux_sclk_uart2_p)         = { "uart2_pre", "uart2_frac", "xin24m" };
208 PNAME(mux_sclk_uart3_p)         = { "uart3_pre", "uart3_frac", "xin24m" };
209 PNAME(mux_sclk_hsadc_p)         = { "hsadc_src", "hsadc_frac", "ext_hsadc" };
210 PNAME(mux_mac_p)                = { "gpll", "dpll" };
211 PNAME(mux_sclk_macref_p)        = { "mac_src", "ext_rmii" };
212
213 static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = {
214         [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
215                      RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates),
216         [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
217                      RK2928_MODE_CON, 4, 4, 0, NULL),
218         [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
219                      RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
220         [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
221                      RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
222 };
223
224 static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
225         [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
226                      RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates),
227         [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
228                      RK2928_MODE_CON, 4, 5, 0, NULL),
229         [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
230                      RK2928_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
231         [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
232                      RK2928_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
233 };
234
235 #define MFLAGS CLK_MUX_HIWORD_MASK
236 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
237 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
238
239 /* 2 ^ (val + 1) */
240 static struct clk_div_table div_core_peri_t[] = {
241         { .val = 0, .div = 2 },
242         { .val = 1, .div = 4 },
243         { .val = 2, .div = 8 },
244         { .val = 3, .div = 16 },
245         { /* sentinel */ },
246 };
247
248 static struct rockchip_clk_branch common_clk_branches[] __initdata = {
249         /*
250          * Clock-Architecture Diagram 2
251          */
252
253         GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
254
255         /* these two are set by the cpuclk and should not be changed */
256         COMPOSITE_NOMUX_DIVTBL(CORE_PERI, "core_peri", "armclk", 0,
257                         RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
258                         div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS),
259
260         COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
261                         RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
262                         RK2928_CLKGATE_CON(3), 9, GFLAGS),
263         GATE(0, "hclk_vepu", "aclk_vepu", 0,
264                         RK2928_CLKGATE_CON(3), 10, GFLAGS),
265         COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
266                         RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
267                         RK2928_CLKGATE_CON(3), 11, GFLAGS),
268         GATE(0, "hclk_vdpu", "aclk_vdpu", 0,
269                         RK2928_CLKGATE_CON(3), 12, GFLAGS),
270
271         GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
272                         RK2928_CLKGATE_CON(1), 7, GFLAGS),
273         COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
274                         RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
275                         RK2928_CLKGATE_CON(0), 2, GFLAGS),
276
277         GATE(0, "aclk_cpu", "aclk_cpu_pre", 0,
278                         RK2928_CLKGATE_CON(0), 3, GFLAGS),
279
280         GATE(0, "atclk_cpu", "pclk_cpu_pre", 0,
281                         RK2928_CLKGATE_CON(0), 6, GFLAGS),
282         GATE(0, "pclk_cpu", "pclk_cpu_pre", 0,
283                         RK2928_CLKGATE_CON(0), 5, GFLAGS),
284         GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,
285                         RK2928_CLKGATE_CON(0), 4, GFLAGS),
286
287         COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
288                         RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
289                         RK2928_CLKGATE_CON(3), 0, GFLAGS),
290         COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
291                         RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS,
292                         RK2928_CLKGATE_CON(1), 4, GFLAGS),
293
294         GATE(0, "aclk_peri", "aclk_peri_pre", 0,
295                         RK2928_CLKGATE_CON(2), 1, GFLAGS),
296         COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_pre", 0,
297                         RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
298                         RK2928_CLKGATE_CON(2), 2, GFLAGS),
299         COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_pre", 0,
300                         RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
301                         RK2928_CLKGATE_CON(2), 3, GFLAGS),
302
303         MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
304                         RK2928_CLKSEL_CON(29), 0, 1, MFLAGS),
305         COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0,
306                         RK2928_CLKSEL_CON(29), 1, 5, DFLAGS,
307                         RK2928_CLKGATE_CON(3), 7, GFLAGS),
308         MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0,
309                         RK2928_CLKSEL_CON(29), 7, 1, MFLAGS),
310
311         GATE(0, "pclkin_cif0", "ext_cif0", 0,
312                         RK2928_CLKGATE_CON(3), 3, GFLAGS),
313
314         /*
315          * the 480m are generated inside the usb block from these clocks,
316          * but they are also a source for the hsicphy clock.
317          */
318         GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,
319                         RK2928_CLKGATE_CON(1), 5, GFLAGS),
320         GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,
321                         RK2928_CLKGATE_CON(1), 6, GFLAGS),
322
323         COMPOSITE(0, "mac_src", mux_mac_p, 0,
324                         RK2928_CLKSEL_CON(21), 0, 1, MFLAGS, 8, 5, DFLAGS,
325                         RK2928_CLKGATE_CON(2), 5, GFLAGS),
326         MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
327                         RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),
328         GATE(0, "sclk_mac_lbtest", "sclk_macref",
329                         RK2928_CLKGATE_CON(2), 12, 0, GFLAGS),
330
331         COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
332                         RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
333                         RK2928_CLKGATE_CON(2), 6, GFLAGS),
334         COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src", 0,
335                         RK2928_CLKSEL_CON(23), 0,
336                         RK2928_CLKGATE_CON(2), 7, GFLAGS),
337         MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0,
338                         RK2928_CLKSEL_CON(22), 4, 2, MFLAGS),
339
340         COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
341                         RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
342                         RK2928_CLKGATE_CON(2), 8, GFLAGS),
343
344         COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
345                         RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
346                         RK2928_CLKGATE_CON(0), 13, GFLAGS),
347         COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0,
348                         RK2928_CLKSEL_CON(9), 0,
349                         RK2928_CLKGATE_CON(0), 14, GFLAGS),
350         MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
351                         RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
352
353         /*
354          * Clock-Architecture Diagram 4
355          */
356
357         GATE(SCLK_SMC, "sclk_smc", "hclk_peri",
358                         RK2928_CLKGATE_CON(2), 4, 0, GFLAGS),
359
360         COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
361                         RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,
362                         RK2928_CLKGATE_CON(2), 9, GFLAGS),
363         COMPOSITE_NOMUX(SCLK_SPI1, "sclk_spi1", "pclk_peri", 0,
364                         RK2928_CLKSEL_CON(25), 8, 7, DFLAGS,
365                         RK2928_CLKGATE_CON(2), 10, GFLAGS),
366
367         COMPOSITE_NOMUX(SCLK_SDMMC, "sclk_sdmmc", "hclk_peri", 0,
368                         RK2928_CLKSEL_CON(11), 0, 6, DFLAGS,
369                         RK2928_CLKGATE_CON(2), 11, GFLAGS),
370         COMPOSITE_NOMUX(SCLK_SDIO, "sclk_sdio", "hclk_peri", 0,
371                         RK2928_CLKSEL_CON(12), 0, 6, DFLAGS,
372                         RK2928_CLKGATE_CON(2), 13, GFLAGS),
373         COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc", "hclk_peri", 0,
374                         RK2928_CLKSEL_CON(12), 8, 6, DFLAGS,
375                         RK2928_CLKGATE_CON(2), 14, GFLAGS),
376
377         MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0,
378                         RK2928_CLKSEL_CON(12), 15, 1, MFLAGS),
379         COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0,
380                         RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
381                         RK2928_CLKGATE_CON(1), 8, GFLAGS),
382         COMPOSITE_FRAC(0, "uart0_frac", "uart0_pre", 0,
383                         RK2928_CLKSEL_CON(17), 0,
384                         RK2928_CLKGATE_CON(1), 9, GFLAGS),
385         MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
386                         RK2928_CLKSEL_CON(13), 8, 2, MFLAGS),
387         COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
388                         RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
389                         RK2928_CLKGATE_CON(1), 10, GFLAGS),
390         COMPOSITE_FRAC(0, "uart1_frac", "uart1_pre", 0,
391                         RK2928_CLKSEL_CON(18), 0,
392                         RK2928_CLKGATE_CON(1), 11, GFLAGS),
393         MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
394                         RK2928_CLKSEL_CON(14), 8, 2, MFLAGS),
395         COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
396                         RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
397                         RK2928_CLKGATE_CON(1), 12, GFLAGS),
398         COMPOSITE_FRAC(0, "uart2_frac", "uart2_pre", 0,
399                         RK2928_CLKSEL_CON(19), 0,
400                         RK2928_CLKGATE_CON(1), 13, GFLAGS),
401         MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0,
402                         RK2928_CLKSEL_CON(15), 8, 2, MFLAGS),
403         COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
404                         RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
405                         RK2928_CLKGATE_CON(1), 14, GFLAGS),
406         COMPOSITE_FRAC(0, "uart3_frac", "uart3_pre", 0,
407                         RK2928_CLKSEL_CON(20), 0,
408                         RK2928_CLKGATE_CON(1), 15, GFLAGS),
409         MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0,
410                         RK2928_CLKSEL_CON(16), 8, 2, MFLAGS),
411
412         GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS),
413
414         GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS),
415         GATE(SCLK_TIMER1, "timer1", "xin24m", 0, RK2928_CLKGATE_CON(1), 1, GFLAGS),
416
417         /* clk_core_pre gates */
418         GATE(0, "core_dbg", "armclk", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
419
420         /* aclk_cpu gates */
421         GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
422         GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
423         GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
424
425         /* hclk_cpu gates */
426         GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
427         GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
428         GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
429         GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS),
430         /* hclk_ahb2apb is part of a clk branch */
431         GATE(0, "hclk_vio_bus", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
432         GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
433         GATE(HCLK_LCDC1, "hclk_lcdc1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
434         GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
435         GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS),
436         GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
437
438         /* hclk_peri gates */
439         GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
440         GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS),
441         GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 7, GFLAGS),
442         GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
443         GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
444         GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 5, GFLAGS),
445         GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
446         GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS),
447         GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS),
448         GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
449         GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
450         GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 12, GFLAGS),
451
452         /* aclk_lcdc0_pre gates */
453         GATE(0, "aclk_vio0", "aclk_lcdc0_pre", 0, RK2928_CLKGATE_CON(6), 13, GFLAGS),
454         GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS),
455         GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS),
456         GATE(ACLK_IPP, "aclk_ipp", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 8, GFLAGS),
457
458         /* aclk_lcdc1_pre gates */
459         GATE(0, "aclk_vio1", "aclk_lcdc1_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
460         GATE(ACLK_LCDC1, "aclk_lcdc1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 3, GFLAGS),
461         GATE(ACLK_RGA, "aclk_rga", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS),
462
463         /* atclk_cpu gates */
464         GATE(0, "atclk", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 3, GFLAGS),
465         GATE(0, "trace", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
466
467         /* pclk_cpu gates */
468         GATE(PCLK_PWM01, "pclk_pwm01", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
469         GATE(PCLK_TIMER0, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
470         GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
471         GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
472         GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
473         GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
474         GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
475         GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS),
476         GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS),
477         GATE(0, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
478         GATE(0, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
479         GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
480         GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
481         GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS),
482
483         /* aclk_peri */
484         GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
485         GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS),
486         GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 4, GFLAGS),
487         GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
488         GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
489
490         /* pclk_peri gates */
491         GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
492         GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS),
493         GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
494         GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
495         GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 13, GFLAGS),
496         GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
497         GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
498         GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
499         GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
500         GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
501         GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
502         GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
503 };
504
505 PNAME(mux_rk3066_lcdc0_p)       = { "dclk_lcdc0_src", "xin27m" };
506 PNAME(mux_rk3066_lcdc1_p)       = { "dclk_lcdc1_src", "xin27m" };
507 PNAME(mux_sclk_cif1_p)          = { "cif1_pre", "xin24m" };
508 PNAME(mux_sclk_i2s1_p)          = { "i2s1_pre", "i2s1_frac", "xin12m" };
509 PNAME(mux_sclk_i2s2_p)          = { "i2s2_pre", "i2s2_frac", "xin12m" };
510
511 static struct clk_div_table div_aclk_cpu_t[] = {
512         { .val = 0, .div = 1 },
513         { .val = 1, .div = 2 },
514         { .val = 2, .div = 3 },
515         { .val = 3, .div = 4 },
516         { .val = 4, .div = 8 },
517         { /* sentinel */ },
518 };
519
520 static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
521         DIVTBL(0, "aclk_cpu_pre", "armclk", 0,
522                         RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t),
523         DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
524                         RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
525                                                             | CLK_DIVIDER_READ_ONLY),
526         DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
527                         RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
528                                                            | CLK_DIVIDER_READ_ONLY),
529         COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
530                         RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
531                                                             | CLK_DIVIDER_READ_ONLY,
532                         RK2928_CLKGATE_CON(4), 9, GFLAGS),
533
534         GATE(CORE_L2C, "core_l2c", "aclk_cpu", CLK_IGNORE_UNUSED,
535                         RK2928_CLKGATE_CON(9), 4, GFLAGS),
536
537         COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0,
538                         RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
539                         RK2928_CLKGATE_CON(2), 0, GFLAGS),
540
541         COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,
542                         RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
543                         RK2928_CLKGATE_CON(3), 1, GFLAGS),
544         MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, 0,
545                         RK2928_CLKSEL_CON(27), 4, 1, MFLAGS),
546         COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,
547                         RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
548                         RK2928_CLKGATE_CON(3), 2, GFLAGS),
549         MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, 0,
550                         RK2928_CLKSEL_CON(28), 4, 1, MFLAGS),
551
552         COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0,
553                         RK2928_CLKSEL_CON(29), 8, 5, DFLAGS,
554                         RK2928_CLKGATE_CON(3), 8, GFLAGS),
555         MUX(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_p, 0,
556                         RK2928_CLKSEL_CON(29), 15, 1, MFLAGS),
557
558         GATE(0, "pclkin_cif1", "ext_cif1", 0,
559                         RK2928_CLKGATE_CON(3), 4, GFLAGS),
560
561         COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
562                         RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS,
563                         RK2928_CLKGATE_CON(3), 13, GFLAGS),
564         GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
565                         RK2928_CLKGATE_CON(5), 15, GFLAGS),
566
567         GATE(SCLK_TIMER2, "timer2", "xin24m", 0,
568                         RK2928_CLKGATE_CON(3), 2, GFLAGS),
569
570         COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0,
571                         RK2928_CLKSEL_CON(34), 0, 16, DFLAGS,
572                         RK2928_CLKGATE_CON(2), 15, GFLAGS),
573
574         MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
575                         RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
576         COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
577                         RK2928_CLKSEL_CON(2), 0, 7, DFLAGS,
578                         RK2928_CLKGATE_CON(0), 7, GFLAGS),
579         COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0,
580                         RK2928_CLKSEL_CON(6), 0,
581                         RK2928_CLKGATE_CON(0), 8, GFLAGS),
582         MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
583                         RK2928_CLKSEL_CON(2), 8, 2, MFLAGS),
584         COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0,
585                         RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
586                         RK2928_CLKGATE_CON(0), 9, GFLAGS),
587         COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_pre", 0,
588                         RK2928_CLKSEL_CON(7), 0,
589                         RK2928_CLKGATE_CON(0), 10, GFLAGS),
590         MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0,
591                         RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
592         COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0,
593                         RK2928_CLKSEL_CON(4), 0, 7, DFLAGS,
594                         RK2928_CLKGATE_CON(0), 11, GFLAGS),
595         COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_pre", 0,
596                         RK2928_CLKSEL_CON(8), 0,
597                         RK2928_CLKGATE_CON(0), 12, GFLAGS),
598         MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
599                         RK2928_CLKSEL_CON(4), 8, 2, MFLAGS),
600
601         GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
602         GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
603         GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
604         GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
605
606         GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
607                         RK2928_CLKGATE_CON(5), 14, GFLAGS),
608
609         GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
610
611         GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS),
612         GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
613         GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
614         GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
615         GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
616
617         GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
618         GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 13, GFLAGS),
619 };
620
621 static struct clk_div_table div_rk3188_aclk_core_t[] = {
622         { .val = 0, .div = 1 },
623         { .val = 1, .div = 2 },
624         { .val = 2, .div = 3 },
625         { .val = 3, .div = 4 },
626         { .val = 4, .div = 8 },
627         { /* sentinel */ },
628 };
629
630 PNAME(mux_hsicphy_p)            = { "sclk_otgphy0", "sclk_otgphy1",
631                                     "gpll", "cpll" };
632
633 static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
634         COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
635                         RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
636                         div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
637
638         /* do not source aclk_cpu_pre from the apll, to keep complexity down */
639         COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT,
640                         RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS),
641         DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
642                         RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
643         DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
644                         RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
645         COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
646                         RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
647                         RK2928_CLKGATE_CON(4), 9, GFLAGS),
648
649         GATE(CORE_L2C, "core_l2c", "armclk", CLK_IGNORE_UNUSED,
650                         RK2928_CLKGATE_CON(9), 4, GFLAGS),
651
652         COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,
653                         RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
654                         RK2928_CLKGATE_CON(2), 0, GFLAGS),
655
656         COMPOSITE(DCLK_LCDC0, "dclk_lcdc0", mux_pll_src_cpll_gpll_p, 0,
657                         RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
658                         RK2928_CLKGATE_CON(3), 1, GFLAGS),
659         COMPOSITE(DCLK_LCDC1, "dclk_lcdc1", mux_pll_src_cpll_gpll_p, 0,
660                         RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
661                         RK2928_CLKGATE_CON(3), 2, GFLAGS),
662
663         COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
664                         RK2928_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 5, DFLAGS,
665                         RK2928_CLKGATE_CON(3), 15, GFLAGS),
666         GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
667                         RK2928_CLKGATE_CON(9), 7, GFLAGS),
668
669         GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS),
670         GATE(SCLK_TIMER3, "timer3", "xin24m", 0, RK2928_CLKGATE_CON(1), 2, GFLAGS),
671         GATE(SCLK_TIMER4, "timer4", "xin24m", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
672         GATE(SCLK_TIMER5, "timer5", "xin24m", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
673         GATE(SCLK_TIMER6, "timer6", "xin24m", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
674
675         COMPOSITE_NODIV(0, "sclk_hsicphy_480m", mux_hsicphy_p, 0,
676                         RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
677                         RK2928_CLKGATE_CON(3), 6, GFLAGS),
678         DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
679                         RK2928_CLKSEL_CON(11), 8, 6, DFLAGS),
680
681         MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
682                         RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
683         COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
684                         RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
685                         RK2928_CLKGATE_CON(0), 9, GFLAGS),
686         COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0,
687                         RK2928_CLKSEL_CON(7), 0,
688                         RK2928_CLKGATE_CON(0), 10, GFLAGS),
689         MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
690                         RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
691
692         GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
693         GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
694
695         GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
696                         RK2928_CLKGATE_CON(7), 3, GFLAGS),
697         GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
698
699         GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
700
701         GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
702         GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
703
704         GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
705 };
706
707 static const char *rk3188_critical_clocks[] __initconst = {
708         "aclk_cpu",
709         "aclk_peri",
710         "hclk_peri",
711 };
712
713 static void __init rk3188_common_clk_init(struct device_node *np)
714 {
715         void __iomem *reg_base;
716         struct clk *clk;
717
718         reg_base = of_iomap(np, 0);
719         if (!reg_base) {
720                 pr_err("%s: could not map cru region\n", __func__);
721                 return;
722         }
723
724         rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
725
726         /* xin12m is created by an cru-internal divider */
727         clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
728         if (IS_ERR(clk))
729                 pr_warn("%s: could not register clock xin12m: %ld\n",
730                         __func__, PTR_ERR(clk));
731
732         clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
733         if (IS_ERR(clk))
734                 pr_warn("%s: could not register clock usb480m: %ld\n",
735                         __func__, PTR_ERR(clk));
736
737         rockchip_clk_register_branches(common_clk_branches,
738                                   ARRAY_SIZE(common_clk_branches));
739         rockchip_clk_protect_critical(rk3188_critical_clocks,
740                                       ARRAY_SIZE(rk3188_critical_clocks));
741
742         rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
743                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
744
745         rockchip_register_restart_notifier(RK2928_GLB_SRST_FST);
746 }
747
748 static void __init rk3066a_clk_init(struct device_node *np)
749 {
750         rk3188_common_clk_init(np);
751         rockchip_clk_register_plls(rk3066_pll_clks,
752                                    ARRAY_SIZE(rk3066_pll_clks),
753                                    RK3066_GRF_SOC_STATUS);
754         rockchip_clk_register_branches(rk3066a_clk_branches,
755                                   ARRAY_SIZE(rk3066a_clk_branches));
756         rockchip_clk_register_armclk(ARMCLK, "armclk",
757                         mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
758                         &rk3066_cpuclk_data, rk3066_cpuclk_rates,
759                         ARRAY_SIZE(rk3066_cpuclk_rates));
760 }
761 CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
762
763 static void __init rk3188a_clk_init(struct device_node *np)
764 {
765         struct clk *clk1, *clk2;
766         unsigned long rate;
767         int ret;
768
769         rk3188_common_clk_init(np);
770         rockchip_clk_register_plls(rk3188_pll_clks,
771                                    ARRAY_SIZE(rk3188_pll_clks),
772                                    RK3188_GRF_SOC_STATUS);
773         rockchip_clk_register_branches(rk3188_clk_branches,
774                                   ARRAY_SIZE(rk3188_clk_branches));
775         rockchip_clk_register_armclk(ARMCLK, "armclk",
776                                   mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
777                                   &rk3188_cpuclk_data, rk3188_cpuclk_rates,
778                                   ARRAY_SIZE(rk3188_cpuclk_rates));
779
780         /* reparent aclk_cpu_pre from apll */
781         clk1 = __clk_lookup("aclk_cpu_pre");
782         clk2 = __clk_lookup("gpll");
783         if (clk1 && clk2) {
784                 rate = clk_get_rate(clk1);
785
786                 ret = clk_set_parent(clk1, clk2);
787                 if (ret < 0)
788                         pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n",
789                                 __func__);
790
791                 clk_set_rate(clk1, rate);
792         } else {
793                 pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n",
794                         __func__);
795         }
796 }
797 CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init);
798
799 static void __init rk3188_clk_init(struct device_node *np)
800 {
801         int i;
802
803         for (i = 0; i < ARRAY_SIZE(rk3188_pll_clks); i++) {
804                 struct rockchip_pll_clock *pll = &rk3188_pll_clks[i];
805                 struct rockchip_pll_rate_table *rate;
806
807                 if (!pll->rate_table)
808                         continue;
809
810                 rate = pll->rate_table;
811                 while (rate->rate > 0) {
812                         rate->bwadj = 0;
813                         rate++;
814                 }
815         }
816
817         rk3188a_clk_init(np);
818 }
819 CLK_OF_DECLARE(rk3188_cru, "rockchip,rk3188-cru", rk3188_clk_init);