drivers/clk/qcom/mmcc-msm8960.c

   1 /*
   2  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/delay.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/clk-provider.h>
  23 #include <linux/regmap.h>
  24 #include <linux/reset-controller.h>
  25
  26 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
  27 #include <dt-bindings/reset/qcom,mmcc-msm8960.h>
  28
  29 #include "common.h"
  30 #include "clk-regmap.h"
  31 #include "clk-pll.h"
  32 #include "clk-rcg.h"
  33 #include "clk-branch.h"
  34 #include "reset.h"
  35
  36 #define P_PXO   0
  37 #define P_PLL8  1
  38 #define P_PLL2  2
  39 #define P_PLL3  3
  40
  41 static u8 mmcc_pxo_pll8_pll2_map[] = {
  42         [P_PXO]         = 0,
  43         [P_PLL8]        = 2,
  44         [P_PLL2]        = 1,
  45 };
  46
  47 static const char *mmcc_pxo_pll8_pll2[] = {
  48         "pxo",
  49         "pll8_vote",
  50         "pll2",
  51 };
  52
  53 static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
  54         [P_PXO]         = 0,
  55         [P_PLL8]        = 2,
  56         [P_PLL2]        = 1,
  57         [P_PLL3]        = 3,
  58 };
  59
  60 static const char *mmcc_pxo_pll8_pll2_pll3[] = {
  61         "pxo",
  62         "pll2",
  63         "pll8_vote",
  64         "pll3",
  65 };
  66
  67 static struct clk_pll pll2 = {
  68         .l_reg = 0x320,
  69         .m_reg = 0x324,
  70         .n_reg = 0x328,
  71         .config_reg = 0x32c,
  72         .mode_reg = 0x31c,
  73         .status_reg = 0x334,
  74         .status_bit = 16,
  75         .clkr.hw.init = &(struct clk_init_data){
  76                 .name = "pll2",
  77                 .parent_names = (const char *[]){ "pxo" },
  78                 .num_parents = 1,
  79                 .ops = &clk_pll_ops,
  80         },
  81 };
  82
  83 static struct freq_tbl clk_tbl_cam[] = {
  84         {   6000000, P_PLL8, 4, 1, 16 },
  85         {   8000000, P_PLL8, 4, 1, 12 },
  86         {  12000000, P_PLL8, 4, 1,  8 },
  87         {  16000000, P_PLL8, 4, 1,  6 },
  88         {  19200000, P_PLL8, 4, 1,  5 },
  89         {  24000000, P_PLL8, 4, 1,  4 },
  90         {  32000000, P_PLL8, 4, 1,  3 },
  91         {  48000000, P_PLL8, 4, 1,  2 },
  92         {  64000000, P_PLL8, 3, 1,  2 },
  93         {  96000000, P_PLL8, 4, 0,  0 },
  94         { 128000000, P_PLL8, 3, 0,  0 },
  95         { }
  96 };
  97
  98 static struct clk_rcg camclk0_src = {
  99         .ns_reg = 0x0148,
 100         .md_reg = 0x0144,
 101         .mn = {
 102                 .mnctr_en_bit = 5,
 103                 .mnctr_reset_bit = 8,
 104                 .reset_in_cc = true,
 105                 .mnctr_mode_shift = 6,
 106                 .n_val_shift = 24,
 107                 .m_val_shift = 8,
 108                 .width = 8,
 109         },
 110         .p = {
 111                 .pre_div_shift = 14,
 112                 .pre_div_width = 2,
 113         },
 114         .s = {
 115                 .src_sel_shift = 0,
 116                 .parent_map = mmcc_pxo_pll8_pll2_map,
 117         },
 118         .freq_tbl = clk_tbl_cam,
 119         .clkr = {
 120                 .enable_reg = 0x0140,
 121                 .enable_mask = BIT(2),
 122                 .hw.init = &(struct clk_init_data){
 123                         .name = "camclk0_src",
 124                         .parent_names = mmcc_pxo_pll8_pll2,
 125                         .num_parents = 3,
 126                         .ops = &clk_rcg_ops,
 127                 },
 128         },
 129 };
 130
 131 static struct clk_branch camclk0_clk = {
 132         .halt_reg = 0x01e8,
 133         .halt_bit = 15,
 134         .clkr = {
 135                 .enable_reg = 0x0140,
 136                 .enable_mask = BIT(0),
 137                 .hw.init = &(struct clk_init_data){
 138                         .name = "camclk0_clk",
 139                         .parent_names = (const char *[]){ "camclk0_src" },
 140                         .num_parents = 1,
 141                         .ops = &clk_branch_ops,
 142                 },
 143         },
 144
 145 };
 146
 147 static struct clk_rcg camclk1_src = {
 148         .ns_reg = 0x015c,
 149         .md_reg = 0x0158,
 150         .mn = {
 151                 .mnctr_en_bit = 5,
 152                 .mnctr_reset_bit = 8,
 153                 .reset_in_cc = true,
 154                 .mnctr_mode_shift = 6,
 155                 .n_val_shift = 24,
 156                 .m_val_shift = 8,
 157                 .width = 8,
 158         },
 159         .p = {
 160                 .pre_div_shift = 14,
 161                 .pre_div_width = 2,
 162         },
 163         .s = {
 164                 .src_sel_shift = 0,
 165                 .parent_map = mmcc_pxo_pll8_pll2_map,
 166         },
 167         .freq_tbl = clk_tbl_cam,
 168         .clkr = {
 169                 .enable_reg = 0x0154,
 170                 .enable_mask = BIT(2),
 171                 .hw.init = &(struct clk_init_data){
 172                         .name = "camclk1_src",
 173                         .parent_names = mmcc_pxo_pll8_pll2,
 174                         .num_parents = 3,
 175                         .ops = &clk_rcg_ops,
 176                 },
 177         },
 178 };
 179
 180 static struct clk_branch camclk1_clk = {
 181         .halt_reg = 0x01e8,
 182         .halt_bit = 16,
 183         .clkr = {
 184                 .enable_reg = 0x0154,
 185                 .enable_mask = BIT(0),
 186                 .hw.init = &(struct clk_init_data){
 187                         .name = "camclk1_clk",
 188                         .parent_names = (const char *[]){ "camclk1_src" },
 189                         .num_parents = 1,
 190                         .ops = &clk_branch_ops,
 191                 },
 192         },
 193
 194 };
 195
 196 static struct clk_rcg camclk2_src = {
 197         .ns_reg = 0x0228,
 198         .md_reg = 0x0224,
 199         .mn = {
 200                 .mnctr_en_bit = 5,
 201                 .mnctr_reset_bit = 8,
 202                 .reset_in_cc = true,
 203                 .mnctr_mode_shift = 6,
 204                 .n_val_shift = 24,
 205                 .m_val_shift = 8,
 206                 .width = 8,
 207         },
 208         .p = {
 209                 .pre_div_shift = 14,
 210                 .pre_div_width = 2,
 211         },
 212         .s = {
 213                 .src_sel_shift = 0,
 214                 .parent_map = mmcc_pxo_pll8_pll2_map,
 215         },
 216         .freq_tbl = clk_tbl_cam,
 217         .clkr = {
 218                 .enable_reg = 0x0220,
 219                 .enable_mask = BIT(2),
 220                 .hw.init = &(struct clk_init_data){
 221                         .name = "camclk2_src",
 222                         .parent_names = mmcc_pxo_pll8_pll2,
 223                         .num_parents = 3,
 224                         .ops = &clk_rcg_ops,
 225                 },
 226         },
 227 };
 228
 229 static struct clk_branch camclk2_clk = {
 230         .halt_reg = 0x01e8,
 231         .halt_bit = 16,
 232         .clkr = {
 233                 .enable_reg = 0x0220,
 234                 .enable_mask = BIT(0),
 235                 .hw.init = &(struct clk_init_data){
 236                         .name = "camclk2_clk",
 237                         .parent_names = (const char *[]){ "camclk2_src" },
 238                         .num_parents = 1,
 239                         .ops = &clk_branch_ops,
 240                 },
 241         },
 242
 243 };
 244
 245 static struct freq_tbl clk_tbl_csi[] = {
 246         {  27000000, P_PXO,  1, 0, 0 },
 247         {  85330000, P_PLL8, 1, 2, 9 },
 248         { 177780000, P_PLL2, 1, 2, 9 },
 249         { }
 250 };
 251
 252 static struct clk_rcg csi0_src = {
 253         .ns_reg = 0x0048,
 254         .md_reg = 0x0044,
 255         .mn = {
 256                 .mnctr_en_bit = 5,
 257                 .mnctr_reset_bit = 7,
 258                 .mnctr_mode_shift = 6,
 259                 .n_val_shift = 24,
 260                 .m_val_shift = 8,
 261                 .width = 8,
 262         },
 263         .p = {
 264                 .pre_div_shift = 14,
 265                 .pre_div_width = 2,
 266         },
 267         .s = {
 268                 .src_sel_shift = 0,
 269                 .parent_map = mmcc_pxo_pll8_pll2_map,
 270         },
 271         .freq_tbl = clk_tbl_csi,
 272         .clkr = {
 273                 .enable_reg = 0x0040,
 274                 .enable_mask = BIT(2),
 275                 .hw.init = &(struct clk_init_data){
 276                         .name = "csi0_src",
 277                         .parent_names = mmcc_pxo_pll8_pll2,
 278                         .num_parents = 3,
 279                         .ops = &clk_rcg_ops,
 280                 },
 281         },
 282 };
 283
 284 static struct clk_branch csi0_clk = {
 285         .halt_reg = 0x01cc,
 286         .halt_bit = 13,
 287         .clkr = {
 288                 .enable_reg = 0x0040,
 289                 .enable_mask = BIT(0),
 290                 .hw.init = &(struct clk_init_data){
 291                         .parent_names = (const char *[]){ "csi0_src" },
 292                         .num_parents = 1,
 293                         .name = "csi0_clk",
 294                         .ops = &clk_branch_ops,
 295                         .flags = CLK_SET_RATE_PARENT,
 296                 },
 297         },
 298 };
 299
 300 static struct clk_branch csi0_phy_clk = {
 301         .halt_reg = 0x01e8,
 302         .halt_bit = 9,
 303         .clkr = {
 304                 .enable_reg = 0x0040,
 305                 .enable_mask = BIT(8),
 306                 .hw.init = &(struct clk_init_data){
 307                         .parent_names = (const char *[]){ "csi0_src" },
 308                         .num_parents = 1,
 309                         .name = "csi0_phy_clk",
 310                         .ops = &clk_branch_ops,
 311                         .flags = CLK_SET_RATE_PARENT,
 312                 },
 313         },
 314 };
 315
 316 static struct clk_rcg csi1_src = {
 317         .ns_reg = 0x0010,
 318         .md_reg = 0x0028,
 319         .mn = {
 320                 .mnctr_en_bit = 5,
 321                 .mnctr_reset_bit = 7,
 322                 .mnctr_mode_shift = 6,
 323                 .n_val_shift = 24,
 324                 .m_val_shift = 8,
 325                 .width = 8,
 326         },
 327         .p = {
 328                 .pre_div_shift = 14,
 329                 .pre_div_width = 2,
 330         },
 331         .s = {
 332                 .src_sel_shift = 0,
 333                 .parent_map = mmcc_pxo_pll8_pll2_map,
 334         },
 335         .freq_tbl = clk_tbl_csi,
 336         .clkr = {
 337                 .enable_reg = 0x0024,
 338                 .enable_mask = BIT(2),
 339                 .hw.init = &(struct clk_init_data){
 340                         .name = "csi1_src",
 341                         .parent_names = mmcc_pxo_pll8_pll2,
 342                         .num_parents = 3,
 343                         .ops = &clk_rcg_ops,
 344                 },
 345         },
 346 };
 347
 348 static struct clk_branch csi1_clk = {
 349         .halt_reg = 0x01cc,
 350         .halt_bit = 14,
 351         .clkr = {
 352                 .enable_reg = 0x0024,
 353                 .enable_mask = BIT(0),
 354                 .hw.init = &(struct clk_init_data){
 355                         .parent_names = (const char *[]){ "csi1_src" },
 356                         .num_parents = 1,
 357                         .name = "csi1_clk",
 358                         .ops = &clk_branch_ops,
 359                         .flags = CLK_SET_RATE_PARENT,
 360                 },
 361         },
 362 };
 363
 364 static struct clk_branch csi1_phy_clk = {
 365         .halt_reg = 0x01e8,
 366         .halt_bit = 10,
 367         .clkr = {
 368                 .enable_reg = 0x0024,
 369                 .enable_mask = BIT(8),
 370                 .hw.init = &(struct clk_init_data){
 371                         .parent_names = (const char *[]){ "csi1_src" },
 372                         .num_parents = 1,
 373                         .name = "csi1_phy_clk",
 374                         .ops = &clk_branch_ops,
 375                         .flags = CLK_SET_RATE_PARENT,
 376                 },
 377         },
 378 };
 379
 380 static struct clk_rcg csi2_src = {
 381         .ns_reg = 0x0234,
 382         .md_reg = 0x022c,
 383         .mn = {
 384                 .mnctr_en_bit = 5,
 385                 .mnctr_reset_bit = 7,
 386                 .mnctr_mode_shift = 6,
 387                 .n_val_shift = 24,
 388                 .m_val_shift = 8,
 389                 .width = 8,
 390         },
 391         .p = {
 392                 .pre_div_shift = 14,
 393                 .pre_div_width = 2,
 394         },
 395         .s = {
 396                 .src_sel_shift = 0,
 397                 .parent_map = mmcc_pxo_pll8_pll2_map,
 398         },
 399         .freq_tbl = clk_tbl_csi,
 400         .clkr = {
 401                 .enable_reg = 0x022c,
 402                 .enable_mask = BIT(2),
 403                 .hw.init = &(struct clk_init_data){
 404                         .name = "csi2_src",
 405                         .parent_names = mmcc_pxo_pll8_pll2,
 406                         .num_parents = 3,
 407                         .ops = &clk_rcg_ops,
 408                 },
 409         },
 410 };
 411
 412 static struct clk_branch csi2_clk = {
 413         .halt_reg = 0x01cc,
 414         .halt_bit = 29,
 415         .clkr = {
 416                 .enable_reg = 0x022c,
 417                 .enable_mask = BIT(0),
 418                 .hw.init = &(struct clk_init_data){
 419                         .parent_names = (const char *[]){ "csi2_src" },
 420                         .num_parents = 1,
 421                         .name = "csi2_clk",
 422                         .ops = &clk_branch_ops,
 423                         .flags = CLK_SET_RATE_PARENT,
 424                 },
 425         },
 426 };
 427
 428 static struct clk_branch csi2_phy_clk = {
 429         .halt_reg = 0x01e8,
 430         .halt_bit = 29,
 431         .clkr = {
 432                 .enable_reg = 0x022c,
 433                 .enable_mask = BIT(8),
 434                 .hw.init = &(struct clk_init_data){
 435                         .parent_names = (const char *[]){ "csi2_src" },
 436                         .num_parents = 1,
 437                         .name = "csi2_phy_clk",
 438                         .ops = &clk_branch_ops,
 439                         .flags = CLK_SET_RATE_PARENT,
 440                 },
 441         },
 442 };
 443
 444 struct clk_pix_rdi {
 445         u32 s_reg;
 446         u32 s_mask;
 447         u32 s2_reg;
 448         u32 s2_mask;
 449         struct clk_regmap clkr;
 450 };
 451
 452 #define to_clk_pix_rdi(_hw) \
 453         container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
 454
 455 static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
 456 {
 457         int i;
 458         int ret = 0;
 459         u32 val;
 460         struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
 461         struct clk *clk = hw->clk;
 462         int num_parents = __clk_get_num_parents(hw->clk);
 463
 464         /*
 465          * These clocks select three inputs via two muxes. One mux selects
 466          * between csi0 and csi1 and the second mux selects between that mux's
 467          * output and csi2. The source and destination selections for each
 468          * mux must be clocking for the switch to succeed so just turn on
 469          * all three sources because it's easier than figuring out what source
 470          * needs to be on at what time.
 471          */
 472         for (i = 0; i < num_parents; i++) {
 473                 ret = clk_prepare_enable(clk_get_parent_by_index(clk, i));
 474                 if (ret)
 475                         goto err;
 476         }
 477
 478         if (index == 2)
 479                 val = rdi->s2_mask;
 480         else
 481                 val = 0;
 482         regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
 483         /*
 484          * Wait at least 6 cycles of slowest clock
 485          * for the glitch-free MUX to fully switch sources.
 486          */
 487         udelay(1);
 488
 489         if (index == 1)
 490                 val = rdi->s_mask;
 491         else
 492                 val = 0;
 493         regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
 494         /*
 495          * Wait at least 6 cycles of slowest clock
 496          * for the glitch-free MUX to fully switch sources.
 497          */
 498         udelay(1);
 499
 500 err:
 501         for (i--; i >= 0; i--)
 502                 clk_disable_unprepare(clk_get_parent_by_index(clk, i));
 503
 504         return ret;
 505 }
 506
 507 static u8 pix_rdi_get_parent(struct clk_hw *hw)
 508 {
 509         u32 val;
 510         struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
 511
 512
 513         regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
 514         if (val & rdi->s2_mask)
 515                 return 2;
 516
 517         regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
 518         if (val & rdi->s_mask)
 519                 return 1;
 520
 521         return 0;
 522 }
 523
 524 static const struct clk_ops clk_ops_pix_rdi = {
 525         .enable = clk_enable_regmap,
 526         .disable = clk_disable_regmap,
 527         .set_parent = pix_rdi_set_parent,
 528         .get_parent = pix_rdi_get_parent,
 529         .determine_rate = __clk_mux_determine_rate,
 530 };
 531
 532 static const char *pix_rdi_parents[] = {
 533         "csi0_clk",
 534         "csi1_clk",
 535         "csi2_clk",
 536 };
 537
 538 static struct clk_pix_rdi csi_pix_clk = {
 539         .s_reg = 0x0058,
 540         .s_mask = BIT(25),
 541         .s2_reg = 0x0238,
 542         .s2_mask = BIT(13),
 543         .clkr = {
 544                 .enable_reg = 0x0058,
 545                 .enable_mask = BIT(26),
 546                 .hw.init = &(struct clk_init_data){
 547                         .name = "csi_pix_clk",
 548                         .parent_names = pix_rdi_parents,
 549                         .num_parents = 3,
 550                         .ops = &clk_ops_pix_rdi,
 551                 },
 552         },
 553 };
 554
 555 static struct clk_pix_rdi csi_pix1_clk = {
 556         .s_reg = 0x0238,
 557         .s_mask = BIT(8),
 558         .s2_reg = 0x0238,
 559         .s2_mask = BIT(9),
 560         .clkr = {
 561                 .enable_reg = 0x0238,
 562                 .enable_mask = BIT(10),
 563                 .hw.init = &(struct clk_init_data){
 564                         .name = "csi_pix1_clk",
 565                         .parent_names = pix_rdi_parents,
 566                         .num_parents = 3,
 567                         .ops = &clk_ops_pix_rdi,
 568                 },
 569         },
 570 };
 571
 572 static struct clk_pix_rdi csi_rdi_clk = {
 573         .s_reg = 0x0058,
 574         .s_mask = BIT(12),
 575         .s2_reg = 0x0238,
 576         .s2_mask = BIT(12),
 577         .clkr = {
 578                 .enable_reg = 0x0058,
 579                 .enable_mask = BIT(13),
 580                 .hw.init = &(struct clk_init_data){
 581                         .name = "csi_rdi_clk",
 582                         .parent_names = pix_rdi_parents,
 583                         .num_parents = 3,
 584                         .ops = &clk_ops_pix_rdi,
 585                 },
 586         },
 587 };
 588
 589 static struct clk_pix_rdi csi_rdi1_clk = {
 590         .s_reg = 0x0238,
 591         .s_mask = BIT(0),
 592         .s2_reg = 0x0238,
 593         .s2_mask = BIT(1),
 594         .clkr = {
 595                 .enable_reg = 0x0238,
 596                 .enable_mask = BIT(2),
 597                 .hw.init = &(struct clk_init_data){
 598                         .name = "csi_rdi1_clk",
 599                         .parent_names = pix_rdi_parents,
 600                         .num_parents = 3,
 601                         .ops = &clk_ops_pix_rdi,
 602                 },
 603         },
 604 };
 605
 606 static struct clk_pix_rdi csi_rdi2_clk = {
 607         .s_reg = 0x0238,
 608         .s_mask = BIT(4),
 609         .s2_reg = 0x0238,
 610         .s2_mask = BIT(5),
 611         .clkr = {
 612                 .enable_reg = 0x0238,
 613                 .enable_mask = BIT(6),
 614                 .hw.init = &(struct clk_init_data){
 615                         .name = "csi_rdi2_clk",
 616                         .parent_names = pix_rdi_parents,
 617                         .num_parents = 3,
 618                         .ops = &clk_ops_pix_rdi,
 619                 },
 620         },
 621 };
 622
 623 static struct freq_tbl clk_tbl_csiphytimer[] = {
 624         {  85330000, P_PLL8, 1, 2, 9 },
 625         { 177780000, P_PLL2, 1, 2, 9 },
 626         { }
 627 };
 628
 629 static struct clk_rcg csiphytimer_src = {
 630         .ns_reg = 0x0168,
 631         .md_reg = 0x0164,
 632         .mn = {
 633                 .mnctr_en_bit = 5,
 634                 .mnctr_reset_bit = 8,
 635                 .reset_in_cc = true,
 636                 .mnctr_mode_shift = 6,
 637                 .n_val_shift = 24,
 638                 .m_val_shift = 8,
 639                 .width = 8,
 640         },
 641         .p = {
 642                 .pre_div_shift = 14,
 643                 .pre_div_width = 2,
 644         },
 645         .s = {
 646                 .src_sel_shift = 0,
 647                 .parent_map = mmcc_pxo_pll8_pll2_map,
 648         },
 649         .freq_tbl = clk_tbl_csiphytimer,
 650         .clkr = {
 651                 .enable_reg = 0x0160,
 652                 .enable_mask = BIT(2),
 653                 .hw.init = &(struct clk_init_data){
 654                         .name = "csiphytimer_src",
 655                         .parent_names = mmcc_pxo_pll8_pll2,
 656                         .num_parents = 3,
 657                         .ops = &clk_rcg_ops,
 658                 },
 659         },
 660 };
 661
 662 static const char *csixphy_timer_src[] = { "csiphytimer_src" };
 663
 664 static struct clk_branch csiphy0_timer_clk = {
 665         .halt_reg = 0x01e8,
 666         .halt_bit = 17,
 667         .clkr = {
 668                 .enable_reg = 0x0160,
 669                 .enable_mask = BIT(0),
 670                 .hw.init = &(struct clk_init_data){
 671                         .parent_names = csixphy_timer_src,
 672                         .num_parents = 1,
 673                         .name = "csiphy0_timer_clk",
 674                         .ops = &clk_branch_ops,
 675                         .flags = CLK_SET_RATE_PARENT,
 676                 },
 677         },
 678 };
 679
 680 static struct clk_branch csiphy1_timer_clk = {
 681         .halt_reg = 0x01e8,
 682         .halt_bit = 18,
 683         .clkr = {
 684                 .enable_reg = 0x0160,
 685                 .enable_mask = BIT(9),
 686                 .hw.init = &(struct clk_init_data){
 687                         .parent_names = csixphy_timer_src,
 688                         .num_parents = 1,
 689                         .name = "csiphy1_timer_clk",
 690                         .ops = &clk_branch_ops,
 691                         .flags = CLK_SET_RATE_PARENT,
 692                 },
 693         },
 694 };
 695
 696 static struct clk_branch csiphy2_timer_clk = {
 697         .halt_reg = 0x01e8,
 698         .halt_bit = 30,
 699         .clkr = {
 700                 .enable_reg = 0x0160,
 701                 .enable_mask = BIT(11),
 702                 .hw.init = &(struct clk_init_data){
 703                         .parent_names = csixphy_timer_src,
 704                         .num_parents = 1,
 705                         .name = "csiphy2_timer_clk",
 706                         .ops = &clk_branch_ops,
 707                         .flags = CLK_SET_RATE_PARENT,
 708                 },
 709         },
 710 };
 711
 712 static struct freq_tbl clk_tbl_gfx2d[] = {
 713         {  27000000, P_PXO,  1,  0 },
 714         {  48000000, P_PLL8, 1,  8 },
 715         {  54857000, P_PLL8, 1,  7 },
 716         {  64000000, P_PLL8, 1,  6 },
 717         {  76800000, P_PLL8, 1,  5 },
 718         {  96000000, P_PLL8, 1,  4 },
 719         { 128000000, P_PLL8, 1,  3 },
 720         { 145455000, P_PLL2, 2, 11 },
 721         { 160000000, P_PLL2, 1,  5 },
 722         { 177778000, P_PLL2, 2,  9 },
 723         { 200000000, P_PLL2, 1,  4 },
 724         { 228571000, P_PLL2, 2,  7 },
 725         { }
 726 };
 727
 728 static struct clk_dyn_rcg gfx2d0_src = {
 729         .ns_reg = 0x0070,
 730         .md_reg[0] = 0x0064,
 731         .md_reg[1] = 0x0068,
 732         .mn[0] = {
 733                 .mnctr_en_bit = 8,
 734                 .mnctr_reset_bit = 25,
 735                 .mnctr_mode_shift = 9,
 736                 .n_val_shift = 20,
 737                 .m_val_shift = 4,
 738                 .width = 4,
 739         },
 740         .mn[1] = {
 741                 .mnctr_en_bit = 5,
 742                 .mnctr_reset_bit = 24,
 743                 .mnctr_mode_shift = 6,
 744                 .n_val_shift = 16,
 745                 .m_val_shift = 4,
 746                 .width = 4,
 747         },
 748         .s[0] = {
 749                 .src_sel_shift = 3,
 750                 .parent_map = mmcc_pxo_pll8_pll2_map,
 751         },
 752         .s[1] = {
 753                 .src_sel_shift = 0,
 754                 .parent_map = mmcc_pxo_pll8_pll2_map,
 755         },
 756         .mux_sel_bit = 11,
 757         .freq_tbl = clk_tbl_gfx2d,
 758         .clkr = {
 759                 .enable_reg = 0x0060,
 760                 .enable_mask = BIT(2),
 761                 .hw.init = &(struct clk_init_data){
 762                         .name = "gfx2d0_src",
 763                         .parent_names = mmcc_pxo_pll8_pll2,
 764                         .num_parents = 3,
 765                         .ops = &clk_dyn_rcg_ops,
 766                 },
 767         },
 768 };
 769
 770 static struct clk_branch gfx2d0_clk = {
 771         .halt_reg = 0x01c8,
 772         .halt_bit = 9,
 773         .clkr = {
 774                 .enable_reg = 0x0060,
 775                 .enable_mask = BIT(0),
 776                 .hw.init = &(struct clk_init_data){
 777                         .name = "gfx2d0_clk",
 778                         .parent_names = (const char *[]){ "gfx2d0_src" },
 779                         .num_parents = 1,
 780                         .ops = &clk_branch_ops,
 781                         .flags = CLK_SET_RATE_PARENT,
 782                 },
 783         },
 784 };
 785
 786 static struct clk_dyn_rcg gfx2d1_src = {
 787         .ns_reg = 0x007c,
 788         .md_reg[0] = 0x0078,
 789         .md_reg[1] = 0x006c,
 790         .mn[0] = {
 791                 .mnctr_en_bit = 8,
 792                 .mnctr_reset_bit = 25,
 793                 .mnctr_mode_shift = 9,
 794                 .n_val_shift = 20,
 795                 .m_val_shift = 4,
 796                 .width = 4,
 797         },
 798         .mn[1] = {
 799                 .mnctr_en_bit = 5,
 800                 .mnctr_reset_bit = 24,
 801                 .mnctr_mode_shift = 6,
 802                 .n_val_shift = 16,
 803                 .m_val_shift = 4,
 804                 .width = 4,
 805         },
 806         .s[0] = {
 807                 .src_sel_shift = 3,
 808                 .parent_map = mmcc_pxo_pll8_pll2_map,
 809         },
 810         .s[1] = {
 811                 .src_sel_shift = 0,
 812                 .parent_map = mmcc_pxo_pll8_pll2_map,
 813         },
 814         .mux_sel_bit = 11,
 815         .freq_tbl = clk_tbl_gfx2d,
 816         .clkr = {
 817                 .enable_reg = 0x0074,
 818                 .enable_mask = BIT(2),
 819                 .hw.init = &(struct clk_init_data){
 820                         .name = "gfx2d1_src",
 821                         .parent_names = mmcc_pxo_pll8_pll2,
 822                         .num_parents = 3,
 823                         .ops = &clk_dyn_rcg_ops,
 824                 },
 825         },
 826 };
 827
 828 static struct clk_branch gfx2d1_clk = {
 829         .halt_reg = 0x01c8,
 830         .halt_bit = 14,
 831         .clkr = {
 832                 .enable_reg = 0x0074,
 833                 .enable_mask = BIT(0),
 834                 .hw.init = &(struct clk_init_data){
 835                         .name = "gfx2d1_clk",
 836                         .parent_names = (const char *[]){ "gfx2d1_src" },
 837                         .num_parents = 1,
 838                         .ops = &clk_branch_ops,
 839                         .flags = CLK_SET_RATE_PARENT,
 840                 },
 841         },
 842 };
 843
 844 static struct freq_tbl clk_tbl_gfx3d[] = {
 845         {  27000000, P_PXO,  1,  0 },
 846         {  48000000, P_PLL8, 1,  8 },
 847         {  54857000, P_PLL8, 1,  7 },
 848         {  64000000, P_PLL8, 1,  6 },
 849         {  76800000, P_PLL8, 1,  5 },
 850         {  96000000, P_PLL8, 1,  4 },
 851         { 128000000, P_PLL8, 1,  3 },
 852         { 145455000, P_PLL2, 2, 11 },
 853         { 160000000, P_PLL2, 1,  5 },
 854         { 177778000, P_PLL2, 2,  9 },
 855         { 200000000, P_PLL2, 1,  4 },
 856         { 228571000, P_PLL2, 2,  7 },
 857         { 266667000, P_PLL2, 1,  3 },
 858         { 300000000, P_PLL3, 1,  4 },
 859         { 320000000, P_PLL2, 2,  5 },
 860         { 400000000, P_PLL2, 1,  2 },
 861         { }
 862 };
 863
 864 static struct clk_dyn_rcg gfx3d_src = {
 865         .ns_reg = 0x008c,
 866         .md_reg[0] = 0x0084,
 867         .md_reg[1] = 0x0088,
 868         .mn[0] = {
 869                 .mnctr_en_bit = 8,
 870                 .mnctr_reset_bit = 25,
 871                 .mnctr_mode_shift = 9,
 872                 .n_val_shift = 18,
 873                 .m_val_shift = 4,
 874                 .width = 4,
 875         },
 876         .mn[1] = {
 877                 .mnctr_en_bit = 5,
 878                 .mnctr_reset_bit = 24,
 879                 .mnctr_mode_shift = 6,
 880                 .n_val_shift = 14,
 881                 .m_val_shift = 4,
 882                 .width = 4,
 883         },
 884         .s[0] = {
 885                 .src_sel_shift = 3,
 886                 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
 887         },
 888         .s[1] = {
 889                 .src_sel_shift = 0,
 890                 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
 891         },
 892         .mux_sel_bit = 11,
 893         .freq_tbl = clk_tbl_gfx3d,
 894         .clkr = {
 895                 .enable_reg = 0x0080,
 896                 .enable_mask = BIT(2),
 897                 .hw.init = &(struct clk_init_data){
 898                         .name = "gfx3d_src",
 899                         .parent_names = mmcc_pxo_pll8_pll2_pll3,
 900                         .num_parents = 3,
 901                         .ops = &clk_dyn_rcg_ops,
 902                 },
 903         },
 904 };
 905
 906 static struct clk_branch gfx3d_clk = {
 907         .halt_reg = 0x01c8,
 908         .halt_bit = 4,
 909         .clkr = {
 910                 .enable_reg = 0x0080,
 911                 .enable_mask = BIT(0),
 912                 .hw.init = &(struct clk_init_data){
 913                         .name = "gfx3d_clk",
 914                         .parent_names = (const char *[]){ "gfx3d_src" },
 915                         .num_parents = 1,
 916                         .ops = &clk_branch_ops,
 917                         .flags = CLK_SET_RATE_PARENT,
 918                 },
 919         },
 920 };
 921
 922 static struct freq_tbl clk_tbl_ijpeg[] = {
 923         {  27000000, P_PXO,  1, 0,  0 },
 924         {  36570000, P_PLL8, 1, 2, 21 },
 925         {  54860000, P_PLL8, 7, 0,  0 },
 926         {  96000000, P_PLL8, 4, 0,  0 },
 927         { 109710000, P_PLL8, 1, 2,  7 },
 928         { 128000000, P_PLL8, 3, 0,  0 },
 929         { 153600000, P_PLL8, 1, 2,  5 },
 930         { 200000000, P_PLL2, 4, 0,  0 },
 931         { 228571000, P_PLL2, 1, 2,  7 },
 932         { 266667000, P_PLL2, 1, 1,  3 },
 933         { 320000000, P_PLL2, 1, 2,  5 },
 934         { }
 935 };
 936
 937 static struct clk_rcg ijpeg_src = {
 938         .ns_reg = 0x00a0,
 939         .md_reg = 0x009c,
 940         .mn = {
 941                 .mnctr_en_bit = 5,
 942                 .mnctr_reset_bit = 7,
 943                 .mnctr_mode_shift = 6,
 944                 .n_val_shift = 16,
 945                 .m_val_shift = 8,
 946                 .width = 8,
 947         },
 948         .p = {
 949                 .pre_div_shift = 12,
 950                 .pre_div_width = 2,
 951         },
 952         .s = {
 953                 .src_sel_shift = 0,
 954                 .parent_map = mmcc_pxo_pll8_pll2_map,
 955         },
 956         .freq_tbl = clk_tbl_ijpeg,
 957         .clkr = {
 958                 .enable_reg = 0x0098,
 959                 .enable_mask = BIT(2),
 960                 .hw.init = &(struct clk_init_data){
 961                         .name = "ijpeg_src",
 962                         .parent_names = mmcc_pxo_pll8_pll2,
 963                         .num_parents = 3,
 964                         .ops = &clk_rcg_ops,
 965                 },
 966         },
 967 };
 968
 969 static struct clk_branch ijpeg_clk = {
 970         .halt_reg = 0x01c8,
 971         .halt_bit = 24,
 972         .clkr = {
 973                 .enable_reg = 0x0098,
 974                 .enable_mask = BIT(0),
 975                 .hw.init = &(struct clk_init_data){
 976                         .name = "ijpeg_clk",
 977                         .parent_names = (const char *[]){ "ijpeg_src" },
 978                         .num_parents = 1,
 979                         .ops = &clk_branch_ops,
 980                         .flags = CLK_SET_RATE_PARENT,
 981                 },
 982         },
 983 };
 984
 985 static struct freq_tbl clk_tbl_jpegd[] = {
 986         {  64000000, P_PLL8, 6 },
 987         {  76800000, P_PLL8, 5 },
 988         {  96000000, P_PLL8, 4 },
 989         { 160000000, P_PLL2, 5 },
 990         { 200000000, P_PLL2, 4 },
 991         { }
 992 };
 993
 994 static struct clk_rcg jpegd_src = {
 995         .ns_reg = 0x00ac,
 996         .p = {
 997                 .pre_div_shift = 12,
 998                 .pre_div_width = 2,
 999         },
1000         .s = {
1001                 .src_sel_shift = 0,
1002                 .parent_map = mmcc_pxo_pll8_pll2_map,
1003         },
1004         .freq_tbl = clk_tbl_jpegd,
1005         .clkr = {
1006                 .enable_reg = 0x00a4,
1007                 .enable_mask = BIT(2),
1008                 .hw.init = &(struct clk_init_data){
1009                         .name = "jpegd_src",
1010                         .parent_names = mmcc_pxo_pll8_pll2,
1011                         .num_parents = 3,
1012                         .ops = &clk_rcg_ops,
1013                 },
1014         },
1015 };
1016
1017 static struct clk_branch jpegd_clk = {
1018         .halt_reg = 0x01c8,
1019         .halt_bit = 19,
1020         .clkr = {
1021                 .enable_reg = 0x00a4,
1022                 .enable_mask = BIT(0),
1023                 .hw.init = &(struct clk_init_data){
1024                         .name = "jpegd_clk",
1025                         .parent_names = (const char *[]){ "jpegd_src" },
1026                         .num_parents = 1,
1027                         .ops = &clk_branch_ops,
1028                         .flags = CLK_SET_RATE_PARENT,
1029                 },
1030         },
1031 };
1032
1033 static struct freq_tbl clk_tbl_mdp[] = {
1034         {   9600000, P_PLL8, 1, 1, 40 },
1035         {  13710000, P_PLL8, 1, 1, 28 },
1036         {  27000000, P_PXO,  1, 0,  0 },
1037         {  29540000, P_PLL8, 1, 1, 13 },
1038         {  34910000, P_PLL8, 1, 1, 11 },
1039         {  38400000, P_PLL8, 1, 1, 10 },
1040         {  59080000, P_PLL8, 1, 2, 13 },
1041         {  76800000, P_PLL8, 1, 1,  5 },
1042         {  85330000, P_PLL8, 1, 2,  9 },
1043         {  96000000, P_PLL8, 1, 1,  4 },
1044         { 128000000, P_PLL8, 1, 1,  3 },
1045         { 160000000, P_PLL2, 1, 1,  5 },
1046         { 177780000, P_PLL2, 1, 2,  9 },
1047         { 200000000, P_PLL2, 1, 1,  4 },
1048         { 228571000, P_PLL2, 1, 2,  7 },
1049         { 266667000, P_PLL2, 1, 1,  3 },
1050         { }
1051 };
1052
1053 static struct clk_dyn_rcg mdp_src = {
1054         .ns_reg = 0x00d0,
1055         .md_reg[0] = 0x00c4,
1056         .md_reg[1] = 0x00c8,
1057         .mn[0] = {
1058                 .mnctr_en_bit = 8,
1059                 .mnctr_reset_bit = 31,
1060                 .mnctr_mode_shift = 9,
1061                 .n_val_shift = 22,
1062                 .m_val_shift = 8,
1063                 .width = 8,
1064         },
1065         .mn[1] = {
1066                 .mnctr_en_bit = 5,
1067                 .mnctr_reset_bit = 30,
1068                 .mnctr_mode_shift = 6,
1069                 .n_val_shift = 14,
1070                 .m_val_shift = 8,
1071                 .width = 8,
1072         },
1073         .s[0] = {
1074                 .src_sel_shift = 3,
1075                 .parent_map = mmcc_pxo_pll8_pll2_map,
1076         },
1077         .s[1] = {
1078                 .src_sel_shift = 0,
1079                 .parent_map = mmcc_pxo_pll8_pll2_map,
1080         },
1081         .mux_sel_bit = 11,
1082         .freq_tbl = clk_tbl_mdp,
1083         .clkr = {
1084                 .enable_reg = 0x00c0,
1085                 .enable_mask = BIT(2),
1086                 .hw.init = &(struct clk_init_data){
1087                         .name = "mdp_src",
1088                         .parent_names = mmcc_pxo_pll8_pll2,
1089                         .num_parents = 3,
1090                         .ops = &clk_dyn_rcg_ops,
1091                 },
1092         },
1093 };
1094
1095 static struct clk_branch mdp_clk = {
1096         .halt_reg = 0x01d0,
1097         .halt_bit = 10,
1098         .clkr = {
1099                 .enable_reg = 0x00c0,
1100                 .enable_mask = BIT(0),
1101                 .hw.init = &(struct clk_init_data){
1102                         .name = "mdp_clk",
1103                         .parent_names = (const char *[]){ "mdp_src" },
1104                         .num_parents = 1,
1105                         .ops = &clk_branch_ops,
1106                         .flags = CLK_SET_RATE_PARENT,
1107                 },
1108         },
1109 };
1110
1111 static struct clk_branch mdp_lut_clk = {
1112         .halt_reg = 0x01e8,
1113         .halt_bit = 13,
1114         .clkr = {
1115                 .enable_reg = 0x016c,
1116                 .enable_mask = BIT(0),
1117                 .hw.init = &(struct clk_init_data){
1118                         .parent_names = (const char *[]){ "mdp_clk" },
1119                         .num_parents = 1,
1120                         .name = "mdp_lut_clk",
1121                         .ops = &clk_branch_ops,
1122                         .flags = CLK_SET_RATE_PARENT,
1123                 },
1124         },
1125 };
1126
1127 static struct clk_branch mdp_vsync_clk = {
1128         .halt_reg = 0x01cc,
1129         .halt_bit = 22,
1130         .clkr = {
1131                 .enable_reg = 0x0058,
1132                 .enable_mask = BIT(6),
1133                 .hw.init = &(struct clk_init_data){
1134                         .name = "mdp_vsync_clk",
1135                         .parent_names = (const char *[]){ "pxo" },
1136                         .num_parents = 1,
1137                         .ops = &clk_branch_ops
1138                 },
1139         },
1140 };
1141
1142 static struct freq_tbl clk_tbl_rot[] = {
1143         {  27000000, P_PXO,   1 },
1144         {  29540000, P_PLL8, 13 },
1145         {  32000000, P_PLL8, 12 },
1146         {  38400000, P_PLL8, 10 },
1147         {  48000000, P_PLL8,  8 },
1148         {  54860000, P_PLL8,  7 },
1149         {  64000000, P_PLL8,  6 },
1150         {  76800000, P_PLL8,  5 },
1151         {  96000000, P_PLL8,  4 },
1152         { 100000000, P_PLL2,  8 },
1153         { 114290000, P_PLL2,  7 },
1154         { 133330000, P_PLL2,  6 },
1155         { 160000000, P_PLL2,  5 },
1156         { 200000000, P_PLL2,  4 },
1157         { }
1158 };
1159
1160 static struct clk_dyn_rcg rot_src = {
1161         .ns_reg = 0x00e8,
1162         .p[0] = {
1163                 .pre_div_shift = 22,
1164                 .pre_div_width = 4,
1165         },
1166         .p[1] = {
1167                 .pre_div_shift = 26,
1168                 .pre_div_width = 4,
1169         },
1170         .s[0] = {
1171                 .src_sel_shift = 16,
1172                 .parent_map = mmcc_pxo_pll8_pll2_map,
1173         },
1174         .s[1] = {
1175                 .src_sel_shift = 19,
1176                 .parent_map = mmcc_pxo_pll8_pll2_map,
1177         },
1178         .mux_sel_bit = 30,
1179         .freq_tbl = clk_tbl_rot,
1180         .clkr = {
1181                 .enable_reg = 0x00e0,
1182                 .enable_mask = BIT(2),
1183                 .hw.init = &(struct clk_init_data){
1184                         .name = "rot_src",
1185                         .parent_names = mmcc_pxo_pll8_pll2,
1186                         .num_parents = 3,
1187                         .ops = &clk_dyn_rcg_ops,
1188                 },
1189         },
1190 };
1191
1192 static struct clk_branch rot_clk = {
1193         .halt_reg = 0x01d0,
1194         .halt_bit = 15,
1195         .clkr = {
1196                 .enable_reg = 0x00e0,
1197                 .enable_mask = BIT(0),
1198                 .hw.init = &(struct clk_init_data){
1199                         .name = "rot_clk",
1200                         .parent_names = (const char *[]){ "rot_src" },
1201                         .num_parents = 1,
1202                         .ops = &clk_branch_ops,
1203                         .flags = CLK_SET_RATE_PARENT,
1204                 },
1205         },
1206 };
1207
1208 #define P_HDMI_PLL 1
1209
1210 static u8 mmcc_pxo_hdmi_map[] = {
1211         [P_PXO]         = 0,
1212         [P_HDMI_PLL]    = 2,
1213 };
1214
1215 static const char *mmcc_pxo_hdmi[] = {
1216         "pxo",
1217         "hdmi_pll",
1218 };
1219
1220 static struct freq_tbl clk_tbl_tv[] = {
1221         {  25200000, P_HDMI_PLL, 1, 0, 0 },
1222         {  27000000, P_HDMI_PLL, 1, 0, 0 },
1223         {  27030000, P_HDMI_PLL, 1, 0, 0 },
1224         {  74250000, P_HDMI_PLL, 1, 0, 0 },
1225         { 108000000, P_HDMI_PLL, 1, 0, 0 },
1226         { 148500000, P_HDMI_PLL, 1, 0, 0 },
1227         { }
1228 };
1229
1230 static struct clk_rcg tv_src = {
1231         .ns_reg = 0x00f4,
1232         .md_reg = 0x00f0,
1233         .mn = {
1234                 .mnctr_en_bit = 5,
1235                 .mnctr_reset_bit = 7,
1236                 .mnctr_mode_shift = 6,
1237                 .n_val_shift = 16,
1238                 .m_val_shift = 8,
1239                 .width = 8,
1240         },
1241         .p = {
1242                 .pre_div_shift = 14,
1243                 .pre_div_width = 2,
1244         },
1245         .s = {
1246                 .src_sel_shift = 0,
1247                 .parent_map = mmcc_pxo_hdmi_map,
1248         },
1249         .freq_tbl = clk_tbl_tv,
1250         .clkr = {
1251                 .enable_reg = 0x00ec,
1252                 .enable_mask = BIT(2),
1253                 .hw.init = &(struct clk_init_data){
1254                         .name = "tv_src",
1255                         .parent_names = mmcc_pxo_hdmi,
1256                         .num_parents = 2,
1257                         .ops = &clk_rcg_ops,
1258                         .flags = CLK_SET_RATE_PARENT,
1259                 },
1260         },
1261 };
1262
1263 static const char *tv_src_name[] = { "tv_src" };
1264
1265 static struct clk_branch tv_enc_clk = {
1266         .halt_reg = 0x01d4,
1267         .halt_bit = 9,
1268         .clkr = {
1269                 .enable_reg = 0x00ec,
1270                 .enable_mask = BIT(8),
1271                 .hw.init = &(struct clk_init_data){
1272                         .parent_names = tv_src_name,
1273                         .num_parents = 1,
1274                         .name = "tv_enc_clk",
1275                         .ops = &clk_branch_ops,
1276                         .flags = CLK_SET_RATE_PARENT,
1277                 },
1278         },
1279 };
1280
1281 static struct clk_branch tv_dac_clk = {
1282         .halt_reg = 0x01d4,
1283         .halt_bit = 10,
1284         .clkr = {
1285                 .enable_reg = 0x00ec,
1286                 .enable_mask = BIT(10),
1287                 .hw.init = &(struct clk_init_data){
1288                         .parent_names = tv_src_name,
1289                         .num_parents = 1,
1290                         .name = "tv_dac_clk",
1291                         .ops = &clk_branch_ops,
1292                         .flags = CLK_SET_RATE_PARENT,
1293                 },
1294         },
1295 };
1296
1297 static struct clk_branch mdp_tv_clk = {
1298         .halt_reg = 0x01d4,
1299         .halt_bit = 12,
1300         .clkr = {
1301                 .enable_reg = 0x00ec,
1302                 .enable_mask = BIT(0),
1303                 .hw.init = &(struct clk_init_data){
1304                         .parent_names = tv_src_name,
1305                         .num_parents = 1,
1306                         .name = "mdp_tv_clk",
1307                         .ops = &clk_branch_ops,
1308                         .flags = CLK_SET_RATE_PARENT,
1309                 },
1310         },
1311 };
1312
1313 static struct clk_branch hdmi_tv_clk = {
1314         .halt_reg = 0x01d4,
1315         .halt_bit = 11,
1316         .clkr = {
1317                 .enable_reg = 0x00ec,
1318                 .enable_mask = BIT(12),
1319                 .hw.init = &(struct clk_init_data){
1320                         .parent_names = tv_src_name,
1321                         .num_parents = 1,
1322                         .name = "hdmi_tv_clk",
1323                         .ops = &clk_branch_ops,
1324                         .flags = CLK_SET_RATE_PARENT,
1325                 },
1326         },
1327 };
1328
1329 static struct clk_branch hdmi_app_clk = {
1330         .halt_reg = 0x01cc,
1331         .halt_bit = 25,
1332         .clkr = {
1333                 .enable_reg = 0x005c,
1334                 .enable_mask = BIT(11),
1335                 .hw.init = &(struct clk_init_data){
1336                         .parent_names = (const char *[]){ "pxo" },
1337                         .num_parents = 1,
1338                         .name = "hdmi_app_clk",
1339                         .ops = &clk_branch_ops,
1340                 },
1341         },
1342 };
1343
1344 static struct freq_tbl clk_tbl_vcodec[] = {
1345         {  27000000, P_PXO,  1,  0 },
1346         {  32000000, P_PLL8, 1, 12 },
1347         {  48000000, P_PLL8, 1,  8 },
1348         {  54860000, P_PLL8, 1,  7 },
1349         {  96000000, P_PLL8, 1,  4 },
1350         { 133330000, P_PLL2, 1,  6 },
1351         { 200000000, P_PLL2, 1,  4 },
1352         { 228570000, P_PLL2, 2,  7 },
1353         { 266670000, P_PLL2, 1,  3 },
1354         { }
1355 };
1356
1357 static struct clk_dyn_rcg vcodec_src = {
1358         .ns_reg = 0x0100,
1359         .md_reg[0] = 0x00fc,
1360         .md_reg[1] = 0x0128,
1361         .mn[0] = {
1362                 .mnctr_en_bit = 5,
1363                 .mnctr_reset_bit = 31,
1364                 .mnctr_mode_shift = 6,
1365                 .n_val_shift = 11,
1366                 .m_val_shift = 8,
1367                 .width = 8,
1368         },
1369         .mn[1] = {
1370                 .mnctr_en_bit = 10,
1371                 .mnctr_reset_bit = 30,
1372                 .mnctr_mode_shift = 11,
1373                 .n_val_shift = 19,
1374                 .m_val_shift = 8,
1375                 .width = 8,
1376         },
1377         .s[0] = {
1378                 .src_sel_shift = 27,
1379                 .parent_map = mmcc_pxo_pll8_pll2_map,
1380         },
1381         .s[1] = {
1382                 .src_sel_shift = 0,
1383                 .parent_map = mmcc_pxo_pll8_pll2_map,
1384         },
1385         .mux_sel_bit = 13,
1386         .freq_tbl = clk_tbl_vcodec,
1387         .clkr = {
1388                 .enable_reg = 0x00f8,
1389                 .enable_mask = BIT(2),
1390                 .hw.init = &(struct clk_init_data){
1391                         .name = "vcodec_src",
1392                         .parent_names = mmcc_pxo_pll8_pll2,
1393                         .num_parents = 3,
1394                         .ops = &clk_dyn_rcg_ops,
1395                 },
1396         },
1397 };
1398
1399 static struct clk_branch vcodec_clk = {
1400         .halt_reg = 0x01d0,
1401         .halt_bit = 29,
1402         .clkr = {
1403                 .enable_reg = 0x00f8,
1404                 .enable_mask = BIT(0),
1405                 .hw.init = &(struct clk_init_data){
1406                         .name = "vcodec_clk",
1407                         .parent_names = (const char *[]){ "vcodec_src" },
1408                         .num_parents = 1,
1409                         .ops = &clk_branch_ops,
1410                         .flags = CLK_SET_RATE_PARENT,
1411                 },
1412         },
1413 };
1414
1415 static struct freq_tbl clk_tbl_vpe[] = {
1416         {  27000000, P_PXO,   1 },
1417         {  34909000, P_PLL8, 11 },
1418         {  38400000, P_PLL8, 10 },
1419         {  64000000, P_PLL8,  6 },
1420         {  76800000, P_PLL8,  5 },
1421         {  96000000, P_PLL8,  4 },
1422         { 100000000, P_PLL2,  8 },
1423         { 160000000, P_PLL2,  5 },
1424         { }
1425 };
1426
1427 static struct clk_rcg vpe_src = {
1428         .ns_reg = 0x0118,
1429         .p = {
1430                 .pre_div_shift = 12,
1431                 .pre_div_width = 4,
1432         },
1433         .s = {
1434                 .src_sel_shift = 0,
1435                 .parent_map = mmcc_pxo_pll8_pll2_map,
1436         },
1437         .freq_tbl = clk_tbl_vpe,
1438         .clkr = {
1439                 .enable_reg = 0x0110,
1440                 .enable_mask = BIT(2),
1441                 .hw.init = &(struct clk_init_data){
1442                         .name = "vpe_src",
1443                         .parent_names = mmcc_pxo_pll8_pll2,
1444                         .num_parents = 3,
1445                         .ops = &clk_rcg_ops,
1446                 },
1447         },
1448 };
1449
1450 static struct clk_branch vpe_clk = {
1451         .halt_reg = 0x01c8,
1452         .halt_bit = 28,
1453         .clkr = {
1454                 .enable_reg = 0x0110,
1455                 .enable_mask = BIT(0),
1456                 .hw.init = &(struct clk_init_data){
1457                         .name = "vpe_clk",
1458                         .parent_names = (const char *[]){ "vpe_src" },
1459                         .num_parents = 1,
1460                         .ops = &clk_branch_ops,
1461                         .flags = CLK_SET_RATE_PARENT,
1462                 },
1463         },
1464 };
1465
1466 static struct freq_tbl clk_tbl_vfe[] = {
1467         {  13960000, P_PLL8,  1, 2, 55 },
1468         {  27000000, P_PXO,   1, 0,  0 },
1469         {  36570000, P_PLL8,  1, 2, 21 },
1470         {  38400000, P_PLL8,  2, 1,  5 },
1471         {  45180000, P_PLL8,  1, 2, 17 },
1472         {  48000000, P_PLL8,  2, 1,  4 },
1473         {  54860000, P_PLL8,  1, 1,  7 },
1474         {  64000000, P_PLL8,  2, 1,  3 },
1475         {  76800000, P_PLL8,  1, 1,  5 },
1476         {  96000000, P_PLL8,  2, 1,  2 },
1477         { 109710000, P_PLL8,  1, 2,  7 },
1478         { 128000000, P_PLL8,  1, 1,  3 },
1479         { 153600000, P_PLL8,  1, 2,  5 },
1480         { 200000000, P_PLL2,  2, 1,  2 },
1481         { 228570000, P_PLL2,  1, 2,  7 },
1482         { 266667000, P_PLL2,  1, 1,  3 },
1483         { 320000000, P_PLL2,  1, 2,  5 },
1484         { }
1485 };
1486
1487 static struct clk_rcg vfe_src = {
1488         .ns_reg = 0x0108,
1489         .mn = {
1490                 .mnctr_en_bit = 5,
1491                 .mnctr_reset_bit = 7,
1492                 .mnctr_mode_shift = 6,
1493                 .n_val_shift = 16,
1494                 .m_val_shift = 8,
1495                 .width = 8,
1496         },
1497         .p = {
1498                 .pre_div_shift = 10,
1499                 .pre_div_width = 1,
1500         },
1501         .s = {
1502                 .src_sel_shift = 0,
1503                 .parent_map = mmcc_pxo_pll8_pll2_map,
1504         },
1505         .freq_tbl = clk_tbl_vfe,
1506         .clkr = {
1507                 .enable_reg = 0x0104,
1508                 .enable_mask = BIT(2),
1509                 .hw.init = &(struct clk_init_data){
1510                         .name = "vfe_src",
1511                         .parent_names = mmcc_pxo_pll8_pll2,
1512                         .num_parents = 3,
1513                         .ops = &clk_rcg_ops,
1514                 },
1515         },
1516 };
1517
1518 static struct clk_branch vfe_clk = {
1519         .halt_reg = 0x01cc,
1520         .halt_bit = 6,
1521         .clkr = {
1522                 .enable_reg = 0x0104,
1523                 .enable_mask = BIT(0),
1524                 .hw.init = &(struct clk_init_data){
1525                         .name = "vfe_clk",
1526                         .parent_names = (const char *[]){ "vfe_src" },
1527                         .num_parents = 1,
1528                         .ops = &clk_branch_ops,
1529                         .flags = CLK_SET_RATE_PARENT,
1530                 },
1531         },
1532 };
1533
1534 static struct clk_branch vfe_csi_clk = {
1535         .halt_reg = 0x01cc,
1536         .halt_bit = 8,
1537         .clkr = {
1538                 .enable_reg = 0x0104,
1539                 .enable_mask = BIT(12),
1540                 .hw.init = &(struct clk_init_data){
1541                         .parent_names = (const char *[]){ "vfe_src" },
1542                         .num_parents = 1,
1543                         .name = "vfe_csi_clk",
1544                         .ops = &clk_branch_ops,
1545                         .flags = CLK_SET_RATE_PARENT,
1546                 },
1547         },
1548 };
1549
1550 static struct clk_branch gmem_axi_clk = {
1551         .halt_reg = 0x01d8,
1552         .halt_bit = 6,
1553         .clkr = {
1554                 .enable_reg = 0x0018,
1555                 .enable_mask = BIT(24),
1556                 .hw.init = &(struct clk_init_data){
1557                         .name = "gmem_axi_clk",
1558                         .ops = &clk_branch_ops,
1559                         .flags = CLK_IS_ROOT,
1560                 },
1561         },
1562 };
1563
1564 static struct clk_branch ijpeg_axi_clk = {
1565         .hwcg_reg = 0x0018,
1566         .hwcg_bit = 11,
1567         .halt_reg = 0x01d8,
1568         .halt_bit = 4,
1569         .clkr = {
1570                 .enable_reg = 0x0018,
1571                 .enable_mask = BIT(21),
1572                 .hw.init = &(struct clk_init_data){
1573                         .name = "ijpeg_axi_clk",
1574                         .ops = &clk_branch_ops,
1575                         .flags = CLK_IS_ROOT,
1576                 },
1577         },
1578 };
1579
1580 static struct clk_branch mmss_imem_axi_clk = {
1581         .hwcg_reg = 0x0018,
1582         .hwcg_bit = 15,
1583         .halt_reg = 0x01d8,
1584         .halt_bit = 7,
1585         .clkr = {
1586                 .enable_reg = 0x0018,
1587                 .enable_mask = BIT(22),
1588                 .hw.init = &(struct clk_init_data){
1589                         .name = "mmss_imem_axi_clk",
1590                         .ops = &clk_branch_ops,
1591                         .flags = CLK_IS_ROOT,
1592                 },
1593         },
1594 };
1595
1596 static struct clk_branch jpegd_axi_clk = {
1597         .halt_reg = 0x01d8,
1598         .halt_bit = 5,
1599         .clkr = {
1600                 .enable_reg = 0x0018,
1601                 .enable_mask = BIT(25),
1602                 .hw.init = &(struct clk_init_data){
1603                         .name = "jpegd_axi_clk",
1604                         .ops = &clk_branch_ops,
1605                         .flags = CLK_IS_ROOT,
1606                 },
1607         },
1608 };
1609
1610 static struct clk_branch vcodec_axi_b_clk = {
1611         .hwcg_reg = 0x0114,
1612         .hwcg_bit = 22,
1613         .halt_reg = 0x01e8,
1614         .halt_bit = 25,
1615         .clkr = {
1616                 .enable_reg = 0x0114,
1617                 .enable_mask = BIT(23),
1618                 .hw.init = &(struct clk_init_data){
1619                         .name = "vcodec_axi_b_clk",
1620                         .ops = &clk_branch_ops,
1621                         .flags = CLK_IS_ROOT,
1622                 },
1623         },
1624 };
1625
1626 static struct clk_branch vcodec_axi_a_clk = {
1627         .hwcg_reg = 0x0114,
1628         .hwcg_bit = 24,
1629         .halt_reg = 0x01e8,
1630         .halt_bit = 26,
1631         .clkr = {
1632                 .enable_reg = 0x0114,
1633                 .enable_mask = BIT(25),
1634                 .hw.init = &(struct clk_init_data){
1635                         .name = "vcodec_axi_a_clk",
1636                         .ops = &clk_branch_ops,
1637                         .flags = CLK_IS_ROOT,
1638                 },
1639         },
1640 };
1641
1642 static struct clk_branch vcodec_axi_clk = {
1643         .hwcg_reg = 0x0018,
1644         .hwcg_bit = 13,
1645         .halt_reg = 0x01d8,
1646         .halt_bit = 3,
1647         .clkr = {
1648                 .enable_reg = 0x0018,
1649                 .enable_mask = BIT(19),
1650                 .hw.init = &(struct clk_init_data){
1651                         .name = "vcodec_axi_clk",
1652                         .ops = &clk_branch_ops,
1653                         .flags = CLK_IS_ROOT,
1654                 },
1655         },
1656 };
1657
1658 static struct clk_branch vfe_axi_clk = {
1659         .halt_reg = 0x01d8,
1660         .halt_bit = 0,
1661         .clkr = {
1662                 .enable_reg = 0x0018,
1663                 .enable_mask = BIT(18),
1664                 .hw.init = &(struct clk_init_data){
1665                         .name = "vfe_axi_clk",
1666                         .ops = &clk_branch_ops,
1667                         .flags = CLK_IS_ROOT,
1668                 },
1669         },
1670 };
1671
1672 static struct clk_branch mdp_axi_clk = {
1673         .hwcg_reg = 0x0018,
1674         .hwcg_bit = 16,
1675         .halt_reg = 0x01d8,
1676         .halt_bit = 8,
1677         .clkr = {
1678                 .enable_reg = 0x0018,
1679                 .enable_mask = BIT(23),
1680                 .hw.init = &(struct clk_init_data){
1681                         .name = "mdp_axi_clk",
1682                         .ops = &clk_branch_ops,
1683                         .flags = CLK_IS_ROOT,
1684                 },
1685         },
1686 };
1687
1688 static struct clk_branch rot_axi_clk = {
1689         .hwcg_reg = 0x0020,
1690         .hwcg_bit = 25,
1691         .halt_reg = 0x01d8,
1692         .halt_bit = 2,
1693         .clkr = {
1694                 .enable_reg = 0x0020,
1695                 .enable_mask = BIT(24),
1696                 .hw.init = &(struct clk_init_data){
1697                         .name = "rot_axi_clk",
1698                         .ops = &clk_branch_ops,
1699                         .flags = CLK_IS_ROOT,
1700                 },
1701         },
1702 };
1703
1704 static struct clk_branch vpe_axi_clk = {
1705         .hwcg_reg = 0x0020,
1706         .hwcg_bit = 27,
1707         .halt_reg = 0x01d8,
1708         .halt_bit = 1,
1709         .clkr = {
1710                 .enable_reg = 0x0020,
1711                 .enable_mask = BIT(26),
1712                 .hw.init = &(struct clk_init_data){
1713                         .name = "vpe_axi_clk",
1714                         .ops = &clk_branch_ops,
1715                         .flags = CLK_IS_ROOT,
1716                 },
1717         },
1718 };
1719
1720 static struct clk_branch gfx3d_axi_clk = {
1721         .hwcg_reg = 0x0244,
1722         .hwcg_bit = 24,
1723         .halt_reg = 0x0240,
1724         .halt_bit = 30,
1725         .clkr = {
1726                 .enable_reg = 0x0244,
1727                 .enable_mask = BIT(25),
1728                 .hw.init = &(struct clk_init_data){
1729                         .name = "gfx3d_axi_clk",
1730                         .ops = &clk_branch_ops,
1731                         .flags = CLK_IS_ROOT,
1732                 },
1733         },
1734 };
1735
1736 static struct clk_branch amp_ahb_clk = {
1737         .halt_reg = 0x01dc,
1738         .halt_bit = 18,
1739         .clkr = {
1740                 .enable_reg = 0x0008,
1741                 .enable_mask = BIT(24),
1742                 .hw.init = &(struct clk_init_data){
1743                         .name = "amp_ahb_clk",
1744                         .ops = &clk_branch_ops,
1745                         .flags = CLK_IS_ROOT,
1746                 },
1747         },
1748 };
1749
1750 static struct clk_branch csi_ahb_clk = {
1751         .halt_reg = 0x01dc,
1752         .halt_bit = 16,
1753         .clkr = {
1754                 .enable_reg = 0x0008,
1755                 .enable_mask = BIT(7),
1756                 .hw.init = &(struct clk_init_data){
1757                         .name = "csi_ahb_clk",
1758                         .ops = &clk_branch_ops,
1759                         .flags = CLK_IS_ROOT
1760                 },
1761         },
1762 };
1763
1764 static struct clk_branch dsi_m_ahb_clk = {
1765         .halt_reg = 0x01dc,
1766         .halt_bit = 19,
1767         .clkr = {
1768                 .enable_reg = 0x0008,
1769                 .enable_mask = BIT(9),
1770                 .hw.init = &(struct clk_init_data){
1771                         .name = "dsi_m_ahb_clk",
1772                         .ops = &clk_branch_ops,
1773                         .flags = CLK_IS_ROOT,
1774                 },
1775         },
1776 };
1777
1778 static struct clk_branch dsi_s_ahb_clk = {
1779         .hwcg_reg = 0x0038,
1780         .hwcg_bit = 20,
1781         .halt_reg = 0x01dc,
1782         .halt_bit = 21,
1783         .clkr = {
1784                 .enable_reg = 0x0008,
1785                 .enable_mask = BIT(18),
1786                 .hw.init = &(struct clk_init_data){
1787                         .name = "dsi_s_ahb_clk",
1788                         .ops = &clk_branch_ops,
1789                         .flags = CLK_IS_ROOT,
1790                 },
1791         },
1792 };
1793
1794 static struct clk_branch dsi2_m_ahb_clk = {
1795         .halt_reg = 0x01d8,
1796         .halt_bit = 18,
1797         .clkr = {
1798                 .enable_reg = 0x0008,
1799                 .enable_mask = BIT(17),
1800                 .hw.init = &(struct clk_init_data){
1801                         .name = "dsi2_m_ahb_clk",
1802                         .ops = &clk_branch_ops,
1803                         .flags = CLK_IS_ROOT
1804                 },
1805         },
1806 };
1807
1808 static struct clk_branch dsi2_s_ahb_clk = {
1809         .hwcg_reg = 0x0038,
1810         .hwcg_bit = 15,
1811         .halt_reg = 0x01dc,
1812         .halt_bit = 20,
1813         .clkr = {
1814                 .enable_reg = 0x0008,
1815                 .enable_mask = BIT(22),
1816                 .hw.init = &(struct clk_init_data){
1817                         .name = "dsi2_s_ahb_clk",
1818                         .ops = &clk_branch_ops,
1819                         .flags = CLK_IS_ROOT,
1820                 },
1821         },
1822 };
1823
1824 static struct clk_branch gfx2d0_ahb_clk = {
1825         .hwcg_reg = 0x0038,
1826         .hwcg_bit = 28,
1827         .halt_reg = 0x01dc,
1828         .halt_bit = 2,
1829         .clkr = {
1830                 .enable_reg = 0x0008,
1831                 .enable_mask = BIT(19),
1832                 .hw.init = &(struct clk_init_data){
1833                         .name = "gfx2d0_ahb_clk",
1834                         .ops = &clk_branch_ops,
1835                         .flags = CLK_IS_ROOT,
1836                 },
1837         },
1838 };
1839
1840 static struct clk_branch gfx2d1_ahb_clk = {
1841         .hwcg_reg = 0x0038,
1842         .hwcg_bit = 29,
1843         .halt_reg = 0x01dc,
1844         .halt_bit = 3,
1845         .clkr = {
1846                 .enable_reg = 0x0008,
1847                 .enable_mask = BIT(2),
1848                 .hw.init = &(struct clk_init_data){
1849                         .name = "gfx2d1_ahb_clk",
1850                         .ops = &clk_branch_ops,
1851                         .flags = CLK_IS_ROOT,
1852                 },
1853         },
1854 };
1855
1856 static struct clk_branch gfx3d_ahb_clk = {
1857         .hwcg_reg = 0x0038,
1858         .hwcg_bit = 27,
1859         .halt_reg = 0x01dc,
1860         .halt_bit = 4,
1861         .clkr = {
1862                 .enable_reg = 0x0008,
1863                 .enable_mask = BIT(3),
1864                 .hw.init = &(struct clk_init_data){
1865                         .name = "gfx3d_ahb_clk",
1866                         .ops = &clk_branch_ops,
1867                         .flags = CLK_IS_ROOT,
1868                 },
1869         },
1870 };
1871
1872 static struct clk_branch hdmi_m_ahb_clk = {
1873         .hwcg_reg = 0x0038,
1874         .hwcg_bit = 21,
1875         .halt_reg = 0x01dc,
1876         .halt_bit = 5,
1877         .clkr = {
1878                 .enable_reg = 0x0008,
1879                 .enable_mask = BIT(14),
1880                 .hw.init = &(struct clk_init_data){
1881                         .name = "hdmi_m_ahb_clk",
1882                         .ops = &clk_branch_ops,
1883                         .flags = CLK_IS_ROOT,
1884                 },
1885         },
1886 };
1887
1888 static struct clk_branch hdmi_s_ahb_clk = {
1889         .hwcg_reg = 0x0038,
1890         .hwcg_bit = 22,
1891         .halt_reg = 0x01dc,
1892         .halt_bit = 6,
1893         .clkr = {
1894                 .enable_reg = 0x0008,
1895                 .enable_mask = BIT(4),
1896                 .hw.init = &(struct clk_init_data){
1897                         .name = "hdmi_s_ahb_clk",
1898                         .ops = &clk_branch_ops,
1899                         .flags = CLK_IS_ROOT,
1900                 },
1901         },
1902 };
1903
1904 static struct clk_branch ijpeg_ahb_clk = {
1905         .halt_reg = 0x01dc,
1906         .halt_bit = 9,
1907         .clkr = {
1908                 .enable_reg = 0x0008,
1909                 .enable_mask = BIT(5),
1910                 .hw.init = &(struct clk_init_data){
1911                         .name = "ijpeg_ahb_clk",
1912                         .ops = &clk_branch_ops,
1913                         .flags = CLK_IS_ROOT
1914                 },
1915         },
1916 };
1917
1918 static struct clk_branch mmss_imem_ahb_clk = {
1919         .hwcg_reg = 0x0038,
1920         .hwcg_bit = 12,
1921         .halt_reg = 0x01dc,
1922         .halt_bit = 10,
1923         .clkr = {
1924                 .enable_reg = 0x0008,
1925                 .enable_mask = BIT(6),
1926                 .hw.init = &(struct clk_init_data){
1927                         .name = "mmss_imem_ahb_clk",
1928                         .ops = &clk_branch_ops,
1929                         .flags = CLK_IS_ROOT
1930                 },
1931         },
1932 };
1933
1934 static struct clk_branch jpegd_ahb_clk = {
1935         .halt_reg = 0x01dc,
1936         .halt_bit = 7,
1937         .clkr = {
1938                 .enable_reg = 0x0008,
1939                 .enable_mask = BIT(21),
1940                 .hw.init = &(struct clk_init_data){
1941                         .name = "jpegd_ahb_clk",
1942                         .ops = &clk_branch_ops,
1943                         .flags = CLK_IS_ROOT,
1944                 },
1945         },
1946 };
1947
1948 static struct clk_branch mdp_ahb_clk = {
1949         .halt_reg = 0x01dc,
1950         .halt_bit = 11,
1951         .clkr = {
1952                 .enable_reg = 0x0008,
1953                 .enable_mask = BIT(10),
1954                 .hw.init = &(struct clk_init_data){
1955                         .name = "mdp_ahb_clk",
1956                         .ops = &clk_branch_ops,
1957                         .flags = CLK_IS_ROOT,
1958                 },
1959         },
1960 };
1961
1962 static struct clk_branch rot_ahb_clk = {
1963         .halt_reg = 0x01dc,
1964         .halt_bit = 13,
1965         .clkr = {
1966                 .enable_reg = 0x0008,
1967                 .enable_mask = BIT(12),
1968                 .hw.init = &(struct clk_init_data){
1969                         .name = "rot_ahb_clk",
1970                         .ops = &clk_branch_ops,
1971                         .flags = CLK_IS_ROOT
1972                 },
1973         },
1974 };
1975
1976 static struct clk_branch smmu_ahb_clk = {
1977         .hwcg_reg = 0x0008,
1978         .hwcg_bit = 26,
1979         .halt_reg = 0x01dc,
1980         .halt_bit = 22,
1981         .clkr = {
1982                 .enable_reg = 0x0008,
1983                 .enable_mask = BIT(15),
1984                 .hw.init = &(struct clk_init_data){
1985                         .name = "smmu_ahb_clk",
1986                         .ops = &clk_branch_ops,
1987                         .flags = CLK_IS_ROOT,
1988                 },
1989         },
1990 };
1991
1992 static struct clk_branch tv_enc_ahb_clk = {
1993         .halt_reg = 0x01dc,
1994         .halt_bit = 23,
1995         .clkr = {
1996                 .enable_reg = 0x0008,
1997                 .enable_mask = BIT(25),
1998                 .hw.init = &(struct clk_init_data){
1999                         .name = "tv_enc_ahb_clk",
2000                         .ops = &clk_branch_ops,
2001                         .flags = CLK_IS_ROOT,
2002                 },
2003         },
2004 };
2005
2006 static struct clk_branch vcodec_ahb_clk = {
2007         .hwcg_reg = 0x0038,
2008         .hwcg_bit = 26,
2009         .halt_reg = 0x01dc,
2010         .halt_bit = 12,
2011         .clkr = {
2012                 .enable_reg = 0x0008,
2013                 .enable_mask = BIT(11),
2014                 .hw.init = &(struct clk_init_data){
2015                         .name = "vcodec_ahb_clk",
2016                         .ops = &clk_branch_ops,
2017                         .flags = CLK_IS_ROOT,
2018                 },
2019         },
2020 };
2021
2022 static struct clk_branch vfe_ahb_clk = {
2023         .halt_reg = 0x01dc,
2024         .halt_bit = 14,
2025         .clkr = {
2026                 .enable_reg = 0x0008,
2027                 .enable_mask = BIT(13),
2028                 .hw.init = &(struct clk_init_data){
2029                         .name = "vfe_ahb_clk",
2030                         .ops = &clk_branch_ops,
2031                         .flags = CLK_IS_ROOT,
2032                 },
2033         },
2034 };
2035
2036 static struct clk_branch vpe_ahb_clk = {
2037         .halt_reg = 0x01dc,
2038         .halt_bit = 15,
2039         .clkr = {
2040                 .enable_reg = 0x0008,
2041                 .enable_mask = BIT(16),
2042                 .hw.init = &(struct clk_init_data){
2043                         .name = "vpe_ahb_clk",
2044                         .ops = &clk_branch_ops,
2045                         .flags = CLK_IS_ROOT,
2046                 },
2047         },
2048 };
2049
2050 static struct clk_regmap *mmcc_msm8960_clks[] = {
2051         [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2052         [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2053         [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2054         [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2055         [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2056         [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2057         [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2058         [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2059         [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2060         [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2061         [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2062         [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2063         [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2064         [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2065         [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2066         [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2067         [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2068         [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2069         [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2070         [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2071         [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2072         [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2073         [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2074         [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2075         [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2076         [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2077         [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2078         [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2079         [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2080         [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2081         [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2082         [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2083         [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2084         [CSI0_SRC] = &csi0_src.clkr,
2085         [CSI0_CLK] = &csi0_clk.clkr,
2086         [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2087         [CSI1_SRC] = &csi1_src.clkr,
2088         [CSI1_CLK] = &csi1_clk.clkr,
2089         [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2090         [CSI2_SRC] = &csi2_src.clkr,
2091         [CSI2_CLK] = &csi2_clk.clkr,
2092         [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2093         [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2094         [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2095         [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2096         [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2097         [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2098         [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2099         [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2100         [GFX2D0_SRC] = &gfx2d0_src.clkr,
2101         [GFX2D0_CLK] = &gfx2d0_clk.clkr,
2102         [GFX2D1_SRC] = &gfx2d1_src.clkr,
2103         [GFX2D1_CLK] = &gfx2d1_clk.clkr,
2104         [GFX3D_SRC] = &gfx3d_src.clkr,
2105         [GFX3D_CLK] = &gfx3d_clk.clkr,
2106         [IJPEG_SRC] = &ijpeg_src.clkr,
2107         [IJPEG_CLK] = &ijpeg_clk.clkr,
2108         [JPEGD_SRC] = &jpegd_src.clkr,
2109         [JPEGD_CLK] = &jpegd_clk.clkr,
2110         [MDP_SRC] = &mdp_src.clkr,
2111         [MDP_CLK] = &mdp_clk.clkr,
2112         [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2113         [ROT_SRC] = &rot_src.clkr,
2114         [ROT_CLK] = &rot_clk.clkr,
2115         [TV_ENC_CLK] = &tv_enc_clk.clkr,
2116         [TV_DAC_CLK] = &tv_dac_clk.clkr,
2117         [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2118         [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2119         [TV_SRC] = &tv_src.clkr,
2120         [VCODEC_SRC] = &vcodec_src.clkr,
2121         [VCODEC_CLK] = &vcodec_clk.clkr,
2122         [VFE_SRC] = &vfe_src.clkr,
2123         [VFE_CLK] = &vfe_clk.clkr,
2124         [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2125         [VPE_SRC] = &vpe_src.clkr,
2126         [VPE_CLK] = &vpe_clk.clkr,
2127         [CAMCLK0_SRC] = &camclk0_src.clkr,
2128         [CAMCLK0_CLK] = &camclk0_clk.clkr,
2129         [CAMCLK1_SRC] = &camclk1_src.clkr,
2130         [CAMCLK1_CLK] = &camclk1_clk.clkr,
2131         [CAMCLK2_SRC] = &camclk2_src.clkr,
2132         [CAMCLK2_CLK] = &camclk2_clk.clkr,
2133         [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2134         [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2135         [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2136         [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2137         [PLL2] = &pll2.clkr,
2138 };
2139
2140 static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2141         [VPE_AXI_RESET] = { 0x0208, 15 },
2142         [IJPEG_AXI_RESET] = { 0x0208, 14 },
2143         [MPD_AXI_RESET] = { 0x0208, 13 },
2144         [VFE_AXI_RESET] = { 0x0208, 9 },
2145         [SP_AXI_RESET] = { 0x0208, 8 },
2146         [VCODEC_AXI_RESET] = { 0x0208, 7 },
2147         [ROT_AXI_RESET] = { 0x0208, 6 },
2148         [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2149         [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2150         [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2151         [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2152         [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2153         [FAB_S0_AXI_RESET] = { 0x0208 },
2154         [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2155         [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2156         [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2157         [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2158         [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2159         [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2160         [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2161         [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2162         [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2163         [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2164         [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2165         [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2166         [APU_AHB_RESET] = { 0x020c, 18 },
2167         [CSI_AHB_RESET] = { 0x020c, 17 },
2168         [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2169         [VPE_AHB_RESET] = { 0x020c, 14 },
2170         [FABRIC_AHB_RESET] = { 0x020c, 13 },
2171         [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2172         [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2173         [GFX3D_AHB_RESET] = { 0x020c, 10 },
2174         [HDMI_AHB_RESET] = { 0x020c, 9 },
2175         [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2176         [IJPEG_AHB_RESET] = { 0x020c, 7 },
2177         [DSI_M_AHB_RESET] = { 0x020c, 6 },
2178         [DSI_S_AHB_RESET] = { 0x020c, 5 },
2179         [JPEGD_AHB_RESET] = { 0x020c, 4 },
2180         [MDP_AHB_RESET] = { 0x020c, 3 },
2181         [ROT_AHB_RESET] = { 0x020c, 2 },
2182         [VCODEC_AHB_RESET] = { 0x020c, 1 },
2183         [VFE_AHB_RESET] = { 0x020c, 0 },
2184         [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2185         [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2186         [CSIPHY2_RESET] = { 0x0210, 29 },
2187         [CSI_PIX1_RESET] = { 0x0210, 28 },
2188         [CSIPHY0_RESET] = { 0x0210, 27 },
2189         [CSIPHY1_RESET] = { 0x0210, 26 },
2190         [DSI2_RESET] = { 0x0210, 25 },
2191         [VFE_CSI_RESET] = { 0x0210, 24 },
2192         [MDP_RESET] = { 0x0210, 21 },
2193         [AMP_RESET] = { 0x0210, 20 },
2194         [JPEGD_RESET] = { 0x0210, 19 },
2195         [CSI1_RESET] = { 0x0210, 18 },
2196         [VPE_RESET] = { 0x0210, 17 },
2197         [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2198         [VFE_RESET] = { 0x0210, 15 },
2199         [GFX2D0_RESET] = { 0x0210, 14 },
2200         [GFX2D1_RESET] = { 0x0210, 13 },
2201         [GFX3D_RESET] = { 0x0210, 12 },
2202         [HDMI_RESET] = { 0x0210, 11 },
2203         [MMSS_IMEM_RESET] = { 0x0210, 10 },
2204         [IJPEG_RESET] = { 0x0210, 9 },
2205         [CSI0_RESET] = { 0x0210, 8 },
2206         [DSI_RESET] = { 0x0210, 7 },
2207         [VCODEC_RESET] = { 0x0210, 6 },
2208         [MDP_TV_RESET] = { 0x0210, 4 },
2209         [MDP_VSYNC_RESET] = { 0x0210, 3 },
2210         [ROT_RESET] = { 0x0210, 2 },
2211         [TV_HDMI_RESET] = { 0x0210, 1 },
2212         [TV_ENC_RESET] = { 0x0210 },
2213         [CSI2_RESET] = { 0x0214, 2 },
2214         [CSI_RDI1_RESET] = { 0x0214, 1 },
2215         [CSI_RDI2_RESET] = { 0x0214 },
2216 };
2217
2218 static const struct regmap_config mmcc_msm8960_regmap_config = {
2219         .reg_bits       = 32,
2220         .reg_stride     = 4,
2221         .val_bits       = 32,
2222         .max_register   = 0x334,
2223         .fast_io        = true,
2224 };
2225
2226 static const struct qcom_cc_desc mmcc_msm8960_desc = {
2227         .config = &mmcc_msm8960_regmap_config,
2228         .clks = mmcc_msm8960_clks,
2229         .num_clks = ARRAY_SIZE(mmcc_msm8960_clks),
2230         .resets = mmcc_msm8960_resets,
2231         .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2232 };
2233
2234 static const struct of_device_id mmcc_msm8960_match_table[] = {
2235         { .compatible = "qcom,mmcc-msm8960" },
2236         { }
2237 };
2238 MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2239
2240 static int mmcc_msm8960_probe(struct platform_device *pdev)
2241 {
2242         return qcom_cc_probe(pdev, &mmcc_msm8960_desc);
2243 }
2244
2245 static int mmcc_msm8960_remove(struct platform_device *pdev)
2246 {
2247         qcom_cc_remove(pdev);
2248         return 0;
2249 }
2250
2251 static struct platform_driver mmcc_msm8960_driver = {
2252         .probe          = mmcc_msm8960_probe,
2253         .remove         = mmcc_msm8960_remove,
2254         .driver         = {
2255                 .name   = "mmcc-msm8960",
2256                 .owner  = THIS_MODULE,
2257                 .of_match_table = mmcc_msm8960_match_table,
2258         },
2259 };
2260
2261 module_platform_driver(mmcc_msm8960_driver);
2262
2263 MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
2264 MODULE_LICENSE("GPL v2");
2265 MODULE_ALIAS("platform:mmcc-msm8960");