drivers/clk/qcom/gcc-msm8998.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
  18
  19 #include "common.h"
  20 #include "clk-regmap.h"
  21 #include "clk-alpha-pll.h"
  22 #include "clk-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "reset.h"
  26 #include "gdsc.h"
  27
  28 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  29
  30 enum {
  31         P_AUD_REF_CLK,
  32         P_CORE_BI_PLL_TEST_SE,
  33         P_GPLL0_OUT_MAIN,
  34         P_GPLL4_OUT_MAIN,
  35         P_PLL0_EARLY_DIV_CLK_SRC,
  36         P_SLEEP_CLK,
  37         P_XO,
  38 };
  39
  40 static const struct parent_map gcc_parent_map_0[] = {
  41         { P_XO, 0 },
  42         { P_GPLL0_OUT_MAIN, 1 },
  43         { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
  44         { P_CORE_BI_PLL_TEST_SE, 7 },
  45 };
  46
  47 static const char * const gcc_parent_names_0[] = {
  48         "xo",
  49         "gpll0_out_main",
  50         "gpll0_out_main",
  51         "core_bi_pll_test_se",
  52 };
  53
  54 static const struct parent_map gcc_parent_map_1[] = {
  55         { P_XO, 0 },
  56         { P_GPLL0_OUT_MAIN, 1 },
  57         { P_CORE_BI_PLL_TEST_SE, 7 },
  58 };
  59
  60 static const char * const gcc_parent_names_1[] = {
  61         "xo",
  62         "gpll0_out_main",
  63         "core_bi_pll_test_se",
  64 };
  65
  66 static const struct parent_map gcc_parent_map_2[] = {
  67         { P_XO, 0 },
  68         { P_GPLL0_OUT_MAIN, 1 },
  69         { P_SLEEP_CLK, 5 },
  70         { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
  71         { P_CORE_BI_PLL_TEST_SE, 7 },
  72 };
  73
  74 static const char * const gcc_parent_names_2[] = {
  75         "xo",
  76         "gpll0_out_main",
  77         "core_pi_sleep_clk",
  78         "gpll0_out_main",
  79         "core_bi_pll_test_se",
  80 };
  81
  82 static const struct parent_map gcc_parent_map_3[] = {
  83         { P_XO, 0 },
  84         { P_SLEEP_CLK, 5 },
  85         { P_CORE_BI_PLL_TEST_SE, 7 },
  86 };
  87
  88 static const char * const gcc_parent_names_3[] = {
  89         "xo",
  90         "core_pi_sleep_clk",
  91         "core_bi_pll_test_se",
  92 };
  93
  94 static const struct parent_map gcc_parent_map_4[] = {
  95         { P_XO, 0 },
  96         { P_GPLL0_OUT_MAIN, 1 },
  97         { P_GPLL4_OUT_MAIN, 5 },
  98         { P_CORE_BI_PLL_TEST_SE, 7 },
  99 };
 100
 101 static const char * const gcc_parent_names_4[] = {
 102         "xo",
 103         "gpll0_out_main",
 104         "gpll4_out_main",
 105         "core_bi_pll_test_se",
 106 };
 107
 108 static const struct parent_map gcc_parent_map_5[] = {
 109         { P_XO, 0 },
 110         { P_GPLL0_OUT_MAIN, 1 },
 111         { P_AUD_REF_CLK, 2 },
 112         { P_CORE_BI_PLL_TEST_SE, 7 },
 113 };
 114
 115 static const char * const gcc_parent_names_5[] = {
 116         "xo",
 117         "gpll0_out_main",
 118         "aud_ref_clk",
 119         "core_bi_pll_test_se",
 120 };
 121
 122 static struct pll_vco fabia_vco[] = {
 123         { 250000000, 2000000000, 0 },
 124         { 125000000, 1000000000, 1 },
 125 };
 126
 127 static struct clk_alpha_pll gpll0 = {
 128         .offset = 0x0,
 129         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 130         .vco_table = fabia_vco,
 131         .num_vco = ARRAY_SIZE(fabia_vco),
 132         .clkr = {
 133                 .enable_reg = 0x52000,
 134                 .enable_mask = BIT(0),
 135                 .hw.init = &(struct clk_init_data){
 136                         .name = "gpll0",
 137                         .parent_names = (const char *[]){ "xo" },
 138                         .num_parents = 1,
 139                         .ops = &clk_alpha_pll_ops,
 140                 }
 141         },
 142 };
 143
 144 static struct clk_alpha_pll_postdiv gpll0_out_even = {
 145         .offset = 0x0,
 146         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 147         .clkr.hw.init = &(struct clk_init_data){
 148                 .name = "gpll0_out_even",
 149                 .parent_names = (const char *[]){ "gpll0" },
 150                 .num_parents = 1,
 151                 .ops = &clk_alpha_pll_postdiv_ops,
 152         },
 153 };
 154
 155 static struct clk_alpha_pll_postdiv gpll0_out_main = {
 156         .offset = 0x0,
 157         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 158         .clkr.hw.init = &(struct clk_init_data){
 159                 .name = "gpll0_out_main",
 160                 .parent_names = (const char *[]){ "gpll0" },
 161                 .num_parents = 1,
 162                 .ops = &clk_alpha_pll_postdiv_ops,
 163         },
 164 };
 165
 166 static struct clk_alpha_pll_postdiv gpll0_out_odd = {
 167         .offset = 0x0,
 168         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 169         .clkr.hw.init = &(struct clk_init_data){
 170                 .name = "gpll0_out_odd",
 171                 .parent_names = (const char *[]){ "gpll0" },
 172                 .num_parents = 1,
 173                 .ops = &clk_alpha_pll_postdiv_ops,
 174         },
 175 };
 176
 177 static struct clk_alpha_pll_postdiv gpll0_out_test = {
 178         .offset = 0x0,
 179         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 180         .clkr.hw.init = &(struct clk_init_data){
 181                 .name = "gpll0_out_test",
 182                 .parent_names = (const char *[]){ "gpll0" },
 183                 .num_parents = 1,
 184                 .ops = &clk_alpha_pll_postdiv_ops,
 185         },
 186 };
 187
 188 static struct clk_alpha_pll gpll1 = {
 189         .offset = 0x1000,
 190         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 191         .vco_table = fabia_vco,
 192         .num_vco = ARRAY_SIZE(fabia_vco),
 193         .clkr = {
 194                 .enable_reg = 0x52000,
 195                 .enable_mask = BIT(1),
 196                 .hw.init = &(struct clk_init_data){
 197                         .name = "gpll1",
 198                         .parent_names = (const char *[]){ "xo" },
 199                         .num_parents = 1,
 200                         .ops = &clk_alpha_pll_ops,
 201                 }
 202         },
 203 };
 204
 205 static struct clk_alpha_pll_postdiv gpll1_out_even = {
 206         .offset = 0x1000,
 207         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 208         .clkr.hw.init = &(struct clk_init_data){
 209                 .name = "gpll1_out_even",
 210                 .parent_names = (const char *[]){ "gpll1" },
 211                 .num_parents = 1,
 212                 .ops = &clk_alpha_pll_postdiv_ops,
 213         },
 214 };
 215
 216 static struct clk_alpha_pll_postdiv gpll1_out_main = {
 217         .offset = 0x1000,
 218         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 219         .clkr.hw.init = &(struct clk_init_data){
 220                 .name = "gpll1_out_main",
 221                 .parent_names = (const char *[]){ "gpll1" },
 222                 .num_parents = 1,
 223                 .ops = &clk_alpha_pll_postdiv_ops,
 224         },
 225 };
 226
 227 static struct clk_alpha_pll_postdiv gpll1_out_odd = {
 228         .offset = 0x1000,
 229         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 230         .clkr.hw.init = &(struct clk_init_data){
 231                 .name = "gpll1_out_odd",
 232                 .parent_names = (const char *[]){ "gpll1" },
 233                 .num_parents = 1,
 234                 .ops = &clk_alpha_pll_postdiv_ops,
 235         },
 236 };
 237
 238 static struct clk_alpha_pll_postdiv gpll1_out_test = {
 239         .offset = 0x1000,
 240         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 241         .clkr.hw.init = &(struct clk_init_data){
 242                 .name = "gpll1_out_test",
 243                 .parent_names = (const char *[]){ "gpll1" },
 244                 .num_parents = 1,
 245                 .ops = &clk_alpha_pll_postdiv_ops,
 246         },
 247 };
 248
 249 static struct clk_alpha_pll gpll2 = {
 250         .offset = 0x2000,
 251         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 252         .vco_table = fabia_vco,
 253         .num_vco = ARRAY_SIZE(fabia_vco),
 254         .clkr = {
 255                 .enable_reg = 0x52000,
 256                 .enable_mask = BIT(2),
 257                 .hw.init = &(struct clk_init_data){
 258                         .name = "gpll2",
 259                         .parent_names = (const char *[]){ "xo" },
 260                         .num_parents = 1,
 261                         .ops = &clk_alpha_pll_ops,
 262                 }
 263         },
 264 };
 265
 266 static struct clk_alpha_pll_postdiv gpll2_out_even = {
 267         .offset = 0x2000,
 268         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 269         .clkr.hw.init = &(struct clk_init_data){
 270                 .name = "gpll2_out_even",
 271                 .parent_names = (const char *[]){ "gpll2" },
 272                 .num_parents = 1,
 273                 .ops = &clk_alpha_pll_postdiv_ops,
 274         },
 275 };
 276
 277 static struct clk_alpha_pll_postdiv gpll2_out_main = {
 278         .offset = 0x2000,
 279         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 280         .clkr.hw.init = &(struct clk_init_data){
 281                 .name = "gpll2_out_main",
 282                 .parent_names = (const char *[]){ "gpll2" },
 283                 .num_parents = 1,
 284                 .ops = &clk_alpha_pll_postdiv_ops,
 285         },
 286 };
 287
 288 static struct clk_alpha_pll_postdiv gpll2_out_odd = {
 289         .offset = 0x2000,
 290         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 291         .clkr.hw.init = &(struct clk_init_data){
 292                 .name = "gpll2_out_odd",
 293                 .parent_names = (const char *[]){ "gpll2" },
 294                 .num_parents = 1,
 295                 .ops = &clk_alpha_pll_postdiv_ops,
 296         },
 297 };
 298
 299 static struct clk_alpha_pll_postdiv gpll2_out_test = {
 300         .offset = 0x2000,
 301         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 302         .clkr.hw.init = &(struct clk_init_data){
 303                 .name = "gpll2_out_test",
 304                 .parent_names = (const char *[]){ "gpll2" },
 305                 .num_parents = 1,
 306                 .ops = &clk_alpha_pll_postdiv_ops,
 307         },
 308 };
 309
 310 static struct clk_alpha_pll gpll3 = {
 311         .offset = 0x3000,
 312         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 313         .vco_table = fabia_vco,
 314         .num_vco = ARRAY_SIZE(fabia_vco),
 315         .clkr = {
 316                 .enable_reg = 0x52000,
 317                 .enable_mask = BIT(3),
 318                 .hw.init = &(struct clk_init_data){
 319                         .name = "gpll3",
 320                         .parent_names = (const char *[]){ "xo" },
 321                         .num_parents = 1,
 322                         .ops = &clk_alpha_pll_ops,
 323                 }
 324         },
 325 };
 326
 327 static struct clk_alpha_pll_postdiv gpll3_out_even = {
 328         .offset = 0x3000,
 329         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 330         .clkr.hw.init = &(struct clk_init_data){
 331                 .name = "gpll3_out_even",
 332                 .parent_names = (const char *[]){ "gpll3" },
 333                 .num_parents = 1,
 334                 .ops = &clk_alpha_pll_postdiv_ops,
 335         },
 336 };
 337
 338 static struct clk_alpha_pll_postdiv gpll3_out_main = {
 339         .offset = 0x3000,
 340         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 341         .clkr.hw.init = &(struct clk_init_data){
 342                 .name = "gpll3_out_main",
 343                 .parent_names = (const char *[]){ "gpll3" },
 344                 .num_parents = 1,
 345                 .ops = &clk_alpha_pll_postdiv_ops,
 346         },
 347 };
 348
 349 static struct clk_alpha_pll_postdiv gpll3_out_odd = {
 350         .offset = 0x3000,
 351         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 352         .clkr.hw.init = &(struct clk_init_data){
 353                 .name = "gpll3_out_odd",
 354                 .parent_names = (const char *[]){ "gpll3" },
 355                 .num_parents = 1,
 356                 .ops = &clk_alpha_pll_postdiv_ops,
 357         },
 358 };
 359
 360 static struct clk_alpha_pll_postdiv gpll3_out_test = {
 361         .offset = 0x3000,
 362         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 363         .clkr.hw.init = &(struct clk_init_data){
 364                 .name = "gpll3_out_test",
 365                 .parent_names = (const char *[]){ "gpll3" },
 366                 .num_parents = 1,
 367                 .ops = &clk_alpha_pll_postdiv_ops,
 368         },
 369 };
 370
 371 static struct clk_alpha_pll gpll4 = {
 372         .offset = 0x77000,
 373         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 374         .vco_table = fabia_vco,
 375         .num_vco = ARRAY_SIZE(fabia_vco),
 376         .clkr = {
 377                 .enable_reg = 0x52000,
 378                 .enable_mask = BIT(4),
 379                 .hw.init = &(struct clk_init_data){
 380                         .name = "gpll4",
 381                         .parent_names = (const char *[]){ "xo" },
 382                         .num_parents = 1,
 383                         .ops = &clk_alpha_pll_ops,
 384                 }
 385         },
 386 };
 387
 388 static struct clk_alpha_pll_postdiv gpll4_out_even = {
 389         .offset = 0x77000,
 390         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 391         .clkr.hw.init = &(struct clk_init_data){
 392                 .name = "gpll4_out_even",
 393                 .parent_names = (const char *[]){ "gpll4" },
 394                 .num_parents = 1,
 395                 .ops = &clk_alpha_pll_postdiv_ops,
 396         },
 397 };
 398
 399 static struct clk_alpha_pll_postdiv gpll4_out_main = {
 400         .offset = 0x77000,
 401         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 402         .clkr.hw.init = &(struct clk_init_data){
 403                 .name = "gpll4_out_main",
 404                 .parent_names = (const char *[]){ "gpll4" },
 405                 .num_parents = 1,
 406                 .ops = &clk_alpha_pll_postdiv_ops,
 407         },
 408 };
 409
 410 static struct clk_alpha_pll_postdiv gpll4_out_odd = {
 411         .offset = 0x77000,
 412         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 413         .clkr.hw.init = &(struct clk_init_data){
 414                 .name = "gpll4_out_odd",
 415                 .parent_names = (const char *[]){ "gpll4" },
 416                 .num_parents = 1,
 417                 .ops = &clk_alpha_pll_postdiv_ops,
 418         },
 419 };
 420
 421 static struct clk_alpha_pll_postdiv gpll4_out_test = {
 422         .offset = 0x77000,
 423         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 424         .clkr.hw.init = &(struct clk_init_data){
 425                 .name = "gpll4_out_test",
 426                 .parent_names = (const char *[]){ "gpll4" },
 427                 .num_parents = 1,
 428                 .ops = &clk_alpha_pll_postdiv_ops,
 429         },
 430 };
 431
 432 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
 433         F(19200000, P_XO, 1, 0, 0),
 434         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 435         { }
 436 };
 437
 438 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 439         .cmd_rcgr = 0x19020,
 440         .mnd_width = 0,
 441         .hid_width = 5,
 442         .parent_map = gcc_parent_map_1,
 443         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 444         .clkr.hw.init = &(struct clk_init_data){
 445                 .name = "blsp1_qup1_i2c_apps_clk_src",
 446                 .parent_names = gcc_parent_names_1,
 447                 .num_parents = 3,
 448                 .ops = &clk_rcg2_ops,
 449         },
 450 };
 451
 452 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
 453         F(960000, P_XO, 10, 1, 2),
 454         F(4800000, P_XO, 4, 0, 0),
 455         F(9600000, P_XO, 2, 0, 0),
 456         F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
 457         F(19200000, P_XO, 1, 0, 0),
 458         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
 459         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 460         { }
 461 };
 462
 463 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 464         .cmd_rcgr = 0x1900c,
 465         .mnd_width = 8,
 466         .hid_width = 5,
 467         .parent_map = gcc_parent_map_0,
 468         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 469         .clkr.hw.init = &(struct clk_init_data){
 470                 .name = "blsp1_qup1_spi_apps_clk_src",
 471                 .parent_names = gcc_parent_names_0,
 472                 .num_parents = 4,
 473                 .ops = &clk_rcg2_ops,
 474         },
 475 };
 476
 477 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 478         .cmd_rcgr = 0x1b020,
 479         .mnd_width = 0,
 480         .hid_width = 5,
 481         .parent_map = gcc_parent_map_1,
 482         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 483         .clkr.hw.init = &(struct clk_init_data){
 484                 .name = "blsp1_qup2_i2c_apps_clk_src",
 485                 .parent_names = gcc_parent_names_1,
 486                 .num_parents = 3,
 487                 .ops = &clk_rcg2_ops,
 488         },
 489 };
 490
 491 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 492         .cmd_rcgr = 0x1b00c,
 493         .mnd_width = 8,
 494         .hid_width = 5,
 495         .parent_map = gcc_parent_map_0,
 496         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 497         .clkr.hw.init = &(struct clk_init_data){
 498                 .name = "blsp1_qup2_spi_apps_clk_src",
 499                 .parent_names = gcc_parent_names_0,
 500                 .num_parents = 4,
 501                 .ops = &clk_rcg2_ops,
 502         },
 503 };
 504
 505 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 506         .cmd_rcgr = 0x1d020,
 507         .mnd_width = 0,
 508         .hid_width = 5,
 509         .parent_map = gcc_parent_map_1,
 510         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 511         .clkr.hw.init = &(struct clk_init_data){
 512                 .name = "blsp1_qup3_i2c_apps_clk_src",
 513                 .parent_names = gcc_parent_names_1,
 514                 .num_parents = 3,
 515                 .ops = &clk_rcg2_ops,
 516         },
 517 };
 518
 519 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 520         .cmd_rcgr = 0x1d00c,
 521         .mnd_width = 8,
 522         .hid_width = 5,
 523         .parent_map = gcc_parent_map_0,
 524         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 525         .clkr.hw.init = &(struct clk_init_data){
 526                 .name = "blsp1_qup3_spi_apps_clk_src",
 527                 .parent_names = gcc_parent_names_0,
 528                 .num_parents = 4,
 529                 .ops = &clk_rcg2_ops,
 530         },
 531 };
 532
 533 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 534         .cmd_rcgr = 0x1f020,
 535         .mnd_width = 0,
 536         .hid_width = 5,
 537         .parent_map = gcc_parent_map_1,
 538         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 539         .clkr.hw.init = &(struct clk_init_data){
 540                 .name = "blsp1_qup4_i2c_apps_clk_src",
 541                 .parent_names = gcc_parent_names_1,
 542                 .num_parents = 3,
 543                 .ops = &clk_rcg2_ops,
 544         },
 545 };
 546
 547 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 548         .cmd_rcgr = 0x1f00c,
 549         .mnd_width = 8,
 550         .hid_width = 5,
 551         .parent_map = gcc_parent_map_0,
 552         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 553         .clkr.hw.init = &(struct clk_init_data){
 554                 .name = "blsp1_qup4_spi_apps_clk_src",
 555                 .parent_names = gcc_parent_names_0,
 556                 .num_parents = 4,
 557                 .ops = &clk_rcg2_ops,
 558         },
 559 };
 560
 561 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 562         .cmd_rcgr = 0x21020,
 563         .mnd_width = 0,
 564         .hid_width = 5,
 565         .parent_map = gcc_parent_map_1,
 566         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 567         .clkr.hw.init = &(struct clk_init_data){
 568                 .name = "blsp1_qup5_i2c_apps_clk_src",
 569                 .parent_names = gcc_parent_names_1,
 570                 .num_parents = 3,
 571                 .ops = &clk_rcg2_ops,
 572         },
 573 };
 574
 575 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 576         .cmd_rcgr = 0x2100c,
 577         .mnd_width = 8,
 578         .hid_width = 5,
 579         .parent_map = gcc_parent_map_0,
 580         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 581         .clkr.hw.init = &(struct clk_init_data){
 582                 .name = "blsp1_qup5_spi_apps_clk_src",
 583                 .parent_names = gcc_parent_names_0,
 584                 .num_parents = 4,
 585                 .ops = &clk_rcg2_ops,
 586         },
 587 };
 588
 589 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 590         .cmd_rcgr = 0x23020,
 591         .mnd_width = 0,
 592         .hid_width = 5,
 593         .parent_map = gcc_parent_map_1,
 594         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 595         .clkr.hw.init = &(struct clk_init_data){
 596                 .name = "blsp1_qup6_i2c_apps_clk_src",
 597                 .parent_names = gcc_parent_names_1,
 598                 .num_parents = 3,
 599                 .ops = &clk_rcg2_ops,
 600         },
 601 };
 602
 603 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 604         .cmd_rcgr = 0x2300c,
 605         .mnd_width = 8,
 606         .hid_width = 5,
 607         .parent_map = gcc_parent_map_0,
 608         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 609         .clkr.hw.init = &(struct clk_init_data){
 610                 .name = "blsp1_qup6_spi_apps_clk_src",
 611                 .parent_names = gcc_parent_names_0,
 612                 .num_parents = 4,
 613                 .ops = &clk_rcg2_ops,
 614         },
 615 };
 616
 617 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
 618         F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625),
 619         F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625),
 620         F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625),
 621         F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15),
 622         F(19200000, P_XO, 1, 0, 0),
 623         F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
 624         F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
 625         F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
 626         F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
 627         F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
 628         F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
 629         F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
 630         F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
 631         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 632         F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
 633         { }
 634 };
 635
 636 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 637         .cmd_rcgr = 0x1a00c,
 638         .mnd_width = 16,
 639         .hid_width = 5,
 640         .parent_map = gcc_parent_map_0,
 641         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 642         .clkr.hw.init = &(struct clk_init_data){
 643                 .name = "blsp1_uart1_apps_clk_src",
 644                 .parent_names = gcc_parent_names_0,
 645                 .num_parents = 4,
 646                 .ops = &clk_rcg2_ops,
 647         },
 648 };
 649
 650 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 651         .cmd_rcgr = 0x1c00c,
 652         .mnd_width = 16,
 653         .hid_width = 5,
 654         .parent_map = gcc_parent_map_0,
 655         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 656         .clkr.hw.init = &(struct clk_init_data){
 657                 .name = "blsp1_uart2_apps_clk_src",
 658                 .parent_names = gcc_parent_names_0,
 659                 .num_parents = 4,
 660                 .ops = &clk_rcg2_ops,
 661         },
 662 };
 663
 664 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 665         .cmd_rcgr = 0x1e00c,
 666         .mnd_width = 16,
 667         .hid_width = 5,
 668         .parent_map = gcc_parent_map_0,
 669         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 670         .clkr.hw.init = &(struct clk_init_data){
 671                 .name = "blsp1_uart3_apps_clk_src",
 672                 .parent_names = gcc_parent_names_0,
 673                 .num_parents = 4,
 674                 .ops = &clk_rcg2_ops,
 675         },
 676 };
 677
 678 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 679         .cmd_rcgr = 0x26020,
 680         .mnd_width = 0,
 681         .hid_width = 5,
 682         .parent_map = gcc_parent_map_1,
 683         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 684         .clkr.hw.init = &(struct clk_init_data){
 685                 .name = "blsp2_qup1_i2c_apps_clk_src",
 686                 .parent_names = gcc_parent_names_1,
 687                 .num_parents = 3,
 688                 .ops = &clk_rcg2_ops,
 689         },
 690 };
 691
 692 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 693         .cmd_rcgr = 0x2600c,
 694         .mnd_width = 8,
 695         .hid_width = 5,
 696         .parent_map = gcc_parent_map_0,
 697         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 698         .clkr.hw.init = &(struct clk_init_data){
 699                 .name = "blsp2_qup1_spi_apps_clk_src",
 700                 .parent_names = gcc_parent_names_0,
 701                 .num_parents = 4,
 702                 .ops = &clk_rcg2_ops,
 703         },
 704 };
 705
 706 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 707         .cmd_rcgr = 0x28020,
 708         .mnd_width = 0,
 709         .hid_width = 5,
 710         .parent_map = gcc_parent_map_1,
 711         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 712         .clkr.hw.init = &(struct clk_init_data){
 713                 .name = "blsp2_qup2_i2c_apps_clk_src",
 714                 .parent_names = gcc_parent_names_1,
 715                 .num_parents = 3,
 716                 .ops = &clk_rcg2_ops,
 717         },
 718 };
 719
 720 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 721         .cmd_rcgr = 0x2800c,
 722         .mnd_width = 8,
 723         .hid_width = 5,
 724         .parent_map = gcc_parent_map_0,
 725         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 726         .clkr.hw.init = &(struct clk_init_data){
 727                 .name = "blsp2_qup2_spi_apps_clk_src",
 728                 .parent_names = gcc_parent_names_0,
 729                 .num_parents = 4,
 730                 .ops = &clk_rcg2_ops,
 731         },
 732 };
 733
 734 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 735         .cmd_rcgr = 0x2a020,
 736         .mnd_width = 0,
 737         .hid_width = 5,
 738         .parent_map = gcc_parent_map_1,
 739         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 740         .clkr.hw.init = &(struct clk_init_data){
 741                 .name = "blsp2_qup3_i2c_apps_clk_src",
 742                 .parent_names = gcc_parent_names_1,
 743                 .num_parents = 3,
 744                 .ops = &clk_rcg2_ops,
 745         },
 746 };
 747
 748 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 749         .cmd_rcgr = 0x2a00c,
 750         .mnd_width = 8,
 751         .hid_width = 5,
 752         .parent_map = gcc_parent_map_0,
 753         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 754         .clkr.hw.init = &(struct clk_init_data){
 755                 .name = "blsp2_qup3_spi_apps_clk_src",
 756                 .parent_names = gcc_parent_names_0,
 757                 .num_parents = 4,
 758                 .ops = &clk_rcg2_ops,
 759         },
 760 };
 761
 762 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 763         .cmd_rcgr = 0x2c020,
 764         .mnd_width = 0,
 765         .hid_width = 5,
 766         .parent_map = gcc_parent_map_1,
 767         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 768         .clkr.hw.init = &(struct clk_init_data){
 769                 .name = "blsp2_qup4_i2c_apps_clk_src",
 770                 .parent_names = gcc_parent_names_1,
 771                 .num_parents = 3,
 772                 .ops = &clk_rcg2_ops,
 773         },
 774 };
 775
 776 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 777         .cmd_rcgr = 0x2c00c,
 778         .mnd_width = 8,
 779         .hid_width = 5,
 780         .parent_map = gcc_parent_map_0,
 781         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 782         .clkr.hw.init = &(struct clk_init_data){
 783                 .name = "blsp2_qup4_spi_apps_clk_src",
 784                 .parent_names = gcc_parent_names_0,
 785                 .num_parents = 4,
 786                 .ops = &clk_rcg2_ops,
 787         },
 788 };
 789
 790 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 791         .cmd_rcgr = 0x2e020,
 792         .mnd_width = 0,
 793         .hid_width = 5,
 794         .parent_map = gcc_parent_map_1,
 795         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 796         .clkr.hw.init = &(struct clk_init_data){
 797                 .name = "blsp2_qup5_i2c_apps_clk_src",
 798                 .parent_names = gcc_parent_names_1,
 799                 .num_parents = 3,
 800                 .ops = &clk_rcg2_ops,
 801         },
 802 };
 803
 804 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 805         .cmd_rcgr = 0x2e00c,
 806         .mnd_width = 8,
 807         .hid_width = 5,
 808         .parent_map = gcc_parent_map_0,
 809         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 810         .clkr.hw.init = &(struct clk_init_data){
 811                 .name = "blsp2_qup5_spi_apps_clk_src",
 812                 .parent_names = gcc_parent_names_0,
 813                 .num_parents = 4,
 814                 .ops = &clk_rcg2_ops,
 815         },
 816 };
 817
 818 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 819         .cmd_rcgr = 0x30020,
 820         .mnd_width = 0,
 821         .hid_width = 5,
 822         .parent_map = gcc_parent_map_1,
 823         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 824         .clkr.hw.init = &(struct clk_init_data){
 825                 .name = "blsp2_qup6_i2c_apps_clk_src",
 826                 .parent_names = gcc_parent_names_1,
 827                 .num_parents = 3,
 828                 .ops = &clk_rcg2_ops,
 829         },
 830 };
 831
 832 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 833         .cmd_rcgr = 0x3000c,
 834         .mnd_width = 8,
 835         .hid_width = 5,
 836         .parent_map = gcc_parent_map_0,
 837         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 838         .clkr.hw.init = &(struct clk_init_data){
 839                 .name = "blsp2_qup6_spi_apps_clk_src",
 840                 .parent_names = gcc_parent_names_0,
 841                 .num_parents = 4,
 842                 .ops = &clk_rcg2_ops,
 843         },
 844 };
 845
 846 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 847         .cmd_rcgr = 0x2700c,
 848         .mnd_width = 16,
 849         .hid_width = 5,
 850         .parent_map = gcc_parent_map_0,
 851         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 852         .clkr.hw.init = &(struct clk_init_data){
 853                 .name = "blsp2_uart1_apps_clk_src",
 854                 .parent_names = gcc_parent_names_0,
 855                 .num_parents = 4,
 856                 .ops = &clk_rcg2_ops,
 857         },
 858 };
 859
 860 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 861         .cmd_rcgr = 0x2900c,
 862         .mnd_width = 16,
 863         .hid_width = 5,
 864         .parent_map = gcc_parent_map_0,
 865         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 866         .clkr.hw.init = &(struct clk_init_data){
 867                 .name = "blsp2_uart2_apps_clk_src",
 868                 .parent_names = gcc_parent_names_0,
 869                 .num_parents = 4,
 870                 .ops = &clk_rcg2_ops,
 871         },
 872 };
 873
 874 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 875         .cmd_rcgr = 0x2b00c,
 876         .mnd_width = 16,
 877         .hid_width = 5,
 878         .parent_map = gcc_parent_map_0,
 879         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 880         .clkr.hw.init = &(struct clk_init_data){
 881                 .name = "blsp2_uart3_apps_clk_src",
 882                 .parent_names = gcc_parent_names_0,
 883                 .num_parents = 4,
 884                 .ops = &clk_rcg2_ops,
 885         },
 886 };
 887
 888 static const struct freq_tbl ftbl_gp1_clk_src[] = {
 889         F(19200000, P_XO, 1, 0, 0),
 890         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 891         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 892         { }
 893 };
 894
 895 static struct clk_rcg2 gp1_clk_src = {
 896         .cmd_rcgr = 0x64004,
 897         .mnd_width = 8,
 898         .hid_width = 5,
 899         .parent_map = gcc_parent_map_2,
 900         .freq_tbl = ftbl_gp1_clk_src,
 901         .clkr.hw.init = &(struct clk_init_data){
 902                 .name = "gp1_clk_src",
 903                 .parent_names = gcc_parent_names_2,
 904                 .num_parents = 5,
 905                 .ops = &clk_rcg2_ops,
 906         },
 907 };
 908
 909 static struct clk_rcg2 gp2_clk_src = {
 910         .cmd_rcgr = 0x65004,
 911         .mnd_width = 8,
 912         .hid_width = 5,
 913         .parent_map = gcc_parent_map_2,
 914         .freq_tbl = ftbl_gp1_clk_src,
 915         .clkr.hw.init = &(struct clk_init_data){
 916                 .name = "gp2_clk_src",
 917                 .parent_names = gcc_parent_names_2,
 918                 .num_parents = 5,
 919                 .ops = &clk_rcg2_ops,
 920         },
 921 };
 922
 923 static struct clk_rcg2 gp3_clk_src = {
 924         .cmd_rcgr = 0x66004,
 925         .mnd_width = 8,
 926         .hid_width = 5,
 927         .parent_map = gcc_parent_map_2,
 928         .freq_tbl = ftbl_gp1_clk_src,
 929         .clkr.hw.init = &(struct clk_init_data){
 930                 .name = "gp3_clk_src",
 931                 .parent_names = gcc_parent_names_2,
 932                 .num_parents = 5,
 933                 .ops = &clk_rcg2_ops,
 934         },
 935 };
 936
 937 static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = {
 938         F(19200000, P_XO, 1, 0, 0),
 939         F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 940         F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 941         { }
 942 };
 943
 944 static struct clk_rcg2 hmss_ahb_clk_src = {
 945         .cmd_rcgr = 0x48014,
 946         .mnd_width = 0,
 947         .hid_width = 5,
 948         .parent_map = gcc_parent_map_1,
 949         .freq_tbl = ftbl_hmss_ahb_clk_src,
 950         .clkr.hw.init = &(struct clk_init_data){
 951                 .name = "hmss_ahb_clk_src",
 952                 .parent_names = gcc_parent_names_1,
 953                 .num_parents = 3,
 954                 .ops = &clk_rcg2_ops,
 955         },
 956 };
 957
 958 static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
 959         F(19200000, P_XO, 1, 0, 0),
 960         { }
 961 };
 962
 963 static struct clk_rcg2 hmss_rbcpr_clk_src = {
 964         .cmd_rcgr = 0x48044,
 965         .mnd_width = 0,
 966         .hid_width = 5,
 967         .parent_map = gcc_parent_map_1,
 968         .freq_tbl = ftbl_hmss_rbcpr_clk_src,
 969         .clkr.hw.init = &(struct clk_init_data){
 970                 .name = "hmss_rbcpr_clk_src",
 971                 .parent_names = gcc_parent_names_1,
 972                 .num_parents = 3,
 973                 .ops = &clk_rcg2_ops,
 974         },
 975 };
 976
 977 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
 978         F(1010526, P_XO, 1, 1, 19),
 979         { }
 980 };
 981
 982 static struct clk_rcg2 pcie_aux_clk_src = {
 983         .cmd_rcgr = 0x6c000,
 984         .mnd_width = 16,
 985         .hid_width = 5,
 986         .parent_map = gcc_parent_map_3,
 987         .freq_tbl = ftbl_pcie_aux_clk_src,
 988         .clkr.hw.init = &(struct clk_init_data){
 989                 .name = "pcie_aux_clk_src",
 990                 .parent_names = gcc_parent_names_3,
 991                 .num_parents = 3,
 992                 .ops = &clk_rcg2_ops,
 993         },
 994 };
 995
 996 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
 997         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 998         { }
 999 };
1000
1001 static struct clk_rcg2 pdm2_clk_src = {
1002         .cmd_rcgr = 0x33010,
1003         .mnd_width = 0,
1004         .hid_width = 5,
1005         .parent_map = gcc_parent_map_1,
1006         .freq_tbl = ftbl_pdm2_clk_src,
1007         .clkr.hw.init = &(struct clk_init_data){
1008                 .name = "pdm2_clk_src",
1009                 .parent_names = gcc_parent_names_1,
1010                 .num_parents = 3,
1011                 .ops = &clk_rcg2_ops,
1012         },
1013 };
1014
1015 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1016         F(144000, P_XO, 16, 3, 25),
1017         F(400000, P_XO, 12, 1, 4),
1018         F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
1019         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
1020         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1021         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1022         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1023         { }
1024 };
1025
1026 static struct clk_rcg2 sdcc2_apps_clk_src = {
1027         .cmd_rcgr = 0x14010,
1028         .mnd_width = 8,
1029         .hid_width = 5,
1030         .parent_map = gcc_parent_map_4,
1031         .freq_tbl = ftbl_sdcc2_apps_clk_src,
1032         .clkr.hw.init = &(struct clk_init_data){
1033                 .name = "sdcc2_apps_clk_src",
1034                 .parent_names = gcc_parent_names_4,
1035                 .num_parents = 4,
1036                 .ops = &clk_rcg2_ops,
1037         },
1038 };
1039
1040 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
1041         F(144000, P_XO, 16, 3, 25),
1042         F(400000, P_XO, 12, 1, 4),
1043         F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
1044         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
1045         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1046         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1047         { }
1048 };
1049
1050 static struct clk_rcg2 sdcc4_apps_clk_src = {
1051         .cmd_rcgr = 0x16010,
1052         .mnd_width = 8,
1053         .hid_width = 5,
1054         .parent_map = gcc_parent_map_1,
1055         .freq_tbl = ftbl_sdcc4_apps_clk_src,
1056         .clkr.hw.init = &(struct clk_init_data){
1057                 .name = "sdcc4_apps_clk_src",
1058                 .parent_names = gcc_parent_names_1,
1059                 .num_parents = 3,
1060                 .ops = &clk_rcg2_ops,
1061         },
1062 };
1063
1064 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1065         F(105495, P_XO, 1, 1, 182),
1066         { }
1067 };
1068
1069 static struct clk_rcg2 tsif_ref_clk_src = {
1070         .cmd_rcgr = 0x36010,
1071         .mnd_width = 8,
1072         .hid_width = 5,
1073         .parent_map = gcc_parent_map_5,
1074         .freq_tbl = ftbl_tsif_ref_clk_src,
1075         .clkr.hw.init = &(struct clk_init_data){
1076                 .name = "tsif_ref_clk_src",
1077                 .parent_names = gcc_parent_names_5,
1078                 .num_parents = 4,
1079                 .ops = &clk_rcg2_ops,
1080         },
1081 };
1082
1083 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1084         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1085         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1086         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1087         { }
1088 };
1089
1090 static struct clk_rcg2 ufs_axi_clk_src = {
1091         .cmd_rcgr = 0x75018,
1092         .mnd_width = 8,
1093         .hid_width = 5,
1094         .parent_map = gcc_parent_map_0,
1095         .freq_tbl = ftbl_ufs_axi_clk_src,
1096         .clkr.hw.init = &(struct clk_init_data){
1097                 .name = "ufs_axi_clk_src",
1098                 .parent_names = gcc_parent_names_0,
1099                 .num_parents = 4,
1100                 .ops = &clk_rcg2_ops,
1101         },
1102 };
1103
1104 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1105         F(19200000, P_XO, 1, 0, 0),
1106         F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1107         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1108         { }
1109 };
1110
1111 static struct clk_rcg2 usb30_master_clk_src = {
1112         .cmd_rcgr = 0xf014,
1113         .mnd_width = 8,
1114         .hid_width = 5,
1115         .parent_map = gcc_parent_map_0,
1116         .freq_tbl = ftbl_usb30_master_clk_src,
1117         .clkr.hw.init = &(struct clk_init_data){
1118                 .name = "usb30_master_clk_src",
1119                 .parent_names = gcc_parent_names_0,
1120                 .num_parents = 4,
1121                 .ops = &clk_rcg2_ops,
1122         },
1123 };
1124
1125 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1126         .cmd_rcgr = 0xf028,
1127         .mnd_width = 0,
1128         .hid_width = 5,
1129         .parent_map = gcc_parent_map_0,
1130         .freq_tbl = ftbl_hmss_rbcpr_clk_src,
1131         .clkr.hw.init = &(struct clk_init_data){
1132                 .name = "usb30_mock_utmi_clk_src",
1133                 .parent_names = gcc_parent_names_0,
1134                 .num_parents = 4,
1135                 .ops = &clk_rcg2_ops,
1136         },
1137 };
1138
1139 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1140         F(1200000, P_XO, 16, 0, 0),
1141         { }
1142 };
1143
1144 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1145         .cmd_rcgr = 0x5000c,
1146         .mnd_width = 0,
1147         .hid_width = 5,
1148         .parent_map = gcc_parent_map_3,
1149         .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1150         .clkr.hw.init = &(struct clk_init_data){
1151                 .name = "usb3_phy_aux_clk_src",
1152                 .parent_names = gcc_parent_names_3,
1153                 .num_parents = 3,
1154                 .ops = &clk_rcg2_ops,
1155         },
1156 };
1157
1158 static struct clk_branch gcc_aggre1_noc_xo_clk = {
1159         .halt_reg = 0x8202c,
1160         .halt_check = BRANCH_HALT,
1161         .clkr = {
1162                 .enable_reg = 0x8202c,
1163                 .enable_mask = BIT(0),
1164                 .hw.init = &(struct clk_init_data){
1165                         .name = "gcc_aggre1_noc_xo_clk",
1166                         .ops = &clk_branch2_ops,
1167                 },
1168         },
1169 };
1170
1171 static struct clk_branch gcc_aggre1_ufs_axi_clk = {
1172         .halt_reg = 0x82028,
1173         .halt_check = BRANCH_HALT,
1174         .clkr = {
1175                 .enable_reg = 0x82028,
1176                 .enable_mask = BIT(0),
1177                 .hw.init = &(struct clk_init_data){
1178                         .name = "gcc_aggre1_ufs_axi_clk",
1179                         .parent_names = (const char *[]){
1180                                 "ufs_axi_clk_src",
1181                         },
1182                         .num_parents = 1,
1183                         .ops = &clk_branch2_ops,
1184                 },
1185         },
1186 };
1187
1188 static struct clk_branch gcc_aggre1_usb3_axi_clk = {
1189         .halt_reg = 0x82024,
1190         .halt_check = BRANCH_HALT,
1191         .clkr = {
1192                 .enable_reg = 0x82024,
1193                 .enable_mask = BIT(0),
1194                 .hw.init = &(struct clk_init_data){
1195                         .name = "gcc_aggre1_usb3_axi_clk",
1196                         .parent_names = (const char *[]){
1197                                 "usb30_master_clk_src",
1198                         },
1199                         .num_parents = 1,
1200                         .ops = &clk_branch2_ops,
1201                 },
1202         },
1203 };
1204
1205 static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = {
1206         .halt_reg = 0x48090,
1207         .halt_check = BRANCH_HALT,
1208         .clkr = {
1209                 .enable_reg = 0x48090,
1210                 .enable_mask = BIT(0),
1211                 .hw.init = &(struct clk_init_data){
1212                         .name = "gcc_apss_qdss_tsctr_div2_clk",
1213                         .ops = &clk_branch2_ops,
1214                 },
1215         },
1216 };
1217
1218 static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = {
1219         .halt_reg = 0x48094,
1220         .halt_check = BRANCH_HALT,
1221         .clkr = {
1222                 .enable_reg = 0x48094,
1223                 .enable_mask = BIT(0),
1224                 .hw.init = &(struct clk_init_data){
1225                         .name = "gcc_apss_qdss_tsctr_div8_clk",
1226                         .ops = &clk_branch2_ops,
1227                 },
1228         },
1229 };
1230
1231 static struct clk_branch gcc_bimc_hmss_axi_clk = {
1232         .halt_reg = 0x48004,
1233         .halt_check = BRANCH_HALT_VOTED,
1234         .clkr = {
1235                 .enable_reg = 0x52004,
1236                 .enable_mask = BIT(22),
1237                 .hw.init = &(struct clk_init_data){
1238                         .name = "gcc_bimc_hmss_axi_clk",
1239                         .ops = &clk_branch2_ops,
1240                 },
1241         },
1242 };
1243
1244 static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
1245         .halt_reg = 0x4401c,
1246         .halt_check = BRANCH_HALT,
1247         .clkr = {
1248                 .enable_reg = 0x4401c,
1249                 .enable_mask = BIT(0),
1250                 .hw.init = &(struct clk_init_data){
1251                         .name = "gcc_bimc_mss_q6_axi_clk",
1252                         .ops = &clk_branch2_ops,
1253                 },
1254         },
1255 };
1256
1257 static struct clk_branch gcc_blsp1_ahb_clk = {
1258         .halt_reg = 0x17004,
1259         .halt_check = BRANCH_HALT_VOTED,
1260         .clkr = {
1261                 .enable_reg = 0x52004,
1262                 .enable_mask = BIT(17),
1263                 .hw.init = &(struct clk_init_data){
1264                         .name = "gcc_blsp1_ahb_clk",
1265                         .ops = &clk_branch2_ops,
1266                 },
1267         },
1268 };
1269
1270 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1271         .halt_reg = 0x19008,
1272         .halt_check = BRANCH_HALT,
1273         .clkr = {
1274                 .enable_reg = 0x19008,
1275                 .enable_mask = BIT(0),
1276                 .hw.init = &(struct clk_init_data){
1277                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1278                         .parent_names = (const char *[]){
1279                                 "blsp1_qup1_i2c_apps_clk_src",
1280                         },
1281                         .num_parents = 1,
1282                         .ops = &clk_branch2_ops,
1283                 },
1284         },
1285 };
1286
1287 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1288         .halt_reg = 0x19004,
1289         .halt_check = BRANCH_HALT,
1290         .clkr = {
1291                 .enable_reg = 0x19004,
1292                 .enable_mask = BIT(0),
1293                 .hw.init = &(struct clk_init_data){
1294                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1295                         .parent_names = (const char *[]){
1296                                 "blsp1_qup1_spi_apps_clk_src",
1297                         },
1298                         .num_parents = 1,
1299                         .ops = &clk_branch2_ops,
1300                 },
1301         },
1302 };
1303
1304 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1305         .halt_reg = 0x1b008,
1306         .halt_check = BRANCH_HALT,
1307         .clkr = {
1308                 .enable_reg = 0x1b008,
1309                 .enable_mask = BIT(0),
1310                 .hw.init = &(struct clk_init_data){
1311                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1312                         .parent_names = (const char *[]){
1313                                 "blsp1_qup2_i2c_apps_clk_src",
1314                         },
1315                         .num_parents = 1,
1316                         .ops = &clk_branch2_ops,
1317                 },
1318         },
1319 };
1320
1321 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1322         .halt_reg = 0x1b004,
1323         .halt_check = BRANCH_HALT,
1324         .clkr = {
1325                 .enable_reg = 0x1b004,
1326                 .enable_mask = BIT(0),
1327                 .hw.init = &(struct clk_init_data){
1328                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1329                         .parent_names = (const char *[]){
1330                                 "blsp1_qup2_spi_apps_clk_src",
1331                         },
1332                         .num_parents = 1,
1333                         .ops = &clk_branch2_ops,
1334                 },
1335         },
1336 };
1337
1338 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1339         .halt_reg = 0x1d008,
1340         .halt_check = BRANCH_HALT,
1341         .clkr = {
1342                 .enable_reg = 0x1d008,
1343                 .enable_mask = BIT(0),
1344                 .hw.init = &(struct clk_init_data){
1345                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1346                         .parent_names = (const char *[]){
1347                                 "blsp1_qup3_i2c_apps_clk_src",
1348                         },
1349                         .num_parents = 1,
1350                         .ops = &clk_branch2_ops,
1351                 },
1352         },
1353 };
1354
1355 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1356         .halt_reg = 0x1d004,
1357         .halt_check = BRANCH_HALT,
1358         .clkr = {
1359                 .enable_reg = 0x1d004,
1360                 .enable_mask = BIT(0),
1361                 .hw.init = &(struct clk_init_data){
1362                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1363                         .parent_names = (const char *[]){
1364                                 "blsp1_qup3_spi_apps_clk_src",
1365                         },
1366                         .num_parents = 1,
1367                         .ops = &clk_branch2_ops,
1368                 },
1369         },
1370 };
1371
1372 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1373         .halt_reg = 0x1f008,
1374         .halt_check = BRANCH_HALT,
1375         .clkr = {
1376                 .enable_reg = 0x1f008,
1377                 .enable_mask = BIT(0),
1378                 .hw.init = &(struct clk_init_data){
1379                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1380                         .parent_names = (const char *[]){
1381                                 "blsp1_qup4_i2c_apps_clk_src",
1382                         },
1383                         .num_parents = 1,
1384                         .ops = &clk_branch2_ops,
1385                 },
1386         },
1387 };
1388
1389 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1390         .halt_reg = 0x1f004,
1391         .halt_check = BRANCH_HALT,
1392         .clkr = {
1393                 .enable_reg = 0x1f004,
1394                 .enable_mask = BIT(0),
1395                 .hw.init = &(struct clk_init_data){
1396                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1397                         .parent_names = (const char *[]){
1398                                 "blsp1_qup4_spi_apps_clk_src",
1399                         },
1400                         .num_parents = 1,
1401                         .ops = &clk_branch2_ops,
1402                 },
1403         },
1404 };
1405
1406 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1407         .halt_reg = 0x21008,
1408         .halt_check = BRANCH_HALT,
1409         .clkr = {
1410                 .enable_reg = 0x21008,
1411                 .enable_mask = BIT(0),
1412                 .hw.init = &(struct clk_init_data){
1413                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1414                         .parent_names = (const char *[]){
1415                                 "blsp1_qup5_i2c_apps_clk_src",
1416                         },
1417                         .num_parents = 1,
1418                         .ops = &clk_branch2_ops,
1419                 },
1420         },
1421 };
1422
1423 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1424         .halt_reg = 0x21004,
1425         .halt_check = BRANCH_HALT,
1426         .clkr = {
1427                 .enable_reg = 0x21004,
1428                 .enable_mask = BIT(0),
1429                 .hw.init = &(struct clk_init_data){
1430                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1431                         .parent_names = (const char *[]){
1432                                 "blsp1_qup5_spi_apps_clk_src",
1433                         },
1434                         .num_parents = 1,
1435                         .ops = &clk_branch2_ops,
1436                 },
1437         },
1438 };
1439
1440 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1441         .halt_reg = 0x23008,
1442         .halt_check = BRANCH_HALT,
1443         .clkr = {
1444                 .enable_reg = 0x23008,
1445                 .enable_mask = BIT(0),
1446                 .hw.init = &(struct clk_init_data){
1447                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1448                         .parent_names = (const char *[]){
1449                                 "blsp1_qup6_i2c_apps_clk_src",
1450                         },
1451                         .num_parents = 1,
1452                         .ops = &clk_branch2_ops,
1453                 },
1454         },
1455 };
1456
1457 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1458         .halt_reg = 0x23004,
1459         .halt_check = BRANCH_HALT,
1460         .clkr = {
1461                 .enable_reg = 0x23004,
1462                 .enable_mask = BIT(0),
1463                 .hw.init = &(struct clk_init_data){
1464                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1465                         .parent_names = (const char *[]){
1466                                 "blsp1_qup6_spi_apps_clk_src",
1467                         },
1468                         .num_parents = 1,
1469                         .ops = &clk_branch2_ops,
1470                 },
1471         },
1472 };
1473
1474 static struct clk_branch gcc_blsp1_sleep_clk = {
1475         .halt_reg = 0x17008,
1476         .halt_check = BRANCH_HALT_VOTED,
1477         .clkr = {
1478                 .enable_reg = 0x52004,
1479                 .enable_mask = BIT(16),
1480                 .hw.init = &(struct clk_init_data){
1481                         .name = "gcc_blsp1_sleep_clk",
1482                         .ops = &clk_branch2_ops,
1483                 },
1484         },
1485 };
1486
1487 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1488         .halt_reg = 0x1a004,
1489         .halt_check = BRANCH_HALT,
1490         .clkr = {
1491                 .enable_reg = 0x1a004,
1492                 .enable_mask = BIT(0),
1493                 .hw.init = &(struct clk_init_data){
1494                         .name = "gcc_blsp1_uart1_apps_clk",
1495                         .parent_names = (const char *[]){
1496                                 "blsp1_uart1_apps_clk_src",
1497                         },
1498                         .num_parents = 1,
1499                         .ops = &clk_branch2_ops,
1500                 },
1501         },
1502 };
1503
1504 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1505         .halt_reg = 0x1c004,
1506         .halt_check = BRANCH_HALT,
1507         .clkr = {
1508                 .enable_reg = 0x1c004,
1509                 .enable_mask = BIT(0),
1510                 .hw.init = &(struct clk_init_data){
1511                         .name = "gcc_blsp1_uart2_apps_clk",
1512                         .parent_names = (const char *[]){
1513                                 "blsp1_uart2_apps_clk_src",
1514                         },
1515                         .num_parents = 1,
1516                         .ops = &clk_branch2_ops,
1517                 },
1518         },
1519 };
1520
1521 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1522         .halt_reg = 0x1e004,
1523         .halt_check = BRANCH_HALT,
1524         .clkr = {
1525                 .enable_reg = 0x1e004,
1526                 .enable_mask = BIT(0),
1527                 .hw.init = &(struct clk_init_data){
1528                         .name = "gcc_blsp1_uart3_apps_clk",
1529                         .parent_names = (const char *[]){
1530                                 "blsp1_uart3_apps_clk_src",
1531                         },
1532                         .num_parents = 1,
1533                         .ops = &clk_branch2_ops,
1534                 },
1535         },
1536 };
1537
1538 static struct clk_branch gcc_blsp2_ahb_clk = {
1539         .halt_reg = 0x25004,
1540         .halt_check = BRANCH_HALT_VOTED,
1541         .clkr = {
1542                 .enable_reg = 0x52004,
1543                 .enable_mask = BIT(15),
1544                 .hw.init = &(struct clk_init_data){
1545                         .name = "gcc_blsp2_ahb_clk",
1546                         .ops = &clk_branch2_ops,
1547                 },
1548         },
1549 };
1550
1551 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1552         .halt_reg = 0x26008,
1553         .halt_check = BRANCH_HALT,
1554         .clkr = {
1555                 .enable_reg = 0x26008,
1556                 .enable_mask = BIT(0),
1557                 .hw.init = &(struct clk_init_data){
1558                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1559                         .parent_names = (const char *[]){
1560                                 "blsp2_qup1_i2c_apps_clk_src",
1561                         },
1562                         .num_parents = 1,
1563                         .ops = &clk_branch2_ops,
1564                 },
1565         },
1566 };
1567
1568 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1569         .halt_reg = 0x26004,
1570         .halt_check = BRANCH_HALT,
1571         .clkr = {
1572                 .enable_reg = 0x26004,
1573                 .enable_mask = BIT(0),
1574                 .hw.init = &(struct clk_init_data){
1575                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1576                         .parent_names = (const char *[]){
1577                                 "blsp2_qup1_spi_apps_clk_src",
1578                         },
1579                         .num_parents = 1,
1580                         .ops = &clk_branch2_ops,
1581                 },
1582         },
1583 };
1584
1585 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1586         .halt_reg = 0x28008,
1587         .halt_check = BRANCH_HALT,
1588         .clkr = {
1589                 .enable_reg = 0x28008,
1590                 .enable_mask = BIT(0),
1591                 .hw.init = &(struct clk_init_data){
1592                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
1593                         .parent_names = (const char *[]){
1594                                 "blsp2_qup2_i2c_apps_clk_src",
1595                         },
1596                         .num_parents = 1,
1597                         .ops = &clk_branch2_ops,
1598                 },
1599         },
1600 };
1601
1602 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1603         .halt_reg = 0x28004,
1604         .halt_check = BRANCH_HALT,
1605         .clkr = {
1606                 .enable_reg = 0x28004,
1607                 .enable_mask = BIT(0),
1608                 .hw.init = &(struct clk_init_data){
1609                         .name = "gcc_blsp2_qup2_spi_apps_clk",
1610                         .parent_names = (const char *[]){
1611                                 "blsp2_qup2_spi_apps_clk_src",
1612                         },
1613                         .num_parents = 1,
1614                         .ops = &clk_branch2_ops,
1615                 },
1616         },
1617 };
1618
1619 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1620         .halt_reg = 0x2a008,
1621         .halt_check = BRANCH_HALT,
1622         .clkr = {
1623                 .enable_reg = 0x2a008,
1624                 .enable_mask = BIT(0),
1625                 .hw.init = &(struct clk_init_data){
1626                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
1627                         .parent_names = (const char *[]){
1628                                 "blsp2_qup3_i2c_apps_clk_src",
1629                         },
1630                         .num_parents = 1,
1631                         .ops = &clk_branch2_ops,
1632                 },
1633         },
1634 };
1635
1636 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1637         .halt_reg = 0x2a004,
1638         .halt_check = BRANCH_HALT,
1639         .clkr = {
1640                 .enable_reg = 0x2a004,
1641                 .enable_mask = BIT(0),
1642                 .hw.init = &(struct clk_init_data){
1643                         .name = "gcc_blsp2_qup3_spi_apps_clk",
1644                         .parent_names = (const char *[]){
1645                                 "blsp2_qup3_spi_apps_clk_src",
1646                         },
1647                         .num_parents = 1,
1648                         .ops = &clk_branch2_ops,
1649                 },
1650         },
1651 };
1652
1653 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1654         .halt_reg = 0x2c008,
1655         .halt_check = BRANCH_HALT,
1656         .clkr = {
1657                 .enable_reg = 0x2c008,
1658                 .enable_mask = BIT(0),
1659                 .hw.init = &(struct clk_init_data){
1660                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
1661                         .parent_names = (const char *[]){
1662                                 "blsp2_qup4_i2c_apps_clk_src",
1663                         },
1664                         .num_parents = 1,
1665                         .ops = &clk_branch2_ops,
1666                 },
1667         },
1668 };
1669
1670 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1671         .halt_reg = 0x2c004,
1672         .halt_check = BRANCH_HALT,
1673         .clkr = {
1674                 .enable_reg = 0x2c004,
1675                 .enable_mask = BIT(0),
1676                 .hw.init = &(struct clk_init_data){
1677                         .name = "gcc_blsp2_qup4_spi_apps_clk",
1678                         .parent_names = (const char *[]){
1679                                 "blsp2_qup4_spi_apps_clk_src",
1680                         },
1681                         .num_parents = 1,
1682                         .ops = &clk_branch2_ops,
1683                 },
1684         },
1685 };
1686
1687 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1688         .halt_reg = 0x2e008,
1689         .halt_check = BRANCH_HALT,
1690         .clkr = {
1691                 .enable_reg = 0x2e008,
1692                 .enable_mask = BIT(0),
1693                 .hw.init = &(struct clk_init_data){
1694                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
1695                         .parent_names = (const char *[]){
1696                                 "blsp2_qup5_i2c_apps_clk_src",
1697                         },
1698                         .num_parents = 1,
1699                         .ops = &clk_branch2_ops,
1700                 },
1701         },
1702 };
1703
1704 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1705         .halt_reg = 0x2e004,
1706         .halt_check = BRANCH_HALT,
1707         .clkr = {
1708                 .enable_reg = 0x2e004,
1709                 .enable_mask = BIT(0),
1710                 .hw.init = &(struct clk_init_data){
1711                         .name = "gcc_blsp2_qup5_spi_apps_clk",
1712                         .parent_names = (const char *[]){
1713                                 "blsp2_qup5_spi_apps_clk_src",
1714                         },
1715                         .num_parents = 1,
1716                         .ops = &clk_branch2_ops,
1717                 },
1718         },
1719 };
1720
1721 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1722         .halt_reg = 0x30008,
1723         .halt_check = BRANCH_HALT,
1724         .clkr = {
1725                 .enable_reg = 0x30008,
1726                 .enable_mask = BIT(0),
1727                 .hw.init = &(struct clk_init_data){
1728                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
1729                         .parent_names = (const char *[]){
1730                                 "blsp2_qup6_i2c_apps_clk_src",
1731                         },
1732                         .num_parents = 1,
1733                         .ops = &clk_branch2_ops,
1734                 },
1735         },
1736 };
1737
1738 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1739         .halt_reg = 0x30004,
1740         .halt_check = BRANCH_HALT,
1741         .clkr = {
1742                 .enable_reg = 0x30004,
1743                 .enable_mask = BIT(0),
1744                 .hw.init = &(struct clk_init_data){
1745                         .name = "gcc_blsp2_qup6_spi_apps_clk",
1746                         .parent_names = (const char *[]){
1747                                 "blsp2_qup6_spi_apps_clk_src",
1748                         },
1749                         .num_parents = 1,
1750                         .ops = &clk_branch2_ops,
1751                 },
1752         },
1753 };
1754
1755 static struct clk_branch gcc_blsp2_sleep_clk = {
1756         .halt_reg = 0x25008,
1757         .halt_check = BRANCH_HALT_VOTED,
1758         .clkr = {
1759                 .enable_reg = 0x52004,
1760                 .enable_mask = BIT(14),
1761                 .hw.init = &(struct clk_init_data){
1762                         .name = "gcc_blsp2_sleep_clk",
1763                         .ops = &clk_branch2_ops,
1764                 },
1765         },
1766 };
1767
1768 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1769         .halt_reg = 0x27004,
1770         .halt_check = BRANCH_HALT,
1771         .clkr = {
1772                 .enable_reg = 0x27004,
1773                 .enable_mask = BIT(0),
1774                 .hw.init = &(struct clk_init_data){
1775                         .name = "gcc_blsp2_uart1_apps_clk",
1776                         .parent_names = (const char *[]){
1777                                 "blsp2_uart1_apps_clk_src",
1778                         },
1779                         .num_parents = 1,
1780                         .ops = &clk_branch2_ops,
1781                 },
1782         },
1783 };
1784
1785 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1786         .halt_reg = 0x29004,
1787         .halt_check = BRANCH_HALT,
1788         .clkr = {
1789                 .enable_reg = 0x29004,
1790                 .enable_mask = BIT(0),
1791                 .hw.init = &(struct clk_init_data){
1792                         .name = "gcc_blsp2_uart2_apps_clk",
1793                         .parent_names = (const char *[]){
1794                                 "blsp2_uart2_apps_clk_src",
1795                         },
1796                         .num_parents = 1,
1797                         .ops = &clk_branch2_ops,
1798                 },
1799         },
1800 };
1801
1802 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1803         .halt_reg = 0x2b004,
1804         .halt_check = BRANCH_HALT,
1805         .clkr = {
1806                 .enable_reg = 0x2b004,
1807                 .enable_mask = BIT(0),
1808                 .hw.init = &(struct clk_init_data){
1809                         .name = "gcc_blsp2_uart3_apps_clk",
1810                         .parent_names = (const char *[]){
1811                                 "blsp2_uart3_apps_clk_src",
1812                         },
1813                         .num_parents = 1,
1814                         .ops = &clk_branch2_ops,
1815                 },
1816         },
1817 };
1818
1819 static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
1820         .halt_reg = 0x5018,
1821         .halt_check = BRANCH_HALT,
1822         .clkr = {
1823                 .enable_reg = 0x5018,
1824                 .enable_mask = BIT(0),
1825                 .hw.init = &(struct clk_init_data){
1826                         .name = "gcc_cfg_noc_usb3_axi_clk",
1827                         .parent_names = (const char *[]){
1828                                 "usb30_master_clk_src",
1829                         },
1830                         .num_parents = 1,
1831                         .ops = &clk_branch2_ops,
1832                 },
1833         },
1834 };
1835
1836 static struct clk_branch gcc_gp1_clk = {
1837         .halt_reg = 0x64000,
1838         .halt_check = BRANCH_HALT,
1839         .clkr = {
1840                 .enable_reg = 0x64000,
1841                 .enable_mask = BIT(0),
1842                 .hw.init = &(struct clk_init_data){
1843                         .name = "gcc_gp1_clk",
1844                         .parent_names = (const char *[]){
1845                                 "gp1_clk_src",
1846                         },
1847                         .num_parents = 1,
1848                         .ops = &clk_branch2_ops,
1849                 },
1850         },
1851 };
1852
1853 static struct clk_branch gcc_gp2_clk = {
1854         .halt_reg = 0x65000,
1855         .halt_check = BRANCH_HALT,
1856         .clkr = {
1857                 .enable_reg = 0x65000,
1858                 .enable_mask = BIT(0),
1859                 .hw.init = &(struct clk_init_data){
1860                         .name = "gcc_gp2_clk",
1861                         .parent_names = (const char *[]){
1862                                 "gp2_clk_src",
1863                         },
1864                         .num_parents = 1,
1865                         .ops = &clk_branch2_ops,
1866                 },
1867         },
1868 };
1869
1870 static struct clk_branch gcc_gp3_clk = {
1871         .halt_reg = 0x66000,
1872         .halt_check = BRANCH_HALT,
1873         .clkr = {
1874                 .enable_reg = 0x66000,
1875                 .enable_mask = BIT(0),
1876                 .hw.init = &(struct clk_init_data){
1877                         .name = "gcc_gp3_clk",
1878                         .parent_names = (const char *[]){
1879                                 "gp3_clk_src",
1880                         },
1881                         .num_parents = 1,
1882                         .ops = &clk_branch2_ops,
1883                 },
1884         },
1885 };
1886
1887 static struct clk_branch gcc_gpu_bimc_gfx_clk = {
1888         .halt_reg = 0x71010,
1889         .halt_check = BRANCH_HALT,
1890         .clkr = {
1891                 .enable_reg = 0x71010,
1892                 .enable_mask = BIT(0),
1893                 .hw.init = &(struct clk_init_data){
1894                         .name = "gcc_gpu_bimc_gfx_clk",
1895                         .ops = &clk_branch2_ops,
1896                 },
1897         },
1898 };
1899
1900 static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
1901         .halt_reg = 0x7100c,
1902         .halt_check = BRANCH_HALT,
1903         .clkr = {
1904                 .enable_reg = 0x7100c,
1905                 .enable_mask = BIT(0),
1906                 .hw.init = &(struct clk_init_data){
1907                         .name = "gcc_gpu_bimc_gfx_src_clk",
1908                         .ops = &clk_branch2_ops,
1909                 },
1910         },
1911 };
1912
1913 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1914         .halt_reg = 0x71004,
1915         .halt_check = BRANCH_HALT,
1916         .clkr = {
1917                 .enable_reg = 0x71004,
1918                 .enable_mask = BIT(0),
1919                 .hw.init = &(struct clk_init_data){
1920                         .name = "gcc_gpu_cfg_ahb_clk",
1921                         .ops = &clk_branch2_ops,
1922                 },
1923         },
1924 };
1925
1926 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1927         .halt_reg = 0x71018,
1928         .halt_check = BRANCH_HALT,
1929         .clkr = {
1930                 .enable_reg = 0x71018,
1931                 .enable_mask = BIT(0),
1932                 .hw.init = &(struct clk_init_data){
1933                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
1934                         .ops = &clk_branch2_ops,
1935                 },
1936         },
1937 };
1938
1939 static struct clk_branch gcc_hmss_ahb_clk = {
1940         .halt_reg = 0x48000,
1941         .halt_check = BRANCH_HALT_VOTED,
1942         .clkr = {
1943                 .enable_reg = 0x52004,
1944                 .enable_mask = BIT(21),
1945                 .hw.init = &(struct clk_init_data){
1946                         .name = "gcc_hmss_ahb_clk",
1947                         .parent_names = (const char *[]){
1948                                 "hmss_ahb_clk_src",
1949                         },
1950                         .num_parents = 1,
1951                         .ops = &clk_branch2_ops,
1952                 },
1953         },
1954 };
1955
1956 static struct clk_branch gcc_hmss_at_clk = {
1957         .halt_reg = 0x48010,
1958         .halt_check = BRANCH_HALT,
1959         .clkr = {
1960                 .enable_reg = 0x48010,
1961                 .enable_mask = BIT(0),
1962                 .hw.init = &(struct clk_init_data){
1963                         .name = "gcc_hmss_at_clk",
1964                         .ops = &clk_branch2_ops,
1965                 },
1966         },
1967 };
1968
1969 static struct clk_branch gcc_hmss_dvm_bus_clk = {
1970         .halt_reg = 0x4808c,
1971         .halt_check = BRANCH_HALT,
1972         .clkr = {
1973                 .enable_reg = 0x4808c,
1974                 .enable_mask = BIT(0),
1975                 .hw.init = &(struct clk_init_data){
1976                         .name = "gcc_hmss_dvm_bus_clk",
1977                         .ops = &clk_branch2_ops,
1978                 },
1979         },
1980 };
1981
1982 static struct clk_branch gcc_hmss_rbcpr_clk = {
1983         .halt_reg = 0x48008,
1984         .halt_check = BRANCH_HALT,
1985         .clkr = {
1986                 .enable_reg = 0x48008,
1987                 .enable_mask = BIT(0),
1988                 .hw.init = &(struct clk_init_data){
1989                         .name = "gcc_hmss_rbcpr_clk",
1990                         .parent_names = (const char *[]){
1991                                 "hmss_rbcpr_clk_src",
1992                         },
1993                         .num_parents = 1,
1994                         .ops = &clk_branch2_ops,
1995                 },
1996         },
1997 };
1998
1999 static struct clk_branch gcc_hmss_trig_clk = {
2000         .halt_reg = 0x4800c,
2001         .halt_check = BRANCH_HALT,
2002         .clkr = {
2003                 .enable_reg = 0x4800c,
2004                 .enable_mask = BIT(0),
2005                 .hw.init = &(struct clk_init_data){
2006                         .name = "gcc_hmss_trig_clk",
2007                         .ops = &clk_branch2_ops,
2008                 },
2009         },
2010 };
2011
2012 static struct clk_branch gcc_lpass_at_clk = {
2013         .halt_reg = 0x47020,
2014         .halt_check = BRANCH_HALT,
2015         .clkr = {
2016                 .enable_reg = 0x47020,
2017                 .enable_mask = BIT(0),
2018                 .hw.init = &(struct clk_init_data){
2019                         .name = "gcc_lpass_at_clk",
2020                         .ops = &clk_branch2_ops,
2021                 },
2022         },
2023 };
2024
2025 static struct clk_branch gcc_lpass_trig_clk = {
2026         .halt_reg = 0x4701c,
2027         .halt_check = BRANCH_HALT,
2028         .clkr = {
2029                 .enable_reg = 0x4701c,
2030                 .enable_mask = BIT(0),
2031                 .hw.init = &(struct clk_init_data){
2032                         .name = "gcc_lpass_trig_clk",
2033                         .ops = &clk_branch2_ops,
2034                 },
2035         },
2036 };
2037
2038 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
2039         .halt_reg = 0x9004,
2040         .halt_check = BRANCH_HALT,
2041         .clkr = {
2042                 .enable_reg = 0x9004,
2043                 .enable_mask = BIT(0),
2044                 .hw.init = &(struct clk_init_data){
2045                         .name = "gcc_mmss_noc_cfg_ahb_clk",
2046                         .ops = &clk_branch2_ops,
2047                 },
2048         },
2049 };
2050
2051 static struct clk_branch gcc_mmss_qm_ahb_clk = {
2052         .halt_reg = 0x9030,
2053         .halt_check = BRANCH_HALT,
2054         .clkr = {
2055                 .enable_reg = 0x9030,
2056                 .enable_mask = BIT(0),
2057                 .hw.init = &(struct clk_init_data){
2058                         .name = "gcc_mmss_qm_ahb_clk",
2059                         .ops = &clk_branch2_ops,
2060                 },
2061         },
2062 };
2063
2064 static struct clk_branch gcc_mmss_qm_core_clk = {
2065         .halt_reg = 0x900c,
2066         .halt_check = BRANCH_HALT,
2067         .clkr = {
2068                 .enable_reg = 0x900c,
2069                 .enable_mask = BIT(0),
2070                 .hw.init = &(struct clk_init_data){
2071                         .name = "gcc_mmss_qm_core_clk",
2072                         .ops = &clk_branch2_ops,
2073                 },
2074         },
2075 };
2076
2077 static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
2078         .halt_reg = 0x9000,
2079         .halt_check = BRANCH_HALT,
2080         .clkr = {
2081                 .enable_reg = 0x9000,
2082                 .enable_mask = BIT(0),
2083                 .hw.init = &(struct clk_init_data){
2084                         .name = "gcc_mmss_sys_noc_axi_clk",
2085                         .ops = &clk_branch2_ops,
2086                 },
2087         },
2088 };
2089
2090 static struct clk_branch gcc_mss_at_clk = {
2091         .halt_reg = 0x8a00c,
2092         .halt_check = BRANCH_HALT,
2093         .clkr = {
2094                 .enable_reg = 0x8a00c,
2095                 .enable_mask = BIT(0),
2096                 .hw.init = &(struct clk_init_data){
2097                         .name = "gcc_mss_at_clk",
2098                         .ops = &clk_branch2_ops,
2099                 },
2100         },
2101 };
2102
2103 static struct clk_branch gcc_pcie_0_aux_clk = {
2104         .halt_reg = 0x6b014,
2105         .halt_check = BRANCH_HALT,
2106         .clkr = {
2107                 .enable_reg = 0x6b014,
2108                 .enable_mask = BIT(0),
2109                 .hw.init = &(struct clk_init_data){
2110                         .name = "gcc_pcie_0_aux_clk",
2111                         .parent_names = (const char *[]){
2112                                 "pcie_aux_clk_src",
2113                         },
2114                         .num_parents = 1,
2115                         .ops = &clk_branch2_ops,
2116                 },
2117         },
2118 };
2119
2120 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2121         .halt_reg = 0x6b010,
2122         .halt_check = BRANCH_HALT,
2123         .clkr = {
2124                 .enable_reg = 0x6b010,
2125                 .enable_mask = BIT(0),
2126                 .hw.init = &(struct clk_init_data){
2127                         .name = "gcc_pcie_0_cfg_ahb_clk",
2128                         .ops = &clk_branch2_ops,
2129                 },
2130         },
2131 };
2132
2133 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2134         .halt_reg = 0x6b00c,
2135         .halt_check = BRANCH_HALT,
2136         .clkr = {
2137                 .enable_reg = 0x6b00c,
2138                 .enable_mask = BIT(0),
2139                 .hw.init = &(struct clk_init_data){
2140                         .name = "gcc_pcie_0_mstr_axi_clk",
2141                         .ops = &clk_branch2_ops,
2142                 },
2143         },
2144 };
2145
2146 static struct clk_branch gcc_pcie_0_pipe_clk = {
2147         .halt_reg = 0x6b018,
2148         .halt_check = BRANCH_HALT,
2149         .clkr = {
2150                 .enable_reg = 0x6b018,
2151                 .enable_mask = BIT(0),
2152                 .hw.init = &(struct clk_init_data){
2153                         .name = "gcc_pcie_0_pipe_clk",
2154                         .ops = &clk_branch2_ops,
2155                 },
2156         },
2157 };
2158
2159 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2160         .halt_reg = 0x6b008,
2161         .halt_check = BRANCH_HALT,
2162         .clkr = {
2163                 .enable_reg = 0x6b008,
2164                 .enable_mask = BIT(0),
2165                 .hw.init = &(struct clk_init_data){
2166                         .name = "gcc_pcie_0_slv_axi_clk",
2167                         .ops = &clk_branch2_ops,
2168                 },
2169         },
2170 };
2171
2172 static struct clk_branch gcc_pcie_phy_aux_clk = {
2173         .halt_reg = 0x6f004,
2174         .halt_check = BRANCH_HALT,
2175         .clkr = {
2176                 .enable_reg = 0x6f004,
2177                 .enable_mask = BIT(0),
2178                 .hw.init = &(struct clk_init_data){
2179                         .name = "gcc_pcie_phy_aux_clk",
2180                         .parent_names = (const char *[]){
2181                                 "pcie_aux_clk_src",
2182                         },
2183                         .num_parents = 1,
2184                         .ops = &clk_branch2_ops,
2185                 },
2186         },
2187 };
2188
2189 static struct clk_branch gcc_pdm2_clk = {
2190         .halt_reg = 0x3300c,
2191         .halt_check = BRANCH_HALT,
2192         .clkr = {
2193                 .enable_reg = 0x3300c,
2194                 .enable_mask = BIT(0),
2195                 .hw.init = &(struct clk_init_data){
2196                         .name = "gcc_pdm2_clk",
2197                         .parent_names = (const char *[]){
2198                                 "pdm2_clk_src",
2199                         },
2200                         .num_parents = 1,
2201                         .ops = &clk_branch2_ops,
2202                 },
2203         },
2204 };
2205
2206 static struct clk_branch gcc_pdm_ahb_clk = {
2207         .halt_reg = 0x33004,
2208         .halt_check = BRANCH_HALT,
2209         .clkr = {
2210                 .enable_reg = 0x33004,
2211                 .enable_mask = BIT(0),
2212                 .hw.init = &(struct clk_init_data){
2213                         .name = "gcc_pdm_ahb_clk",
2214                         .ops = &clk_branch2_ops,
2215                 },
2216         },
2217 };
2218
2219 static struct clk_branch gcc_pdm_xo4_clk = {
2220         .halt_reg = 0x33008,
2221         .halt_check = BRANCH_HALT,
2222         .clkr = {
2223                 .enable_reg = 0x33008,
2224                 .enable_mask = BIT(0),
2225                 .hw.init = &(struct clk_init_data){
2226                         .name = "gcc_pdm_xo4_clk",
2227                         .ops = &clk_branch2_ops,
2228                 },
2229         },
2230 };
2231
2232 static struct clk_branch gcc_prng_ahb_clk = {
2233         .halt_reg = 0x34004,
2234         .halt_check = BRANCH_HALT_VOTED,
2235         .clkr = {
2236                 .enable_reg = 0x52004,
2237                 .enable_mask = BIT(13),
2238                 .hw.init = &(struct clk_init_data){
2239                         .name = "gcc_prng_ahb_clk",
2240                         .ops = &clk_branch2_ops,
2241                 },
2242         },
2243 };
2244
2245 static struct clk_branch gcc_sdcc2_ahb_clk = {
2246         .halt_reg = 0x14008,
2247         .halt_check = BRANCH_HALT,
2248         .clkr = {
2249                 .enable_reg = 0x14008,
2250                 .enable_mask = BIT(0),
2251                 .hw.init = &(struct clk_init_data){
2252                         .name = "gcc_sdcc2_ahb_clk",
2253                         .ops = &clk_branch2_ops,
2254                 },
2255         },
2256 };
2257
2258 static struct clk_branch gcc_sdcc2_apps_clk = {
2259         .halt_reg = 0x14004,
2260         .halt_check = BRANCH_HALT,
2261         .clkr = {
2262                 .enable_reg = 0x14004,
2263                 .enable_mask = BIT(0),
2264                 .hw.init = &(struct clk_init_data){
2265                         .name = "gcc_sdcc2_apps_clk",
2266                         .parent_names = (const char *[]){
2267                                 "sdcc2_apps_clk_src",
2268                         },
2269                         .num_parents = 1,
2270                         .ops = &clk_branch2_ops,
2271                 },
2272         },
2273 };
2274
2275 static struct clk_branch gcc_sdcc4_ahb_clk = {
2276         .halt_reg = 0x16008,
2277         .halt_check = BRANCH_HALT,
2278         .clkr = {
2279                 .enable_reg = 0x16008,
2280                 .enable_mask = BIT(0),
2281                 .hw.init = &(struct clk_init_data){
2282                         .name = "gcc_sdcc4_ahb_clk",
2283                         .ops = &clk_branch2_ops,
2284                 },
2285         },
2286 };
2287
2288 static struct clk_branch gcc_sdcc4_apps_clk = {
2289         .halt_reg = 0x16004,
2290         .halt_check = BRANCH_HALT,
2291         .clkr = {
2292                 .enable_reg = 0x16004,
2293                 .enable_mask = BIT(0),
2294                 .hw.init = &(struct clk_init_data){
2295                         .name = "gcc_sdcc4_apps_clk",
2296                         .parent_names = (const char *[]){
2297                                 "sdcc4_apps_clk_src",
2298                         },
2299                         .num_parents = 1,
2300                         .ops = &clk_branch2_ops,
2301                 },
2302         },
2303 };
2304
2305 static struct clk_branch gcc_tsif_ahb_clk = {
2306         .halt_reg = 0x36004,
2307         .halt_check = BRANCH_HALT,
2308         .clkr = {
2309                 .enable_reg = 0x36004,
2310                 .enable_mask = BIT(0),
2311                 .hw.init = &(struct clk_init_data){
2312                         .name = "gcc_tsif_ahb_clk",
2313                         .ops = &clk_branch2_ops,
2314                 },
2315         },
2316 };
2317
2318 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2319         .halt_reg = 0x3600c,
2320         .halt_check = BRANCH_HALT,
2321         .clkr = {
2322                 .enable_reg = 0x3600c,
2323                 .enable_mask = BIT(0),
2324                 .hw.init = &(struct clk_init_data){
2325                         .name = "gcc_tsif_inactivity_timers_clk",
2326                         .ops = &clk_branch2_ops,
2327                 },
2328         },
2329 };
2330
2331 static struct clk_branch gcc_tsif_ref_clk = {
2332         .halt_reg = 0x36008,
2333         .halt_check = BRANCH_HALT,
2334         .clkr = {
2335                 .enable_reg = 0x36008,
2336                 .enable_mask = BIT(0),
2337                 .hw.init = &(struct clk_init_data){
2338                         .name = "gcc_tsif_ref_clk",
2339                         .parent_names = (const char *[]){
2340                                 "tsif_ref_clk_src",
2341                         },
2342                         .num_parents = 1,
2343                         .ops = &clk_branch2_ops,
2344                 },
2345         },
2346 };
2347
2348 static struct clk_branch gcc_ufs_ahb_clk = {
2349         .halt_reg = 0x7500c,
2350         .halt_check = BRANCH_HALT,
2351         .clkr = {
2352                 .enable_reg = 0x7500c,
2353                 .enable_mask = BIT(0),
2354                 .hw.init = &(struct clk_init_data){
2355                         .name = "gcc_ufs_ahb_clk",
2356                         .ops = &clk_branch2_ops,
2357                 },
2358         },
2359 };
2360
2361 static struct clk_branch gcc_ufs_axi_clk = {
2362         .halt_reg = 0x75008,
2363         .halt_check = BRANCH_HALT,
2364         .clkr = {
2365                 .enable_reg = 0x75008,
2366                 .enable_mask = BIT(0),
2367                 .hw.init = &(struct clk_init_data){
2368                         .name = "gcc_ufs_axi_clk",
2369                         .parent_names = (const char *[]){
2370                                 "ufs_axi_clk_src",
2371                         },
2372                         .num_parents = 1,
2373                         .ops = &clk_branch2_ops,
2374                 },
2375         },
2376 };
2377
2378 static struct clk_branch gcc_ufs_ice_core_clk = {
2379         .halt_reg = 0x7600c,
2380         .halt_check = BRANCH_HALT,
2381         .clkr = {
2382                 .enable_reg = 0x7600c,
2383                 .enable_mask = BIT(0),
2384                 .hw.init = &(struct clk_init_data){
2385                         .name = "gcc_ufs_ice_core_clk",
2386                         .ops = &clk_branch2_ops,
2387                 },
2388         },
2389 };
2390
2391 static struct clk_branch gcc_ufs_phy_aux_clk = {
2392         .halt_reg = 0x76040,
2393         .halt_check = BRANCH_HALT,
2394         .clkr = {
2395                 .enable_reg = 0x76040,
2396                 .enable_mask = BIT(0),
2397                 .hw.init = &(struct clk_init_data){
2398                         .name = "gcc_ufs_phy_aux_clk",
2399                         .ops = &clk_branch2_ops,
2400                 },
2401         },
2402 };
2403
2404 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2405         .halt_reg = 0x75014,
2406         .halt_check = BRANCH_HALT,
2407         .clkr = {
2408                 .enable_reg = 0x75014,
2409                 .enable_mask = BIT(0),
2410                 .hw.init = &(struct clk_init_data){
2411                         .name = "gcc_ufs_rx_symbol_0_clk",
2412                         .ops = &clk_branch2_ops,
2413                 },
2414         },
2415 };
2416
2417 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2418         .halt_reg = 0x7605c,
2419         .halt_check = BRANCH_HALT,
2420         .clkr = {
2421                 .enable_reg = 0x7605c,
2422                 .enable_mask = BIT(0),
2423                 .hw.init = &(struct clk_init_data){
2424                         .name = "gcc_ufs_rx_symbol_1_clk",
2425                         .ops = &clk_branch2_ops,
2426                 },
2427         },
2428 };
2429
2430 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2431         .halt_reg = 0x75010,
2432         .halt_check = BRANCH_HALT,
2433         .clkr = {
2434                 .enable_reg = 0x75010,
2435                 .enable_mask = BIT(0),
2436                 .hw.init = &(struct clk_init_data){
2437                         .name = "gcc_ufs_tx_symbol_0_clk",
2438                         .ops = &clk_branch2_ops,
2439                 },
2440         },
2441 };
2442
2443 static struct clk_branch gcc_ufs_unipro_core_clk = {
2444         .halt_reg = 0x76008,
2445         .halt_check = BRANCH_HALT,
2446         .clkr = {
2447                 .enable_reg = 0x76008,
2448                 .enable_mask = BIT(0),
2449                 .hw.init = &(struct clk_init_data){
2450                         .name = "gcc_ufs_unipro_core_clk",
2451                         .ops = &clk_branch2_ops,
2452                 },
2453         },
2454 };
2455
2456 static struct clk_branch gcc_usb30_master_clk = {
2457         .halt_reg = 0xf008,
2458         .halt_check = BRANCH_HALT,
2459         .clkr = {
2460                 .enable_reg = 0xf008,
2461                 .enable_mask = BIT(0),
2462                 .hw.init = &(struct clk_init_data){
2463                         .name = "gcc_usb30_master_clk",
2464                         .parent_names = (const char *[]){
2465                                 "usb30_master_clk_src",
2466                         },
2467                         .num_parents = 1,
2468                         .ops = &clk_branch2_ops,
2469                 },
2470         },
2471 };
2472
2473 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2474         .halt_reg = 0xf010,
2475         .halt_check = BRANCH_HALT,
2476         .clkr = {
2477                 .enable_reg = 0xf010,
2478                 .enable_mask = BIT(0),
2479                 .hw.init = &(struct clk_init_data){
2480                         .name = "gcc_usb30_mock_utmi_clk",
2481                         .parent_names = (const char *[]){
2482                                 "usb30_mock_utmi_clk_src",
2483                         },
2484                         .num_parents = 1,
2485                         .ops = &clk_branch2_ops,
2486                 },
2487         },
2488 };
2489
2490 static struct clk_branch gcc_usb30_sleep_clk = {
2491         .halt_reg = 0xf00c,
2492         .halt_check = BRANCH_HALT,
2493         .clkr = {
2494                 .enable_reg = 0xf00c,
2495                 .enable_mask = BIT(0),
2496                 .hw.init = &(struct clk_init_data){
2497                         .name = "gcc_usb30_sleep_clk",
2498                         .ops = &clk_branch2_ops,
2499                 },
2500         },
2501 };
2502
2503 static struct clk_branch gcc_usb3_phy_aux_clk = {
2504         .halt_reg = 0x50000,
2505         .halt_check = BRANCH_HALT,
2506         .clkr = {
2507                 .enable_reg = 0x50000,
2508                 .enable_mask = BIT(0),
2509                 .hw.init = &(struct clk_init_data){
2510                         .name = "gcc_usb3_phy_aux_clk",
2511                         .parent_names = (const char *[]){
2512                                 "usb3_phy_aux_clk_src",
2513                         },
2514                         .num_parents = 1,
2515                         .ops = &clk_branch2_ops,
2516                 },
2517         },
2518 };
2519
2520 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2521         .halt_reg = 0x50004,
2522         .halt_check = BRANCH_HALT,
2523         .clkr = {
2524                 .enable_reg = 0x50004,
2525                 .enable_mask = BIT(0),
2526                 .hw.init = &(struct clk_init_data){
2527                         .name = "gcc_usb3_phy_pipe_clk",
2528                         .ops = &clk_branch2_ops,
2529                 },
2530         },
2531 };
2532
2533 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2534         .halt_reg = 0x6a004,
2535         .halt_check = BRANCH_HALT,
2536         .clkr = {
2537                 .enable_reg = 0x6a004,
2538                 .enable_mask = BIT(0),
2539                 .hw.init = &(struct clk_init_data){
2540                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2541                         .ops = &clk_branch2_ops,
2542                 },
2543         },
2544 };
2545
2546 static struct gdsc pcie_0_gdsc = {
2547         .gdscr = 0x6b004,
2548         .gds_hw_ctrl = 0x0,
2549         .pd = {
2550                 .name = "pcie_0_gdsc",
2551         },
2552         .pwrsts = PWRSTS_OFF_ON,
2553         .flags = VOTABLE,
2554 };
2555
2556 static struct gdsc ufs_gdsc = {
2557         .gdscr = 0x75004,
2558         .gds_hw_ctrl = 0x0,
2559         .pd = {
2560                 .name = "ufs_gdsc",
2561         },
2562         .pwrsts = PWRSTS_OFF_ON,
2563         .flags = VOTABLE,
2564 };
2565
2566 static struct gdsc usb_30_gdsc = {
2567         .gdscr = 0xf004,
2568         .gds_hw_ctrl = 0x0,
2569         .pd = {
2570                 .name = "usb_30_gdsc",
2571         },
2572         .pwrsts = PWRSTS_OFF_ON,
2573         .flags = VOTABLE,
2574 };
2575
2576 static struct clk_regmap *gcc_msm8998_clocks[] = {
2577         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2578         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2579         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2580         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2581         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2582         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2583         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2584         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2585         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2586         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2587         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2588         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2589         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2590         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2591         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2592         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2593         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2594         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2595         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2596         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2597         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2598         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2599         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2600         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2601         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2602         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2603         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2604         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2605         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2606         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2607         [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr,
2608         [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr,
2609         [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr,
2610         [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr,
2611         [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr,
2612         [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
2613         [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
2614         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2615         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2616         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2617         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2618         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2619         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2620         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2621         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2622         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2623         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2624         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2625         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2626         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2627         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
2628         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2629         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2630         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2631         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2632         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2633         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2634         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2635         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2636         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2637         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2638         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2639         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2640         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2641         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2642         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2643         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2644         [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
2645         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2646         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2647         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2648         [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
2649         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2650         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2651         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2652         [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
2653         [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
2654         [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2655         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2656         [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
2657         [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,
2658         [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
2659         [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
2660         [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr,
2661         [GCC_LPASS_AT_CLK] = &gcc_lpass_at_clk.clkr,
2662         [GCC_LPASS_TRIG_CLK] = &gcc_lpass_trig_clk.clkr,
2663         [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2664         [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,
2665         [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr,
2666         [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
2667         [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr,
2668         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2669         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2670         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2671         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2672         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2673         [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
2674         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2675         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2676         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2677         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2678         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2679         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2680         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2681         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2682         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2683         [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
2684         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2685         [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2686         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2687         [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
2688         [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
2689         [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2690         [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2691         [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2692         [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
2693         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2694         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2695         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2696         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2697         [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2698         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2699         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2700         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2701         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2702         [GPLL0] = &gpll0.clkr,
2703         [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2704         [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
2705         [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
2706         [GPLL0_OUT_TEST] = &gpll0_out_test.clkr,
2707         [GPLL1] = &gpll1.clkr,
2708         [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr,
2709         [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
2710         [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr,
2711         [GPLL1_OUT_TEST] = &gpll1_out_test.clkr,
2712         [GPLL2] = &gpll2.clkr,
2713         [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr,
2714         [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
2715         [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr,
2716         [GPLL2_OUT_TEST] = &gpll2_out_test.clkr,
2717         [GPLL3] = &gpll3.clkr,
2718         [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,
2719         [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
2720         [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr,
2721         [GPLL3_OUT_TEST] = &gpll3_out_test.clkr,
2722         [GPLL4] = &gpll4.clkr,
2723         [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr,
2724         [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
2725         [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr,
2726         [GPLL4_OUT_TEST] = &gpll4_out_test.clkr,
2727         [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr,
2728         [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
2729         [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
2730         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2731         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2732         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2733         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2734         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2735         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2736         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2737         [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2738 };
2739
2740 static struct gdsc *gcc_msm8998_gdscs[] = {
2741         [PCIE_0_GDSC] = &pcie_0_gdsc,
2742         [UFS_GDSC] = &ufs_gdsc,
2743         [USB_30_GDSC] = &usb_30_gdsc,
2744 };
2745
2746 static const struct qcom_reset_map gcc_msm8998_resets[] = {
2747         [GCC_BLSP1_QUP1_BCR] = { 0x102400 },
2748         [GCC_BLSP1_QUP2_BCR] = { 0x110592 },
2749         [GCC_BLSP1_QUP3_BCR] = { 0x118784 },
2750         [GCC_BLSP1_QUP4_BCR] = { 0x126976 },
2751         [GCC_BLSP1_QUP5_BCR] = { 0x135168 },
2752         [GCC_BLSP1_QUP6_BCR] = { 0x143360 },
2753         [GCC_BLSP2_QUP1_BCR] = { 0x155648 },
2754         [GCC_BLSP2_QUP2_BCR] = { 0x163840 },
2755         [GCC_BLSP2_QUP3_BCR] = { 0x172032 },
2756         [GCC_BLSP2_QUP4_BCR] = { 0x180224 },
2757         [GCC_BLSP2_QUP5_BCR] = { 0x188416 },
2758         [GCC_BLSP2_QUP6_BCR] = { 0x196608 },
2759         [GCC_PCIE_0_BCR] = { 0x438272 },
2760         [GCC_PDM_BCR] = { 0x208896 },
2761         [GCC_SDCC2_BCR] = { 0x81920 },
2762         [GCC_SDCC4_BCR] = { 0x90112 },
2763         [GCC_TSIF_BCR] = { 0x221184 },
2764         [GCC_UFS_BCR] = { 0x479232 },
2765         [GCC_USB_30_BCR] = { 0x61440 },
2766 };
2767
2768 static const struct regmap_config gcc_msm8998_regmap_config = {
2769         .reg_bits       = 32,
2770         .reg_stride     = 4,
2771         .val_bits       = 32,
2772         .max_register   = 0x8f000,
2773         .fast_io        = true,
2774 };
2775
2776 static const struct qcom_cc_desc gcc_msm8998_desc = {
2777         .config = &gcc_msm8998_regmap_config,
2778         .clks = gcc_msm8998_clocks,
2779         .num_clks = ARRAY_SIZE(gcc_msm8998_clocks),
2780         .resets = gcc_msm8998_resets,
2781         .num_resets = ARRAY_SIZE(gcc_msm8998_resets),
2782         .gdscs = gcc_msm8998_gdscs,
2783         .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),
2784 };
2785
2786 static int gcc_msm8998_probe(struct platform_device *pdev)
2787 {
2788         struct regmap *regmap;
2789         int ret;
2790
2791         regmap = qcom_cc_map(pdev, &gcc_msm8998_desc);
2792         if (IS_ERR(regmap))
2793                 return PTR_ERR(regmap);
2794
2795         /*
2796          * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
2797          * turned off by hardware during certain apps low power modes.
2798          */
2799         ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
2800         if (ret)
2801                 return ret;
2802
2803         return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
2804 }
2805
2806 static const struct of_device_id gcc_msm8998_match_table[] = {
2807         { .compatible = "qcom,gcc-msm8998" },
2808         { }
2809 };
2810 MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table);
2811
2812 static struct platform_driver gcc_msm8998_driver = {
2813         .probe          = gcc_msm8998_probe,
2814         .driver         = {
2815                 .name   = "gcc-msm8998",
2816                 .of_match_table = gcc_msm8998_match_table,
2817         },
2818 };
2819
2820 static int __init gcc_msm8998_init(void)
2821 {
2822         return platform_driver_register(&gcc_msm8998_driver);
2823 }
2824 core_initcall(gcc_msm8998_init);
2825
2826 static void __exit gcc_msm8998_exit(void)
2827 {
2828         platform_driver_unregister(&gcc_msm8998_driver);
2829 }
2830 module_exit(gcc_msm8998_exit);
2831
2832 MODULE_DESCRIPTION("QCOM GCC msm8998 Driver");
2833 MODULE_LICENSE("GPL v2");
2834 MODULE_ALIAS("platform:gcc-msm8998");