drivers/clk/qcom/gcc-ipq806x.c

   1 /*
   2  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
  26 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  27
  28 #include "common.h"
  29 #include "clk-regmap.h"
  30 #include "clk-pll.h"
  31 #include "clk-rcg.h"
  32 #include "clk-branch.h"
  33 #include "clk-hfpll.h"
  34 #include "reset.h"
  35
  36 static struct clk_pll pll0 = {
  37         .l_reg = 0x30c4,
  38         .m_reg = 0x30c8,
  39         .n_reg = 0x30cc,
  40         .config_reg = 0x30d4,
  41         .mode_reg = 0x30c0,
  42         .status_reg = 0x30d8,
  43         .status_bit = 16,
  44         .clkr.hw.init = &(struct clk_init_data){
  45                 .name = "pll0",
  46                 .parent_names = (const char *[]){ "pxo" },
  47                 .num_parents = 1,
  48                 .ops = &clk_pll_ops,
  49         },
  50 };
  51
  52 static struct clk_regmap pll0_vote = {
  53         .enable_reg = 0x34c0,
  54         .enable_mask = BIT(0),
  55         .hw.init = &(struct clk_init_data){
  56                 .name = "pll0_vote",
  57                 .parent_names = (const char *[]){ "pll0" },
  58                 .num_parents = 1,
  59                 .ops = &clk_pll_vote_ops,
  60         },
  61 };
  62
  63 static struct clk_pll pll3 = {
  64         .l_reg = 0x3164,
  65         .m_reg = 0x3168,
  66         .n_reg = 0x316c,
  67         .config_reg = 0x3174,
  68         .mode_reg = 0x3160,
  69         .status_reg = 0x3178,
  70         .status_bit = 16,
  71         .clkr.hw.init = &(struct clk_init_data){
  72                 .name = "pll3",
  73                 .parent_names = (const char *[]){ "pxo" },
  74                 .num_parents = 1,
  75                 .ops = &clk_pll_ops,
  76         },
  77 };
  78
  79 static struct clk_regmap pll4_vote = {
  80         .enable_reg = 0x34c0,
  81         .enable_mask = BIT(4),
  82         .hw.init = &(struct clk_init_data){
  83                 .name = "pll4_vote",
  84                 .parent_names = (const char *[]){ "pll4" },
  85                 .num_parents = 1,
  86                 .ops = &clk_pll_vote_ops,
  87         },
  88 };
  89
  90 static struct clk_pll pll8 = {
  91         .l_reg = 0x3144,
  92         .m_reg = 0x3148,
  93         .n_reg = 0x314c,
  94         .config_reg = 0x3154,
  95         .mode_reg = 0x3140,
  96         .status_reg = 0x3158,
  97         .status_bit = 16,
  98         .clkr.hw.init = &(struct clk_init_data){
  99                 .name = "pll8",
 100                 .parent_names = (const char *[]){ "pxo" },
 101                 .num_parents = 1,
 102                 .ops = &clk_pll_ops,
 103         },
 104 };
 105
 106 static struct clk_regmap pll8_vote = {
 107         .enable_reg = 0x34c0,
 108         .enable_mask = BIT(8),
 109         .hw.init = &(struct clk_init_data){
 110                 .name = "pll8_vote",
 111                 .parent_names = (const char *[]){ "pll8" },
 112                 .num_parents = 1,
 113                 .ops = &clk_pll_vote_ops,
 114         },
 115 };
 116
 117 static struct hfpll_data hfpll0_data = {
 118         .mode_reg = 0x3200,
 119         .l_reg = 0x3208,
 120         .m_reg = 0x320c,
 121         .n_reg = 0x3210,
 122         .config_reg = 0x3204,
 123         .status_reg = 0x321c,
 124         .config_val = 0x7845c665,
 125         .droop_reg = 0x3214,
 126         .droop_val = 0x0108c000,
 127         .min_rate = 600000000UL,
 128         .max_rate = 1800000000UL,
 129 };
 130
 131 static struct clk_hfpll hfpll0 = {
 132         .d = &hfpll0_data,
 133         .clkr.hw.init = &(struct clk_init_data){
 134                 .parent_names = (const char *[]){ "pxo" },
 135                 .num_parents = 1,
 136                 .name = "hfpll0",
 137                 .ops = &clk_ops_hfpll,
 138                 .flags = CLK_IGNORE_UNUSED,
 139         },
 140         .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
 141 };
 142
 143 static struct hfpll_data hfpll1_data = {
 144         .mode_reg = 0x3240,
 145         .l_reg = 0x3248,
 146         .m_reg = 0x324c,
 147         .n_reg = 0x3250,
 148         .config_reg = 0x3244,
 149         .status_reg = 0x325c,
 150         .config_val = 0x7845c665,
 151         .droop_reg = 0x3314,
 152         .droop_val = 0x0108c000,
 153         .min_rate = 600000000UL,
 154         .max_rate = 1800000000UL,
 155 };
 156
 157 static struct clk_hfpll hfpll1 = {
 158         .d = &hfpll1_data,
 159         .clkr.hw.init = &(struct clk_init_data){
 160                 .parent_names = (const char *[]){ "pxo" },
 161                 .num_parents = 1,
 162                 .name = "hfpll1",
 163                 .ops = &clk_ops_hfpll,
 164                 .flags = CLK_IGNORE_UNUSED,
 165         },
 166         .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
 167 };
 168
 169 static struct hfpll_data hfpll_l2_data = {
 170         .mode_reg = 0x3300,
 171         .l_reg = 0x3308,
 172         .m_reg = 0x330c,
 173         .n_reg = 0x3310,
 174         .config_reg = 0x3304,
 175         .status_reg = 0x331c,
 176         .config_val = 0x7845c665,
 177         .droop_reg = 0x3314,
 178         .droop_val = 0x0108c000,
 179         .min_rate = 600000000UL,
 180         .max_rate = 1800000000UL,
 181 };
 182
 183 static struct clk_hfpll hfpll_l2 = {
 184         .d = &hfpll_l2_data,
 185         .clkr.hw.init = &(struct clk_init_data){
 186                 .parent_names = (const char *[]){ "pxo" },
 187                 .num_parents = 1,
 188                 .name = "hfpll_l2",
 189                 .ops = &clk_ops_hfpll,
 190                 .flags = CLK_IGNORE_UNUSED,
 191         },
 192         .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
 193 };
 194
 195 static struct clk_pll pll14 = {
 196         .l_reg = 0x31c4,
 197         .m_reg = 0x31c8,
 198         .n_reg = 0x31cc,
 199         .config_reg = 0x31d4,
 200         .mode_reg = 0x31c0,
 201         .status_reg = 0x31d8,
 202         .status_bit = 16,
 203         .clkr.hw.init = &(struct clk_init_data){
 204                 .name = "pll14",
 205                 .parent_names = (const char *[]){ "pxo" },
 206                 .num_parents = 1,
 207                 .ops = &clk_pll_ops,
 208         },
 209 };
 210
 211 static struct clk_regmap pll14_vote = {
 212         .enable_reg = 0x34c0,
 213         .enable_mask = BIT(14),
 214         .hw.init = &(struct clk_init_data){
 215                 .name = "pll14_vote",
 216                 .parent_names = (const char *[]){ "pll14" },
 217                 .num_parents = 1,
 218                 .ops = &clk_pll_vote_ops,
 219         },
 220 };
 221
 222 #define NSS_PLL_RATE(f, _l, _m, _n, i) \
 223         {  \
 224                 .freq = f,  \
 225                 .l = _l, \
 226                 .m = _m, \
 227                 .n = _n, \
 228                 .ibits = i, \
 229         }
 230
 231 static struct pll_freq_tbl pll18_freq_tbl[] = {
 232         NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
 233         NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
 234 };
 235
 236 static struct clk_pll pll18 = {
 237         .l_reg = 0x31a4,
 238         .m_reg = 0x31a8,
 239         .n_reg = 0x31ac,
 240         .config_reg = 0x31b4,
 241         .mode_reg = 0x31a0,
 242         .status_reg = 0x31b8,
 243         .status_bit = 16,
 244         .post_div_shift = 16,
 245         .post_div_width = 1,
 246         .freq_tbl = pll18_freq_tbl,
 247         .clkr.hw.init = &(struct clk_init_data){
 248                 .name = "pll18",
 249                 .parent_names = (const char *[]){ "pxo" },
 250                 .num_parents = 1,
 251                 .ops = &clk_pll_ops,
 252         },
 253 };
 254
 255 enum {
 256         P_PXO,
 257         P_PLL8,
 258         P_PLL3,
 259         P_PLL0,
 260         P_CXO,
 261         P_PLL14,
 262         P_PLL18,
 263 };
 264
 265 static const struct parent_map gcc_pxo_pll8_map[] = {
 266         { P_PXO, 0 },
 267         { P_PLL8, 3 }
 268 };
 269
 270 static const char * const gcc_pxo_pll8[] = {
 271         "pxo",
 272         "pll8_vote",
 273 };
 274
 275 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
 276         { P_PXO, 0 },
 277         { P_PLL8, 3 },
 278         { P_CXO, 5 }
 279 };
 280
 281 static const char * const gcc_pxo_pll8_cxo[] = {
 282         "pxo",
 283         "pll8_vote",
 284         "cxo",
 285 };
 286
 287 static const struct parent_map gcc_pxo_pll3_map[] = {
 288         { P_PXO, 0 },
 289         { P_PLL3, 1 }
 290 };
 291
 292 static const struct parent_map gcc_pxo_pll3_sata_map[] = {
 293         { P_PXO, 0 },
 294         { P_PLL3, 6 }
 295 };
 296
 297 static const char * const gcc_pxo_pll3[] = {
 298         "pxo",
 299         "pll3",
 300 };
 301
 302 static const struct parent_map gcc_pxo_pll8_pll0[] = {
 303         { P_PXO, 0 },
 304         { P_PLL8, 3 },
 305         { P_PLL0, 2 }
 306 };
 307
 308 static const char * const gcc_pxo_pll8_pll0_map[] = {
 309         "pxo",
 310         "pll8_vote",
 311         "pll0_vote",
 312 };
 313
 314 static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
 315         { P_PXO, 0 },
 316         { P_PLL8, 4 },
 317         { P_PLL0, 2 },
 318         { P_PLL14, 5 },
 319         { P_PLL18, 1 }
 320 };
 321
 322 static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = {
 323         "pxo",
 324         "pll8_vote",
 325         "pll0_vote",
 326         "pll14",
 327         "pll18",
 328 };
 329
 330 static struct freq_tbl clk_tbl_gsbi_uart[] = {
 331         {  1843200, P_PLL8, 2,  6, 625 },
 332         {  3686400, P_PLL8, 2, 12, 625 },
 333         {  7372800, P_PLL8, 2, 24, 625 },
 334         { 14745600, P_PLL8, 2, 48, 625 },
 335         { 16000000, P_PLL8, 4,  1,   6 },
 336         { 24000000, P_PLL8, 4,  1,   4 },
 337         { 32000000, P_PLL8, 4,  1,   3 },
 338         { 40000000, P_PLL8, 1,  5,  48 },
 339         { 46400000, P_PLL8, 1, 29, 240 },
 340         { 48000000, P_PLL8, 4,  1,   2 },
 341         { 51200000, P_PLL8, 1,  2,  15 },
 342         { 56000000, P_PLL8, 1,  7,  48 },
 343         { 58982400, P_PLL8, 1, 96, 625 },
 344         { 64000000, P_PLL8, 2,  1,   3 },
 345         { }
 346 };
 347
 348 static struct clk_rcg gsbi1_uart_src = {
 349         .ns_reg = 0x29d4,
 350         .md_reg = 0x29d0,
 351         .mn = {
 352                 .mnctr_en_bit = 8,
 353                 .mnctr_reset_bit = 7,
 354                 .mnctr_mode_shift = 5,
 355                 .n_val_shift = 16,
 356                 .m_val_shift = 16,
 357                 .width = 16,
 358         },
 359         .p = {
 360                 .pre_div_shift = 3,
 361                 .pre_div_width = 2,
 362         },
 363         .s = {
 364                 .src_sel_shift = 0,
 365                 .parent_map = gcc_pxo_pll8_map,
 366         },
 367         .freq_tbl = clk_tbl_gsbi_uart,
 368         .clkr = {
 369                 .enable_reg = 0x29d4,
 370                 .enable_mask = BIT(11),
 371                 .hw.init = &(struct clk_init_data){
 372                         .name = "gsbi1_uart_src",
 373                         .parent_names = gcc_pxo_pll8,
 374                         .num_parents = 2,
 375                         .ops = &clk_rcg_ops,
 376                         .flags = CLK_SET_PARENT_GATE,
 377                 },
 378         },
 379 };
 380
 381 static struct clk_branch gsbi1_uart_clk = {
 382         .halt_reg = 0x2fcc,
 383         .halt_bit = 12,
 384         .clkr = {
 385                 .enable_reg = 0x29d4,
 386                 .enable_mask = BIT(9),
 387                 .hw.init = &(struct clk_init_data){
 388                         .name = "gsbi1_uart_clk",
 389                         .parent_names = (const char *[]){
 390                                 "gsbi1_uart_src",
 391                         },
 392                         .num_parents = 1,
 393                         .ops = &clk_branch_ops,
 394                         .flags = CLK_SET_RATE_PARENT,
 395                 },
 396         },
 397 };
 398
 399 static struct clk_rcg gsbi2_uart_src = {
 400         .ns_reg = 0x29f4,
 401         .md_reg = 0x29f0,
 402         .mn = {
 403                 .mnctr_en_bit = 8,
 404                 .mnctr_reset_bit = 7,
 405                 .mnctr_mode_shift = 5,
 406                 .n_val_shift = 16,
 407                 .m_val_shift = 16,
 408                 .width = 16,
 409         },
 410         .p = {
 411                 .pre_div_shift = 3,
 412                 .pre_div_width = 2,
 413         },
 414         .s = {
 415                 .src_sel_shift = 0,
 416                 .parent_map = gcc_pxo_pll8_map,
 417         },
 418         .freq_tbl = clk_tbl_gsbi_uart,
 419         .clkr = {
 420                 .enable_reg = 0x29f4,
 421                 .enable_mask = BIT(11),
 422                 .hw.init = &(struct clk_init_data){
 423                         .name = "gsbi2_uart_src",
 424                         .parent_names = gcc_pxo_pll8,
 425                         .num_parents = 2,
 426                         .ops = &clk_rcg_ops,
 427                         .flags = CLK_SET_PARENT_GATE,
 428                 },
 429         },
 430 };
 431
 432 static struct clk_branch gsbi2_uart_clk = {
 433         .halt_reg = 0x2fcc,
 434         .halt_bit = 8,
 435         .clkr = {
 436                 .enable_reg = 0x29f4,
 437                 .enable_mask = BIT(9),
 438                 .hw.init = &(struct clk_init_data){
 439                         .name = "gsbi2_uart_clk",
 440                         .parent_names = (const char *[]){
 441                                 "gsbi2_uart_src",
 442                         },
 443                         .num_parents = 1,
 444                         .ops = &clk_branch_ops,
 445                         .flags = CLK_SET_RATE_PARENT,
 446                 },
 447         },
 448 };
 449
 450 static struct clk_rcg gsbi4_uart_src = {
 451         .ns_reg = 0x2a34,
 452         .md_reg = 0x2a30,
 453         .mn = {
 454                 .mnctr_en_bit = 8,
 455                 .mnctr_reset_bit = 7,
 456                 .mnctr_mode_shift = 5,
 457                 .n_val_shift = 16,
 458                 .m_val_shift = 16,
 459                 .width = 16,
 460         },
 461         .p = {
 462                 .pre_div_shift = 3,
 463                 .pre_div_width = 2,
 464         },
 465         .s = {
 466                 .src_sel_shift = 0,
 467                 .parent_map = gcc_pxo_pll8_map,
 468         },
 469         .freq_tbl = clk_tbl_gsbi_uart,
 470         .clkr = {
 471                 .enable_reg = 0x2a34,
 472                 .enable_mask = BIT(11),
 473                 .hw.init = &(struct clk_init_data){
 474                         .name = "gsbi4_uart_src",
 475                         .parent_names = gcc_pxo_pll8,
 476                         .num_parents = 2,
 477                         .ops = &clk_rcg_ops,
 478                         .flags = CLK_SET_PARENT_GATE,
 479                 },
 480         },
 481 };
 482
 483 static struct clk_branch gsbi4_uart_clk = {
 484         .halt_reg = 0x2fd0,
 485         .halt_bit = 26,
 486         .clkr = {
 487                 .enable_reg = 0x2a34,
 488                 .enable_mask = BIT(9),
 489                 .hw.init = &(struct clk_init_data){
 490                         .name = "gsbi4_uart_clk",
 491                         .parent_names = (const char *[]){
 492                                 "gsbi4_uart_src",
 493                         },
 494                         .num_parents = 1,
 495                         .ops = &clk_branch_ops,
 496                         .flags = CLK_SET_RATE_PARENT,
 497                 },
 498         },
 499 };
 500
 501 static struct clk_rcg gsbi5_uart_src = {
 502         .ns_reg = 0x2a54,
 503         .md_reg = 0x2a50,
 504         .mn = {
 505                 .mnctr_en_bit = 8,
 506                 .mnctr_reset_bit = 7,
 507                 .mnctr_mode_shift = 5,
 508                 .n_val_shift = 16,
 509                 .m_val_shift = 16,
 510                 .width = 16,
 511         },
 512         .p = {
 513                 .pre_div_shift = 3,
 514                 .pre_div_width = 2,
 515         },
 516         .s = {
 517                 .src_sel_shift = 0,
 518                 .parent_map = gcc_pxo_pll8_map,
 519         },
 520         .freq_tbl = clk_tbl_gsbi_uart,
 521         .clkr = {
 522                 .enable_reg = 0x2a54,
 523                 .enable_mask = BIT(11),
 524                 .hw.init = &(struct clk_init_data){
 525                         .name = "gsbi5_uart_src",
 526                         .parent_names = gcc_pxo_pll8,
 527                         .num_parents = 2,
 528                         .ops = &clk_rcg_ops,
 529                         .flags = CLK_SET_PARENT_GATE,
 530                 },
 531         },
 532 };
 533
 534 static struct clk_branch gsbi5_uart_clk = {
 535         .halt_reg = 0x2fd0,
 536         .halt_bit = 22,
 537         .clkr = {
 538                 .enable_reg = 0x2a54,
 539                 .enable_mask = BIT(9),
 540                 .hw.init = &(struct clk_init_data){
 541                         .name = "gsbi5_uart_clk",
 542                         .parent_names = (const char *[]){
 543                                 "gsbi5_uart_src",
 544                         },
 545                         .num_parents = 1,
 546                         .ops = &clk_branch_ops,
 547                         .flags = CLK_SET_RATE_PARENT,
 548                 },
 549         },
 550 };
 551
 552 static struct clk_rcg gsbi6_uart_src = {
 553         .ns_reg = 0x2a74,
 554         .md_reg = 0x2a70,
 555         .mn = {
 556                 .mnctr_en_bit = 8,
 557                 .mnctr_reset_bit = 7,
 558                 .mnctr_mode_shift = 5,
 559                 .n_val_shift = 16,
 560                 .m_val_shift = 16,
 561                 .width = 16,
 562         },
 563         .p = {
 564                 .pre_div_shift = 3,
 565                 .pre_div_width = 2,
 566         },
 567         .s = {
 568                 .src_sel_shift = 0,
 569                 .parent_map = gcc_pxo_pll8_map,
 570         },
 571         .freq_tbl = clk_tbl_gsbi_uart,
 572         .clkr = {
 573                 .enable_reg = 0x2a74,
 574                 .enable_mask = BIT(11),
 575                 .hw.init = &(struct clk_init_data){
 576                         .name = "gsbi6_uart_src",
 577                         .parent_names = gcc_pxo_pll8,
 578                         .num_parents = 2,
 579                         .ops = &clk_rcg_ops,
 580                         .flags = CLK_SET_PARENT_GATE,
 581                 },
 582         },
 583 };
 584
 585 static struct clk_branch gsbi6_uart_clk = {
 586         .halt_reg = 0x2fd0,
 587         .halt_bit = 18,
 588         .clkr = {
 589                 .enable_reg = 0x2a74,
 590                 .enable_mask = BIT(9),
 591                 .hw.init = &(struct clk_init_data){
 592                         .name = "gsbi6_uart_clk",
 593                         .parent_names = (const char *[]){
 594                                 "gsbi6_uart_src",
 595                         },
 596                         .num_parents = 1,
 597                         .ops = &clk_branch_ops,
 598                         .flags = CLK_SET_RATE_PARENT,
 599                 },
 600         },
 601 };
 602
 603 static struct clk_rcg gsbi7_uart_src = {
 604         .ns_reg = 0x2a94,
 605         .md_reg = 0x2a90,
 606         .mn = {
 607                 .mnctr_en_bit = 8,
 608                 .mnctr_reset_bit = 7,
 609                 .mnctr_mode_shift = 5,
 610                 .n_val_shift = 16,
 611                 .m_val_shift = 16,
 612                 .width = 16,
 613         },
 614         .p = {
 615                 .pre_div_shift = 3,
 616                 .pre_div_width = 2,
 617         },
 618         .s = {
 619                 .src_sel_shift = 0,
 620                 .parent_map = gcc_pxo_pll8_map,
 621         },
 622         .freq_tbl = clk_tbl_gsbi_uart,
 623         .clkr = {
 624                 .enable_reg = 0x2a94,
 625                 .enable_mask = BIT(11),
 626                 .hw.init = &(struct clk_init_data){
 627                         .name = "gsbi7_uart_src",
 628                         .parent_names = gcc_pxo_pll8,
 629                         .num_parents = 2,
 630                         .ops = &clk_rcg_ops,
 631                         .flags = CLK_SET_PARENT_GATE,
 632                 },
 633         },
 634 };
 635
 636 static struct clk_branch gsbi7_uart_clk = {
 637         .halt_reg = 0x2fd0,
 638         .halt_bit = 14,
 639         .clkr = {
 640                 .enable_reg = 0x2a94,
 641                 .enable_mask = BIT(9),
 642                 .hw.init = &(struct clk_init_data){
 643                         .name = "gsbi7_uart_clk",
 644                         .parent_names = (const char *[]){
 645                                 "gsbi7_uart_src",
 646                         },
 647                         .num_parents = 1,
 648                         .ops = &clk_branch_ops,
 649                         .flags = CLK_SET_RATE_PARENT,
 650                 },
 651         },
 652 };
 653
 654 static struct freq_tbl clk_tbl_gsbi_qup[] = {
 655         {  1100000, P_PXO,  1, 2, 49 },
 656         {  5400000, P_PXO,  1, 1,  5 },
 657         { 10800000, P_PXO,  1, 2,  5 },
 658         { 15060000, P_PLL8, 1, 2, 51 },
 659         { 24000000, P_PLL8, 4, 1,  4 },
 660         { 25000000, P_PXO,  1, 0,  0 },
 661         { 25600000, P_PLL8, 1, 1, 15 },
 662         { 48000000, P_PLL8, 4, 1,  2 },
 663         { 51200000, P_PLL8, 1, 2, 15 },
 664         { }
 665 };
 666
 667 static struct clk_rcg gsbi1_qup_src = {
 668         .ns_reg = 0x29cc,
 669         .md_reg = 0x29c8,
 670         .mn = {
 671                 .mnctr_en_bit = 8,
 672                 .mnctr_reset_bit = 7,
 673                 .mnctr_mode_shift = 5,
 674                 .n_val_shift = 16,
 675                 .m_val_shift = 16,
 676                 .width = 8,
 677         },
 678         .p = {
 679                 .pre_div_shift = 3,
 680                 .pre_div_width = 2,
 681         },
 682         .s = {
 683                 .src_sel_shift = 0,
 684                 .parent_map = gcc_pxo_pll8_map,
 685         },
 686         .freq_tbl = clk_tbl_gsbi_qup,
 687         .clkr = {
 688                 .enable_reg = 0x29cc,
 689                 .enable_mask = BIT(11),
 690                 .hw.init = &(struct clk_init_data){
 691                         .name = "gsbi1_qup_src",
 692                         .parent_names = gcc_pxo_pll8,
 693                         .num_parents = 2,
 694                         .ops = &clk_rcg_ops,
 695                         .flags = CLK_SET_PARENT_GATE,
 696                 },
 697         },
 698 };
 699
 700 static struct clk_branch gsbi1_qup_clk = {
 701         .halt_reg = 0x2fcc,
 702         .halt_bit = 11,
 703         .clkr = {
 704                 .enable_reg = 0x29cc,
 705                 .enable_mask = BIT(9),
 706                 .hw.init = &(struct clk_init_data){
 707                         .name = "gsbi1_qup_clk",
 708                         .parent_names = (const char *[]){ "gsbi1_qup_src" },
 709                         .num_parents = 1,
 710                         .ops = &clk_branch_ops,
 711                         .flags = CLK_SET_RATE_PARENT,
 712                 },
 713         },
 714 };
 715
 716 static struct clk_rcg gsbi2_qup_src = {
 717         .ns_reg = 0x29ec,
 718         .md_reg = 0x29e8,
 719         .mn = {
 720                 .mnctr_en_bit = 8,
 721                 .mnctr_reset_bit = 7,
 722                 .mnctr_mode_shift = 5,
 723                 .n_val_shift = 16,
 724                 .m_val_shift = 16,
 725                 .width = 8,
 726         },
 727         .p = {
 728                 .pre_div_shift = 3,
 729                 .pre_div_width = 2,
 730         },
 731         .s = {
 732                 .src_sel_shift = 0,
 733                 .parent_map = gcc_pxo_pll8_map,
 734         },
 735         .freq_tbl = clk_tbl_gsbi_qup,
 736         .clkr = {
 737                 .enable_reg = 0x29ec,
 738                 .enable_mask = BIT(11),
 739                 .hw.init = &(struct clk_init_data){
 740                         .name = "gsbi2_qup_src",
 741                         .parent_names = gcc_pxo_pll8,
 742                         .num_parents = 2,
 743                         .ops = &clk_rcg_ops,
 744                         .flags = CLK_SET_PARENT_GATE,
 745                 },
 746         },
 747 };
 748
 749 static struct clk_branch gsbi2_qup_clk = {
 750         .halt_reg = 0x2fcc,
 751         .halt_bit = 6,
 752         .clkr = {
 753                 .enable_reg = 0x29ec,
 754                 .enable_mask = BIT(9),
 755                 .hw.init = &(struct clk_init_data){
 756                         .name = "gsbi2_qup_clk",
 757                         .parent_names = (const char *[]){ "gsbi2_qup_src" },
 758                         .num_parents = 1,
 759                         .ops = &clk_branch_ops,
 760                         .flags = CLK_SET_RATE_PARENT,
 761                 },
 762         },
 763 };
 764
 765 static struct clk_rcg gsbi4_qup_src = {
 766         .ns_reg = 0x2a2c,
 767         .md_reg = 0x2a28,
 768         .mn = {
 769                 .mnctr_en_bit = 8,
 770                 .mnctr_reset_bit = 7,
 771                 .mnctr_mode_shift = 5,
 772                 .n_val_shift = 16,
 773                 .m_val_shift = 16,
 774                 .width = 8,
 775         },
 776         .p = {
 777                 .pre_div_shift = 3,
 778                 .pre_div_width = 2,
 779         },
 780         .s = {
 781                 .src_sel_shift = 0,
 782                 .parent_map = gcc_pxo_pll8_map,
 783         },
 784         .freq_tbl = clk_tbl_gsbi_qup,
 785         .clkr = {
 786                 .enable_reg = 0x2a2c,
 787                 .enable_mask = BIT(11),
 788                 .hw.init = &(struct clk_init_data){
 789                         .name = "gsbi4_qup_src",
 790                         .parent_names = gcc_pxo_pll8,
 791                         .num_parents = 2,
 792                         .ops = &clk_rcg_ops,
 793                         .flags = CLK_SET_PARENT_GATE,
 794                 },
 795         },
 796 };
 797
 798 static struct clk_branch gsbi4_qup_clk = {
 799         .halt_reg = 0x2fd0,
 800         .halt_bit = 24,
 801         .clkr = {
 802                 .enable_reg = 0x2a2c,
 803                 .enable_mask = BIT(9),
 804                 .hw.init = &(struct clk_init_data){
 805                         .name = "gsbi4_qup_clk",
 806                         .parent_names = (const char *[]){ "gsbi4_qup_src" },
 807                         .num_parents = 1,
 808                         .ops = &clk_branch_ops,
 809                         .flags = CLK_SET_RATE_PARENT,
 810                 },
 811         },
 812 };
 813
 814 static struct clk_rcg gsbi5_qup_src = {
 815         .ns_reg = 0x2a4c,
 816         .md_reg = 0x2a48,
 817         .mn = {
 818                 .mnctr_en_bit = 8,
 819                 .mnctr_reset_bit = 7,
 820                 .mnctr_mode_shift = 5,
 821                 .n_val_shift = 16,
 822                 .m_val_shift = 16,
 823                 .width = 8,
 824         },
 825         .p = {
 826                 .pre_div_shift = 3,
 827                 .pre_div_width = 2,
 828         },
 829         .s = {
 830                 .src_sel_shift = 0,
 831                 .parent_map = gcc_pxo_pll8_map,
 832         },
 833         .freq_tbl = clk_tbl_gsbi_qup,
 834         .clkr = {
 835                 .enable_reg = 0x2a4c,
 836                 .enable_mask = BIT(11),
 837                 .hw.init = &(struct clk_init_data){
 838                         .name = "gsbi5_qup_src",
 839                         .parent_names = gcc_pxo_pll8,
 840                         .num_parents = 2,
 841                         .ops = &clk_rcg_ops,
 842                         .flags = CLK_SET_PARENT_GATE,
 843                 },
 844         },
 845 };
 846
 847 static struct clk_branch gsbi5_qup_clk = {
 848         .halt_reg = 0x2fd0,
 849         .halt_bit = 20,
 850         .clkr = {
 851                 .enable_reg = 0x2a4c,
 852                 .enable_mask = BIT(9),
 853                 .hw.init = &(struct clk_init_data){
 854                         .name = "gsbi5_qup_clk",
 855                         .parent_names = (const char *[]){ "gsbi5_qup_src" },
 856                         .num_parents = 1,
 857                         .ops = &clk_branch_ops,
 858                         .flags = CLK_SET_RATE_PARENT,
 859                 },
 860         },
 861 };
 862
 863 static struct clk_rcg gsbi6_qup_src = {
 864         .ns_reg = 0x2a6c,
 865         .md_reg = 0x2a68,
 866         .mn = {
 867                 .mnctr_en_bit = 8,
 868                 .mnctr_reset_bit = 7,
 869                 .mnctr_mode_shift = 5,
 870                 .n_val_shift = 16,
 871                 .m_val_shift = 16,
 872                 .width = 8,
 873         },
 874         .p = {
 875                 .pre_div_shift = 3,
 876                 .pre_div_width = 2,
 877         },
 878         .s = {
 879                 .src_sel_shift = 0,
 880                 .parent_map = gcc_pxo_pll8_map,
 881         },
 882         .freq_tbl = clk_tbl_gsbi_qup,
 883         .clkr = {
 884                 .enable_reg = 0x2a6c,
 885                 .enable_mask = BIT(11),
 886                 .hw.init = &(struct clk_init_data){
 887                         .name = "gsbi6_qup_src",
 888                         .parent_names = gcc_pxo_pll8,
 889                         .num_parents = 2,
 890                         .ops = &clk_rcg_ops,
 891                         .flags = CLK_SET_PARENT_GATE,
 892                 },
 893         },
 894 };
 895
 896 static struct clk_branch gsbi6_qup_clk = {
 897         .halt_reg = 0x2fd0,
 898         .halt_bit = 16,
 899         .clkr = {
 900                 .enable_reg = 0x2a6c,
 901                 .enable_mask = BIT(9),
 902                 .hw.init = &(struct clk_init_data){
 903                         .name = "gsbi6_qup_clk",
 904                         .parent_names = (const char *[]){ "gsbi6_qup_src" },
 905                         .num_parents = 1,
 906                         .ops = &clk_branch_ops,
 907                         .flags = CLK_SET_RATE_PARENT,
 908                 },
 909         },
 910 };
 911
 912 static struct clk_rcg gsbi7_qup_src = {
 913         .ns_reg = 0x2a8c,
 914         .md_reg = 0x2a88,
 915         .mn = {
 916                 .mnctr_en_bit = 8,
 917                 .mnctr_reset_bit = 7,
 918                 .mnctr_mode_shift = 5,
 919                 .n_val_shift = 16,
 920                 .m_val_shift = 16,
 921                 .width = 8,
 922         },
 923         .p = {
 924                 .pre_div_shift = 3,
 925                 .pre_div_width = 2,
 926         },
 927         .s = {
 928                 .src_sel_shift = 0,
 929                 .parent_map = gcc_pxo_pll8_map,
 930         },
 931         .freq_tbl = clk_tbl_gsbi_qup,
 932         .clkr = {
 933                 .enable_reg = 0x2a8c,
 934                 .enable_mask = BIT(11),
 935                 .hw.init = &(struct clk_init_data){
 936                         .name = "gsbi7_qup_src",
 937                         .parent_names = gcc_pxo_pll8,
 938                         .num_parents = 2,
 939                         .ops = &clk_rcg_ops,
 940                         .flags = CLK_SET_PARENT_GATE,
 941                 },
 942         },
 943 };
 944
 945 static struct clk_branch gsbi7_qup_clk = {
 946         .halt_reg = 0x2fd0,
 947         .halt_bit = 12,
 948         .clkr = {
 949                 .enable_reg = 0x2a8c,
 950                 .enable_mask = BIT(9),
 951                 .hw.init = &(struct clk_init_data){
 952                         .name = "gsbi7_qup_clk",
 953                         .parent_names = (const char *[]){ "gsbi7_qup_src" },
 954                         .num_parents = 1,
 955                         .ops = &clk_branch_ops,
 956                         .flags = CLK_SET_RATE_PARENT,
 957                 },
 958         },
 959 };
 960
 961 static struct clk_branch gsbi1_h_clk = {
 962         .hwcg_reg = 0x29c0,
 963         .hwcg_bit = 6,
 964         .halt_reg = 0x2fcc,
 965         .halt_bit = 13,
 966         .clkr = {
 967                 .enable_reg = 0x29c0,
 968                 .enable_mask = BIT(4),
 969                 .hw.init = &(struct clk_init_data){
 970                         .name = "gsbi1_h_clk",
 971                         .ops = &clk_branch_ops,
 972                 },
 973         },
 974 };
 975
 976 static struct clk_branch gsbi2_h_clk = {
 977         .hwcg_reg = 0x29e0,
 978         .hwcg_bit = 6,
 979         .halt_reg = 0x2fcc,
 980         .halt_bit = 9,
 981         .clkr = {
 982                 .enable_reg = 0x29e0,
 983                 .enable_mask = BIT(4),
 984                 .hw.init = &(struct clk_init_data){
 985                         .name = "gsbi2_h_clk",
 986                         .ops = &clk_branch_ops,
 987                 },
 988         },
 989 };
 990
 991 static struct clk_branch gsbi4_h_clk = {
 992         .hwcg_reg = 0x2a20,
 993         .hwcg_bit = 6,
 994         .halt_reg = 0x2fd0,
 995         .halt_bit = 27,
 996         .clkr = {
 997                 .enable_reg = 0x2a20,
 998                 .enable_mask = BIT(4),
 999                 .hw.init = &(struct clk_init_data){
1000                         .name = "gsbi4_h_clk",
1001                         .ops = &clk_branch_ops,
1002                 },
1003         },
1004 };
1005
1006 static struct clk_branch gsbi5_h_clk = {
1007         .hwcg_reg = 0x2a40,
1008         .hwcg_bit = 6,
1009         .halt_reg = 0x2fd0,
1010         .halt_bit = 23,
1011         .clkr = {
1012                 .enable_reg = 0x2a40,
1013                 .enable_mask = BIT(4),
1014                 .hw.init = &(struct clk_init_data){
1015                         .name = "gsbi5_h_clk",
1016                         .ops = &clk_branch_ops,
1017                 },
1018         },
1019 };
1020
1021 static struct clk_branch gsbi6_h_clk = {
1022         .hwcg_reg = 0x2a60,
1023         .hwcg_bit = 6,
1024         .halt_reg = 0x2fd0,
1025         .halt_bit = 19,
1026         .clkr = {
1027                 .enable_reg = 0x2a60,
1028                 .enable_mask = BIT(4),
1029                 .hw.init = &(struct clk_init_data){
1030                         .name = "gsbi6_h_clk",
1031                         .ops = &clk_branch_ops,
1032                 },
1033         },
1034 };
1035
1036 static struct clk_branch gsbi7_h_clk = {
1037         .hwcg_reg = 0x2a80,
1038         .hwcg_bit = 6,
1039         .halt_reg = 0x2fd0,
1040         .halt_bit = 15,
1041         .clkr = {
1042                 .enable_reg = 0x2a80,
1043                 .enable_mask = BIT(4),
1044                 .hw.init = &(struct clk_init_data){
1045                         .name = "gsbi7_h_clk",
1046                         .ops = &clk_branch_ops,
1047                 },
1048         },
1049 };
1050
1051 static const struct freq_tbl clk_tbl_gp[] = {
1052         { 12500000, P_PXO,  2, 0, 0 },
1053         { 25000000, P_PXO,  1, 0, 0 },
1054         { 64000000, P_PLL8, 2, 1, 3 },
1055         { 76800000, P_PLL8, 1, 1, 5 },
1056         { 96000000, P_PLL8, 4, 0, 0 },
1057         { 128000000, P_PLL8, 3, 0, 0 },
1058         { 192000000, P_PLL8, 2, 0, 0 },
1059         { }
1060 };
1061
1062 static struct clk_rcg gp0_src = {
1063         .ns_reg = 0x2d24,
1064         .md_reg = 0x2d00,
1065         .mn = {
1066                 .mnctr_en_bit = 8,
1067                 .mnctr_reset_bit = 7,
1068                 .mnctr_mode_shift = 5,
1069                 .n_val_shift = 16,
1070                 .m_val_shift = 16,
1071                 .width = 8,
1072         },
1073         .p = {
1074                 .pre_div_shift = 3,
1075                 .pre_div_width = 2,
1076         },
1077         .s = {
1078                 .src_sel_shift = 0,
1079                 .parent_map = gcc_pxo_pll8_cxo_map,
1080         },
1081         .freq_tbl = clk_tbl_gp,
1082         .clkr = {
1083                 .enable_reg = 0x2d24,
1084                 .enable_mask = BIT(11),
1085                 .hw.init = &(struct clk_init_data){
1086                         .name = "gp0_src",
1087                         .parent_names = gcc_pxo_pll8_cxo,
1088                         .num_parents = 3,
1089                         .ops = &clk_rcg_ops,
1090                         .flags = CLK_SET_PARENT_GATE,
1091                 },
1092         }
1093 };
1094
1095 static struct clk_branch gp0_clk = {
1096         .halt_reg = 0x2fd8,
1097         .halt_bit = 7,
1098         .clkr = {
1099                 .enable_reg = 0x2d24,
1100                 .enable_mask = BIT(9),
1101                 .hw.init = &(struct clk_init_data){
1102                         .name = "gp0_clk",
1103                         .parent_names = (const char *[]){ "gp0_src" },
1104                         .num_parents = 1,
1105                         .ops = &clk_branch_ops,
1106                         .flags = CLK_SET_RATE_PARENT,
1107                 },
1108         },
1109 };
1110
1111 static struct clk_rcg gp1_src = {
1112         .ns_reg = 0x2d44,
1113         .md_reg = 0x2d40,
1114         .mn = {
1115                 .mnctr_en_bit = 8,
1116                 .mnctr_reset_bit = 7,
1117                 .mnctr_mode_shift = 5,
1118                 .n_val_shift = 16,
1119                 .m_val_shift = 16,
1120                 .width = 8,
1121         },
1122         .p = {
1123                 .pre_div_shift = 3,
1124                 .pre_div_width = 2,
1125         },
1126         .s = {
1127                 .src_sel_shift = 0,
1128                 .parent_map = gcc_pxo_pll8_cxo_map,
1129         },
1130         .freq_tbl = clk_tbl_gp,
1131         .clkr = {
1132                 .enable_reg = 0x2d44,
1133                 .enable_mask = BIT(11),
1134                 .hw.init = &(struct clk_init_data){
1135                         .name = "gp1_src",
1136                         .parent_names = gcc_pxo_pll8_cxo,
1137                         .num_parents = 3,
1138                         .ops = &clk_rcg_ops,
1139                         .flags = CLK_SET_RATE_GATE,
1140                 },
1141         }
1142 };
1143
1144 static struct clk_branch gp1_clk = {
1145         .halt_reg = 0x2fd8,
1146         .halt_bit = 6,
1147         .clkr = {
1148                 .enable_reg = 0x2d44,
1149                 .enable_mask = BIT(9),
1150                 .hw.init = &(struct clk_init_data){
1151                         .name = "gp1_clk",
1152                         .parent_names = (const char *[]){ "gp1_src" },
1153                         .num_parents = 1,
1154                         .ops = &clk_branch_ops,
1155                         .flags = CLK_SET_RATE_PARENT,
1156                 },
1157         },
1158 };
1159
1160 static struct clk_rcg gp2_src = {
1161         .ns_reg = 0x2d64,
1162         .md_reg = 0x2d60,
1163         .mn = {
1164                 .mnctr_en_bit = 8,
1165                 .mnctr_reset_bit = 7,
1166                 .mnctr_mode_shift = 5,
1167                 .n_val_shift = 16,
1168                 .m_val_shift = 16,
1169                 .width = 8,
1170         },
1171         .p = {
1172                 .pre_div_shift = 3,
1173                 .pre_div_width = 2,
1174         },
1175         .s = {
1176                 .src_sel_shift = 0,
1177                 .parent_map = gcc_pxo_pll8_cxo_map,
1178         },
1179         .freq_tbl = clk_tbl_gp,
1180         .clkr = {
1181                 .enable_reg = 0x2d64,
1182                 .enable_mask = BIT(11),
1183                 .hw.init = &(struct clk_init_data){
1184                         .name = "gp2_src",
1185                         .parent_names = gcc_pxo_pll8_cxo,
1186                         .num_parents = 3,
1187                         .ops = &clk_rcg_ops,
1188                         .flags = CLK_SET_RATE_GATE,
1189                 },
1190         }
1191 };
1192
1193 static struct clk_branch gp2_clk = {
1194         .halt_reg = 0x2fd8,
1195         .halt_bit = 5,
1196         .clkr = {
1197                 .enable_reg = 0x2d64,
1198                 .enable_mask = BIT(9),
1199                 .hw.init = &(struct clk_init_data){
1200                         .name = "gp2_clk",
1201                         .parent_names = (const char *[]){ "gp2_src" },
1202                         .num_parents = 1,
1203                         .ops = &clk_branch_ops,
1204                         .flags = CLK_SET_RATE_PARENT,
1205                 },
1206         },
1207 };
1208
1209 static struct clk_branch pmem_clk = {
1210         .hwcg_reg = 0x25a0,
1211         .hwcg_bit = 6,
1212         .halt_reg = 0x2fc8,
1213         .halt_bit = 20,
1214         .clkr = {
1215                 .enable_reg = 0x25a0,
1216                 .enable_mask = BIT(4),
1217                 .hw.init = &(struct clk_init_data){
1218                         .name = "pmem_clk",
1219                         .ops = &clk_branch_ops,
1220                 },
1221         },
1222 };
1223
1224 static struct clk_rcg prng_src = {
1225         .ns_reg = 0x2e80,
1226         .p = {
1227                 .pre_div_shift = 3,
1228                 .pre_div_width = 4,
1229         },
1230         .s = {
1231                 .src_sel_shift = 0,
1232                 .parent_map = gcc_pxo_pll8_map,
1233         },
1234         .clkr = {
1235                 .hw.init = &(struct clk_init_data){
1236                         .name = "prng_src",
1237                         .parent_names = gcc_pxo_pll8,
1238                         .num_parents = 2,
1239                         .ops = &clk_rcg_ops,
1240                 },
1241         },
1242 };
1243
1244 static struct clk_branch prng_clk = {
1245         .halt_reg = 0x2fd8,
1246         .halt_check = BRANCH_HALT_VOTED,
1247         .halt_bit = 10,
1248         .clkr = {
1249                 .enable_reg = 0x3080,
1250                 .enable_mask = BIT(10),
1251                 .hw.init = &(struct clk_init_data){
1252                         .name = "prng_clk",
1253                         .parent_names = (const char *[]){ "prng_src" },
1254                         .num_parents = 1,
1255                         .ops = &clk_branch_ops,
1256                 },
1257         },
1258 };
1259
1260 static const struct freq_tbl clk_tbl_sdc[] = {
1261         {    200000, P_PXO,   2, 2, 125 },
1262         {    400000, P_PLL8,  4, 1, 240 },
1263         {  16000000, P_PLL8,  4, 1,   6 },
1264         {  17070000, P_PLL8,  1, 2,  45 },
1265         {  20210000, P_PLL8,  1, 1,  19 },
1266         {  24000000, P_PLL8,  4, 1,   4 },
1267         {  48000000, P_PLL8,  4, 1,   2 },
1268         {  64000000, P_PLL8,  3, 1,   2 },
1269         {  96000000, P_PLL8,  4, 0,   0 },
1270         { 192000000, P_PLL8,  2, 0,   0 },
1271         { }
1272 };
1273
1274 static struct clk_rcg sdc1_src = {
1275         .ns_reg = 0x282c,
1276         .md_reg = 0x2828,
1277         .mn = {
1278                 .mnctr_en_bit = 8,
1279                 .mnctr_reset_bit = 7,
1280                 .mnctr_mode_shift = 5,
1281                 .n_val_shift = 16,
1282                 .m_val_shift = 16,
1283                 .width = 8,
1284         },
1285         .p = {
1286                 .pre_div_shift = 3,
1287                 .pre_div_width = 2,
1288         },
1289         .s = {
1290                 .src_sel_shift = 0,
1291                 .parent_map = gcc_pxo_pll8_map,
1292         },
1293         .freq_tbl = clk_tbl_sdc,
1294         .clkr = {
1295                 .enable_reg = 0x282c,
1296                 .enable_mask = BIT(11),
1297                 .hw.init = &(struct clk_init_data){
1298                         .name = "sdc1_src",
1299                         .parent_names = gcc_pxo_pll8,
1300                         .num_parents = 2,
1301                         .ops = &clk_rcg_ops,
1302                 },
1303         }
1304 };
1305
1306 static struct clk_branch sdc1_clk = {
1307         .halt_reg = 0x2fc8,
1308         .halt_bit = 6,
1309         .clkr = {
1310                 .enable_reg = 0x282c,
1311                 .enable_mask = BIT(9),
1312                 .hw.init = &(struct clk_init_data){
1313                         .name = "sdc1_clk",
1314                         .parent_names = (const char *[]){ "sdc1_src" },
1315                         .num_parents = 1,
1316                         .ops = &clk_branch_ops,
1317                         .flags = CLK_SET_RATE_PARENT,
1318                 },
1319         },
1320 };
1321
1322 static struct clk_rcg sdc3_src = {
1323         .ns_reg = 0x286c,
1324         .md_reg = 0x2868,
1325         .mn = {
1326                 .mnctr_en_bit = 8,
1327                 .mnctr_reset_bit = 7,
1328                 .mnctr_mode_shift = 5,
1329                 .n_val_shift = 16,
1330                 .m_val_shift = 16,
1331                 .width = 8,
1332         },
1333         .p = {
1334                 .pre_div_shift = 3,
1335                 .pre_div_width = 2,
1336         },
1337         .s = {
1338                 .src_sel_shift = 0,
1339                 .parent_map = gcc_pxo_pll8_map,
1340         },
1341         .freq_tbl = clk_tbl_sdc,
1342         .clkr = {
1343                 .enable_reg = 0x286c,
1344                 .enable_mask = BIT(11),
1345                 .hw.init = &(struct clk_init_data){
1346                         .name = "sdc3_src",
1347                         .parent_names = gcc_pxo_pll8,
1348                         .num_parents = 2,
1349                         .ops = &clk_rcg_ops,
1350                 },
1351         }
1352 };
1353
1354 static struct clk_branch sdc3_clk = {
1355         .halt_reg = 0x2fc8,
1356         .halt_bit = 4,
1357         .clkr = {
1358                 .enable_reg = 0x286c,
1359                 .enable_mask = BIT(9),
1360                 .hw.init = &(struct clk_init_data){
1361                         .name = "sdc3_clk",
1362                         .parent_names = (const char *[]){ "sdc3_src" },
1363                         .num_parents = 1,
1364                         .ops = &clk_branch_ops,
1365                         .flags = CLK_SET_RATE_PARENT,
1366                 },
1367         },
1368 };
1369
1370 static struct clk_branch sdc1_h_clk = {
1371         .hwcg_reg = 0x2820,
1372         .hwcg_bit = 6,
1373         .halt_reg = 0x2fc8,
1374         .halt_bit = 11,
1375         .clkr = {
1376                 .enable_reg = 0x2820,
1377                 .enable_mask = BIT(4),
1378                 .hw.init = &(struct clk_init_data){
1379                         .name = "sdc1_h_clk",
1380                         .ops = &clk_branch_ops,
1381                 },
1382         },
1383 };
1384
1385 static struct clk_branch sdc3_h_clk = {
1386         .hwcg_reg = 0x2860,
1387         .hwcg_bit = 6,
1388         .halt_reg = 0x2fc8,
1389         .halt_bit = 9,
1390         .clkr = {
1391                 .enable_reg = 0x2860,
1392                 .enable_mask = BIT(4),
1393                 .hw.init = &(struct clk_init_data){
1394                         .name = "sdc3_h_clk",
1395                         .ops = &clk_branch_ops,
1396                 },
1397         },
1398 };
1399
1400 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1401         { 105000, P_PXO,  1, 1, 256 },
1402         { }
1403 };
1404
1405 static struct clk_rcg tsif_ref_src = {
1406         .ns_reg = 0x2710,
1407         .md_reg = 0x270c,
1408         .mn = {
1409                 .mnctr_en_bit = 8,
1410                 .mnctr_reset_bit = 7,
1411                 .mnctr_mode_shift = 5,
1412                 .n_val_shift = 16,
1413                 .m_val_shift = 16,
1414                 .width = 16,
1415         },
1416         .p = {
1417                 .pre_div_shift = 3,
1418                 .pre_div_width = 2,
1419         },
1420         .s = {
1421                 .src_sel_shift = 0,
1422                 .parent_map = gcc_pxo_pll8_map,
1423         },
1424         .freq_tbl = clk_tbl_tsif_ref,
1425         .clkr = {
1426                 .enable_reg = 0x2710,
1427                 .enable_mask = BIT(11),
1428                 .hw.init = &(struct clk_init_data){
1429                         .name = "tsif_ref_src",
1430                         .parent_names = gcc_pxo_pll8,
1431                         .num_parents = 2,
1432                         .ops = &clk_rcg_ops,
1433                 },
1434         }
1435 };
1436
1437 static struct clk_branch tsif_ref_clk = {
1438         .halt_reg = 0x2fd4,
1439         .halt_bit = 5,
1440         .clkr = {
1441                 .enable_reg = 0x2710,
1442                 .enable_mask = BIT(9),
1443                 .hw.init = &(struct clk_init_data){
1444                         .name = "tsif_ref_clk",
1445                         .parent_names = (const char *[]){ "tsif_ref_src" },
1446                         .num_parents = 1,
1447                         .ops = &clk_branch_ops,
1448                         .flags = CLK_SET_RATE_PARENT,
1449                 },
1450         },
1451 };
1452
1453 static struct clk_branch tsif_h_clk = {
1454         .hwcg_reg = 0x2700,
1455         .hwcg_bit = 6,
1456         .halt_reg = 0x2fd4,
1457         .halt_bit = 7,
1458         .clkr = {
1459                 .enable_reg = 0x2700,
1460                 .enable_mask = BIT(4),
1461                 .hw.init = &(struct clk_init_data){
1462                         .name = "tsif_h_clk",
1463                         .ops = &clk_branch_ops,
1464                 },
1465         },
1466 };
1467
1468 static struct clk_branch dma_bam_h_clk = {
1469         .hwcg_reg = 0x25c0,
1470         .hwcg_bit = 6,
1471         .halt_reg = 0x2fc8,
1472         .halt_bit = 12,
1473         .clkr = {
1474                 .enable_reg = 0x25c0,
1475                 .enable_mask = BIT(4),
1476                 .hw.init = &(struct clk_init_data){
1477                         .name = "dma_bam_h_clk",
1478                         .ops = &clk_branch_ops,
1479                 },
1480         },
1481 };
1482
1483 static struct clk_branch adm0_clk = {
1484         .halt_reg = 0x2fdc,
1485         .halt_check = BRANCH_HALT_VOTED,
1486         .halt_bit = 12,
1487         .clkr = {
1488                 .enable_reg = 0x3080,
1489                 .enable_mask = BIT(2),
1490                 .hw.init = &(struct clk_init_data){
1491                         .name = "adm0_clk",
1492                         .ops = &clk_branch_ops,
1493                 },
1494         },
1495 };
1496
1497 static struct clk_branch adm0_pbus_clk = {
1498         .hwcg_reg = 0x2208,
1499         .hwcg_bit = 6,
1500         .halt_reg = 0x2fdc,
1501         .halt_check = BRANCH_HALT_VOTED,
1502         .halt_bit = 11,
1503         .clkr = {
1504                 .enable_reg = 0x3080,
1505                 .enable_mask = BIT(3),
1506                 .hw.init = &(struct clk_init_data){
1507                         .name = "adm0_pbus_clk",
1508                         .ops = &clk_branch_ops,
1509                 },
1510         },
1511 };
1512
1513 static struct clk_branch pmic_arb0_h_clk = {
1514         .halt_reg = 0x2fd8,
1515         .halt_check = BRANCH_HALT_VOTED,
1516         .halt_bit = 22,
1517         .clkr = {
1518                 .enable_reg = 0x3080,
1519                 .enable_mask = BIT(8),
1520                 .hw.init = &(struct clk_init_data){
1521                         .name = "pmic_arb0_h_clk",
1522                         .ops = &clk_branch_ops,
1523                 },
1524         },
1525 };
1526
1527 static struct clk_branch pmic_arb1_h_clk = {
1528         .halt_reg = 0x2fd8,
1529         .halt_check = BRANCH_HALT_VOTED,
1530         .halt_bit = 21,
1531         .clkr = {
1532                 .enable_reg = 0x3080,
1533                 .enable_mask = BIT(9),
1534                 .hw.init = &(struct clk_init_data){
1535                         .name = "pmic_arb1_h_clk",
1536                         .ops = &clk_branch_ops,
1537                 },
1538         },
1539 };
1540
1541 static struct clk_branch pmic_ssbi2_clk = {
1542         .halt_reg = 0x2fd8,
1543         .halt_check = BRANCH_HALT_VOTED,
1544         .halt_bit = 23,
1545         .clkr = {
1546                 .enable_reg = 0x3080,
1547                 .enable_mask = BIT(7),
1548                 .hw.init = &(struct clk_init_data){
1549                         .name = "pmic_ssbi2_clk",
1550                         .ops = &clk_branch_ops,
1551                 },
1552         },
1553 };
1554
1555 static struct clk_branch rpm_msg_ram_h_clk = {
1556         .hwcg_reg = 0x27e0,
1557         .hwcg_bit = 6,
1558         .halt_reg = 0x2fd8,
1559         .halt_check = BRANCH_HALT_VOTED,
1560         .halt_bit = 12,
1561         .clkr = {
1562                 .enable_reg = 0x3080,
1563                 .enable_mask = BIT(6),
1564                 .hw.init = &(struct clk_init_data){
1565                         .name = "rpm_msg_ram_h_clk",
1566                         .ops = &clk_branch_ops,
1567                 },
1568         },
1569 };
1570
1571 static const struct freq_tbl clk_tbl_pcie_ref[] = {
1572         { 100000000, P_PLL3,  12, 0, 0 },
1573         { }
1574 };
1575
1576 static struct clk_rcg pcie_ref_src = {
1577         .ns_reg = 0x3860,
1578         .p = {
1579                 .pre_div_shift = 3,
1580                 .pre_div_width = 4,
1581         },
1582         .s = {
1583                 .src_sel_shift = 0,
1584                 .parent_map = gcc_pxo_pll3_map,
1585         },
1586         .freq_tbl = clk_tbl_pcie_ref,
1587         .clkr = {
1588                 .enable_reg = 0x3860,
1589                 .enable_mask = BIT(11),
1590                 .hw.init = &(struct clk_init_data){
1591                         .name = "pcie_ref_src",
1592                         .parent_names = gcc_pxo_pll3,
1593                         .num_parents = 2,
1594                         .ops = &clk_rcg_ops,
1595                         .flags = CLK_SET_RATE_GATE,
1596                 },
1597         },
1598 };
1599
1600 static struct clk_branch pcie_ref_src_clk = {
1601         .halt_reg = 0x2fdc,
1602         .halt_bit = 30,
1603         .clkr = {
1604                 .enable_reg = 0x3860,
1605                 .enable_mask = BIT(9),
1606                 .hw.init = &(struct clk_init_data){
1607                         .name = "pcie_ref_src_clk",
1608                         .parent_names = (const char *[]){ "pcie_ref_src" },
1609                         .num_parents = 1,
1610                         .ops = &clk_branch_ops,
1611                         .flags = CLK_SET_RATE_PARENT,
1612                 },
1613         },
1614 };
1615
1616 static struct clk_branch pcie_a_clk = {
1617         .halt_reg = 0x2fc0,
1618         .halt_bit = 13,
1619         .clkr = {
1620                 .enable_reg = 0x22c0,
1621                 .enable_mask = BIT(4),
1622                 .hw.init = &(struct clk_init_data){
1623                         .name = "pcie_a_clk",
1624                         .ops = &clk_branch_ops,
1625                 },
1626         },
1627 };
1628
1629 static struct clk_branch pcie_aux_clk = {
1630         .halt_reg = 0x2fdc,
1631         .halt_bit = 31,
1632         .clkr = {
1633                 .enable_reg = 0x22c8,
1634                 .enable_mask = BIT(4),
1635                 .hw.init = &(struct clk_init_data){
1636                         .name = "pcie_aux_clk",
1637                         .ops = &clk_branch_ops,
1638                 },
1639         },
1640 };
1641
1642 static struct clk_branch pcie_h_clk = {
1643         .halt_reg = 0x2fd4,
1644         .halt_bit = 8,
1645         .clkr = {
1646                 .enable_reg = 0x22cc,
1647                 .enable_mask = BIT(4),
1648                 .hw.init = &(struct clk_init_data){
1649                         .name = "pcie_h_clk",
1650                         .ops = &clk_branch_ops,
1651                 },
1652         },
1653 };
1654
1655 static struct clk_branch pcie_phy_clk = {
1656         .halt_reg = 0x2fdc,
1657         .halt_bit = 29,
1658         .clkr = {
1659                 .enable_reg = 0x22d0,
1660                 .enable_mask = BIT(4),
1661                 .hw.init = &(struct clk_init_data){
1662                         .name = "pcie_phy_clk",
1663                         .ops = &clk_branch_ops,
1664                 },
1665         },
1666 };
1667
1668 static struct clk_rcg pcie1_ref_src = {
1669         .ns_reg = 0x3aa0,
1670         .p = {
1671                 .pre_div_shift = 3,
1672                 .pre_div_width = 4,
1673         },
1674         .s = {
1675                 .src_sel_shift = 0,
1676                 .parent_map = gcc_pxo_pll3_map,
1677         },
1678         .freq_tbl = clk_tbl_pcie_ref,
1679         .clkr = {
1680                 .enable_reg = 0x3aa0,
1681                 .enable_mask = BIT(11),
1682                 .hw.init = &(struct clk_init_data){
1683                         .name = "pcie1_ref_src",
1684                         .parent_names = gcc_pxo_pll3,
1685                         .num_parents = 2,
1686                         .ops = &clk_rcg_ops,
1687                         .flags = CLK_SET_RATE_GATE,
1688                 },
1689         },
1690 };
1691
1692 static struct clk_branch pcie1_ref_src_clk = {
1693         .halt_reg = 0x2fdc,
1694         .halt_bit = 27,
1695         .clkr = {
1696                 .enable_reg = 0x3aa0,
1697                 .enable_mask = BIT(9),
1698                 .hw.init = &(struct clk_init_data){
1699                         .name = "pcie1_ref_src_clk",
1700                         .parent_names = (const char *[]){ "pcie1_ref_src" },
1701                         .num_parents = 1,
1702                         .ops = &clk_branch_ops,
1703                         .flags = CLK_SET_RATE_PARENT,
1704                 },
1705         },
1706 };
1707
1708 static struct clk_branch pcie1_a_clk = {
1709         .halt_reg = 0x2fc0,
1710         .halt_bit = 10,
1711         .clkr = {
1712                 .enable_reg = 0x3a80,
1713                 .enable_mask = BIT(4),
1714                 .hw.init = &(struct clk_init_data){
1715                         .name = "pcie1_a_clk",
1716                         .ops = &clk_branch_ops,
1717                 },
1718         },
1719 };
1720
1721 static struct clk_branch pcie1_aux_clk = {
1722         .halt_reg = 0x2fdc,
1723         .halt_bit = 28,
1724         .clkr = {
1725                 .enable_reg = 0x3a88,
1726                 .enable_mask = BIT(4),
1727                 .hw.init = &(struct clk_init_data){
1728                         .name = "pcie1_aux_clk",
1729                         .ops = &clk_branch_ops,
1730                 },
1731         },
1732 };
1733
1734 static struct clk_branch pcie1_h_clk = {
1735         .halt_reg = 0x2fd4,
1736         .halt_bit = 9,
1737         .clkr = {
1738                 .enable_reg = 0x3a8c,
1739                 .enable_mask = BIT(4),
1740                 .hw.init = &(struct clk_init_data){
1741                         .name = "pcie1_h_clk",
1742                         .ops = &clk_branch_ops,
1743                 },
1744         },
1745 };
1746
1747 static struct clk_branch pcie1_phy_clk = {
1748         .halt_reg = 0x2fdc,
1749         .halt_bit = 26,
1750         .clkr = {
1751                 .enable_reg = 0x3a90,
1752                 .enable_mask = BIT(4),
1753                 .hw.init = &(struct clk_init_data){
1754                         .name = "pcie1_phy_clk",
1755                         .ops = &clk_branch_ops,
1756                 },
1757         },
1758 };
1759
1760 static struct clk_rcg pcie2_ref_src = {
1761         .ns_reg = 0x3ae0,
1762         .p = {
1763                 .pre_div_shift = 3,
1764                 .pre_div_width = 4,
1765         },
1766         .s = {
1767                 .src_sel_shift = 0,
1768                 .parent_map = gcc_pxo_pll3_map,
1769         },
1770         .freq_tbl = clk_tbl_pcie_ref,
1771         .clkr = {
1772                 .enable_reg = 0x3ae0,
1773                 .enable_mask = BIT(11),
1774                 .hw.init = &(struct clk_init_data){
1775                         .name = "pcie2_ref_src",
1776                         .parent_names = gcc_pxo_pll3,
1777                         .num_parents = 2,
1778                         .ops = &clk_rcg_ops,
1779                         .flags = CLK_SET_RATE_GATE,
1780                 },
1781         },
1782 };
1783
1784 static struct clk_branch pcie2_ref_src_clk = {
1785         .halt_reg = 0x2fdc,
1786         .halt_bit = 24,
1787         .clkr = {
1788                 .enable_reg = 0x3ae0,
1789                 .enable_mask = BIT(9),
1790                 .hw.init = &(struct clk_init_data){
1791                         .name = "pcie2_ref_src_clk",
1792                         .parent_names = (const char *[]){ "pcie2_ref_src" },
1793                         .num_parents = 1,
1794                         .ops = &clk_branch_ops,
1795                         .flags = CLK_SET_RATE_PARENT,
1796                 },
1797         },
1798 };
1799
1800 static struct clk_branch pcie2_a_clk = {
1801         .halt_reg = 0x2fc0,
1802         .halt_bit = 9,
1803         .clkr = {
1804                 .enable_reg = 0x3ac0,
1805                 .enable_mask = BIT(4),
1806                 .hw.init = &(struct clk_init_data){
1807                         .name = "pcie2_a_clk",
1808                         .ops = &clk_branch_ops,
1809                 },
1810         },
1811 };
1812
1813 static struct clk_branch pcie2_aux_clk = {
1814         .halt_reg = 0x2fdc,
1815         .halt_bit = 25,
1816         .clkr = {
1817                 .enable_reg = 0x3ac8,
1818                 .enable_mask = BIT(4),
1819                 .hw.init = &(struct clk_init_data){
1820                         .name = "pcie2_aux_clk",
1821                         .ops = &clk_branch_ops,
1822                 },
1823         },
1824 };
1825
1826 static struct clk_branch pcie2_h_clk = {
1827         .halt_reg = 0x2fd4,
1828         .halt_bit = 10,
1829         .clkr = {
1830                 .enable_reg = 0x3acc,
1831                 .enable_mask = BIT(4),
1832                 .hw.init = &(struct clk_init_data){
1833                         .name = "pcie2_h_clk",
1834                         .ops = &clk_branch_ops,
1835                 },
1836         },
1837 };
1838
1839 static struct clk_branch pcie2_phy_clk = {
1840         .halt_reg = 0x2fdc,
1841         .halt_bit = 23,
1842         .clkr = {
1843                 .enable_reg = 0x3ad0,
1844                 .enable_mask = BIT(4),
1845                 .hw.init = &(struct clk_init_data){
1846                         .name = "pcie2_phy_clk",
1847                         .ops = &clk_branch_ops,
1848                 },
1849         },
1850 };
1851
1852 static const struct freq_tbl clk_tbl_sata_ref[] = {
1853         { 100000000, P_PLL3,  12, 0, 0 },
1854         { }
1855 };
1856
1857 static struct clk_rcg sata_ref_src = {
1858         .ns_reg = 0x2c08,
1859         .p = {
1860                 .pre_div_shift = 3,
1861                 .pre_div_width = 4,
1862         },
1863         .s = {
1864                 .src_sel_shift = 0,
1865                 .parent_map = gcc_pxo_pll3_sata_map,
1866         },
1867         .freq_tbl = clk_tbl_sata_ref,
1868         .clkr = {
1869                 .enable_reg = 0x2c08,
1870                 .enable_mask = BIT(7),
1871                 .hw.init = &(struct clk_init_data){
1872                         .name = "sata_ref_src",
1873                         .parent_names = gcc_pxo_pll3,
1874                         .num_parents = 2,
1875                         .ops = &clk_rcg_ops,
1876                         .flags = CLK_SET_RATE_GATE,
1877                 },
1878         },
1879 };
1880
1881 static struct clk_branch sata_rxoob_clk = {
1882         .halt_reg = 0x2fdc,
1883         .halt_bit = 20,
1884         .clkr = {
1885                 .enable_reg = 0x2c0c,
1886                 .enable_mask = BIT(4),
1887                 .hw.init = &(struct clk_init_data){
1888                         .name = "sata_rxoob_clk",
1889                         .parent_names = (const char *[]){ "sata_ref_src" },
1890                         .num_parents = 1,
1891                         .ops = &clk_branch_ops,
1892                         .flags = CLK_SET_RATE_PARENT,
1893                 },
1894         },
1895 };
1896
1897 static struct clk_branch sata_pmalive_clk = {
1898         .halt_reg = 0x2fdc,
1899         .halt_bit = 19,
1900         .clkr = {
1901                 .enable_reg = 0x2c10,
1902                 .enable_mask = BIT(4),
1903                 .hw.init = &(struct clk_init_data){
1904                         .name = "sata_pmalive_clk",
1905                         .parent_names = (const char *[]){ "sata_ref_src" },
1906                         .num_parents = 1,
1907                         .ops = &clk_branch_ops,
1908                         .flags = CLK_SET_RATE_PARENT,
1909                 },
1910         },
1911 };
1912
1913 static struct clk_branch sata_phy_ref_clk = {
1914         .halt_reg = 0x2fdc,
1915         .halt_bit = 18,
1916         .clkr = {
1917                 .enable_reg = 0x2c14,
1918                 .enable_mask = BIT(4),
1919                 .hw.init = &(struct clk_init_data){
1920                         .name = "sata_phy_ref_clk",
1921                         .parent_names = (const char *[]){ "pxo" },
1922                         .num_parents = 1,
1923                         .ops = &clk_branch_ops,
1924                 },
1925         },
1926 };
1927
1928 static struct clk_branch sata_a_clk = {
1929         .halt_reg = 0x2fc0,
1930         .halt_bit = 12,
1931         .clkr = {
1932                 .enable_reg = 0x2c20,
1933                 .enable_mask = BIT(4),
1934                 .hw.init = &(struct clk_init_data){
1935                         .name = "sata_a_clk",
1936                         .ops = &clk_branch_ops,
1937                 },
1938         },
1939 };
1940
1941 static struct clk_branch sata_h_clk = {
1942         .halt_reg = 0x2fdc,
1943         .halt_bit = 21,
1944         .clkr = {
1945                 .enable_reg = 0x2c00,
1946                 .enable_mask = BIT(4),
1947                 .hw.init = &(struct clk_init_data){
1948                         .name = "sata_h_clk",
1949                         .ops = &clk_branch_ops,
1950                 },
1951         },
1952 };
1953
1954 static struct clk_branch sfab_sata_s_h_clk = {
1955         .halt_reg = 0x2fc4,
1956         .halt_bit = 14,
1957         .clkr = {
1958                 .enable_reg = 0x2480,
1959                 .enable_mask = BIT(4),
1960                 .hw.init = &(struct clk_init_data){
1961                         .name = "sfab_sata_s_h_clk",
1962                         .ops = &clk_branch_ops,
1963                 },
1964         },
1965 };
1966
1967 static struct clk_branch sata_phy_cfg_clk = {
1968         .halt_reg = 0x2fcc,
1969         .halt_bit = 14,
1970         .clkr = {
1971                 .enable_reg = 0x2c40,
1972                 .enable_mask = BIT(4),
1973                 .hw.init = &(struct clk_init_data){
1974                         .name = "sata_phy_cfg_clk",
1975                         .ops = &clk_branch_ops,
1976                 },
1977         },
1978 };
1979
1980 static const struct freq_tbl clk_tbl_usb30_master[] = {
1981         { 125000000, P_PLL0,  1, 5, 32 },
1982         { }
1983 };
1984
1985 static struct clk_rcg usb30_master_clk_src = {
1986         .ns_reg = 0x3b2c,
1987         .md_reg = 0x3b28,
1988         .mn = {
1989                 .mnctr_en_bit = 8,
1990                 .mnctr_reset_bit = 7,
1991                 .mnctr_mode_shift = 5,
1992                 .n_val_shift = 16,
1993                 .m_val_shift = 16,
1994                 .width = 8,
1995         },
1996         .p = {
1997                 .pre_div_shift = 3,
1998                 .pre_div_width = 2,
1999         },
2000         .s = {
2001                 .src_sel_shift = 0,
2002                 .parent_map = gcc_pxo_pll8_pll0,
2003         },
2004         .freq_tbl = clk_tbl_usb30_master,
2005         .clkr = {
2006                 .enable_reg = 0x3b2c,
2007                 .enable_mask = BIT(11),
2008                 .hw.init = &(struct clk_init_data){
2009                         .name = "usb30_master_ref_src",
2010                         .parent_names = gcc_pxo_pll8_pll0_map,
2011                         .num_parents = 3,
2012                         .ops = &clk_rcg_ops,
2013                         .flags = CLK_SET_RATE_GATE,
2014                 },
2015         },
2016 };
2017
2018 static struct clk_branch usb30_0_branch_clk = {
2019         .halt_reg = 0x2fc4,
2020         .halt_bit = 22,
2021         .clkr = {
2022                 .enable_reg = 0x3b24,
2023                 .enable_mask = BIT(4),
2024                 .hw.init = &(struct clk_init_data){
2025                         .name = "usb30_0_branch_clk",
2026                         .parent_names = (const char *[]){ "usb30_master_ref_src", },
2027                         .num_parents = 1,
2028                         .ops = &clk_branch_ops,
2029                         .flags = CLK_SET_RATE_PARENT,
2030                 },
2031         },
2032 };
2033
2034 static struct clk_branch usb30_1_branch_clk = {
2035         .halt_reg = 0x2fc4,
2036         .halt_bit = 17,
2037         .clkr = {
2038                 .enable_reg = 0x3b34,
2039                 .enable_mask = BIT(4),
2040                 .hw.init = &(struct clk_init_data){
2041                         .name = "usb30_1_branch_clk",
2042                         .parent_names = (const char *[]){ "usb30_master_ref_src", },
2043                         .num_parents = 1,
2044                         .ops = &clk_branch_ops,
2045                         .flags = CLK_SET_RATE_PARENT,
2046                 },
2047         },
2048 };
2049
2050 static const struct freq_tbl clk_tbl_usb30_utmi[] = {
2051         { 60000000, P_PLL8,  1, 5, 32 },
2052         { }
2053 };
2054
2055 static struct clk_rcg usb30_utmi_clk = {
2056         .ns_reg = 0x3b44,
2057         .md_reg = 0x3b40,
2058         .mn = {
2059                 .mnctr_en_bit = 8,
2060                 .mnctr_reset_bit = 7,
2061                 .mnctr_mode_shift = 5,
2062                 .n_val_shift = 16,
2063                 .m_val_shift = 16,
2064                 .width = 8,
2065         },
2066         .p = {
2067                 .pre_div_shift = 3,
2068                 .pre_div_width = 2,
2069         },
2070         .s = {
2071                 .src_sel_shift = 0,
2072                 .parent_map = gcc_pxo_pll8_pll0,
2073         },
2074         .freq_tbl = clk_tbl_usb30_utmi,
2075         .clkr = {
2076                 .enable_reg = 0x3b44,
2077                 .enable_mask = BIT(11),
2078                 .hw.init = &(struct clk_init_data){
2079                         .name = "usb30_utmi_clk",
2080                         .parent_names = gcc_pxo_pll8_pll0_map,
2081                         .num_parents = 3,
2082                         .ops = &clk_rcg_ops,
2083                         .flags = CLK_SET_RATE_GATE,
2084                 },
2085         },
2086 };
2087
2088 static struct clk_branch usb30_0_utmi_clk_ctl = {
2089         .halt_reg = 0x2fc4,
2090         .halt_bit = 21,
2091         .clkr = {
2092                 .enable_reg = 0x3b48,
2093                 .enable_mask = BIT(4),
2094                 .hw.init = &(struct clk_init_data){
2095                         .name = "usb30_0_utmi_clk_ctl",
2096                         .parent_names = (const char *[]){ "usb30_utmi_clk", },
2097                         .num_parents = 1,
2098                         .ops = &clk_branch_ops,
2099                         .flags = CLK_SET_RATE_PARENT,
2100                 },
2101         },
2102 };
2103
2104 static struct clk_branch usb30_1_utmi_clk_ctl = {
2105         .halt_reg = 0x2fc4,
2106         .halt_bit = 15,
2107         .clkr = {
2108                 .enable_reg = 0x3b4c,
2109                 .enable_mask = BIT(4),
2110                 .hw.init = &(struct clk_init_data){
2111                         .name = "usb30_1_utmi_clk_ctl",
2112                         .parent_names = (const char *[]){ "usb30_utmi_clk", },
2113                         .num_parents = 1,
2114                         .ops = &clk_branch_ops,
2115                         .flags = CLK_SET_RATE_PARENT,
2116                 },
2117         },
2118 };
2119
2120 static const struct freq_tbl clk_tbl_usb[] = {
2121         { 60000000, P_PLL8,  1, 5, 32 },
2122         { }
2123 };
2124
2125 static struct clk_rcg usb_hs1_xcvr_clk_src = {
2126         .ns_reg = 0x290C,
2127         .md_reg = 0x2908,
2128         .mn = {
2129                 .mnctr_en_bit = 8,
2130                 .mnctr_reset_bit = 7,
2131                 .mnctr_mode_shift = 5,
2132                 .n_val_shift = 16,
2133                 .m_val_shift = 16,
2134                 .width = 8,
2135         },
2136         .p = {
2137                 .pre_div_shift = 3,
2138                 .pre_div_width = 2,
2139         },
2140         .s = {
2141                 .src_sel_shift = 0,
2142                 .parent_map = gcc_pxo_pll8_pll0,
2143         },
2144         .freq_tbl = clk_tbl_usb,
2145         .clkr = {
2146                 .enable_reg = 0x2968,
2147                 .enable_mask = BIT(11),
2148                 .hw.init = &(struct clk_init_data){
2149                         .name = "usb_hs1_xcvr_src",
2150                         .parent_names = gcc_pxo_pll8_pll0_map,
2151                         .num_parents = 3,
2152                         .ops = &clk_rcg_ops,
2153                         .flags = CLK_SET_RATE_GATE,
2154                 },
2155         },
2156 };
2157
2158 static struct clk_branch usb_hs1_xcvr_clk = {
2159         .halt_reg = 0x2fcc,
2160         .halt_bit = 17,
2161         .clkr = {
2162                 .enable_reg = 0x290c,
2163                 .enable_mask = BIT(9),
2164                 .hw.init = &(struct clk_init_data){
2165                         .name = "usb_hs1_xcvr_clk",
2166                         .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
2167                         .num_parents = 1,
2168                         .ops = &clk_branch_ops,
2169                         .flags = CLK_SET_RATE_PARENT,
2170                 },
2171         },
2172 };
2173
2174 static struct clk_branch usb_hs1_h_clk = {
2175         .hwcg_reg = 0x2900,
2176         .hwcg_bit = 6,
2177         .halt_reg = 0x2fc8,
2178         .halt_bit = 1,
2179         .clkr = {
2180                 .enable_reg = 0x2900,
2181                 .enable_mask = BIT(4),
2182                 .hw.init = &(struct clk_init_data){
2183                         .name = "usb_hs1_h_clk",
2184                         .ops = &clk_branch_ops,
2185                 },
2186         },
2187 };
2188
2189 static struct clk_rcg usb_fs1_xcvr_clk_src = {
2190         .ns_reg = 0x2968,
2191         .md_reg = 0x2964,
2192         .mn = {
2193                 .mnctr_en_bit = 8,
2194                 .mnctr_reset_bit = 7,
2195                 .mnctr_mode_shift = 5,
2196                 .n_val_shift = 16,
2197                 .m_val_shift = 16,
2198                 .width = 8,
2199         },
2200         .p = {
2201                 .pre_div_shift = 3,
2202                 .pre_div_width = 2,
2203         },
2204         .s = {
2205                 .src_sel_shift = 0,
2206                 .parent_map = gcc_pxo_pll8_pll0,
2207         },
2208         .freq_tbl = clk_tbl_usb,
2209         .clkr = {
2210                 .enable_reg = 0x2968,
2211                 .enable_mask = BIT(11),
2212                 .hw.init = &(struct clk_init_data){
2213                         .name = "usb_fs1_xcvr_src",
2214                         .parent_names = gcc_pxo_pll8_pll0_map,
2215                         .num_parents = 3,
2216                         .ops = &clk_rcg_ops,
2217                         .flags = CLK_SET_RATE_GATE,
2218                 },
2219         },
2220 };
2221
2222 static struct clk_branch usb_fs1_xcvr_clk = {
2223         .halt_reg = 0x2fcc,
2224         .halt_bit = 17,
2225         .clkr = {
2226                 .enable_reg = 0x2968,
2227                 .enable_mask = BIT(9),
2228                 .hw.init = &(struct clk_init_data){
2229                         .name = "usb_fs1_xcvr_clk",
2230                         .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2231                         .num_parents = 1,
2232                         .ops = &clk_branch_ops,
2233                         .flags = CLK_SET_RATE_PARENT,
2234                 },
2235         },
2236 };
2237
2238 static struct clk_branch usb_fs1_sys_clk = {
2239         .halt_reg = 0x2fcc,
2240         .halt_bit = 18,
2241         .clkr = {
2242                 .enable_reg = 0x296c,
2243                 .enable_mask = BIT(4),
2244                 .hw.init = &(struct clk_init_data){
2245                         .name = "usb_fs1_sys_clk",
2246                         .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2247                         .num_parents = 1,
2248                         .ops = &clk_branch_ops,
2249                         .flags = CLK_SET_RATE_PARENT,
2250                 },
2251         },
2252 };
2253
2254 static struct clk_branch usb_fs1_h_clk = {
2255         .halt_reg = 0x2fcc,
2256         .halt_bit = 19,
2257         .clkr = {
2258                 .enable_reg = 0x2960,
2259                 .enable_mask = BIT(4),
2260                 .hw.init = &(struct clk_init_data){
2261                         .name = "usb_fs1_h_clk",
2262                         .ops = &clk_branch_ops,
2263                 },
2264         },
2265 };
2266
2267 static struct clk_branch ebi2_clk = {
2268         .hwcg_reg = 0x3b00,
2269         .hwcg_bit = 6,
2270         .halt_reg = 0x2fcc,
2271         .halt_bit = 1,
2272         .clkr = {
2273                 .enable_reg = 0x3b00,
2274                 .enable_mask = BIT(4),
2275                 .hw.init = &(struct clk_init_data){
2276                         .name = "ebi2_clk",
2277                         .ops = &clk_branch_ops,
2278                 },
2279         },
2280 };
2281
2282 static struct clk_branch ebi2_aon_clk = {
2283         .halt_reg = 0x2fcc,
2284         .halt_bit = 0,
2285         .clkr = {
2286                 .enable_reg = 0x3b00,
2287                 .enable_mask = BIT(8),
2288                 .hw.init = &(struct clk_init_data){
2289                         .name = "ebi2_always_on_clk",
2290                         .ops = &clk_branch_ops,
2291                 },
2292         },
2293 };
2294
2295 static const struct freq_tbl clk_tbl_gmac[] = {
2296         { 133000000, P_PLL0, 1,  50, 301 },
2297         { 266000000, P_PLL0, 1, 127, 382 },
2298         { }
2299 };
2300
2301 static struct clk_dyn_rcg gmac_core1_src = {
2302         .ns_reg[0] = 0x3cac,
2303         .ns_reg[1] = 0x3cb0,
2304         .md_reg[0] = 0x3ca4,
2305         .md_reg[1] = 0x3ca8,
2306         .bank_reg = 0x3ca0,
2307         .mn[0] = {
2308                 .mnctr_en_bit = 8,
2309                 .mnctr_reset_bit = 7,
2310                 .mnctr_mode_shift = 5,
2311                 .n_val_shift = 16,
2312                 .m_val_shift = 16,
2313                 .width = 8,
2314         },
2315         .mn[1] = {
2316                 .mnctr_en_bit = 8,
2317                 .mnctr_reset_bit = 7,
2318                 .mnctr_mode_shift = 5,
2319                 .n_val_shift = 16,
2320                 .m_val_shift = 16,
2321                 .width = 8,
2322         },
2323         .s[0] = {
2324                 .src_sel_shift = 0,
2325                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2326         },
2327         .s[1] = {
2328                 .src_sel_shift = 0,
2329                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2330         },
2331         .p[0] = {
2332                 .pre_div_shift = 3,
2333                 .pre_div_width = 2,
2334         },
2335         .p[1] = {
2336                 .pre_div_shift = 3,
2337                 .pre_div_width = 2,
2338         },
2339         .mux_sel_bit = 0,
2340         .freq_tbl = clk_tbl_gmac,
2341         .clkr = {
2342                 .enable_reg = 0x3ca0,
2343                 .enable_mask = BIT(1),
2344                 .hw.init = &(struct clk_init_data){
2345                         .name = "gmac_core1_src",
2346                         .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2347                         .num_parents = 5,
2348                         .ops = &clk_dyn_rcg_ops,
2349                 },
2350         },
2351 };
2352
2353 static struct clk_branch gmac_core1_clk = {
2354         .halt_reg = 0x3c20,
2355         .halt_bit = 4,
2356         .hwcg_reg = 0x3cb4,
2357         .hwcg_bit = 6,
2358         .clkr = {
2359                 .enable_reg = 0x3cb4,
2360                 .enable_mask = BIT(4),
2361                 .hw.init = &(struct clk_init_data){
2362                         .name = "gmac_core1_clk",
2363                         .parent_names = (const char *[]){
2364                                 "gmac_core1_src",
2365                         },
2366                         .num_parents = 1,
2367                         .ops = &clk_branch_ops,
2368                         .flags = CLK_SET_RATE_PARENT,
2369                 },
2370         },
2371 };
2372
2373 static struct clk_dyn_rcg gmac_core2_src = {
2374         .ns_reg[0] = 0x3ccc,
2375         .ns_reg[1] = 0x3cd0,
2376         .md_reg[0] = 0x3cc4,
2377         .md_reg[1] = 0x3cc8,
2378         .bank_reg = 0x3ca0,
2379         .mn[0] = {
2380                 .mnctr_en_bit = 8,
2381                 .mnctr_reset_bit = 7,
2382                 .mnctr_mode_shift = 5,
2383                 .n_val_shift = 16,
2384                 .m_val_shift = 16,
2385                 .width = 8,
2386         },
2387         .mn[1] = {
2388                 .mnctr_en_bit = 8,
2389                 .mnctr_reset_bit = 7,
2390                 .mnctr_mode_shift = 5,
2391                 .n_val_shift = 16,
2392                 .m_val_shift = 16,
2393                 .width = 8,
2394         },
2395         .s[0] = {
2396                 .src_sel_shift = 0,
2397                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2398         },
2399         .s[1] = {
2400                 .src_sel_shift = 0,
2401                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2402         },
2403         .p[0] = {
2404                 .pre_div_shift = 3,
2405                 .pre_div_width = 2,
2406         },
2407         .p[1] = {
2408                 .pre_div_shift = 3,
2409                 .pre_div_width = 2,
2410         },
2411         .mux_sel_bit = 0,
2412         .freq_tbl = clk_tbl_gmac,
2413         .clkr = {
2414                 .enable_reg = 0x3cc0,
2415                 .enable_mask = BIT(1),
2416                 .hw.init = &(struct clk_init_data){
2417                         .name = "gmac_core2_src",
2418                         .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2419                         .num_parents = 5,
2420                         .ops = &clk_dyn_rcg_ops,
2421                 },
2422         },
2423 };
2424
2425 static struct clk_branch gmac_core2_clk = {
2426         .halt_reg = 0x3c20,
2427         .halt_bit = 5,
2428         .hwcg_reg = 0x3cd4,
2429         .hwcg_bit = 6,
2430         .clkr = {
2431                 .enable_reg = 0x3cd4,
2432                 .enable_mask = BIT(4),
2433                 .hw.init = &(struct clk_init_data){
2434                         .name = "gmac_core2_clk",
2435                         .parent_names = (const char *[]){
2436                                 "gmac_core2_src",
2437                         },
2438                         .num_parents = 1,
2439                         .ops = &clk_branch_ops,
2440                         .flags = CLK_SET_RATE_PARENT,
2441                 },
2442         },
2443 };
2444
2445 static struct clk_dyn_rcg gmac_core3_src = {
2446         .ns_reg[0] = 0x3cec,
2447         .ns_reg[1] = 0x3cf0,
2448         .md_reg[0] = 0x3ce4,
2449         .md_reg[1] = 0x3ce8,
2450         .bank_reg = 0x3ce0,
2451         .mn[0] = {
2452                 .mnctr_en_bit = 8,
2453                 .mnctr_reset_bit = 7,
2454                 .mnctr_mode_shift = 5,
2455                 .n_val_shift = 16,
2456                 .m_val_shift = 16,
2457                 .width = 8,
2458         },
2459         .mn[1] = {
2460                 .mnctr_en_bit = 8,
2461                 .mnctr_reset_bit = 7,
2462                 .mnctr_mode_shift = 5,
2463                 .n_val_shift = 16,
2464                 .m_val_shift = 16,
2465                 .width = 8,
2466         },
2467         .s[0] = {
2468                 .src_sel_shift = 0,
2469                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2470         },
2471         .s[1] = {
2472                 .src_sel_shift = 0,
2473                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2474         },
2475         .p[0] = {
2476                 .pre_div_shift = 3,
2477                 .pre_div_width = 2,
2478         },
2479         .p[1] = {
2480                 .pre_div_shift = 3,
2481                 .pre_div_width = 2,
2482         },
2483         .mux_sel_bit = 0,
2484         .freq_tbl = clk_tbl_gmac,
2485         .clkr = {
2486                 .enable_reg = 0x3ce0,
2487                 .enable_mask = BIT(1),
2488                 .hw.init = &(struct clk_init_data){
2489                         .name = "gmac_core3_src",
2490                         .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2491                         .num_parents = 5,
2492                         .ops = &clk_dyn_rcg_ops,
2493                 },
2494         },
2495 };
2496
2497 static struct clk_branch gmac_core3_clk = {
2498         .halt_reg = 0x3c20,
2499         .halt_bit = 6,
2500         .hwcg_reg = 0x3cf4,
2501         .hwcg_bit = 6,
2502         .clkr = {
2503                 .enable_reg = 0x3cf4,
2504                 .enable_mask = BIT(4),
2505                 .hw.init = &(struct clk_init_data){
2506                         .name = "gmac_core3_clk",
2507                         .parent_names = (const char *[]){
2508                                 "gmac_core3_src",
2509                         },
2510                         .num_parents = 1,
2511                         .ops = &clk_branch_ops,
2512                         .flags = CLK_SET_RATE_PARENT,
2513                 },
2514         },
2515 };
2516
2517 static struct clk_dyn_rcg gmac_core4_src = {
2518         .ns_reg[0] = 0x3d0c,
2519         .ns_reg[1] = 0x3d10,
2520         .md_reg[0] = 0x3d04,
2521         .md_reg[1] = 0x3d08,
2522         .bank_reg = 0x3d00,
2523         .mn[0] = {
2524                 .mnctr_en_bit = 8,
2525                 .mnctr_reset_bit = 7,
2526                 .mnctr_mode_shift = 5,
2527                 .n_val_shift = 16,
2528                 .m_val_shift = 16,
2529                 .width = 8,
2530         },
2531         .mn[1] = {
2532                 .mnctr_en_bit = 8,
2533                 .mnctr_reset_bit = 7,
2534                 .mnctr_mode_shift = 5,
2535                 .n_val_shift = 16,
2536                 .m_val_shift = 16,
2537                 .width = 8,
2538         },
2539         .s[0] = {
2540                 .src_sel_shift = 0,
2541                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2542         },
2543         .s[1] = {
2544                 .src_sel_shift = 0,
2545                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2546         },
2547         .p[0] = {
2548                 .pre_div_shift = 3,
2549                 .pre_div_width = 2,
2550         },
2551         .p[1] = {
2552                 .pre_div_shift = 3,
2553                 .pre_div_width = 2,
2554         },
2555         .mux_sel_bit = 0,
2556         .freq_tbl = clk_tbl_gmac,
2557         .clkr = {
2558                 .enable_reg = 0x3d00,
2559                 .enable_mask = BIT(1),
2560                 .hw.init = &(struct clk_init_data){
2561                         .name = "gmac_core4_src",
2562                         .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2563                         .num_parents = 5,
2564                         .ops = &clk_dyn_rcg_ops,
2565                 },
2566         },
2567 };
2568
2569 static struct clk_branch gmac_core4_clk = {
2570         .halt_reg = 0x3c20,
2571         .halt_bit = 7,
2572         .hwcg_reg = 0x3d14,
2573         .hwcg_bit = 6,
2574         .clkr = {
2575                 .enable_reg = 0x3d14,
2576                 .enable_mask = BIT(4),
2577                 .hw.init = &(struct clk_init_data){
2578                         .name = "gmac_core4_clk",
2579                         .parent_names = (const char *[]){
2580                                 "gmac_core4_src",
2581                         },
2582                         .num_parents = 1,
2583                         .ops = &clk_branch_ops,
2584                         .flags = CLK_SET_RATE_PARENT,
2585                 },
2586         },
2587 };
2588
2589 static const struct freq_tbl clk_tbl_nss_tcm[] = {
2590         { 266000000, P_PLL0, 3, 0, 0 },
2591         { 400000000, P_PLL0, 2, 0, 0 },
2592         { }
2593 };
2594
2595 static struct clk_dyn_rcg nss_tcm_src = {
2596         .ns_reg[0] = 0x3dc4,
2597         .ns_reg[1] = 0x3dc8,
2598         .bank_reg = 0x3dc0,
2599         .s[0] = {
2600                 .src_sel_shift = 0,
2601                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2602         },
2603         .s[1] = {
2604                 .src_sel_shift = 0,
2605                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2606         },
2607         .p[0] = {
2608                 .pre_div_shift = 3,
2609                 .pre_div_width = 4,
2610         },
2611         .p[1] = {
2612                 .pre_div_shift = 3,
2613                 .pre_div_width = 4,
2614         },
2615         .mux_sel_bit = 0,
2616         .freq_tbl = clk_tbl_nss_tcm,
2617         .clkr = {
2618                 .enable_reg = 0x3dc0,
2619                 .enable_mask = BIT(1),
2620                 .hw.init = &(struct clk_init_data){
2621                         .name = "nss_tcm_src",
2622                         .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2623                         .num_parents = 5,
2624                         .ops = &clk_dyn_rcg_ops,
2625                 },
2626         },
2627 };
2628
2629 static struct clk_branch nss_tcm_clk = {
2630         .halt_reg = 0x3c20,
2631         .halt_bit = 14,
2632         .clkr = {
2633                 .enable_reg = 0x3dd0,
2634                 .enable_mask = BIT(6) | BIT(4),
2635                 .hw.init = &(struct clk_init_data){
2636                         .name = "nss_tcm_clk",
2637                         .parent_names = (const char *[]){
2638                                 "nss_tcm_src",
2639                         },
2640                         .num_parents = 1,
2641                         .ops = &clk_branch_ops,
2642                         .flags = CLK_SET_RATE_PARENT,
2643                 },
2644         },
2645 };
2646
2647 static const struct freq_tbl clk_tbl_nss[] = {
2648         { 110000000, P_PLL18, 1, 1, 5 },
2649         { 275000000, P_PLL18, 2, 0, 0 },
2650         { 550000000, P_PLL18, 1, 0, 0 },
2651         { 733000000, P_PLL18, 1, 0, 0 },
2652         { }
2653 };
2654
2655 static struct clk_dyn_rcg ubi32_core1_src_clk = {
2656         .ns_reg[0] = 0x3d2c,
2657         .ns_reg[1] = 0x3d30,
2658         .md_reg[0] = 0x3d24,
2659         .md_reg[1] = 0x3d28,
2660         .bank_reg = 0x3d20,
2661         .mn[0] = {
2662                 .mnctr_en_bit = 8,
2663                 .mnctr_reset_bit = 7,
2664                 .mnctr_mode_shift = 5,
2665                 .n_val_shift = 16,
2666                 .m_val_shift = 16,
2667                 .width = 8,
2668         },
2669         .mn[1] = {
2670                 .mnctr_en_bit = 8,
2671                 .mnctr_reset_bit = 7,
2672                 .mnctr_mode_shift = 5,
2673                 .n_val_shift = 16,
2674                 .m_val_shift = 16,
2675                 .width = 8,
2676         },
2677         .s[0] = {
2678                 .src_sel_shift = 0,
2679                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2680         },
2681         .s[1] = {
2682                 .src_sel_shift = 0,
2683                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2684         },
2685         .p[0] = {
2686                 .pre_div_shift = 3,
2687                 .pre_div_width = 2,
2688         },
2689         .p[1] = {
2690                 .pre_div_shift = 3,
2691                 .pre_div_width = 2,
2692         },
2693         .mux_sel_bit = 0,
2694         .freq_tbl = clk_tbl_nss,
2695         .clkr = {
2696                 .enable_reg = 0x3d20,
2697                 .enable_mask = BIT(1),
2698                 .hw.init = &(struct clk_init_data){
2699                         .name = "ubi32_core1_src_clk",
2700                         .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2701                         .num_parents = 5,
2702                         .ops = &clk_dyn_rcg_ops,
2703                         .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2704                 },
2705         },
2706 };
2707
2708 static struct clk_dyn_rcg ubi32_core2_src_clk = {
2709         .ns_reg[0] = 0x3d4c,
2710         .ns_reg[1] = 0x3d50,
2711         .md_reg[0] = 0x3d44,
2712         .md_reg[1] = 0x3d48,
2713         .bank_reg = 0x3d40,
2714         .mn[0] = {
2715                 .mnctr_en_bit = 8,
2716                 .mnctr_reset_bit = 7,
2717                 .mnctr_mode_shift = 5,
2718                 .n_val_shift = 16,
2719                 .m_val_shift = 16,
2720                 .width = 8,
2721         },
2722         .mn[1] = {
2723                 .mnctr_en_bit = 8,
2724                 .mnctr_reset_bit = 7,
2725                 .mnctr_mode_shift = 5,
2726                 .n_val_shift = 16,
2727                 .m_val_shift = 16,
2728                 .width = 8,
2729         },
2730         .s[0] = {
2731                 .src_sel_shift = 0,
2732                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2733         },
2734         .s[1] = {
2735                 .src_sel_shift = 0,
2736                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2737         },
2738         .p[0] = {
2739                 .pre_div_shift = 3,
2740                 .pre_div_width = 2,
2741         },
2742         .p[1] = {
2743                 .pre_div_shift = 3,
2744                 .pre_div_width = 2,
2745         },
2746         .mux_sel_bit = 0,
2747         .freq_tbl = clk_tbl_nss,
2748         .clkr = {
2749                 .enable_reg = 0x3d40,
2750                 .enable_mask = BIT(1),
2751                 .hw.init = &(struct clk_init_data){
2752                         .name = "ubi32_core2_src_clk",
2753                         .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2754                         .num_parents = 5,
2755                         .ops = &clk_dyn_rcg_ops,
2756                         .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2757                 },
2758         },
2759 };
2760
2761 static struct clk_regmap *gcc_ipq806x_clks[] = {
2762         [PLL0] = &pll0.clkr,
2763         [PLL0_VOTE] = &pll0_vote,
2764         [PLL3] = &pll3.clkr,
2765         [PLL4_VOTE] = &pll4_vote,
2766         [PLL8] = &pll8.clkr,
2767         [PLL8_VOTE] = &pll8_vote,
2768         [PLL14] = &pll14.clkr,
2769         [PLL14_VOTE] = &pll14_vote,
2770         [PLL18] = &pll18.clkr,
2771         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2772         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2773         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2774         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2775         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2776         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2777         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2778         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2779         [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2780         [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2781         [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2782         [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2783         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2784         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2785         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2786         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2787         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2788         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2789         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2790         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2791         [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2792         [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2793         [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2794         [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2795         [GP0_SRC] = &gp0_src.clkr,
2796         [GP0_CLK] = &gp0_clk.clkr,
2797         [GP1_SRC] = &gp1_src.clkr,
2798         [GP1_CLK] = &gp1_clk.clkr,
2799         [GP2_SRC] = &gp2_src.clkr,
2800         [GP2_CLK] = &gp2_clk.clkr,
2801         [PMEM_A_CLK] = &pmem_clk.clkr,
2802         [PRNG_SRC] = &prng_src.clkr,
2803         [PRNG_CLK] = &prng_clk.clkr,
2804         [SDC1_SRC] = &sdc1_src.clkr,
2805         [SDC1_CLK] = &sdc1_clk.clkr,
2806         [SDC3_SRC] = &sdc3_src.clkr,
2807         [SDC3_CLK] = &sdc3_clk.clkr,
2808         [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2809         [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2810         [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
2811         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2812         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2813         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2814         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2815         [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2816         [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2817         [TSIF_H_CLK] = &tsif_h_clk.clkr,
2818         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2819         [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2820         [ADM0_CLK] = &adm0_clk.clkr,
2821         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2822         [PCIE_A_CLK] = &pcie_a_clk.clkr,
2823         [PCIE_AUX_CLK] = &pcie_aux_clk.clkr,
2824         [PCIE_H_CLK] = &pcie_h_clk.clkr,
2825         [PCIE_PHY_CLK] = &pcie_phy_clk.clkr,
2826         [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
2827         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2828         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2829         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2830         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2831         [SATA_H_CLK] = &sata_h_clk.clkr,
2832         [SATA_CLK_SRC] = &sata_ref_src.clkr,
2833         [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
2834         [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
2835         [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
2836         [SATA_A_CLK] = &sata_a_clk.clkr,
2837         [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
2838         [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr,
2839         [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr,
2840         [PCIE_1_A_CLK] = &pcie1_a_clk.clkr,
2841         [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr,
2842         [PCIE_1_H_CLK] = &pcie1_h_clk.clkr,
2843         [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr,
2844         [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr,
2845         [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr,
2846         [PCIE_2_A_CLK] = &pcie2_a_clk.clkr,
2847         [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr,
2848         [PCIE_2_H_CLK] = &pcie2_h_clk.clkr,
2849         [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr,
2850         [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr,
2851         [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr,
2852         [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr,
2853         [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr,
2854         [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr,
2855         [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr,
2856         [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr,
2857         [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr,
2858         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2859         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr,
2860         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2861         [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2862         [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
2863         [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
2864         [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
2865         [EBI2_CLK] = &ebi2_clk.clkr,
2866         [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
2867         [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr,
2868         [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr,
2869         [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr,
2870         [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr,
2871         [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr,
2872         [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr,
2873         [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr,
2874         [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr,
2875         [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr,
2876         [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
2877         [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
2878         [NSSTCM_CLK] = &nss_tcm_clk.clkr,
2879         [PLL9] = &hfpll0.clkr,
2880         [PLL10] = &hfpll1.clkr,
2881         [PLL12] = &hfpll_l2.clkr,
2882 };
2883
2884 static const struct qcom_reset_map gcc_ipq806x_resets[] = {
2885         [QDSS_STM_RESET] = { 0x2060, 6 },
2886         [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2887         [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2888         [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
2889         [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
2890         [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
2891         [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2892         [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2893         [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
2894         [ADM0_C2_RESET] = { 0x220c, 4 },
2895         [ADM0_C1_RESET] = { 0x220c, 3 },
2896         [ADM0_C0_RESET] = { 0x220c, 2 },
2897         [ADM0_PBUS_RESET] = { 0x220c, 1 },
2898         [ADM0_RESET] = { 0x220c, 0 },
2899         [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
2900         [QDSS_POR_RESET] = { 0x2260, 4 },
2901         [QDSS_TSCTR_RESET] = { 0x2260, 3 },
2902         [QDSS_HRESET_RESET] = { 0x2260, 2 },
2903         [QDSS_AXI_RESET] = { 0x2260, 1 },
2904         [QDSS_DBG_RESET] = { 0x2260, 0 },
2905         [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
2906         [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
2907         [PCIE_EXT_RESET] = { 0x22dc, 6 },
2908         [PCIE_PHY_RESET] = { 0x22dc, 5 },
2909         [PCIE_PCI_RESET] = { 0x22dc, 4 },
2910         [PCIE_POR_RESET] = { 0x22dc, 3 },
2911         [PCIE_HCLK_RESET] = { 0x22dc, 2 },
2912         [PCIE_ACLK_RESET] = { 0x22dc, 0 },
2913         [SFAB_LPASS_RESET] = { 0x23a0, 7 },
2914         [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2915         [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2916         [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2917         [SFAB_SATA_S_RESET] = { 0x2480, 7 },
2918         [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2919         [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2920         [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2921         [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2922         [DFAB_ARB0_RESET] = { 0x2560, 7 },
2923         [DFAB_ARB1_RESET] = { 0x2564, 7 },
2924         [PPSS_PROC_RESET] = { 0x2594, 1 },
2925         [PPSS_RESET] = { 0x2594, 0 },
2926         [DMA_BAM_RESET] = { 0x25c0, 7 },
2927         [SPS_TIC_H_RESET] = { 0x2600, 7 },
2928         [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2929         [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2930         [TSIF_H_RESET] = { 0x2700, 7 },
2931         [CE1_H_RESET] = { 0x2720, 7 },
2932         [CE1_CORE_RESET] = { 0x2724, 7 },
2933         [CE1_SLEEP_RESET] = { 0x2728, 7 },
2934         [CE2_H_RESET] = { 0x2740, 7 },
2935         [CE2_CORE_RESET] = { 0x2744, 7 },
2936         [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2937         [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2938         [RPM_PROC_RESET] = { 0x27c0, 7 },
2939         [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2940         [SDC1_RESET] = { 0x2830, 0 },
2941         [SDC2_RESET] = { 0x2850, 0 },
2942         [SDC3_RESET] = { 0x2870, 0 },
2943         [SDC4_RESET] = { 0x2890, 0 },
2944         [USB_HS1_RESET] = { 0x2910, 0 },
2945         [USB_HSIC_RESET] = { 0x2934, 0 },
2946         [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2947         [USB_FS1_RESET] = { 0x2974, 0 },
2948         [GSBI1_RESET] = { 0x29dc, 0 },
2949         [GSBI2_RESET] = { 0x29fc, 0 },
2950         [GSBI3_RESET] = { 0x2a1c, 0 },
2951         [GSBI4_RESET] = { 0x2a3c, 0 },
2952         [GSBI5_RESET] = { 0x2a5c, 0 },
2953         [GSBI6_RESET] = { 0x2a7c, 0 },
2954         [GSBI7_RESET] = { 0x2a9c, 0 },
2955         [SPDM_RESET] = { 0x2b6c, 0 },
2956         [SEC_CTRL_RESET] = { 0x2b80, 7 },
2957         [TLMM_H_RESET] = { 0x2ba0, 7 },
2958         [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
2959         [SATA_RESET] = { 0x2c1c, 0 },
2960         [TSSC_RESET] = { 0x2ca0, 7 },
2961         [PDM_RESET] = { 0x2cc0, 12 },
2962         [MPM_H_RESET] = { 0x2da0, 7 },
2963         [MPM_RESET] = { 0x2da4, 0 },
2964         [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2965         [PRNG_RESET] = { 0x2e80, 12 },
2966         [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
2967         [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
2968         [CE3_SLEEP_RESET] = { 0x36d0, 7 },
2969         [PCIE_1_M_RESET] = { 0x3a98, 1 },
2970         [PCIE_1_S_RESET] = { 0x3a98, 0 },
2971         [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
2972         [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
2973         [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
2974         [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
2975         [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
2976         [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
2977         [PCIE_2_M_RESET] = { 0x3ad8, 1 },
2978         [PCIE_2_S_RESET] = { 0x3ad8, 0 },
2979         [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
2980         [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
2981         [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
2982         [PCIE_2_POR_RESET] = { 0x3adc, 3 },
2983         [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
2984         [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
2985         [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
2986         [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
2987         [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
2988         [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
2989         [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
2990         [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
2991         [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
2992         [USB30_0_PHY_RESET] = { 0x3b50, 0 },
2993         [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
2994         [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
2995         [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
2996         [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
2997         [USB30_1_PHY_RESET] = { 0x3b58, 0 },
2998         [NSSFB0_RESET] = { 0x3b60, 6 },
2999         [NSSFB1_RESET] = { 0x3b60, 7 },
3000         [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3},
3001         [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 },
3002         [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 },
3003         [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 },
3004         [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 },
3005         [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 },
3006         [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 },
3007         [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 },
3008         [GMAC_CORE1_RESET] = { 0x3cbc, 0 },
3009         [GMAC_CORE2_RESET] = { 0x3cdc, 0 },
3010         [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
3011         [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
3012         [GMAC_AHB_RESET] = { 0x3e24, 0 },
3013         [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
3014         [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
3015         [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
3016         [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 },
3017         [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 },
3018         [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 },
3019         [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 },
3020         [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 },
3021         [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 },
3022         [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 },
3023         [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 },
3024         [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 },
3025         [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 },
3026         [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 },
3027         [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 },
3028         [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 },
3029         [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 },
3030         [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 },
3031         [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 },
3032         [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 },
3033         [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 },
3034         [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 },
3035         [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 },
3036         [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 },
3037         [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 },
3038         [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 },
3039         [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 },
3040         [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 },
3041         [NSS_SRDS_N_RESET] = { 0x3b60, 28 },
3042 };
3043
3044 static const struct regmap_config gcc_ipq806x_regmap_config = {
3045         .reg_bits       = 32,
3046         .reg_stride     = 4,
3047         .val_bits       = 32,
3048         .max_register   = 0x3e40,
3049         .fast_io        = true,
3050 };
3051
3052 static const struct qcom_cc_desc gcc_ipq806x_desc = {
3053         .config = &gcc_ipq806x_regmap_config,
3054         .clks = gcc_ipq806x_clks,
3055         .num_clks = ARRAY_SIZE(gcc_ipq806x_clks),
3056         .resets = gcc_ipq806x_resets,
3057         .num_resets = ARRAY_SIZE(gcc_ipq806x_resets),
3058 };
3059
3060 static const struct of_device_id gcc_ipq806x_match_table[] = {
3061         { .compatible = "qcom,gcc-ipq8064" },
3062         { }
3063 };
3064 MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
3065
3066 static int gcc_ipq806x_probe(struct platform_device *pdev)
3067 {
3068         struct device *dev = &pdev->dev;
3069         struct regmap *regmap;
3070         int ret;
3071
3072         ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000);
3073         if (ret)
3074                 return ret;
3075
3076         ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000);
3077         if (ret)
3078                 return ret;
3079
3080         ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
3081         if (ret)
3082                 return ret;
3083
3084         regmap = dev_get_regmap(dev, NULL);
3085         if (!regmap)
3086                 return -ENODEV;
3087
3088         /* Setup PLL18 static bits */
3089         regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400);
3090         regmap_write(regmap, 0x31b0, 0x3080);
3091
3092         /* Set GMAC footswitch sleep/wakeup values */
3093         regmap_write(regmap, 0x3cb8, 8);
3094         regmap_write(regmap, 0x3cd8, 8);
3095         regmap_write(regmap, 0x3cf8, 8);
3096         regmap_write(regmap, 0x3d18, 8);
3097
3098         return 0;
3099 }
3100
3101 static struct platform_driver gcc_ipq806x_driver = {
3102         .probe          = gcc_ipq806x_probe,
3103         .driver         = {
3104                 .name   = "gcc-ipq806x",
3105                 .of_match_table = gcc_ipq806x_match_table,
3106         },
3107 };
3108
3109 static int __init gcc_ipq806x_init(void)
3110 {
3111         return platform_driver_register(&gcc_ipq806x_driver);
3112 }
3113 core_initcall(gcc_ipq806x_init);
3114
3115 static void __exit gcc_ipq806x_exit(void)
3116 {
3117         platform_driver_unregister(&gcc_ipq806x_driver);
3118 }
3119 module_exit(gcc_ipq806x_exit);
3120
3121 MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
3122 MODULE_LICENSE("GPL v2");
3123 MODULE_ALIAS("platform:gcc-ipq806x");