Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
[sfrench/cifs-2.6.git] / drivers / clk / meson / gxbb.c
1 /*
2  * AmLogic S905 / GXBB Clock Controller Driver
3  *
4  * Copyright (c) 2016 AmLogic, Inc.
5  * Michael Turquette <mturquette@baylibre.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19
20 #include <linux/clk.h>
21 #include <linux/clk-provider.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/init.h>
26
27 #include "clkc.h"
28 #include "gxbb.h"
29
30 static DEFINE_SPINLOCK(clk_lock);
31
32 static const struct pll_rate_table sys_pll_rate_table[] = {
33         PLL_RATE(24000000, 56, 1, 2),
34         PLL_RATE(48000000, 64, 1, 2),
35         PLL_RATE(72000000, 72, 1, 2),
36         PLL_RATE(96000000, 64, 1, 2),
37         PLL_RATE(120000000, 80, 1, 2),
38         PLL_RATE(144000000, 96, 1, 2),
39         PLL_RATE(168000000, 56, 1, 1),
40         PLL_RATE(192000000, 64, 1, 1),
41         PLL_RATE(216000000, 72, 1, 1),
42         PLL_RATE(240000000, 80, 1, 1),
43         PLL_RATE(264000000, 88, 1, 1),
44         PLL_RATE(288000000, 96, 1, 1),
45         PLL_RATE(312000000, 52, 1, 2),
46         PLL_RATE(336000000, 56, 1, 2),
47         PLL_RATE(360000000, 60, 1, 2),
48         PLL_RATE(384000000, 64, 1, 2),
49         PLL_RATE(408000000, 68, 1, 2),
50         PLL_RATE(432000000, 72, 1, 2),
51         PLL_RATE(456000000, 76, 1, 2),
52         PLL_RATE(480000000, 80, 1, 2),
53         PLL_RATE(504000000, 84, 1, 2),
54         PLL_RATE(528000000, 88, 1, 2),
55         PLL_RATE(552000000, 92, 1, 2),
56         PLL_RATE(576000000, 96, 1, 2),
57         PLL_RATE(600000000, 50, 1, 1),
58         PLL_RATE(624000000, 52, 1, 1),
59         PLL_RATE(648000000, 54, 1, 1),
60         PLL_RATE(672000000, 56, 1, 1),
61         PLL_RATE(696000000, 58, 1, 1),
62         PLL_RATE(720000000, 60, 1, 1),
63         PLL_RATE(744000000, 62, 1, 1),
64         PLL_RATE(768000000, 64, 1, 1),
65         PLL_RATE(792000000, 66, 1, 1),
66         PLL_RATE(816000000, 68, 1, 1),
67         PLL_RATE(840000000, 70, 1, 1),
68         PLL_RATE(864000000, 72, 1, 1),
69         PLL_RATE(888000000, 74, 1, 1),
70         PLL_RATE(912000000, 76, 1, 1),
71         PLL_RATE(936000000, 78, 1, 1),
72         PLL_RATE(960000000, 80, 1, 1),
73         PLL_RATE(984000000, 82, 1, 1),
74         PLL_RATE(1008000000, 84, 1, 1),
75         PLL_RATE(1032000000, 86, 1, 1),
76         PLL_RATE(1056000000, 88, 1, 1),
77         PLL_RATE(1080000000, 90, 1, 1),
78         PLL_RATE(1104000000, 92, 1, 1),
79         PLL_RATE(1128000000, 94, 1, 1),
80         PLL_RATE(1152000000, 96, 1, 1),
81         PLL_RATE(1176000000, 98, 1, 1),
82         PLL_RATE(1200000000, 50, 1, 0),
83         PLL_RATE(1224000000, 51, 1, 0),
84         PLL_RATE(1248000000, 52, 1, 0),
85         PLL_RATE(1272000000, 53, 1, 0),
86         PLL_RATE(1296000000, 54, 1, 0),
87         PLL_RATE(1320000000, 55, 1, 0),
88         PLL_RATE(1344000000, 56, 1, 0),
89         PLL_RATE(1368000000, 57, 1, 0),
90         PLL_RATE(1392000000, 58, 1, 0),
91         PLL_RATE(1416000000, 59, 1, 0),
92         PLL_RATE(1440000000, 60, 1, 0),
93         PLL_RATE(1464000000, 61, 1, 0),
94         PLL_RATE(1488000000, 62, 1, 0),
95         PLL_RATE(1512000000, 63, 1, 0),
96         PLL_RATE(1536000000, 64, 1, 0),
97         PLL_RATE(1560000000, 65, 1, 0),
98         PLL_RATE(1584000000, 66, 1, 0),
99         PLL_RATE(1608000000, 67, 1, 0),
100         PLL_RATE(1632000000, 68, 1, 0),
101         PLL_RATE(1656000000, 68, 1, 0),
102         PLL_RATE(1680000000, 68, 1, 0),
103         PLL_RATE(1704000000, 68, 1, 0),
104         PLL_RATE(1728000000, 69, 1, 0),
105         PLL_RATE(1752000000, 69, 1, 0),
106         PLL_RATE(1776000000, 69, 1, 0),
107         PLL_RATE(1800000000, 69, 1, 0),
108         PLL_RATE(1824000000, 70, 1, 0),
109         PLL_RATE(1848000000, 70, 1, 0),
110         PLL_RATE(1872000000, 70, 1, 0),
111         PLL_RATE(1896000000, 70, 1, 0),
112         PLL_RATE(1920000000, 71, 1, 0),
113         PLL_RATE(1944000000, 71, 1, 0),
114         PLL_RATE(1968000000, 71, 1, 0),
115         PLL_RATE(1992000000, 71, 1, 0),
116         PLL_RATE(2016000000, 72, 1, 0),
117         PLL_RATE(2040000000, 72, 1, 0),
118         PLL_RATE(2064000000, 72, 1, 0),
119         PLL_RATE(2088000000, 72, 1, 0),
120         PLL_RATE(2112000000, 73, 1, 0),
121         { /* sentinel */ },
122 };
123
124 static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = {
125         PLL_RATE(96000000, 32, 1, 3),
126         PLL_RATE(99000000, 33, 1, 3),
127         PLL_RATE(102000000, 34, 1, 3),
128         PLL_RATE(105000000, 35, 1, 3),
129         PLL_RATE(108000000, 36, 1, 3),
130         PLL_RATE(111000000, 37, 1, 3),
131         PLL_RATE(114000000, 38, 1, 3),
132         PLL_RATE(117000000, 39, 1, 3),
133         PLL_RATE(120000000, 40, 1, 3),
134         PLL_RATE(123000000, 41, 1, 3),
135         PLL_RATE(126000000, 42, 1, 3),
136         PLL_RATE(129000000, 43, 1, 3),
137         PLL_RATE(132000000, 44, 1, 3),
138         PLL_RATE(135000000, 45, 1, 3),
139         PLL_RATE(138000000, 46, 1, 3),
140         PLL_RATE(141000000, 47, 1, 3),
141         PLL_RATE(144000000, 48, 1, 3),
142         PLL_RATE(147000000, 49, 1, 3),
143         PLL_RATE(150000000, 50, 1, 3),
144         PLL_RATE(153000000, 51, 1, 3),
145         PLL_RATE(156000000, 52, 1, 3),
146         PLL_RATE(159000000, 53, 1, 3),
147         PLL_RATE(162000000, 54, 1, 3),
148         PLL_RATE(165000000, 55, 1, 3),
149         PLL_RATE(168000000, 56, 1, 3),
150         PLL_RATE(171000000, 57, 1, 3),
151         PLL_RATE(174000000, 58, 1, 3),
152         PLL_RATE(177000000, 59, 1, 3),
153         PLL_RATE(180000000, 60, 1, 3),
154         PLL_RATE(183000000, 61, 1, 3),
155         PLL_RATE(186000000, 62, 1, 3),
156         PLL_RATE(192000000, 32, 1, 2),
157         PLL_RATE(198000000, 33, 1, 2),
158         PLL_RATE(204000000, 34, 1, 2),
159         PLL_RATE(210000000, 35, 1, 2),
160         PLL_RATE(216000000, 36, 1, 2),
161         PLL_RATE(222000000, 37, 1, 2),
162         PLL_RATE(228000000, 38, 1, 2),
163         PLL_RATE(234000000, 39, 1, 2),
164         PLL_RATE(240000000, 40, 1, 2),
165         PLL_RATE(246000000, 41, 1, 2),
166         PLL_RATE(252000000, 42, 1, 2),
167         PLL_RATE(258000000, 43, 1, 2),
168         PLL_RATE(264000000, 44, 1, 2),
169         PLL_RATE(270000000, 45, 1, 2),
170         PLL_RATE(276000000, 46, 1, 2),
171         PLL_RATE(282000000, 47, 1, 2),
172         PLL_RATE(288000000, 48, 1, 2),
173         PLL_RATE(294000000, 49, 1, 2),
174         PLL_RATE(300000000, 50, 1, 2),
175         PLL_RATE(306000000, 51, 1, 2),
176         PLL_RATE(312000000, 52, 1, 2),
177         PLL_RATE(318000000, 53, 1, 2),
178         PLL_RATE(324000000, 54, 1, 2),
179         PLL_RATE(330000000, 55, 1, 2),
180         PLL_RATE(336000000, 56, 1, 2),
181         PLL_RATE(342000000, 57, 1, 2),
182         PLL_RATE(348000000, 58, 1, 2),
183         PLL_RATE(354000000, 59, 1, 2),
184         PLL_RATE(360000000, 60, 1, 2),
185         PLL_RATE(366000000, 61, 1, 2),
186         PLL_RATE(372000000, 62, 1, 2),
187         PLL_RATE(384000000, 32, 1, 1),
188         PLL_RATE(396000000, 33, 1, 1),
189         PLL_RATE(408000000, 34, 1, 1),
190         PLL_RATE(420000000, 35, 1, 1),
191         PLL_RATE(432000000, 36, 1, 1),
192         PLL_RATE(444000000, 37, 1, 1),
193         PLL_RATE(456000000, 38, 1, 1),
194         PLL_RATE(468000000, 39, 1, 1),
195         PLL_RATE(480000000, 40, 1, 1),
196         PLL_RATE(492000000, 41, 1, 1),
197         PLL_RATE(504000000, 42, 1, 1),
198         PLL_RATE(516000000, 43, 1, 1),
199         PLL_RATE(528000000, 44, 1, 1),
200         PLL_RATE(540000000, 45, 1, 1),
201         PLL_RATE(552000000, 46, 1, 1),
202         PLL_RATE(564000000, 47, 1, 1),
203         PLL_RATE(576000000, 48, 1, 1),
204         PLL_RATE(588000000, 49, 1, 1),
205         PLL_RATE(600000000, 50, 1, 1),
206         PLL_RATE(612000000, 51, 1, 1),
207         PLL_RATE(624000000, 52, 1, 1),
208         PLL_RATE(636000000, 53, 1, 1),
209         PLL_RATE(648000000, 54, 1, 1),
210         PLL_RATE(660000000, 55, 1, 1),
211         PLL_RATE(672000000, 56, 1, 1),
212         PLL_RATE(684000000, 57, 1, 1),
213         PLL_RATE(696000000, 58, 1, 1),
214         PLL_RATE(708000000, 59, 1, 1),
215         PLL_RATE(720000000, 60, 1, 1),
216         PLL_RATE(732000000, 61, 1, 1),
217         PLL_RATE(744000000, 62, 1, 1),
218         PLL_RATE(768000000, 32, 1, 0),
219         PLL_RATE(792000000, 33, 1, 0),
220         PLL_RATE(816000000, 34, 1, 0),
221         PLL_RATE(840000000, 35, 1, 0),
222         PLL_RATE(864000000, 36, 1, 0),
223         PLL_RATE(888000000, 37, 1, 0),
224         PLL_RATE(912000000, 38, 1, 0),
225         PLL_RATE(936000000, 39, 1, 0),
226         PLL_RATE(960000000, 40, 1, 0),
227         PLL_RATE(984000000, 41, 1, 0),
228         PLL_RATE(1008000000, 42, 1, 0),
229         PLL_RATE(1032000000, 43, 1, 0),
230         PLL_RATE(1056000000, 44, 1, 0),
231         PLL_RATE(1080000000, 45, 1, 0),
232         PLL_RATE(1104000000, 46, 1, 0),
233         PLL_RATE(1128000000, 47, 1, 0),
234         PLL_RATE(1152000000, 48, 1, 0),
235         PLL_RATE(1176000000, 49, 1, 0),
236         PLL_RATE(1200000000, 50, 1, 0),
237         PLL_RATE(1224000000, 51, 1, 0),
238         PLL_RATE(1248000000, 52, 1, 0),
239         PLL_RATE(1272000000, 53, 1, 0),
240         PLL_RATE(1296000000, 54, 1, 0),
241         PLL_RATE(1320000000, 55, 1, 0),
242         PLL_RATE(1344000000, 56, 1, 0),
243         PLL_RATE(1368000000, 57, 1, 0),
244         PLL_RATE(1392000000, 58, 1, 0),
245         PLL_RATE(1416000000, 59, 1, 0),
246         PLL_RATE(1440000000, 60, 1, 0),
247         PLL_RATE(1464000000, 61, 1, 0),
248         PLL_RATE(1488000000, 62, 1, 0),
249         { /* sentinel */ },
250 };
251
252 static const struct pll_rate_table gxl_gp0_pll_rate_table[] = {
253         PLL_RATE(504000000, 42, 1, 1),
254         PLL_RATE(516000000, 43, 1, 1),
255         PLL_RATE(528000000, 44, 1, 1),
256         PLL_RATE(540000000, 45, 1, 1),
257         PLL_RATE(552000000, 46, 1, 1),
258         PLL_RATE(564000000, 47, 1, 1),
259         PLL_RATE(576000000, 48, 1, 1),
260         PLL_RATE(588000000, 49, 1, 1),
261         PLL_RATE(600000000, 50, 1, 1),
262         PLL_RATE(612000000, 51, 1, 1),
263         PLL_RATE(624000000, 52, 1, 1),
264         PLL_RATE(636000000, 53, 1, 1),
265         PLL_RATE(648000000, 54, 1, 1),
266         PLL_RATE(660000000, 55, 1, 1),
267         PLL_RATE(672000000, 56, 1, 1),
268         PLL_RATE(684000000, 57, 1, 1),
269         PLL_RATE(696000000, 58, 1, 1),
270         PLL_RATE(708000000, 59, 1, 1),
271         PLL_RATE(720000000, 60, 1, 1),
272         PLL_RATE(732000000, 61, 1, 1),
273         PLL_RATE(744000000, 62, 1, 1),
274         PLL_RATE(756000000, 63, 1, 1),
275         PLL_RATE(768000000, 64, 1, 1),
276         PLL_RATE(780000000, 65, 1, 1),
277         PLL_RATE(792000000, 66, 1, 1),
278         { /* sentinel */ },
279 };
280
281 static struct meson_clk_pll gxbb_fixed_pll = {
282         .m = {
283                 .reg_off = HHI_MPLL_CNTL,
284                 .shift   = 0,
285                 .width   = 9,
286         },
287         .n = {
288                 .reg_off = HHI_MPLL_CNTL,
289                 .shift   = 9,
290                 .width   = 5,
291         },
292         .od = {
293                 .reg_off = HHI_MPLL_CNTL,
294                 .shift   = 16,
295                 .width   = 2,
296         },
297         .lock = &clk_lock,
298         .hw.init = &(struct clk_init_data){
299                 .name = "fixed_pll",
300                 .ops = &meson_clk_pll_ro_ops,
301                 .parent_names = (const char *[]){ "xtal" },
302                 .num_parents = 1,
303                 .flags = CLK_GET_RATE_NOCACHE,
304         },
305 };
306
307 static struct meson_clk_pll gxbb_hdmi_pll = {
308         .m = {
309                 .reg_off = HHI_HDMI_PLL_CNTL,
310                 .shift   = 0,
311                 .width   = 9,
312         },
313         .n = {
314                 .reg_off = HHI_HDMI_PLL_CNTL,
315                 .shift   = 9,
316                 .width   = 5,
317         },
318         .frac = {
319                 .reg_off = HHI_HDMI_PLL_CNTL2,
320                 .shift   = 0,
321                 .width   = 12,
322         },
323         .od = {
324                 .reg_off = HHI_HDMI_PLL_CNTL2,
325                 .shift   = 16,
326                 .width   = 2,
327         },
328         .od2 = {
329                 .reg_off = HHI_HDMI_PLL_CNTL2,
330                 .shift   = 22,
331                 .width   = 2,
332         },
333         .lock = &clk_lock,
334         .hw.init = &(struct clk_init_data){
335                 .name = "hdmi_pll",
336                 .ops = &meson_clk_pll_ro_ops,
337                 .parent_names = (const char *[]){ "xtal" },
338                 .num_parents = 1,
339                 .flags = CLK_GET_RATE_NOCACHE,
340         },
341 };
342
343 static struct meson_clk_pll gxbb_sys_pll = {
344         .m = {
345                 .reg_off = HHI_SYS_PLL_CNTL,
346                 .shift   = 0,
347                 .width   = 9,
348         },
349         .n = {
350                 .reg_off = HHI_SYS_PLL_CNTL,
351                 .shift   = 9,
352                 .width   = 5,
353         },
354         .od = {
355                 .reg_off = HHI_SYS_PLL_CNTL,
356                 .shift   = 10,
357                 .width   = 2,
358         },
359         .rate_table = sys_pll_rate_table,
360         .rate_count = ARRAY_SIZE(sys_pll_rate_table),
361         .lock = &clk_lock,
362         .hw.init = &(struct clk_init_data){
363                 .name = "sys_pll",
364                 .ops = &meson_clk_pll_ro_ops,
365                 .parent_names = (const char *[]){ "xtal" },
366                 .num_parents = 1,
367                 .flags = CLK_GET_RATE_NOCACHE,
368         },
369 };
370
371 struct pll_params_table gxbb_gp0_params_table[] = {
372         PLL_PARAM(HHI_GP0_PLL_CNTL, 0x6a000228),
373         PLL_PARAM(HHI_GP0_PLL_CNTL2, 0x69c80000),
374         PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a5590c4),
375         PLL_PARAM(HHI_GP0_PLL_CNTL4, 0x0000500d),
376 };
377
378 static struct meson_clk_pll gxbb_gp0_pll = {
379         .m = {
380                 .reg_off = HHI_GP0_PLL_CNTL,
381                 .shift   = 0,
382                 .width   = 9,
383         },
384         .n = {
385                 .reg_off = HHI_GP0_PLL_CNTL,
386                 .shift   = 9,
387                 .width   = 5,
388         },
389         .od = {
390                 .reg_off = HHI_GP0_PLL_CNTL,
391                 .shift   = 16,
392                 .width   = 2,
393         },
394         .params = {
395                 .params_table = gxbb_gp0_params_table,
396                 .params_count = ARRAY_SIZE(gxbb_gp0_params_table),
397                 .no_init_reset = true,
398                 .clear_reset_for_lock = true,
399         },
400         .rate_table = gxbb_gp0_pll_rate_table,
401         .rate_count = ARRAY_SIZE(gxbb_gp0_pll_rate_table),
402         .lock = &clk_lock,
403         .hw.init = &(struct clk_init_data){
404                 .name = "gp0_pll",
405                 .ops = &meson_clk_pll_ops,
406                 .parent_names = (const char *[]){ "xtal" },
407                 .num_parents = 1,
408                 .flags = CLK_GET_RATE_NOCACHE,
409         },
410 };
411
412 struct pll_params_table gxl_gp0_params_table[] = {
413         PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250),
414         PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000),
415         PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be),
416         PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288),
417         PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d),
418         PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000),
419 };
420
421 static struct meson_clk_pll gxl_gp0_pll = {
422         .m = {
423                 .reg_off = HHI_GP0_PLL_CNTL,
424                 .shift   = 0,
425                 .width   = 9,
426         },
427         .n = {
428                 .reg_off = HHI_GP0_PLL_CNTL,
429                 .shift   = 9,
430                 .width   = 5,
431         },
432         .od = {
433                 .reg_off = HHI_GP0_PLL_CNTL,
434                 .shift   = 16,
435                 .width   = 2,
436         },
437         .params = {
438                 .params_table = gxl_gp0_params_table,
439                 .params_count = ARRAY_SIZE(gxl_gp0_params_table),
440                 .no_init_reset = true,
441                 .reset_lock_loop = true,
442         },
443         .rate_table = gxl_gp0_pll_rate_table,
444         .rate_count = ARRAY_SIZE(gxl_gp0_pll_rate_table),
445         .lock = &clk_lock,
446         .hw.init = &(struct clk_init_data){
447                 .name = "gp0_pll",
448                 .ops = &meson_clk_pll_ops,
449                 .parent_names = (const char *[]){ "xtal" },
450                 .num_parents = 1,
451                 .flags = CLK_GET_RATE_NOCACHE,
452         },
453 };
454
455 static struct clk_fixed_factor gxbb_fclk_div2 = {
456         .mult = 1,
457         .div = 2,
458         .hw.init = &(struct clk_init_data){
459                 .name = "fclk_div2",
460                 .ops = &clk_fixed_factor_ops,
461                 .parent_names = (const char *[]){ "fixed_pll" },
462                 .num_parents = 1,
463         },
464 };
465
466 static struct clk_fixed_factor gxbb_fclk_div3 = {
467         .mult = 1,
468         .div = 3,
469         .hw.init = &(struct clk_init_data){
470                 .name = "fclk_div3",
471                 .ops = &clk_fixed_factor_ops,
472                 .parent_names = (const char *[]){ "fixed_pll" },
473                 .num_parents = 1,
474         },
475 };
476
477 static struct clk_fixed_factor gxbb_fclk_div4 = {
478         .mult = 1,
479         .div = 4,
480         .hw.init = &(struct clk_init_data){
481                 .name = "fclk_div4",
482                 .ops = &clk_fixed_factor_ops,
483                 .parent_names = (const char *[]){ "fixed_pll" },
484                 .num_parents = 1,
485         },
486 };
487
488 static struct clk_fixed_factor gxbb_fclk_div5 = {
489         .mult = 1,
490         .div = 5,
491         .hw.init = &(struct clk_init_data){
492                 .name = "fclk_div5",
493                 .ops = &clk_fixed_factor_ops,
494                 .parent_names = (const char *[]){ "fixed_pll" },
495                 .num_parents = 1,
496         },
497 };
498
499 static struct clk_fixed_factor gxbb_fclk_div7 = {
500         .mult = 1,
501         .div = 7,
502         .hw.init = &(struct clk_init_data){
503                 .name = "fclk_div7",
504                 .ops = &clk_fixed_factor_ops,
505                 .parent_names = (const char *[]){ "fixed_pll" },
506                 .num_parents = 1,
507         },
508 };
509
510 static struct meson_clk_mpll gxbb_mpll0 = {
511         .sdm = {
512                 .reg_off = HHI_MPLL_CNTL7,
513                 .shift   = 0,
514                 .width   = 14,
515         },
516         .sdm_en = {
517                 .reg_off = HHI_MPLL_CNTL7,
518                 .shift   = 15,
519                 .width   = 1,
520         },
521         .n2 = {
522                 .reg_off = HHI_MPLL_CNTL7,
523                 .shift   = 16,
524                 .width   = 9,
525         },
526         .en = {
527                 .reg_off = HHI_MPLL_CNTL7,
528                 .shift   = 14,
529                 .width   = 1,
530         },
531         .ssen = {
532                 .reg_off = HHI_MPLL_CNTL,
533                 .shift   = 25,
534                 .width   = 1,
535         },
536         .lock = &clk_lock,
537         .hw.init = &(struct clk_init_data){
538                 .name = "mpll0",
539                 .ops = &meson_clk_mpll_ops,
540                 .parent_names = (const char *[]){ "fixed_pll" },
541                 .num_parents = 1,
542         },
543 };
544
545 static struct meson_clk_mpll gxbb_mpll1 = {
546         .sdm = {
547                 .reg_off = HHI_MPLL_CNTL8,
548                 .shift   = 0,
549                 .width   = 14,
550         },
551         .sdm_en = {
552                 .reg_off = HHI_MPLL_CNTL8,
553                 .shift   = 15,
554                 .width   = 1,
555         },
556         .n2 = {
557                 .reg_off = HHI_MPLL_CNTL8,
558                 .shift   = 16,
559                 .width   = 9,
560         },
561         .en = {
562                 .reg_off = HHI_MPLL_CNTL8,
563                 .shift   = 14,
564                 .width   = 1,
565         },
566         .lock = &clk_lock,
567         .hw.init = &(struct clk_init_data){
568                 .name = "mpll1",
569                 .ops = &meson_clk_mpll_ops,
570                 .parent_names = (const char *[]){ "fixed_pll" },
571                 .num_parents = 1,
572         },
573 };
574
575 static struct meson_clk_mpll gxbb_mpll2 = {
576         .sdm = {
577                 .reg_off = HHI_MPLL_CNTL9,
578                 .shift   = 0,
579                 .width   = 14,
580         },
581         .sdm_en = {
582                 .reg_off = HHI_MPLL_CNTL9,
583                 .shift   = 15,
584                 .width   = 1,
585         },
586         .n2 = {
587                 .reg_off = HHI_MPLL_CNTL9,
588                 .shift   = 16,
589                 .width   = 9,
590         },
591         .en = {
592                 .reg_off = HHI_MPLL_CNTL9,
593                 .shift   = 14,
594                 .width   = 1,
595         },
596         .lock = &clk_lock,
597         .hw.init = &(struct clk_init_data){
598                 .name = "mpll2",
599                 .ops = &meson_clk_mpll_ops,
600                 .parent_names = (const char *[]){ "fixed_pll" },
601                 .num_parents = 1,
602         },
603 };
604
605 /*
606  * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers
607  * and should be modeled with their respective PLLs via the forthcoming
608  * coordinated clock rates feature
609  */
610
611 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
612 static const char * const clk81_parent_names[] = {
613         "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
614         "fclk_div3", "fclk_div5"
615 };
616
617 static struct clk_mux gxbb_mpeg_clk_sel = {
618         .reg = (void *)HHI_MPEG_CLK_CNTL,
619         .mask = 0x7,
620         .shift = 12,
621         .flags = CLK_MUX_READ_ONLY,
622         .table = mux_table_clk81,
623         .lock = &clk_lock,
624         .hw.init = &(struct clk_init_data){
625                 .name = "mpeg_clk_sel",
626                 .ops = &clk_mux_ro_ops,
627                 /*
628                  * bits 14:12 selects from 8 possible parents:
629                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
630                  * fclk_div4, fclk_div3, fclk_div5
631                  */
632                 .parent_names = clk81_parent_names,
633                 .num_parents = ARRAY_SIZE(clk81_parent_names),
634                 .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
635         },
636 };
637
638 static struct clk_divider gxbb_mpeg_clk_div = {
639         .reg = (void *)HHI_MPEG_CLK_CNTL,
640         .shift = 0,
641         .width = 7,
642         .lock = &clk_lock,
643         .hw.init = &(struct clk_init_data){
644                 .name = "mpeg_clk_div",
645                 .ops = &clk_divider_ops,
646                 .parent_names = (const char *[]){ "mpeg_clk_sel" },
647                 .num_parents = 1,
648                 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
649         },
650 };
651
652 /* the mother of dragons^W gates */
653 static struct clk_gate gxbb_clk81 = {
654         .reg = (void *)HHI_MPEG_CLK_CNTL,
655         .bit_idx = 7,
656         .lock = &clk_lock,
657         .hw.init = &(struct clk_init_data){
658                 .name = "clk81",
659                 .ops = &clk_gate_ops,
660                 .parent_names = (const char *[]){ "mpeg_clk_div" },
661                 .num_parents = 1,
662                 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
663         },
664 };
665
666 static struct clk_mux gxbb_sar_adc_clk_sel = {
667         .reg = (void *)HHI_SAR_CLK_CNTL,
668         .mask = 0x3,
669         .shift = 9,
670         .lock = &clk_lock,
671         .hw.init = &(struct clk_init_data){
672                 .name = "sar_adc_clk_sel",
673                 .ops = &clk_mux_ops,
674                 /* NOTE: The datasheet doesn't list the parents for bit 10 */
675                 .parent_names = (const char *[]){ "xtal", "clk81", },
676                 .num_parents = 2,
677         },
678 };
679
680 static struct clk_divider gxbb_sar_adc_clk_div = {
681         .reg = (void *)HHI_SAR_CLK_CNTL,
682         .shift = 0,
683         .width = 8,
684         .lock = &clk_lock,
685         .hw.init = &(struct clk_init_data){
686                 .name = "sar_adc_clk_div",
687                 .ops = &clk_divider_ops,
688                 .parent_names = (const char *[]){ "sar_adc_clk_sel" },
689                 .num_parents = 1,
690         },
691 };
692
693 static struct clk_gate gxbb_sar_adc_clk = {
694         .reg = (void *)HHI_SAR_CLK_CNTL,
695         .bit_idx = 8,
696         .lock = &clk_lock,
697         .hw.init = &(struct clk_init_data){
698                 .name = "sar_adc_clk",
699                 .ops = &clk_gate_ops,
700                 .parent_names = (const char *[]){ "sar_adc_clk_div" },
701                 .num_parents = 1,
702                 .flags = CLK_SET_RATE_PARENT,
703         },
704 };
705
706 /*
707  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
708  * muxed by a glitch-free switch.
709  */
710
711 static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7};
712 static const char * const gxbb_mali_0_1_parent_names[] = {
713         "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
714         "fclk_div4", "fclk_div3", "fclk_div5"
715 };
716
717 static struct clk_mux gxbb_mali_0_sel = {
718         .reg = (void *)HHI_MALI_CLK_CNTL,
719         .mask = 0x7,
720         .shift = 9,
721         .table = mux_table_mali_0_1,
722         .lock = &clk_lock,
723         .hw.init = &(struct clk_init_data){
724                 .name = "mali_0_sel",
725                 .ops = &clk_mux_ops,
726                 /*
727                  * bits 10:9 selects from 8 possible parents:
728                  * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
729                  * fclk_div4, fclk_div3, fclk_div5
730                  */
731                 .parent_names = gxbb_mali_0_1_parent_names,
732                 .num_parents = 8,
733                 .flags = CLK_SET_RATE_NO_REPARENT,
734         },
735 };
736
737 static struct clk_divider gxbb_mali_0_div = {
738         .reg = (void *)HHI_MALI_CLK_CNTL,
739         .shift = 0,
740         .width = 7,
741         .lock = &clk_lock,
742         .hw.init = &(struct clk_init_data){
743                 .name = "mali_0_div",
744                 .ops = &clk_divider_ops,
745                 .parent_names = (const char *[]){ "mali_0_sel" },
746                 .num_parents = 1,
747                 .flags = CLK_SET_RATE_NO_REPARENT,
748         },
749 };
750
751 static struct clk_gate gxbb_mali_0 = {
752         .reg = (void *)HHI_MALI_CLK_CNTL,
753         .bit_idx = 8,
754         .lock = &clk_lock,
755         .hw.init = &(struct clk_init_data){
756                 .name = "mali_0",
757                 .ops = &clk_gate_ops,
758                 .parent_names = (const char *[]){ "mali_0_div" },
759                 .num_parents = 1,
760                 .flags = CLK_SET_RATE_PARENT,
761         },
762 };
763
764 static struct clk_mux gxbb_mali_1_sel = {
765         .reg = (void *)HHI_MALI_CLK_CNTL,
766         .mask = 0x7,
767         .shift = 25,
768         .table = mux_table_mali_0_1,
769         .lock = &clk_lock,
770         .hw.init = &(struct clk_init_data){
771                 .name = "mali_1_sel",
772                 .ops = &clk_mux_ops,
773                 /*
774                  * bits 10:9 selects from 8 possible parents:
775                  * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
776                  * fclk_div4, fclk_div3, fclk_div5
777                  */
778                 .parent_names = gxbb_mali_0_1_parent_names,
779                 .num_parents = 8,
780                 .flags = CLK_SET_RATE_NO_REPARENT,
781         },
782 };
783
784 static struct clk_divider gxbb_mali_1_div = {
785         .reg = (void *)HHI_MALI_CLK_CNTL,
786         .shift = 16,
787         .width = 7,
788         .lock = &clk_lock,
789         .hw.init = &(struct clk_init_data){
790                 .name = "mali_1_div",
791                 .ops = &clk_divider_ops,
792                 .parent_names = (const char *[]){ "mali_1_sel" },
793                 .num_parents = 1,
794                 .flags = CLK_SET_RATE_NO_REPARENT,
795         },
796 };
797
798 static struct clk_gate gxbb_mali_1 = {
799         .reg = (void *)HHI_MALI_CLK_CNTL,
800         .bit_idx = 24,
801         .lock = &clk_lock,
802         .hw.init = &(struct clk_init_data){
803                 .name = "mali_1",
804                 .ops = &clk_gate_ops,
805                 .parent_names = (const char *[]){ "mali_1_div" },
806                 .num_parents = 1,
807                 .flags = CLK_SET_RATE_PARENT,
808         },
809 };
810
811 static u32 mux_table_mali[] = {0, 1};
812 static const char * const gxbb_mali_parent_names[] = {
813         "mali_0", "mali_1"
814 };
815
816 static struct clk_mux gxbb_mali = {
817         .reg = (void *)HHI_MALI_CLK_CNTL,
818         .mask = 1,
819         .shift = 31,
820         .table = mux_table_mali,
821         .lock = &clk_lock,
822         .hw.init = &(struct clk_init_data){
823                 .name = "mali",
824                 .ops = &clk_mux_ops,
825                 .parent_names = gxbb_mali_parent_names,
826                 .num_parents = 2,
827                 .flags = CLK_SET_RATE_NO_REPARENT,
828         },
829 };
830
831 static struct clk_mux gxbb_cts_amclk_sel = {
832         .reg = (void *) HHI_AUD_CLK_CNTL,
833         .mask = 0x3,
834         .shift = 9,
835         /* Default parent unknown (register reset value: 0) */
836         .table = (u32[]){ 1, 2, 3 },
837         .lock = &clk_lock,
838                 .hw.init = &(struct clk_init_data){
839                 .name = "cts_amclk_sel",
840                 .ops = &clk_mux_ops,
841                 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
842                 .num_parents = 3,
843                 .flags = CLK_SET_RATE_PARENT,
844         },
845 };
846
847 static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
848         .div = {
849                 .reg_off = HHI_AUD_CLK_CNTL,
850                 .shift   = 0,
851                 .width   = 8,
852         },
853         .flags = CLK_DIVIDER_ROUND_CLOSEST,
854         .lock = &clk_lock,
855         .hw.init = &(struct clk_init_data){
856                 .name = "cts_amclk_div",
857                 .ops = &meson_clk_audio_divider_ops,
858                 .parent_names = (const char *[]){ "cts_amclk_sel" },
859                 .num_parents = 1,
860                 .flags = CLK_SET_RATE_PARENT,
861         },
862 };
863
864 static struct clk_gate gxbb_cts_amclk = {
865         .reg = (void *) HHI_AUD_CLK_CNTL,
866         .bit_idx = 8,
867         .lock = &clk_lock,
868         .hw.init = &(struct clk_init_data){
869                 .name = "cts_amclk",
870                 .ops = &clk_gate_ops,
871                 .parent_names = (const char *[]){ "cts_amclk_div" },
872                 .num_parents = 1,
873                 .flags = CLK_SET_RATE_PARENT,
874         },
875 };
876
877 static struct clk_mux gxbb_cts_mclk_i958_sel = {
878         .reg = (void *)HHI_AUD_CLK_CNTL2,
879         .mask = 0x3,
880         .shift = 25,
881         /* Default parent unknown (register reset value: 0) */
882         .table = (u32[]){ 1, 2, 3 },
883         .lock = &clk_lock,
884         .hw.init = &(struct clk_init_data) {
885                 .name = "cts_mclk_i958_sel",
886                 .ops = &clk_mux_ops,
887                 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
888                 .num_parents = 3,
889                 .flags = CLK_SET_RATE_PARENT,
890         },
891 };
892
893 static struct clk_divider gxbb_cts_mclk_i958_div = {
894         .reg = (void *)HHI_AUD_CLK_CNTL2,
895         .shift = 16,
896         .width = 8,
897         .lock = &clk_lock,
898         .flags = CLK_DIVIDER_ROUND_CLOSEST,
899         .hw.init = &(struct clk_init_data) {
900                 .name = "cts_mclk_i958_div",
901                 .ops = &clk_divider_ops,
902                 .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
903                 .num_parents = 1,
904                 .flags = CLK_SET_RATE_PARENT,
905         },
906 };
907
908 static struct clk_gate gxbb_cts_mclk_i958 = {
909         .reg = (void *)HHI_AUD_CLK_CNTL2,
910         .bit_idx = 24,
911         .lock = &clk_lock,
912         .hw.init = &(struct clk_init_data){
913                 .name = "cts_mclk_i958",
914                 .ops = &clk_gate_ops,
915                 .parent_names = (const char *[]){ "cts_mclk_i958_div" },
916                 .num_parents = 1,
917                 .flags = CLK_SET_RATE_PARENT,
918         },
919 };
920
921 static struct clk_mux gxbb_cts_i958 = {
922         .reg = (void *)HHI_AUD_CLK_CNTL2,
923         .mask = 0x1,
924         .shift = 27,
925         .lock = &clk_lock,
926                 .hw.init = &(struct clk_init_data){
927                 .name = "cts_i958",
928                 .ops = &clk_mux_ops,
929                 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
930                 .num_parents = 2,
931                 /*
932                  *The parent is specific to origin of the audio data. Let the
933                  * consumer choose the appropriate parent
934                  */
935                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
936         },
937 };
938
939 static struct clk_divider gxbb_32k_clk_div = {
940         .reg = (void *)HHI_32K_CLK_CNTL,
941         .shift = 0,
942         .width = 14,
943         .lock = &clk_lock,
944         .hw.init = &(struct clk_init_data){
945                 .name = "32k_clk_div",
946                 .ops = &clk_divider_ops,
947                 .parent_names = (const char *[]){ "32k_clk_sel" },
948                 .num_parents = 1,
949                 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
950         },
951 };
952
953 static struct clk_gate gxbb_32k_clk = {
954         .reg = (void *)HHI_32K_CLK_CNTL,
955         .bit_idx = 15,
956         .lock = &clk_lock,
957         .hw.init = &(struct clk_init_data){
958                 .name = "32k_clk",
959                 .ops = &clk_gate_ops,
960                 .parent_names = (const char *[]){ "32k_clk_div" },
961                 .num_parents = 1,
962                 .flags = CLK_SET_RATE_PARENT,
963         },
964 };
965
966 static const char * const gxbb_32k_clk_parent_names[] = {
967         "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
968 };
969
970 static struct clk_mux gxbb_32k_clk_sel = {
971         .reg = (void *)HHI_32K_CLK_CNTL,
972         .mask = 0x3,
973         .shift = 16,
974         .lock = &clk_lock,
975                 .hw.init = &(struct clk_init_data){
976                 .name = "32k_clk_sel",
977                 .ops = &clk_mux_ops,
978                 .parent_names = gxbb_32k_clk_parent_names,
979                 .num_parents = 4,
980                 .flags = CLK_SET_RATE_PARENT,
981         },
982 };
983
984 static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
985         "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
986
987         /*
988          * Following these parent clocks, we should also have had mpll2, mpll3
989          * and gp0_pll but these clocks are too precious to be used here. All
990          * the necessary rates for MMC and NAND operation can be acheived using
991          * xtal or fclk_div clocks
992          */
993 };
994
995 /* SDIO clock */
996 static struct clk_mux gxbb_sd_emmc_a_clk0_sel = {
997         .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
998         .mask = 0x7,
999         .shift = 9,
1000         .lock = &clk_lock,
1001         .hw.init = &(struct clk_init_data) {
1002                 .name = "sd_emmc_a_clk0_sel",
1003                 .ops = &clk_mux_ops,
1004                 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1005                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1006                 .flags = CLK_SET_RATE_PARENT,
1007         },
1008 };
1009
1010 static struct clk_divider gxbb_sd_emmc_a_clk0_div = {
1011         .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1012         .shift = 0,
1013         .width = 7,
1014         .lock = &clk_lock,
1015         .flags = CLK_DIVIDER_ROUND_CLOSEST,
1016         .hw.init = &(struct clk_init_data) {
1017                 .name = "sd_emmc_a_clk0_div",
1018                 .ops = &clk_divider_ops,
1019                 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
1020                 .num_parents = 1,
1021                 .flags = CLK_SET_RATE_PARENT,
1022         },
1023 };
1024
1025 static struct clk_gate gxbb_sd_emmc_a_clk0 = {
1026         .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1027         .bit_idx = 7,
1028         .lock = &clk_lock,
1029         .hw.init = &(struct clk_init_data){
1030                 .name = "sd_emmc_a_clk0",
1031                 .ops = &clk_gate_ops,
1032                 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
1033                 .num_parents = 1,
1034
1035                 /*
1036                  * FIXME:
1037                  * We need CLK_IGNORE_UNUSED because mmc DT node point to xtal
1038                  * instead of this clock. CCF would gate this on boot, killing
1039                  * the mmc controller. Please remove this flag once DT properly
1040                  * point to this clock instead of xtal
1041                  *
1042                  * Same goes for emmc B and C clocks
1043                  */
1044                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1045         },
1046 };
1047
1048 /* SDcard clock */
1049 static struct clk_mux gxbb_sd_emmc_b_clk0_sel = {
1050         .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1051         .mask = 0x7,
1052         .shift = 25,
1053         .lock = &clk_lock,
1054         .hw.init = &(struct clk_init_data) {
1055                 .name = "sd_emmc_b_clk0_sel",
1056                 .ops = &clk_mux_ops,
1057                 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1058                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1059                 .flags = CLK_SET_RATE_PARENT,
1060         },
1061 };
1062
1063 static struct clk_divider gxbb_sd_emmc_b_clk0_div = {
1064         .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1065         .shift = 16,
1066         .width = 7,
1067         .lock = &clk_lock,
1068         .flags = CLK_DIVIDER_ROUND_CLOSEST,
1069         .hw.init = &(struct clk_init_data) {
1070                 .name = "sd_emmc_b_clk0_div",
1071                 .ops = &clk_divider_ops,
1072                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
1073                 .num_parents = 1,
1074                 .flags = CLK_SET_RATE_PARENT,
1075         },
1076 };
1077
1078 static struct clk_gate gxbb_sd_emmc_b_clk0 = {
1079         .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1080         .bit_idx = 23,
1081         .lock = &clk_lock,
1082         .hw.init = &(struct clk_init_data){
1083                 .name = "sd_emmc_b_clk0",
1084                 .ops = &clk_gate_ops,
1085                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
1086                 .num_parents = 1,
1087                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1088         },
1089 };
1090
1091 /* EMMC/NAND clock */
1092 static struct clk_mux gxbb_sd_emmc_c_clk0_sel = {
1093         .reg = (void *)HHI_NAND_CLK_CNTL,
1094         .mask = 0x7,
1095         .shift = 9,
1096         .lock = &clk_lock,
1097         .hw.init = &(struct clk_init_data) {
1098                 .name = "sd_emmc_c_clk0_sel",
1099                 .ops = &clk_mux_ops,
1100                 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1101                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1102                 .flags = CLK_SET_RATE_PARENT,
1103         },
1104 };
1105
1106 static struct clk_divider gxbb_sd_emmc_c_clk0_div = {
1107         .reg = (void *)HHI_NAND_CLK_CNTL,
1108         .shift = 0,
1109         .width = 7,
1110         .lock = &clk_lock,
1111         .flags = CLK_DIVIDER_ROUND_CLOSEST,
1112         .hw.init = &(struct clk_init_data) {
1113                 .name = "sd_emmc_c_clk0_div",
1114                 .ops = &clk_divider_ops,
1115                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
1116                 .num_parents = 1,
1117                 .flags = CLK_SET_RATE_PARENT,
1118         },
1119 };
1120
1121 static struct clk_gate gxbb_sd_emmc_c_clk0 = {
1122         .reg = (void *)HHI_NAND_CLK_CNTL,
1123         .bit_idx = 7,
1124         .lock = &clk_lock,
1125         .hw.init = &(struct clk_init_data){
1126                 .name = "sd_emmc_c_clk0",
1127                 .ops = &clk_gate_ops,
1128                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
1129                 .num_parents = 1,
1130                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1131         },
1132 };
1133
1134 /* Everything Else (EE) domain gates */
1135 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
1136 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
1137 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
1138 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
1139 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
1140 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
1141 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
1142 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10);
1143 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
1144 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
1145 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
1146 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
1147 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
1148 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
1149 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
1150 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
1151 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
1152 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
1153 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
1154 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
1155 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
1156 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
1157
1158 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
1159 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
1160 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
1161 static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
1162 static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
1163 static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
1164 static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
1165 static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
1166 static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
1167 static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
1168 static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
1169 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
1170 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
1171 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
1172 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
1173 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
1174 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
1175 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
1176 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
1177 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
1178 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
1179 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
1180 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
1181 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
1182 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
1183
1184 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1185 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1186 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
1187 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
1188 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
1189 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
1190 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
1191 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
1192 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
1193 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22);
1194 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
1195 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1196 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
1197
1198 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
1199 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
1200 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
1201 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
1202 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
1203 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
1204 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
1205 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
1206 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
1207 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
1208 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
1209 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
1210 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
1211 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
1212 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
1213 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
1214
1215 /* Always On (AO) domain gates */
1216
1217 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
1218 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
1219 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
1220 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
1221 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
1222
1223 /* Array of all clocks provided by this provider */
1224
1225 static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
1226         .hws = {
1227                 [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
1228                 [CLKID_HDMI_PLL]            = &gxbb_hdmi_pll.hw,
1229                 [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
1230                 [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
1231                 [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
1232                 [CLKID_FCLK_DIV4]           = &gxbb_fclk_div4.hw,
1233                 [CLKID_FCLK_DIV5]           = &gxbb_fclk_div5.hw,
1234                 [CLKID_FCLK_DIV7]           = &gxbb_fclk_div7.hw,
1235                 [CLKID_GP0_PLL]             = &gxbb_gp0_pll.hw,
1236                 [CLKID_MPEG_SEL]            = &gxbb_mpeg_clk_sel.hw,
1237                 [CLKID_MPEG_DIV]            = &gxbb_mpeg_clk_div.hw,
1238                 [CLKID_CLK81]               = &gxbb_clk81.hw,
1239                 [CLKID_MPLL0]               = &gxbb_mpll0.hw,
1240                 [CLKID_MPLL1]               = &gxbb_mpll1.hw,
1241                 [CLKID_MPLL2]               = &gxbb_mpll2.hw,
1242                 [CLKID_DDR]                 = &gxbb_ddr.hw,
1243                 [CLKID_DOS]                 = &gxbb_dos.hw,
1244                 [CLKID_ISA]                 = &gxbb_isa.hw,
1245                 [CLKID_PL301]               = &gxbb_pl301.hw,
1246                 [CLKID_PERIPHS]             = &gxbb_periphs.hw,
1247                 [CLKID_SPICC]               = &gxbb_spicc.hw,
1248                 [CLKID_I2C]                 = &gxbb_i2c.hw,
1249                 [CLKID_SAR_ADC]             = &gxbb_sar_adc.hw,
1250                 [CLKID_SMART_CARD]          = &gxbb_smart_card.hw,
1251                 [CLKID_RNG0]                = &gxbb_rng0.hw,
1252                 [CLKID_UART0]               = &gxbb_uart0.hw,
1253                 [CLKID_SDHC]                = &gxbb_sdhc.hw,
1254                 [CLKID_STREAM]              = &gxbb_stream.hw,
1255                 [CLKID_ASYNC_FIFO]          = &gxbb_async_fifo.hw,
1256                 [CLKID_SDIO]                = &gxbb_sdio.hw,
1257                 [CLKID_ABUF]                = &gxbb_abuf.hw,
1258                 [CLKID_HIU_IFACE]           = &gxbb_hiu_iface.hw,
1259                 [CLKID_ASSIST_MISC]         = &gxbb_assist_misc.hw,
1260                 [CLKID_SPI]                 = &gxbb_spi.hw,
1261                 [CLKID_I2S_SPDIF]           = &gxbb_i2s_spdif.hw,
1262                 [CLKID_ETH]                 = &gxbb_eth.hw,
1263                 [CLKID_DEMUX]               = &gxbb_demux.hw,
1264                 [CLKID_AIU_GLUE]            = &gxbb_aiu_glue.hw,
1265                 [CLKID_IEC958]              = &gxbb_iec958.hw,
1266                 [CLKID_I2S_OUT]             = &gxbb_i2s_out.hw,
1267                 [CLKID_AMCLK]               = &gxbb_amclk.hw,
1268                 [CLKID_AIFIFO2]             = &gxbb_aififo2.hw,
1269                 [CLKID_MIXER]               = &gxbb_mixer.hw,
1270                 [CLKID_MIXER_IFACE]         = &gxbb_mixer_iface.hw,
1271                 [CLKID_ADC]                 = &gxbb_adc.hw,
1272                 [CLKID_BLKMV]               = &gxbb_blkmv.hw,
1273                 [CLKID_AIU]                 = &gxbb_aiu.hw,
1274                 [CLKID_UART1]               = &gxbb_uart1.hw,
1275                 [CLKID_G2D]                 = &gxbb_g2d.hw,
1276                 [CLKID_USB0]                = &gxbb_usb0.hw,
1277                 [CLKID_USB1]                = &gxbb_usb1.hw,
1278                 [CLKID_RESET]               = &gxbb_reset.hw,
1279                 [CLKID_NAND]                = &gxbb_nand.hw,
1280                 [CLKID_DOS_PARSER]          = &gxbb_dos_parser.hw,
1281                 [CLKID_USB]                 = &gxbb_usb.hw,
1282                 [CLKID_VDIN1]               = &gxbb_vdin1.hw,
1283                 [CLKID_AHB_ARB0]            = &gxbb_ahb_arb0.hw,
1284                 [CLKID_EFUSE]               = &gxbb_efuse.hw,
1285                 [CLKID_BOOT_ROM]            = &gxbb_boot_rom.hw,
1286                 [CLKID_AHB_DATA_BUS]        = &gxbb_ahb_data_bus.hw,
1287                 [CLKID_AHB_CTRL_BUS]        = &gxbb_ahb_ctrl_bus.hw,
1288                 [CLKID_HDMI_INTR_SYNC]      = &gxbb_hdmi_intr_sync.hw,
1289                 [CLKID_HDMI_PCLK]           = &gxbb_hdmi_pclk.hw,
1290                 [CLKID_USB1_DDR_BRIDGE]     = &gxbb_usb1_ddr_bridge.hw,
1291                 [CLKID_USB0_DDR_BRIDGE]     = &gxbb_usb0_ddr_bridge.hw,
1292                 [CLKID_MMC_PCLK]            = &gxbb_mmc_pclk.hw,
1293                 [CLKID_DVIN]                = &gxbb_dvin.hw,
1294                 [CLKID_UART2]               = &gxbb_uart2.hw,
1295                 [CLKID_SANA]                = &gxbb_sana.hw,
1296                 [CLKID_VPU_INTR]            = &gxbb_vpu_intr.hw,
1297                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
1298                 [CLKID_CLK81_A53]           = &gxbb_clk81_a53.hw,
1299                 [CLKID_VCLK2_VENCI0]        = &gxbb_vclk2_venci0.hw,
1300                 [CLKID_VCLK2_VENCI1]        = &gxbb_vclk2_venci1.hw,
1301                 [CLKID_VCLK2_VENCP0]        = &gxbb_vclk2_vencp0.hw,
1302                 [CLKID_VCLK2_VENCP1]        = &gxbb_vclk2_vencp1.hw,
1303                 [CLKID_GCLK_VENCI_INT0]     = &gxbb_gclk_venci_int0.hw,
1304                 [CLKID_GCLK_VENCI_INT]      = &gxbb_gclk_vencp_int.hw,
1305                 [CLKID_DAC_CLK]             = &gxbb_dac_clk.hw,
1306                 [CLKID_AOCLK_GATE]          = &gxbb_aoclk_gate.hw,
1307                 [CLKID_IEC958_GATE]         = &gxbb_iec958_gate.hw,
1308                 [CLKID_ENC480P]             = &gxbb_enc480p.hw,
1309                 [CLKID_RNG1]                = &gxbb_rng1.hw,
1310                 [CLKID_GCLK_VENCI_INT1]     = &gxbb_gclk_venci_int1.hw,
1311                 [CLKID_VCLK2_VENCLMCC]      = &gxbb_vclk2_venclmcc.hw,
1312                 [CLKID_VCLK2_VENCL]         = &gxbb_vclk2_vencl.hw,
1313                 [CLKID_VCLK_OTHER]          = &gxbb_vclk_other.hw,
1314                 [CLKID_EDP]                 = &gxbb_edp.hw,
1315                 [CLKID_AO_MEDIA_CPU]        = &gxbb_ao_media_cpu.hw,
1316                 [CLKID_AO_AHB_SRAM]         = &gxbb_ao_ahb_sram.hw,
1317                 [CLKID_AO_AHB_BUS]          = &gxbb_ao_ahb_bus.hw,
1318                 [CLKID_AO_IFACE]            = &gxbb_ao_iface.hw,
1319                 [CLKID_AO_I2C]              = &gxbb_ao_i2c.hw,
1320                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
1321                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
1322                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
1323                 [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
1324                 [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
1325                 [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
1326                 [CLKID_MALI_0_SEL]          = &gxbb_mali_0_sel.hw,
1327                 [CLKID_MALI_0_DIV]          = &gxbb_mali_0_div.hw,
1328                 [CLKID_MALI_0]              = &gxbb_mali_0.hw,
1329                 [CLKID_MALI_1_SEL]          = &gxbb_mali_1_sel.hw,
1330                 [CLKID_MALI_1_DIV]          = &gxbb_mali_1_div.hw,
1331                 [CLKID_MALI_1]              = &gxbb_mali_1.hw,
1332                 [CLKID_MALI]                = &gxbb_mali.hw,
1333                 [CLKID_CTS_AMCLK]           = &gxbb_cts_amclk.hw,
1334                 [CLKID_CTS_AMCLK_SEL]       = &gxbb_cts_amclk_sel.hw,
1335                 [CLKID_CTS_AMCLK_DIV]       = &gxbb_cts_amclk_div.hw,
1336                 [CLKID_CTS_MCLK_I958]       = &gxbb_cts_mclk_i958.hw,
1337                 [CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
1338                 [CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
1339                 [CLKID_CTS_I958]            = &gxbb_cts_i958.hw,
1340                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
1341                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
1342                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
1343                 [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
1344                 [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
1345                 [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
1346                 [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
1347                 [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
1348                 [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
1349                 [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
1350                 [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
1351                 [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
1352                 [NR_CLKS]                   = NULL,
1353         },
1354         .num = NR_CLKS,
1355 };
1356
1357 static struct clk_hw_onecell_data gxl_hw_onecell_data = {
1358         .hws = {
1359                 [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
1360                 [CLKID_HDMI_PLL]            = &gxbb_hdmi_pll.hw,
1361                 [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
1362                 [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
1363                 [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
1364                 [CLKID_FCLK_DIV4]           = &gxbb_fclk_div4.hw,
1365                 [CLKID_FCLK_DIV5]           = &gxbb_fclk_div5.hw,
1366                 [CLKID_FCLK_DIV7]           = &gxbb_fclk_div7.hw,
1367                 [CLKID_GP0_PLL]             = &gxl_gp0_pll.hw,
1368                 [CLKID_MPEG_SEL]            = &gxbb_mpeg_clk_sel.hw,
1369                 [CLKID_MPEG_DIV]            = &gxbb_mpeg_clk_div.hw,
1370                 [CLKID_CLK81]               = &gxbb_clk81.hw,
1371                 [CLKID_MPLL0]               = &gxbb_mpll0.hw,
1372                 [CLKID_MPLL1]               = &gxbb_mpll1.hw,
1373                 [CLKID_MPLL2]               = &gxbb_mpll2.hw,
1374                 [CLKID_DDR]                 = &gxbb_ddr.hw,
1375                 [CLKID_DOS]                 = &gxbb_dos.hw,
1376                 [CLKID_ISA]                 = &gxbb_isa.hw,
1377                 [CLKID_PL301]               = &gxbb_pl301.hw,
1378                 [CLKID_PERIPHS]             = &gxbb_periphs.hw,
1379                 [CLKID_SPICC]               = &gxbb_spicc.hw,
1380                 [CLKID_I2C]                 = &gxbb_i2c.hw,
1381                 [CLKID_SAR_ADC]             = &gxbb_sar_adc.hw,
1382                 [CLKID_SMART_CARD]          = &gxbb_smart_card.hw,
1383                 [CLKID_RNG0]                = &gxbb_rng0.hw,
1384                 [CLKID_UART0]               = &gxbb_uart0.hw,
1385                 [CLKID_SDHC]                = &gxbb_sdhc.hw,
1386                 [CLKID_STREAM]              = &gxbb_stream.hw,
1387                 [CLKID_ASYNC_FIFO]          = &gxbb_async_fifo.hw,
1388                 [CLKID_SDIO]                = &gxbb_sdio.hw,
1389                 [CLKID_ABUF]                = &gxbb_abuf.hw,
1390                 [CLKID_HIU_IFACE]           = &gxbb_hiu_iface.hw,
1391                 [CLKID_ASSIST_MISC]         = &gxbb_assist_misc.hw,
1392                 [CLKID_SPI]                 = &gxbb_spi.hw,
1393                 [CLKID_I2S_SPDIF]           = &gxbb_i2s_spdif.hw,
1394                 [CLKID_ETH]                 = &gxbb_eth.hw,
1395                 [CLKID_DEMUX]               = &gxbb_demux.hw,
1396                 [CLKID_AIU_GLUE]            = &gxbb_aiu_glue.hw,
1397                 [CLKID_IEC958]              = &gxbb_iec958.hw,
1398                 [CLKID_I2S_OUT]             = &gxbb_i2s_out.hw,
1399                 [CLKID_AMCLK]               = &gxbb_amclk.hw,
1400                 [CLKID_AIFIFO2]             = &gxbb_aififo2.hw,
1401                 [CLKID_MIXER]               = &gxbb_mixer.hw,
1402                 [CLKID_MIXER_IFACE]         = &gxbb_mixer_iface.hw,
1403                 [CLKID_ADC]                 = &gxbb_adc.hw,
1404                 [CLKID_BLKMV]               = &gxbb_blkmv.hw,
1405                 [CLKID_AIU]                 = &gxbb_aiu.hw,
1406                 [CLKID_UART1]               = &gxbb_uart1.hw,
1407                 [CLKID_G2D]                 = &gxbb_g2d.hw,
1408                 [CLKID_USB0]                = &gxbb_usb0.hw,
1409                 [CLKID_USB1]                = &gxbb_usb1.hw,
1410                 [CLKID_RESET]               = &gxbb_reset.hw,
1411                 [CLKID_NAND]                = &gxbb_nand.hw,
1412                 [CLKID_DOS_PARSER]          = &gxbb_dos_parser.hw,
1413                 [CLKID_USB]                 = &gxbb_usb.hw,
1414                 [CLKID_VDIN1]               = &gxbb_vdin1.hw,
1415                 [CLKID_AHB_ARB0]            = &gxbb_ahb_arb0.hw,
1416                 [CLKID_EFUSE]               = &gxbb_efuse.hw,
1417                 [CLKID_BOOT_ROM]            = &gxbb_boot_rom.hw,
1418                 [CLKID_AHB_DATA_BUS]        = &gxbb_ahb_data_bus.hw,
1419                 [CLKID_AHB_CTRL_BUS]        = &gxbb_ahb_ctrl_bus.hw,
1420                 [CLKID_HDMI_INTR_SYNC]      = &gxbb_hdmi_intr_sync.hw,
1421                 [CLKID_HDMI_PCLK]           = &gxbb_hdmi_pclk.hw,
1422                 [CLKID_USB1_DDR_BRIDGE]     = &gxbb_usb1_ddr_bridge.hw,
1423                 [CLKID_USB0_DDR_BRIDGE]     = &gxbb_usb0_ddr_bridge.hw,
1424                 [CLKID_MMC_PCLK]            = &gxbb_mmc_pclk.hw,
1425                 [CLKID_DVIN]                = &gxbb_dvin.hw,
1426                 [CLKID_UART2]               = &gxbb_uart2.hw,
1427                 [CLKID_SANA]                = &gxbb_sana.hw,
1428                 [CLKID_VPU_INTR]            = &gxbb_vpu_intr.hw,
1429                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
1430                 [CLKID_CLK81_A53]           = &gxbb_clk81_a53.hw,
1431                 [CLKID_VCLK2_VENCI0]        = &gxbb_vclk2_venci0.hw,
1432                 [CLKID_VCLK2_VENCI1]        = &gxbb_vclk2_venci1.hw,
1433                 [CLKID_VCLK2_VENCP0]        = &gxbb_vclk2_vencp0.hw,
1434                 [CLKID_VCLK2_VENCP1]        = &gxbb_vclk2_vencp1.hw,
1435                 [CLKID_GCLK_VENCI_INT0]     = &gxbb_gclk_venci_int0.hw,
1436                 [CLKID_GCLK_VENCI_INT]      = &gxbb_gclk_vencp_int.hw,
1437                 [CLKID_DAC_CLK]             = &gxbb_dac_clk.hw,
1438                 [CLKID_AOCLK_GATE]          = &gxbb_aoclk_gate.hw,
1439                 [CLKID_IEC958_GATE]         = &gxbb_iec958_gate.hw,
1440                 [CLKID_ENC480P]             = &gxbb_enc480p.hw,
1441                 [CLKID_RNG1]                = &gxbb_rng1.hw,
1442                 [CLKID_GCLK_VENCI_INT1]     = &gxbb_gclk_venci_int1.hw,
1443                 [CLKID_VCLK2_VENCLMCC]      = &gxbb_vclk2_venclmcc.hw,
1444                 [CLKID_VCLK2_VENCL]         = &gxbb_vclk2_vencl.hw,
1445                 [CLKID_VCLK_OTHER]          = &gxbb_vclk_other.hw,
1446                 [CLKID_EDP]                 = &gxbb_edp.hw,
1447                 [CLKID_AO_MEDIA_CPU]        = &gxbb_ao_media_cpu.hw,
1448                 [CLKID_AO_AHB_SRAM]         = &gxbb_ao_ahb_sram.hw,
1449                 [CLKID_AO_AHB_BUS]          = &gxbb_ao_ahb_bus.hw,
1450                 [CLKID_AO_IFACE]            = &gxbb_ao_iface.hw,
1451                 [CLKID_AO_I2C]              = &gxbb_ao_i2c.hw,
1452                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
1453                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
1454                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
1455                 [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
1456                 [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
1457                 [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
1458                 [CLKID_MALI_0_SEL]          = &gxbb_mali_0_sel.hw,
1459                 [CLKID_MALI_0_DIV]          = &gxbb_mali_0_div.hw,
1460                 [CLKID_MALI_0]              = &gxbb_mali_0.hw,
1461                 [CLKID_MALI_1_SEL]          = &gxbb_mali_1_sel.hw,
1462                 [CLKID_MALI_1_DIV]          = &gxbb_mali_1_div.hw,
1463                 [CLKID_MALI_1]              = &gxbb_mali_1.hw,
1464                 [CLKID_MALI]                = &gxbb_mali.hw,
1465                 [CLKID_CTS_AMCLK]           = &gxbb_cts_amclk.hw,
1466                 [CLKID_CTS_AMCLK_SEL]       = &gxbb_cts_amclk_sel.hw,
1467                 [CLKID_CTS_AMCLK_DIV]       = &gxbb_cts_amclk_div.hw,
1468                 [CLKID_CTS_MCLK_I958]       = &gxbb_cts_mclk_i958.hw,
1469                 [CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
1470                 [CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
1471                 [CLKID_CTS_I958]            = &gxbb_cts_i958.hw,
1472                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
1473                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
1474                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
1475                 [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
1476                 [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
1477                 [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
1478                 [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
1479                 [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
1480                 [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
1481                 [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
1482                 [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
1483                 [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
1484                 [NR_CLKS]                   = NULL,
1485         },
1486         .num = NR_CLKS,
1487 };
1488
1489 /* Convenience tables to populate base addresses in .probe */
1490
1491 static struct meson_clk_pll *const gxbb_clk_plls[] = {
1492         &gxbb_fixed_pll,
1493         &gxbb_hdmi_pll,
1494         &gxbb_sys_pll,
1495         &gxbb_gp0_pll,
1496 };
1497
1498 static struct meson_clk_pll *const gxl_clk_plls[] = {
1499         &gxbb_fixed_pll,
1500         &gxbb_hdmi_pll,
1501         &gxbb_sys_pll,
1502         &gxl_gp0_pll,
1503 };
1504
1505 static struct meson_clk_mpll *const gxbb_clk_mplls[] = {
1506         &gxbb_mpll0,
1507         &gxbb_mpll1,
1508         &gxbb_mpll2,
1509 };
1510
1511 static struct clk_gate *const gxbb_clk_gates[] = {
1512         &gxbb_clk81,
1513         &gxbb_ddr,
1514         &gxbb_dos,
1515         &gxbb_isa,
1516         &gxbb_pl301,
1517         &gxbb_periphs,
1518         &gxbb_spicc,
1519         &gxbb_i2c,
1520         &gxbb_sar_adc,
1521         &gxbb_smart_card,
1522         &gxbb_rng0,
1523         &gxbb_uart0,
1524         &gxbb_sdhc,
1525         &gxbb_stream,
1526         &gxbb_async_fifo,
1527         &gxbb_sdio,
1528         &gxbb_abuf,
1529         &gxbb_hiu_iface,
1530         &gxbb_assist_misc,
1531         &gxbb_spi,
1532         &gxbb_i2s_spdif,
1533         &gxbb_eth,
1534         &gxbb_demux,
1535         &gxbb_aiu_glue,
1536         &gxbb_iec958,
1537         &gxbb_i2s_out,
1538         &gxbb_amclk,
1539         &gxbb_aififo2,
1540         &gxbb_mixer,
1541         &gxbb_mixer_iface,
1542         &gxbb_adc,
1543         &gxbb_blkmv,
1544         &gxbb_aiu,
1545         &gxbb_uart1,
1546         &gxbb_g2d,
1547         &gxbb_usb0,
1548         &gxbb_usb1,
1549         &gxbb_reset,
1550         &gxbb_nand,
1551         &gxbb_dos_parser,
1552         &gxbb_usb,
1553         &gxbb_vdin1,
1554         &gxbb_ahb_arb0,
1555         &gxbb_efuse,
1556         &gxbb_boot_rom,
1557         &gxbb_ahb_data_bus,
1558         &gxbb_ahb_ctrl_bus,
1559         &gxbb_hdmi_intr_sync,
1560         &gxbb_hdmi_pclk,
1561         &gxbb_usb1_ddr_bridge,
1562         &gxbb_usb0_ddr_bridge,
1563         &gxbb_mmc_pclk,
1564         &gxbb_dvin,
1565         &gxbb_uart2,
1566         &gxbb_sana,
1567         &gxbb_vpu_intr,
1568         &gxbb_sec_ahb_ahb3_bridge,
1569         &gxbb_clk81_a53,
1570         &gxbb_vclk2_venci0,
1571         &gxbb_vclk2_venci1,
1572         &gxbb_vclk2_vencp0,
1573         &gxbb_vclk2_vencp1,
1574         &gxbb_gclk_venci_int0,
1575         &gxbb_gclk_vencp_int,
1576         &gxbb_dac_clk,
1577         &gxbb_aoclk_gate,
1578         &gxbb_iec958_gate,
1579         &gxbb_enc480p,
1580         &gxbb_rng1,
1581         &gxbb_gclk_venci_int1,
1582         &gxbb_vclk2_venclmcc,
1583         &gxbb_vclk2_vencl,
1584         &gxbb_vclk_other,
1585         &gxbb_edp,
1586         &gxbb_ao_media_cpu,
1587         &gxbb_ao_ahb_sram,
1588         &gxbb_ao_ahb_bus,
1589         &gxbb_ao_iface,
1590         &gxbb_ao_i2c,
1591         &gxbb_emmc_a,
1592         &gxbb_emmc_b,
1593         &gxbb_emmc_c,
1594         &gxbb_sar_adc_clk,
1595         &gxbb_mali_0,
1596         &gxbb_mali_1,
1597         &gxbb_cts_amclk,
1598         &gxbb_cts_mclk_i958,
1599         &gxbb_32k_clk,
1600         &gxbb_sd_emmc_a_clk0,
1601         &gxbb_sd_emmc_b_clk0,
1602         &gxbb_sd_emmc_c_clk0,
1603 };
1604
1605 static struct clk_mux *const gxbb_clk_muxes[] = {
1606         &gxbb_mpeg_clk_sel,
1607         &gxbb_sar_adc_clk_sel,
1608         &gxbb_mali_0_sel,
1609         &gxbb_mali_1_sel,
1610         &gxbb_mali,
1611         &gxbb_cts_amclk_sel,
1612         &gxbb_cts_mclk_i958_sel,
1613         &gxbb_cts_i958,
1614         &gxbb_32k_clk_sel,
1615         &gxbb_sd_emmc_a_clk0_sel,
1616         &gxbb_sd_emmc_b_clk0_sel,
1617         &gxbb_sd_emmc_c_clk0_sel,
1618 };
1619
1620 static struct clk_divider *const gxbb_clk_dividers[] = {
1621         &gxbb_mpeg_clk_div,
1622         &gxbb_sar_adc_clk_div,
1623         &gxbb_mali_0_div,
1624         &gxbb_mali_1_div,
1625         &gxbb_cts_mclk_i958_div,
1626         &gxbb_32k_clk_div,
1627         &gxbb_sd_emmc_a_clk0_div,
1628         &gxbb_sd_emmc_b_clk0_div,
1629         &gxbb_sd_emmc_c_clk0_div,
1630 };
1631
1632 static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
1633         &gxbb_cts_amclk_div,
1634 };
1635
1636 struct clkc_data {
1637         struct clk_gate *const *clk_gates;
1638         unsigned int clk_gates_count;
1639         struct meson_clk_mpll *const *clk_mplls;
1640         unsigned int clk_mplls_count;
1641         struct meson_clk_pll *const *clk_plls;
1642         unsigned int clk_plls_count;
1643         struct clk_mux *const *clk_muxes;
1644         unsigned int clk_muxes_count;
1645         struct clk_divider *const *clk_dividers;
1646         unsigned int clk_dividers_count;
1647         struct meson_clk_audio_divider *const *clk_audio_dividers;
1648         unsigned int clk_audio_dividers_count;
1649         struct clk_hw_onecell_data *hw_onecell_data;
1650 };
1651
1652 static const struct clkc_data gxbb_clkc_data = {
1653         .clk_gates = gxbb_clk_gates,
1654         .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates),
1655         .clk_mplls = gxbb_clk_mplls,
1656         .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls),
1657         .clk_plls = gxbb_clk_plls,
1658         .clk_plls_count = ARRAY_SIZE(gxbb_clk_plls),
1659         .clk_muxes = gxbb_clk_muxes,
1660         .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
1661         .clk_dividers = gxbb_clk_dividers,
1662         .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
1663         .clk_audio_dividers = gxbb_audio_dividers,
1664         .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
1665         .hw_onecell_data = &gxbb_hw_onecell_data,
1666 };
1667
1668 static const struct clkc_data gxl_clkc_data = {
1669         .clk_gates = gxbb_clk_gates,
1670         .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates),
1671         .clk_mplls = gxbb_clk_mplls,
1672         .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls),
1673         .clk_plls = gxl_clk_plls,
1674         .clk_plls_count = ARRAY_SIZE(gxl_clk_plls),
1675         .clk_muxes = gxbb_clk_muxes,
1676         .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
1677         .clk_dividers = gxbb_clk_dividers,
1678         .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
1679         .clk_audio_dividers = gxbb_audio_dividers,
1680         .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
1681         .hw_onecell_data = &gxl_hw_onecell_data,
1682 };
1683
1684 static const struct of_device_id clkc_match_table[] = {
1685         { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
1686         { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
1687         {},
1688 };
1689
1690 static int gxbb_clkc_probe(struct platform_device *pdev)
1691 {
1692         const struct clkc_data *clkc_data;
1693         void __iomem *clk_base;
1694         int ret, clkid, i;
1695         struct device *dev = &pdev->dev;
1696
1697         clkc_data = of_device_get_match_data(&pdev->dev);
1698         if (!clkc_data)
1699                 return -EINVAL;
1700
1701         /*  Generic clocks and PLLs */
1702         clk_base = of_iomap(dev->of_node, 0);
1703         if (!clk_base) {
1704                 pr_err("%s: Unable to map clk base\n", __func__);
1705                 return -ENXIO;
1706         }
1707
1708         /* Populate base address for PLLs */
1709         for (i = 0; i < clkc_data->clk_plls_count; i++)
1710                 clkc_data->clk_plls[i]->base = clk_base;
1711
1712         /* Populate base address for MPLLs */
1713         for (i = 0; i < clkc_data->clk_mplls_count; i++)
1714                 clkc_data->clk_mplls[i]->base = clk_base;
1715
1716         /* Populate base address for gates */
1717         for (i = 0; i < clkc_data->clk_gates_count; i++)
1718                 clkc_data->clk_gates[i]->reg = clk_base +
1719                         (u64)clkc_data->clk_gates[i]->reg;
1720
1721         /* Populate base address for muxes */
1722         for (i = 0; i < clkc_data->clk_muxes_count; i++)
1723                 clkc_data->clk_muxes[i]->reg = clk_base +
1724                         (u64)clkc_data->clk_muxes[i]->reg;
1725
1726         /* Populate base address for dividers */
1727         for (i = 0; i < clkc_data->clk_dividers_count; i++)
1728                 clkc_data->clk_dividers[i]->reg = clk_base +
1729                         (u64)clkc_data->clk_dividers[i]->reg;
1730
1731         /* Populate base address for the audio dividers */
1732         for (i = 0; i < clkc_data->clk_audio_dividers_count; i++)
1733                 clkc_data->clk_audio_dividers[i]->base = clk_base;
1734
1735         /*
1736          * register all clks
1737          */
1738         for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) {
1739                 /* array might be sparse */
1740                 if (!clkc_data->hw_onecell_data->hws[clkid])
1741                         continue;
1742
1743                 ret = devm_clk_hw_register(dev,
1744                                         clkc_data->hw_onecell_data->hws[clkid]);
1745                 if (ret)
1746                         goto iounmap;
1747         }
1748
1749         return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
1750                         clkc_data->hw_onecell_data);
1751
1752 iounmap:
1753         iounmap(clk_base);
1754         return ret;
1755 }
1756
1757 static struct platform_driver gxbb_driver = {
1758         .probe          = gxbb_clkc_probe,
1759         .driver         = {
1760                 .name   = "gxbb-clkc",
1761                 .of_match_table = clkc_match_table,
1762         },
1763 };
1764
1765 builtin_platform_driver(gxbb_driver);