drivers/clk/meson/gxbb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2016 AmLogic, Inc.
   4  * Michael Turquette <mturquette@baylibre.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/clk-provider.h>
   9 #include <linux/init.h>
  10 #include <linux/of_device.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/regmap.h>
  14
  15 #include "clkc.h"
  16 #include "gxbb.h"
  17 #include "clk-regmap.h"
  18
  19 static DEFINE_SPINLOCK(meson_clk_lock);
  20
  21 static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
  22         PLL_PARAMS(32, 1),
  23         PLL_PARAMS(33, 1),
  24         PLL_PARAMS(34, 1),
  25         PLL_PARAMS(35, 1),
  26         PLL_PARAMS(36, 1),
  27         PLL_PARAMS(37, 1),
  28         PLL_PARAMS(38, 1),
  29         PLL_PARAMS(39, 1),
  30         PLL_PARAMS(40, 1),
  31         PLL_PARAMS(41, 1),
  32         PLL_PARAMS(42, 1),
  33         PLL_PARAMS(43, 1),
  34         PLL_PARAMS(44, 1),
  35         PLL_PARAMS(45, 1),
  36         PLL_PARAMS(46, 1),
  37         PLL_PARAMS(47, 1),
  38         PLL_PARAMS(48, 1),
  39         PLL_PARAMS(49, 1),
  40         PLL_PARAMS(50, 1),
  41         PLL_PARAMS(51, 1),
  42         PLL_PARAMS(52, 1),
  43         PLL_PARAMS(53, 1),
  44         PLL_PARAMS(54, 1),
  45         PLL_PARAMS(55, 1),
  46         PLL_PARAMS(56, 1),
  47         PLL_PARAMS(57, 1),
  48         PLL_PARAMS(58, 1),
  49         PLL_PARAMS(59, 1),
  50         PLL_PARAMS(60, 1),
  51         PLL_PARAMS(61, 1),
  52         PLL_PARAMS(62, 1),
  53         { /* sentinel */ },
  54 };
  55
  56 static const struct pll_params_table gxl_gp0_pll_params_table[] = {
  57         PLL_PARAMS(42, 1),
  58         PLL_PARAMS(43, 1),
  59         PLL_PARAMS(44, 1),
  60         PLL_PARAMS(45, 1),
  61         PLL_PARAMS(46, 1),
  62         PLL_PARAMS(47, 1),
  63         PLL_PARAMS(48, 1),
  64         PLL_PARAMS(49, 1),
  65         PLL_PARAMS(50, 1),
  66         PLL_PARAMS(51, 1),
  67         PLL_PARAMS(52, 1),
  68         PLL_PARAMS(53, 1),
  69         PLL_PARAMS(54, 1),
  70         PLL_PARAMS(55, 1),
  71         PLL_PARAMS(56, 1),
  72         PLL_PARAMS(57, 1),
  73         PLL_PARAMS(58, 1),
  74         PLL_PARAMS(59, 1),
  75         PLL_PARAMS(60, 1),
  76         PLL_PARAMS(61, 1),
  77         PLL_PARAMS(62, 1),
  78         PLL_PARAMS(63, 1),
  79         PLL_PARAMS(64, 1),
  80         PLL_PARAMS(65, 1),
  81         PLL_PARAMS(66, 1),
  82         { /* sentinel */ },
  83 };
  84
  85 static struct clk_regmap gxbb_fixed_pll_dco = {
  86         .data = &(struct meson_clk_pll_data){
  87                 .en = {
  88                         .reg_off = HHI_MPLL_CNTL,
  89                         .shift   = 30,
  90                         .width   = 1,
  91                 },
  92                 .m = {
  93                         .reg_off = HHI_MPLL_CNTL,
  94                         .shift   = 0,
  95                         .width   = 9,
  96                 },
  97                 .n = {
  98                         .reg_off = HHI_MPLL_CNTL,
  99                         .shift   = 9,
 100                         .width   = 5,
 101                 },
 102                 .frac = {
 103                         .reg_off = HHI_MPLL_CNTL2,
 104                         .shift   = 0,
 105                         .width   = 12,
 106                 },
 107                 .l = {
 108                         .reg_off = HHI_MPLL_CNTL,
 109                         .shift   = 31,
 110                         .width   = 1,
 111                 },
 112                 .rst = {
 113                         .reg_off = HHI_MPLL_CNTL,
 114                         .shift   = 29,
 115                         .width   = 1,
 116                 },
 117         },
 118         .hw.init = &(struct clk_init_data){
 119                 .name = "fixed_pll_dco",
 120                 .ops = &meson_clk_pll_ro_ops,
 121                 .parent_names = (const char *[]){ "xtal" },
 122                 .num_parents = 1,
 123         },
 124 };
 125
 126 static struct clk_regmap gxbb_fixed_pll = {
 127         .data = &(struct clk_regmap_div_data){
 128                 .offset = HHI_MPLL_CNTL,
 129                 .shift = 16,
 130                 .width = 2,
 131                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 132         },
 133         .hw.init = &(struct clk_init_data){
 134                 .name = "fixed_pll",
 135                 .ops = &clk_regmap_divider_ro_ops,
 136                 .parent_names = (const char *[]){ "fixed_pll_dco" },
 137                 .num_parents = 1,
 138                 /*
 139                  * This clock won't ever change at runtime so
 140                  * CLK_SET_RATE_PARENT is not required
 141                  */
 142         },
 143 };
 144
 145 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
 146         .mult = 2,
 147         .div = 1,
 148         .hw.init = &(struct clk_init_data){
 149                 .name = "hdmi_pll_pre_mult",
 150                 .ops = &clk_fixed_factor_ops,
 151                 .parent_names = (const char *[]){ "xtal" },
 152                 .num_parents = 1,
 153         },
 154 };
 155
 156 static struct clk_regmap gxbb_hdmi_pll_dco = {
 157         .data = &(struct meson_clk_pll_data){
 158                 .en = {
 159                         .reg_off = HHI_HDMI_PLL_CNTL,
 160                         .shift   = 30,
 161                         .width   = 1,
 162                 },
 163                 .m = {
 164                         .reg_off = HHI_HDMI_PLL_CNTL,
 165                         .shift   = 0,
 166                         .width   = 9,
 167                 },
 168                 .n = {
 169                         .reg_off = HHI_HDMI_PLL_CNTL,
 170                         .shift   = 9,
 171                         .width   = 5,
 172                 },
 173                 .frac = {
 174                         .reg_off = HHI_HDMI_PLL_CNTL2,
 175                         .shift   = 0,
 176                         .width   = 12,
 177                 },
 178                 .l = {
 179                         .reg_off = HHI_HDMI_PLL_CNTL,
 180                         .shift   = 31,
 181                         .width   = 1,
 182                 },
 183                 .rst = {
 184                         .reg_off = HHI_HDMI_PLL_CNTL,
 185                         .shift   = 28,
 186                         .width   = 1,
 187                 },
 188         },
 189         .hw.init = &(struct clk_init_data){
 190                 .name = "hdmi_pll_dco",
 191                 .ops = &meson_clk_pll_ro_ops,
 192                 .parent_names = (const char *[]){ "hdmi_pll_pre_mult" },
 193                 .num_parents = 1,
 194                 /*
 195                  * Display directly handle hdmi pll registers ATM, we need
 196                  * NOCACHE to keep our view of the clock as accurate as possible
 197                  */
 198                 .flags = CLK_GET_RATE_NOCACHE,
 199         },
 200 };
 201
 202 static struct clk_regmap gxbb_hdmi_pll_od = {
 203         .data = &(struct clk_regmap_div_data){
 204                 .offset = HHI_HDMI_PLL_CNTL2,
 205                 .shift = 16,
 206                 .width = 2,
 207                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 208         },
 209         .hw.init = &(struct clk_init_data){
 210                 .name = "hdmi_pll_od",
 211                 .ops = &clk_regmap_divider_ro_ops,
 212                 .parent_names = (const char *[]){ "hdmi_pll_dco" },
 213                 .num_parents = 1,
 214                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 215         },
 216 };
 217
 218 static struct clk_regmap gxbb_hdmi_pll_od2 = {
 219         .data = &(struct clk_regmap_div_data){
 220                 .offset = HHI_HDMI_PLL_CNTL2,
 221                 .shift = 22,
 222                 .width = 2,
 223                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 224         },
 225         .hw.init = &(struct clk_init_data){
 226                 .name = "hdmi_pll_od2",
 227                 .ops = &clk_regmap_divider_ro_ops,
 228                 .parent_names = (const char *[]){ "hdmi_pll_od" },
 229                 .num_parents = 1,
 230                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 231         },
 232 };
 233
 234 static struct clk_regmap gxbb_hdmi_pll = {
 235         .data = &(struct clk_regmap_div_data){
 236                 .offset = HHI_HDMI_PLL_CNTL2,
 237                 .shift = 18,
 238                 .width = 2,
 239                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 240         },
 241         .hw.init = &(struct clk_init_data){
 242                 .name = "hdmi_pll",
 243                 .ops = &clk_regmap_divider_ro_ops,
 244                 .parent_names = (const char *[]){ "hdmi_pll_od2" },
 245                 .num_parents = 1,
 246                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 247         },
 248 };
 249
 250 static struct clk_regmap gxl_hdmi_pll_od = {
 251         .data = &(struct clk_regmap_div_data){
 252                 .offset = HHI_HDMI_PLL_CNTL + 8,
 253                 .shift = 21,
 254                 .width = 2,
 255                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 256         },
 257         .hw.init = &(struct clk_init_data){
 258                 .name = "hdmi_pll_od",
 259                 .ops = &clk_regmap_divider_ro_ops,
 260                 .parent_names = (const char *[]){ "hdmi_pll_dco" },
 261                 .num_parents = 1,
 262                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 263         },
 264 };
 265
 266 static struct clk_regmap gxl_hdmi_pll_od2 = {
 267         .data = &(struct clk_regmap_div_data){
 268                 .offset = HHI_HDMI_PLL_CNTL + 8,
 269                 .shift = 23,
 270                 .width = 2,
 271                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 272         },
 273         .hw.init = &(struct clk_init_data){
 274                 .name = "hdmi_pll_od2",
 275                 .ops = &clk_regmap_divider_ro_ops,
 276                 .parent_names = (const char *[]){ "hdmi_pll_od" },
 277                 .num_parents = 1,
 278                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 279         },
 280 };
 281
 282 static struct clk_regmap gxl_hdmi_pll = {
 283         .data = &(struct clk_regmap_div_data){
 284                 .offset = HHI_HDMI_PLL_CNTL + 8,
 285                 .shift = 19,
 286                 .width = 2,
 287                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 288         },
 289         .hw.init = &(struct clk_init_data){
 290                 .name = "hdmi_pll",
 291                 .ops = &clk_regmap_divider_ro_ops,
 292                 .parent_names = (const char *[]){ "hdmi_pll_od2" },
 293                 .num_parents = 1,
 294                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 295         },
 296 };
 297
 298 static struct clk_regmap gxbb_sys_pll_dco = {
 299         .data = &(struct meson_clk_pll_data){
 300                 .en = {
 301                         .reg_off = HHI_SYS_PLL_CNTL,
 302                         .shift   = 30,
 303                         .width   = 1,
 304                 },
 305                 .m = {
 306                         .reg_off = HHI_SYS_PLL_CNTL,
 307                         .shift   = 0,
 308                         .width   = 9,
 309                 },
 310                 .n = {
 311                         .reg_off = HHI_SYS_PLL_CNTL,
 312                         .shift   = 9,
 313                         .width   = 5,
 314                 },
 315                 .l = {
 316                         .reg_off = HHI_SYS_PLL_CNTL,
 317                         .shift   = 31,
 318                         .width   = 1,
 319                 },
 320                 .rst = {
 321                         .reg_off = HHI_SYS_PLL_CNTL,
 322                         .shift   = 29,
 323                         .width   = 1,
 324                 },
 325         },
 326         .hw.init = &(struct clk_init_data){
 327                 .name = "sys_pll_dco",
 328                 .ops = &meson_clk_pll_ro_ops,
 329                 .parent_names = (const char *[]){ "xtal" },
 330                 .num_parents = 1,
 331         },
 332 };
 333
 334 static struct clk_regmap gxbb_sys_pll = {
 335         .data = &(struct clk_regmap_div_data){
 336                 .offset = HHI_SYS_PLL_CNTL,
 337                 .shift = 10,
 338                 .width = 2,
 339                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 340         },
 341         .hw.init = &(struct clk_init_data){
 342                 .name = "sys_pll",
 343                 .ops = &clk_regmap_divider_ro_ops,
 344                 .parent_names = (const char *[]){ "sys_pll_dco" },
 345                 .num_parents = 1,
 346                 .flags = CLK_SET_RATE_PARENT,
 347         },
 348 };
 349
 350 static const struct reg_sequence gxbb_gp0_init_regs[] = {
 351         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0x69c80000 },
 352         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a5590c4 },
 353         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0x0000500d },
 354 };
 355
 356 static struct clk_regmap gxbb_gp0_pll_dco = {
 357         .data = &(struct meson_clk_pll_data){
 358                 .en = {
 359                         .reg_off = HHI_GP0_PLL_CNTL,
 360                         .shift   = 30,
 361                         .width   = 1,
 362                 },
 363                 .m = {
 364                         .reg_off = HHI_GP0_PLL_CNTL,
 365                         .shift   = 0,
 366                         .width   = 9,
 367                 },
 368                 .n = {
 369                         .reg_off = HHI_GP0_PLL_CNTL,
 370                         .shift   = 9,
 371                         .width   = 5,
 372                 },
 373                 .l = {
 374                         .reg_off = HHI_GP0_PLL_CNTL,
 375                         .shift   = 31,
 376                         .width   = 1,
 377                 },
 378                 .rst = {
 379                         .reg_off = HHI_GP0_PLL_CNTL,
 380                         .shift   = 29,
 381                         .width   = 1,
 382                 },
 383                 .table = gxbb_gp0_pll_params_table,
 384                 .init_regs = gxbb_gp0_init_regs,
 385                 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
 386         },
 387         .hw.init = &(struct clk_init_data){
 388                 .name = "gp0_pll_dco",
 389                 .ops = &meson_clk_pll_ops,
 390                 .parent_names = (const char *[]){ "xtal" },
 391                 .num_parents = 1,
 392         },
 393 };
 394
 395 static const struct reg_sequence gxl_gp0_init_regs[] = {
 396         { .reg = HHI_GP0_PLL_CNTL1,     .def = 0xc084b000 },
 397         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0xb75020be },
 398         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a59a288 },
 399         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0xc000004d },
 400         { .reg = HHI_GP0_PLL_CNTL5,     .def = 0x00078000 },
 401 };
 402
 403 static struct clk_regmap gxl_gp0_pll_dco = {
 404         .data = &(struct meson_clk_pll_data){
 405                 .en = {
 406                         .reg_off = HHI_GP0_PLL_CNTL,
 407                         .shift   = 30,
 408                         .width   = 1,
 409                 },
 410                 .m = {
 411                         .reg_off = HHI_GP0_PLL_CNTL,
 412                         .shift   = 0,
 413                         .width   = 9,
 414                 },
 415                 .n = {
 416                         .reg_off = HHI_GP0_PLL_CNTL,
 417                         .shift   = 9,
 418                         .width   = 5,
 419                 },
 420                 .frac = {
 421                         .reg_off = HHI_GP0_PLL_CNTL1,
 422                         .shift   = 0,
 423                         .width   = 10,
 424                 },
 425                 .l = {
 426                         .reg_off = HHI_GP0_PLL_CNTL,
 427                         .shift   = 31,
 428                         .width   = 1,
 429                 },
 430                 .rst = {
 431                         .reg_off = HHI_GP0_PLL_CNTL,
 432                         .shift   = 29,
 433                         .width   = 1,
 434                 },
 435                 .table = gxl_gp0_pll_params_table,
 436                 .init_regs = gxl_gp0_init_regs,
 437                 .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
 438         },
 439         .hw.init = &(struct clk_init_data){
 440                 .name = "gp0_pll_dco",
 441                 .ops = &meson_clk_pll_ops,
 442                 .parent_names = (const char *[]){ "xtal" },
 443                 .num_parents = 1,
 444         },
 445 };
 446
 447 static struct clk_regmap gxbb_gp0_pll = {
 448         .data = &(struct clk_regmap_div_data){
 449                 .offset = HHI_GP0_PLL_CNTL,
 450                 .shift = 16,
 451                 .width = 2,
 452                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 453         },
 454         .hw.init = &(struct clk_init_data){
 455                 .name = "gp0_pll",
 456                 .ops = &clk_regmap_divider_ops,
 457                 .parent_names = (const char *[]){ "gp0_pll_dco" },
 458                 .num_parents = 1,
 459                 .flags = CLK_SET_RATE_PARENT,
 460         },
 461 };
 462
 463 static struct clk_fixed_factor gxbb_fclk_div2_div = {
 464         .mult = 1,
 465         .div = 2,
 466         .hw.init = &(struct clk_init_data){
 467                 .name = "fclk_div2_div",
 468                 .ops = &clk_fixed_factor_ops,
 469                 .parent_names = (const char *[]){ "fixed_pll" },
 470                 .num_parents = 1,
 471         },
 472 };
 473
 474 static struct clk_regmap gxbb_fclk_div2 = {
 475         .data = &(struct clk_regmap_gate_data){
 476                 .offset = HHI_MPLL_CNTL6,
 477                 .bit_idx = 27,
 478         },
 479         .hw.init = &(struct clk_init_data){
 480                 .name = "fclk_div2",
 481                 .ops = &clk_regmap_gate_ops,
 482                 .parent_names = (const char *[]){ "fclk_div2_div" },
 483                 .num_parents = 1,
 484                 .flags = CLK_IS_CRITICAL,
 485         },
 486 };
 487
 488 static struct clk_fixed_factor gxbb_fclk_div3_div = {
 489         .mult = 1,
 490         .div = 3,
 491         .hw.init = &(struct clk_init_data){
 492                 .name = "fclk_div3_div",
 493                 .ops = &clk_fixed_factor_ops,
 494                 .parent_names = (const char *[]){ "fixed_pll" },
 495                 .num_parents = 1,
 496         },
 497 };
 498
 499 static struct clk_regmap gxbb_fclk_div3 = {
 500         .data = &(struct clk_regmap_gate_data){
 501                 .offset = HHI_MPLL_CNTL6,
 502                 .bit_idx = 28,
 503         },
 504         .hw.init = &(struct clk_init_data){
 505                 .name = "fclk_div3",
 506                 .ops = &clk_regmap_gate_ops,
 507                 .parent_names = (const char *[]){ "fclk_div3_div" },
 508                 .num_parents = 1,
 509         },
 510 };
 511
 512 static struct clk_fixed_factor gxbb_fclk_div4_div = {
 513         .mult = 1,
 514         .div = 4,
 515         .hw.init = &(struct clk_init_data){
 516                 .name = "fclk_div4_div",
 517                 .ops = &clk_fixed_factor_ops,
 518                 .parent_names = (const char *[]){ "fixed_pll" },
 519                 .num_parents = 1,
 520         },
 521 };
 522
 523 static struct clk_regmap gxbb_fclk_div4 = {
 524         .data = &(struct clk_regmap_gate_data){
 525                 .offset = HHI_MPLL_CNTL6,
 526                 .bit_idx = 29,
 527         },
 528         .hw.init = &(struct clk_init_data){
 529                 .name = "fclk_div4",
 530                 .ops = &clk_regmap_gate_ops,
 531                 .parent_names = (const char *[]){ "fclk_div4_div" },
 532                 .num_parents = 1,
 533         },
 534 };
 535
 536 static struct clk_fixed_factor gxbb_fclk_div5_div = {
 537         .mult = 1,
 538         .div = 5,
 539         .hw.init = &(struct clk_init_data){
 540                 .name = "fclk_div5_div",
 541                 .ops = &clk_fixed_factor_ops,
 542                 .parent_names = (const char *[]){ "fixed_pll" },
 543                 .num_parents = 1,
 544         },
 545 };
 546
 547 static struct clk_regmap gxbb_fclk_div5 = {
 548         .data = &(struct clk_regmap_gate_data){
 549                 .offset = HHI_MPLL_CNTL6,
 550                 .bit_idx = 30,
 551         },
 552         .hw.init = &(struct clk_init_data){
 553                 .name = "fclk_div5",
 554                 .ops = &clk_regmap_gate_ops,
 555                 .parent_names = (const char *[]){ "fclk_div5_div" },
 556                 .num_parents = 1,
 557         },
 558 };
 559
 560 static struct clk_fixed_factor gxbb_fclk_div7_div = {
 561         .mult = 1,
 562         .div = 7,
 563         .hw.init = &(struct clk_init_data){
 564                 .name = "fclk_div7_div",
 565                 .ops = &clk_fixed_factor_ops,
 566                 .parent_names = (const char *[]){ "fixed_pll" },
 567                 .num_parents = 1,
 568         },
 569 };
 570
 571 static struct clk_regmap gxbb_fclk_div7 = {
 572         .data = &(struct clk_regmap_gate_data){
 573                 .offset = HHI_MPLL_CNTL6,
 574                 .bit_idx = 31,
 575         },
 576         .hw.init = &(struct clk_init_data){
 577                 .name = "fclk_div7",
 578                 .ops = &clk_regmap_gate_ops,
 579                 .parent_names = (const char *[]){ "fclk_div7_div" },
 580                 .num_parents = 1,
 581         },
 582 };
 583
 584 static struct clk_regmap gxbb_mpll_prediv = {
 585         .data = &(struct clk_regmap_div_data){
 586                 .offset = HHI_MPLL_CNTL5,
 587                 .shift = 12,
 588                 .width = 1,
 589         },
 590         .hw.init = &(struct clk_init_data){
 591                 .name = "mpll_prediv",
 592                 .ops = &clk_regmap_divider_ro_ops,
 593                 .parent_names = (const char *[]){ "fixed_pll" },
 594                 .num_parents = 1,
 595         },
 596 };
 597
 598 static struct clk_regmap gxbb_mpll0_div = {
 599         .data = &(struct meson_clk_mpll_data){
 600                 .sdm = {
 601                         .reg_off = HHI_MPLL_CNTL7,
 602                         .shift   = 0,
 603                         .width   = 14,
 604                 },
 605                 .sdm_en = {
 606                         .reg_off = HHI_MPLL_CNTL7,
 607                         .shift   = 15,
 608                         .width   = 1,
 609                 },
 610                 .n2 = {
 611                         .reg_off = HHI_MPLL_CNTL7,
 612                         .shift   = 16,
 613                         .width   = 9,
 614                 },
 615                 .ssen = {
 616                         .reg_off = HHI_MPLL_CNTL,
 617                         .shift   = 25,
 618                         .width   = 1,
 619                 },
 620                 .lock = &meson_clk_lock,
 621         },
 622         .hw.init = &(struct clk_init_data){
 623                 .name = "mpll0_div",
 624                 .ops = &meson_clk_mpll_ops,
 625                 .parent_names = (const char *[]){ "mpll_prediv" },
 626                 .num_parents = 1,
 627         },
 628 };
 629
 630 static struct clk_regmap gxbb_mpll0 = {
 631         .data = &(struct clk_regmap_gate_data){
 632                 .offset = HHI_MPLL_CNTL7,
 633                 .bit_idx = 14,
 634         },
 635         .hw.init = &(struct clk_init_data){
 636                 .name = "mpll0",
 637                 .ops = &clk_regmap_gate_ops,
 638                 .parent_names = (const char *[]){ "mpll0_div" },
 639                 .num_parents = 1,
 640                 .flags = CLK_SET_RATE_PARENT,
 641         },
 642 };
 643
 644 static struct clk_regmap gxbb_mpll1_div = {
 645         .data = &(struct meson_clk_mpll_data){
 646                 .sdm = {
 647                         .reg_off = HHI_MPLL_CNTL8,
 648                         .shift   = 0,
 649                         .width   = 14,
 650                 },
 651                 .sdm_en = {
 652                         .reg_off = HHI_MPLL_CNTL8,
 653                         .shift   = 15,
 654                         .width   = 1,
 655                 },
 656                 .n2 = {
 657                         .reg_off = HHI_MPLL_CNTL8,
 658                         .shift   = 16,
 659                         .width   = 9,
 660                 },
 661                 .lock = &meson_clk_lock,
 662         },
 663         .hw.init = &(struct clk_init_data){
 664                 .name = "mpll1_div",
 665                 .ops = &meson_clk_mpll_ops,
 666                 .parent_names = (const char *[]){ "mpll_prediv" },
 667                 .num_parents = 1,
 668         },
 669 };
 670
 671 static struct clk_regmap gxbb_mpll1 = {
 672         .data = &(struct clk_regmap_gate_data){
 673                 .offset = HHI_MPLL_CNTL8,
 674                 .bit_idx = 14,
 675         },
 676         .hw.init = &(struct clk_init_data){
 677                 .name = "mpll1",
 678                 .ops = &clk_regmap_gate_ops,
 679                 .parent_names = (const char *[]){ "mpll1_div" },
 680                 .num_parents = 1,
 681                 .flags = CLK_SET_RATE_PARENT,
 682         },
 683 };
 684
 685 static struct clk_regmap gxbb_mpll2_div = {
 686         .data = &(struct meson_clk_mpll_data){
 687                 .sdm = {
 688                         .reg_off = HHI_MPLL_CNTL9,
 689                         .shift   = 0,
 690                         .width   = 14,
 691                 },
 692                 .sdm_en = {
 693                         .reg_off = HHI_MPLL_CNTL9,
 694                         .shift   = 15,
 695                         .width   = 1,
 696                 },
 697                 .n2 = {
 698                         .reg_off = HHI_MPLL_CNTL9,
 699                         .shift   = 16,
 700                         .width   = 9,
 701                 },
 702                 .lock = &meson_clk_lock,
 703         },
 704         .hw.init = &(struct clk_init_data){
 705                 .name = "mpll2_div",
 706                 .ops = &meson_clk_mpll_ops,
 707                 .parent_names = (const char *[]){ "mpll_prediv" },
 708                 .num_parents = 1,
 709         },
 710 };
 711
 712 static struct clk_regmap gxbb_mpll2 = {
 713         .data = &(struct clk_regmap_gate_data){
 714                 .offset = HHI_MPLL_CNTL9,
 715                 .bit_idx = 14,
 716         },
 717         .hw.init = &(struct clk_init_data){
 718                 .name = "mpll2",
 719                 .ops = &clk_regmap_gate_ops,
 720                 .parent_names = (const char *[]){ "mpll2_div" },
 721                 .num_parents = 1,
 722                 .flags = CLK_SET_RATE_PARENT,
 723         },
 724 };
 725
 726 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
 727 static const char * const clk81_parent_names[] = {
 728         "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
 729         "fclk_div3", "fclk_div5"
 730 };
 731
 732 static struct clk_regmap gxbb_mpeg_clk_sel = {
 733         .data = &(struct clk_regmap_mux_data){
 734                 .offset = HHI_MPEG_CLK_CNTL,
 735                 .mask = 0x7,
 736                 .shift = 12,
 737                 .table = mux_table_clk81,
 738         },
 739         .hw.init = &(struct clk_init_data){
 740                 .name = "mpeg_clk_sel",
 741                 .ops = &clk_regmap_mux_ro_ops,
 742                 /*
 743                  * bits 14:12 selects from 8 possible parents:
 744                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 745                  * fclk_div4, fclk_div3, fclk_div5
 746                  */
 747                 .parent_names = clk81_parent_names,
 748                 .num_parents = ARRAY_SIZE(clk81_parent_names),
 749         },
 750 };
 751
 752 static struct clk_regmap gxbb_mpeg_clk_div = {
 753         .data = &(struct clk_regmap_div_data){
 754                 .offset = HHI_MPEG_CLK_CNTL,
 755                 .shift = 0,
 756                 .width = 7,
 757         },
 758         .hw.init = &(struct clk_init_data){
 759                 .name = "mpeg_clk_div",
 760                 .ops = &clk_regmap_divider_ro_ops,
 761                 .parent_names = (const char *[]){ "mpeg_clk_sel" },
 762                 .num_parents = 1,
 763         },
 764 };
 765
 766 /* the mother of dragons gates */
 767 static struct clk_regmap gxbb_clk81 = {
 768         .data = &(struct clk_regmap_gate_data){
 769                 .offset = HHI_MPEG_CLK_CNTL,
 770                 .bit_idx = 7,
 771         },
 772         .hw.init = &(struct clk_init_data){
 773                 .name = "clk81",
 774                 .ops = &clk_regmap_gate_ops,
 775                 .parent_names = (const char *[]){ "mpeg_clk_div" },
 776                 .num_parents = 1,
 777                 .flags = CLK_IS_CRITICAL,
 778         },
 779 };
 780
 781 static struct clk_regmap gxbb_sar_adc_clk_sel = {
 782         .data = &(struct clk_regmap_mux_data){
 783                 .offset = HHI_SAR_CLK_CNTL,
 784                 .mask = 0x3,
 785                 .shift = 9,
 786         },
 787         .hw.init = &(struct clk_init_data){
 788                 .name = "sar_adc_clk_sel",
 789                 .ops = &clk_regmap_mux_ops,
 790                 /* NOTE: The datasheet doesn't list the parents for bit 10 */
 791                 .parent_names = (const char *[]){ "xtal", "clk81", },
 792                 .num_parents = 2,
 793         },
 794 };
 795
 796 static struct clk_regmap gxbb_sar_adc_clk_div = {
 797         .data = &(struct clk_regmap_div_data){
 798                 .offset = HHI_SAR_CLK_CNTL,
 799                 .shift = 0,
 800                 .width = 8,
 801         },
 802         .hw.init = &(struct clk_init_data){
 803                 .name = "sar_adc_clk_div",
 804                 .ops = &clk_regmap_divider_ops,
 805                 .parent_names = (const char *[]){ "sar_adc_clk_sel" },
 806                 .num_parents = 1,
 807         },
 808 };
 809
 810 static struct clk_regmap gxbb_sar_adc_clk = {
 811         .data = &(struct clk_regmap_gate_data){
 812                 .offset = HHI_SAR_CLK_CNTL,
 813                 .bit_idx = 8,
 814         },
 815         .hw.init = &(struct clk_init_data){
 816                 .name = "sar_adc_clk",
 817                 .ops = &clk_regmap_gate_ops,
 818                 .parent_names = (const char *[]){ "sar_adc_clk_div" },
 819                 .num_parents = 1,
 820                 .flags = CLK_SET_RATE_PARENT,
 821         },
 822 };
 823
 824 /*
 825  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
 826  * muxed by a glitch-free switch.
 827  */
 828
 829 static const char * const gxbb_mali_0_1_parent_names[] = {
 830         "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
 831         "fclk_div4", "fclk_div3", "fclk_div5"
 832 };
 833
 834 static struct clk_regmap gxbb_mali_0_sel = {
 835         .data = &(struct clk_regmap_mux_data){
 836                 .offset = HHI_MALI_CLK_CNTL,
 837                 .mask = 0x7,
 838                 .shift = 9,
 839         },
 840         .hw.init = &(struct clk_init_data){
 841                 .name = "mali_0_sel",
 842                 .ops = &clk_regmap_mux_ops,
 843                 /*
 844                  * bits 10:9 selects from 8 possible parents:
 845                  * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
 846                  * fclk_div4, fclk_div3, fclk_div5
 847                  */
 848                 .parent_names = gxbb_mali_0_1_parent_names,
 849                 .num_parents = 8,
 850                 .flags = CLK_SET_RATE_NO_REPARENT,
 851         },
 852 };
 853
 854 static struct clk_regmap gxbb_mali_0_div = {
 855         .data = &(struct clk_regmap_div_data){
 856                 .offset = HHI_MALI_CLK_CNTL,
 857                 .shift = 0,
 858                 .width = 7,
 859         },
 860         .hw.init = &(struct clk_init_data){
 861                 .name = "mali_0_div",
 862                 .ops = &clk_regmap_divider_ops,
 863                 .parent_names = (const char *[]){ "mali_0_sel" },
 864                 .num_parents = 1,
 865                 .flags = CLK_SET_RATE_NO_REPARENT,
 866         },
 867 };
 868
 869 static struct clk_regmap gxbb_mali_0 = {
 870         .data = &(struct clk_regmap_gate_data){
 871                 .offset = HHI_MALI_CLK_CNTL,
 872                 .bit_idx = 8,
 873         },
 874         .hw.init = &(struct clk_init_data){
 875                 .name = "mali_0",
 876                 .ops = &clk_regmap_gate_ops,
 877                 .parent_names = (const char *[]){ "mali_0_div" },
 878                 .num_parents = 1,
 879                 .flags = CLK_SET_RATE_PARENT,
 880         },
 881 };
 882
 883 static struct clk_regmap gxbb_mali_1_sel = {
 884         .data = &(struct clk_regmap_mux_data){
 885                 .offset = HHI_MALI_CLK_CNTL,
 886                 .mask = 0x7,
 887                 .shift = 25,
 888         },
 889         .hw.init = &(struct clk_init_data){
 890                 .name = "mali_1_sel",
 891                 .ops = &clk_regmap_mux_ops,
 892                 /*
 893                  * bits 10:9 selects from 8 possible parents:
 894                  * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
 895                  * fclk_div4, fclk_div3, fclk_div5
 896                  */
 897                 .parent_names = gxbb_mali_0_1_parent_names,
 898                 .num_parents = 8,
 899                 .flags = CLK_SET_RATE_NO_REPARENT,
 900         },
 901 };
 902
 903 static struct clk_regmap gxbb_mali_1_div = {
 904         .data = &(struct clk_regmap_div_data){
 905                 .offset = HHI_MALI_CLK_CNTL,
 906                 .shift = 16,
 907                 .width = 7,
 908         },
 909         .hw.init = &(struct clk_init_data){
 910                 .name = "mali_1_div",
 911                 .ops = &clk_regmap_divider_ops,
 912                 .parent_names = (const char *[]){ "mali_1_sel" },
 913                 .num_parents = 1,
 914                 .flags = CLK_SET_RATE_NO_REPARENT,
 915         },
 916 };
 917
 918 static struct clk_regmap gxbb_mali_1 = {
 919         .data = &(struct clk_regmap_gate_data){
 920                 .offset = HHI_MALI_CLK_CNTL,
 921                 .bit_idx = 24,
 922         },
 923         .hw.init = &(struct clk_init_data){
 924                 .name = "mali_1",
 925                 .ops = &clk_regmap_gate_ops,
 926                 .parent_names = (const char *[]){ "mali_1_div" },
 927                 .num_parents = 1,
 928                 .flags = CLK_SET_RATE_PARENT,
 929         },
 930 };
 931
 932 static const char * const gxbb_mali_parent_names[] = {
 933         "mali_0", "mali_1"
 934 };
 935
 936 static struct clk_regmap gxbb_mali = {
 937         .data = &(struct clk_regmap_mux_data){
 938                 .offset = HHI_MALI_CLK_CNTL,
 939                 .mask = 1,
 940                 .shift = 31,
 941         },
 942         .hw.init = &(struct clk_init_data){
 943                 .name = "mali",
 944                 .ops = &clk_regmap_mux_ops,
 945                 .parent_names = gxbb_mali_parent_names,
 946                 .num_parents = 2,
 947                 .flags = CLK_SET_RATE_NO_REPARENT,
 948         },
 949 };
 950
 951 static struct clk_regmap gxbb_cts_amclk_sel = {
 952         .data = &(struct clk_regmap_mux_data){
 953                 .offset = HHI_AUD_CLK_CNTL,
 954                 .mask = 0x3,
 955                 .shift = 9,
 956                 .table = (u32[]){ 1, 2, 3 },
 957                 .flags = CLK_MUX_ROUND_CLOSEST,
 958         },
 959         .hw.init = &(struct clk_init_data){
 960                 .name = "cts_amclk_sel",
 961                 .ops = &clk_regmap_mux_ops,
 962                 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
 963                 .num_parents = 3,
 964         },
 965 };
 966
 967 static struct clk_regmap gxbb_cts_amclk_div = {
 968         .data = &(struct clk_regmap_div_data) {
 969                 .offset = HHI_AUD_CLK_CNTL,
 970                 .shift = 0,
 971                 .width = 8,
 972                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
 973         },
 974         .hw.init = &(struct clk_init_data){
 975                 .name = "cts_amclk_div",
 976                 .ops = &clk_regmap_divider_ops,
 977                 .parent_names = (const char *[]){ "cts_amclk_sel" },
 978                 .num_parents = 1,
 979                 .flags = CLK_SET_RATE_PARENT,
 980         },
 981 };
 982
 983 static struct clk_regmap gxbb_cts_amclk = {
 984         .data = &(struct clk_regmap_gate_data){
 985                 .offset = HHI_AUD_CLK_CNTL,
 986                 .bit_idx = 8,
 987         },
 988         .hw.init = &(struct clk_init_data){
 989                 .name = "cts_amclk",
 990                 .ops = &clk_regmap_gate_ops,
 991                 .parent_names = (const char *[]){ "cts_amclk_div" },
 992                 .num_parents = 1,
 993                 .flags = CLK_SET_RATE_PARENT,
 994         },
 995 };
 996
 997 static struct clk_regmap gxbb_cts_mclk_i958_sel = {
 998         .data = &(struct clk_regmap_mux_data){
 999                 .offset = HHI_AUD_CLK_CNTL2,
1000                 .mask = 0x3,
1001                 .shift = 25,
1002                 .table = (u32[]){ 1, 2, 3 },
1003                 .flags = CLK_MUX_ROUND_CLOSEST,
1004         },
1005         .hw.init = &(struct clk_init_data) {
1006                 .name = "cts_mclk_i958_sel",
1007                 .ops = &clk_regmap_mux_ops,
1008                 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
1009                 .num_parents = 3,
1010         },
1011 };
1012
1013 static struct clk_regmap gxbb_cts_mclk_i958_div = {
1014         .data = &(struct clk_regmap_div_data){
1015                 .offset = HHI_AUD_CLK_CNTL2,
1016                 .shift = 16,
1017                 .width = 8,
1018                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1019         },
1020         .hw.init = &(struct clk_init_data) {
1021                 .name = "cts_mclk_i958_div",
1022                 .ops = &clk_regmap_divider_ops,
1023                 .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
1024                 .num_parents = 1,
1025                 .flags = CLK_SET_RATE_PARENT,
1026         },
1027 };
1028
1029 static struct clk_regmap gxbb_cts_mclk_i958 = {
1030         .data = &(struct clk_regmap_gate_data){
1031                 .offset = HHI_AUD_CLK_CNTL2,
1032                 .bit_idx = 24,
1033         },
1034         .hw.init = &(struct clk_init_data){
1035                 .name = "cts_mclk_i958",
1036                 .ops = &clk_regmap_gate_ops,
1037                 .parent_names = (const char *[]){ "cts_mclk_i958_div" },
1038                 .num_parents = 1,
1039                 .flags = CLK_SET_RATE_PARENT,
1040         },
1041 };
1042
1043 static struct clk_regmap gxbb_cts_i958 = {
1044         .data = &(struct clk_regmap_mux_data){
1045                 .offset = HHI_AUD_CLK_CNTL2,
1046                 .mask = 0x1,
1047                 .shift = 27,
1048                 },
1049         .hw.init = &(struct clk_init_data){
1050                 .name = "cts_i958",
1051                 .ops = &clk_regmap_mux_ops,
1052                 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
1053                 .num_parents = 2,
1054                 /*
1055                  *The parent is specific to origin of the audio data. Let the
1056                  * consumer choose the appropriate parent
1057                  */
1058                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1059         },
1060 };
1061
1062 static struct clk_regmap gxbb_32k_clk_div = {
1063         .data = &(struct clk_regmap_div_data){
1064                 .offset = HHI_32K_CLK_CNTL,
1065                 .shift = 0,
1066                 .width = 14,
1067         },
1068         .hw.init = &(struct clk_init_data){
1069                 .name = "32k_clk_div",
1070                 .ops = &clk_regmap_divider_ops,
1071                 .parent_names = (const char *[]){ "32k_clk_sel" },
1072                 .num_parents = 1,
1073                 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
1074         },
1075 };
1076
1077 static struct clk_regmap gxbb_32k_clk = {
1078         .data = &(struct clk_regmap_gate_data){
1079                 .offset = HHI_32K_CLK_CNTL,
1080                 .bit_idx = 15,
1081         },
1082         .hw.init = &(struct clk_init_data){
1083                 .name = "32k_clk",
1084                 .ops = &clk_regmap_gate_ops,
1085                 .parent_names = (const char *[]){ "32k_clk_div" },
1086                 .num_parents = 1,
1087                 .flags = CLK_SET_RATE_PARENT,
1088         },
1089 };
1090
1091 static const char * const gxbb_32k_clk_parent_names[] = {
1092         "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
1093 };
1094
1095 static struct clk_regmap gxbb_32k_clk_sel = {
1096         .data = &(struct clk_regmap_mux_data){
1097                 .offset = HHI_32K_CLK_CNTL,
1098                 .mask = 0x3,
1099                 .shift = 16,
1100                 },
1101         .hw.init = &(struct clk_init_data){
1102                 .name = "32k_clk_sel",
1103                 .ops = &clk_regmap_mux_ops,
1104                 .parent_names = gxbb_32k_clk_parent_names,
1105                 .num_parents = 4,
1106                 .flags = CLK_SET_RATE_PARENT,
1107         },
1108 };
1109
1110 static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
1111         "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
1112
1113         /*
1114          * Following these parent clocks, we should also have had mpll2, mpll3
1115          * and gp0_pll but these clocks are too precious to be used here. All
1116          * the necessary rates for MMC and NAND operation can be acheived using
1117          * xtal or fclk_div clocks
1118          */
1119 };
1120
1121 /* SDIO clock */
1122 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
1123         .data = &(struct clk_regmap_mux_data){
1124                 .offset = HHI_SD_EMMC_CLK_CNTL,
1125                 .mask = 0x7,
1126                 .shift = 9,
1127         },
1128         .hw.init = &(struct clk_init_data) {
1129                 .name = "sd_emmc_a_clk0_sel",
1130                 .ops = &clk_regmap_mux_ops,
1131                 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1132                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1133                 .flags = CLK_SET_RATE_PARENT,
1134         },
1135 };
1136
1137 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1138         .data = &(struct clk_regmap_div_data){
1139                 .offset = HHI_SD_EMMC_CLK_CNTL,
1140                 .shift = 0,
1141                 .width = 7,
1142                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1143         },
1144         .hw.init = &(struct clk_init_data) {
1145                 .name = "sd_emmc_a_clk0_div",
1146                 .ops = &clk_regmap_divider_ops,
1147                 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
1148                 .num_parents = 1,
1149                 .flags = CLK_SET_RATE_PARENT,
1150         },
1151 };
1152
1153 static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1154         .data = &(struct clk_regmap_gate_data){
1155                 .offset = HHI_SD_EMMC_CLK_CNTL,
1156                 .bit_idx = 7,
1157         },
1158         .hw.init = &(struct clk_init_data){
1159                 .name = "sd_emmc_a_clk0",
1160                 .ops = &clk_regmap_gate_ops,
1161                 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
1162                 .num_parents = 1,
1163                 .flags = CLK_SET_RATE_PARENT,
1164         },
1165 };
1166
1167 /* SDcard clock */
1168 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1169         .data = &(struct clk_regmap_mux_data){
1170                 .offset = HHI_SD_EMMC_CLK_CNTL,
1171                 .mask = 0x7,
1172                 .shift = 25,
1173         },
1174         .hw.init = &(struct clk_init_data) {
1175                 .name = "sd_emmc_b_clk0_sel",
1176                 .ops = &clk_regmap_mux_ops,
1177                 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1178                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1179                 .flags = CLK_SET_RATE_PARENT,
1180         },
1181 };
1182
1183 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1184         .data = &(struct clk_regmap_div_data){
1185                 .offset = HHI_SD_EMMC_CLK_CNTL,
1186                 .shift = 16,
1187                 .width = 7,
1188                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1189         },
1190         .hw.init = &(struct clk_init_data) {
1191                 .name = "sd_emmc_b_clk0_div",
1192                 .ops = &clk_regmap_divider_ops,
1193                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
1194                 .num_parents = 1,
1195                 .flags = CLK_SET_RATE_PARENT,
1196         },
1197 };
1198
1199 static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1200         .data = &(struct clk_regmap_gate_data){
1201                 .offset = HHI_SD_EMMC_CLK_CNTL,
1202                 .bit_idx = 23,
1203         },
1204         .hw.init = &(struct clk_init_data){
1205                 .name = "sd_emmc_b_clk0",
1206                 .ops = &clk_regmap_gate_ops,
1207                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
1208                 .num_parents = 1,
1209                 .flags = CLK_SET_RATE_PARENT,
1210         },
1211 };
1212
1213 /* EMMC/NAND clock */
1214 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1215         .data = &(struct clk_regmap_mux_data){
1216                 .offset = HHI_NAND_CLK_CNTL,
1217                 .mask = 0x7,
1218                 .shift = 9,
1219         },
1220         .hw.init = &(struct clk_init_data) {
1221                 .name = "sd_emmc_c_clk0_sel",
1222                 .ops = &clk_regmap_mux_ops,
1223                 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1224                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1225                 .flags = CLK_SET_RATE_PARENT,
1226         },
1227 };
1228
1229 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1230         .data = &(struct clk_regmap_div_data){
1231                 .offset = HHI_NAND_CLK_CNTL,
1232                 .shift = 0,
1233                 .width = 7,
1234                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1235         },
1236         .hw.init = &(struct clk_init_data) {
1237                 .name = "sd_emmc_c_clk0_div",
1238                 .ops = &clk_regmap_divider_ops,
1239                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
1240                 .num_parents = 1,
1241                 .flags = CLK_SET_RATE_PARENT,
1242         },
1243 };
1244
1245 static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1246         .data = &(struct clk_regmap_gate_data){
1247                 .offset = HHI_NAND_CLK_CNTL,
1248                 .bit_idx = 7,
1249         },
1250         .hw.init = &(struct clk_init_data){
1251                 .name = "sd_emmc_c_clk0",
1252                 .ops = &clk_regmap_gate_ops,
1253                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
1254                 .num_parents = 1,
1255                 .flags = CLK_SET_RATE_PARENT,
1256         },
1257 };
1258
1259 /* VPU Clock */
1260
1261 static const char * const gxbb_vpu_parent_names[] = {
1262         "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1263 };
1264
1265 static struct clk_regmap gxbb_vpu_0_sel = {
1266         .data = &(struct clk_regmap_mux_data){
1267                 .offset = HHI_VPU_CLK_CNTL,
1268                 .mask = 0x3,
1269                 .shift = 9,
1270         },
1271         .hw.init = &(struct clk_init_data){
1272                 .name = "vpu_0_sel",
1273                 .ops = &clk_regmap_mux_ops,
1274                 /*
1275                  * bits 9:10 selects from 4 possible parents:
1276                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1277                  */
1278                 .parent_names = gxbb_vpu_parent_names,
1279                 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1280                 .flags = CLK_SET_RATE_NO_REPARENT,
1281         },
1282 };
1283
1284 static struct clk_regmap gxbb_vpu_0_div = {
1285         .data = &(struct clk_regmap_div_data){
1286                 .offset = HHI_VPU_CLK_CNTL,
1287                 .shift = 0,
1288                 .width = 7,
1289         },
1290         .hw.init = &(struct clk_init_data){
1291                 .name = "vpu_0_div",
1292                 .ops = &clk_regmap_divider_ops,
1293                 .parent_names = (const char *[]){ "vpu_0_sel" },
1294                 .num_parents = 1,
1295                 .flags = CLK_SET_RATE_PARENT,
1296         },
1297 };
1298
1299 static struct clk_regmap gxbb_vpu_0 = {
1300         .data = &(struct clk_regmap_gate_data){
1301                 .offset = HHI_VPU_CLK_CNTL,
1302                 .bit_idx = 8,
1303         },
1304         .hw.init = &(struct clk_init_data) {
1305                 .name = "vpu_0",
1306                 .ops = &clk_regmap_gate_ops,
1307                 .parent_names = (const char *[]){ "vpu_0_div" },
1308                 .num_parents = 1,
1309                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1310         },
1311 };
1312
1313 static struct clk_regmap gxbb_vpu_1_sel = {
1314         .data = &(struct clk_regmap_mux_data){
1315                 .offset = HHI_VPU_CLK_CNTL,
1316                 .mask = 0x3,
1317                 .shift = 25,
1318         },
1319         .hw.init = &(struct clk_init_data){
1320                 .name = "vpu_1_sel",
1321                 .ops = &clk_regmap_mux_ops,
1322                 /*
1323                  * bits 25:26 selects from 4 possible parents:
1324                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1325                  */
1326                 .parent_names = gxbb_vpu_parent_names,
1327                 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1328                 .flags = CLK_SET_RATE_NO_REPARENT,
1329         },
1330 };
1331
1332 static struct clk_regmap gxbb_vpu_1_div = {
1333         .data = &(struct clk_regmap_div_data){
1334                 .offset = HHI_VPU_CLK_CNTL,
1335                 .shift = 16,
1336                 .width = 7,
1337         },
1338         .hw.init = &(struct clk_init_data){
1339                 .name = "vpu_1_div",
1340                 .ops = &clk_regmap_divider_ops,
1341                 .parent_names = (const char *[]){ "vpu_1_sel" },
1342                 .num_parents = 1,
1343                 .flags = CLK_SET_RATE_PARENT,
1344         },
1345 };
1346
1347 static struct clk_regmap gxbb_vpu_1 = {
1348         .data = &(struct clk_regmap_gate_data){
1349                 .offset = HHI_VPU_CLK_CNTL,
1350                 .bit_idx = 24,
1351         },
1352         .hw.init = &(struct clk_init_data) {
1353                 .name = "vpu_1",
1354                 .ops = &clk_regmap_gate_ops,
1355                 .parent_names = (const char *[]){ "vpu_1_div" },
1356                 .num_parents = 1,
1357                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1358         },
1359 };
1360
1361 static struct clk_regmap gxbb_vpu = {
1362         .data = &(struct clk_regmap_mux_data){
1363                 .offset = HHI_VPU_CLK_CNTL,
1364                 .mask = 1,
1365                 .shift = 31,
1366         },
1367         .hw.init = &(struct clk_init_data){
1368                 .name = "vpu",
1369                 .ops = &clk_regmap_mux_ops,
1370                 /*
1371                  * bit 31 selects from 2 possible parents:
1372                  * vpu_0 or vpu_1
1373                  */
1374                 .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
1375                 .num_parents = 2,
1376                 .flags = CLK_SET_RATE_NO_REPARENT,
1377         },
1378 };
1379
1380 /* VAPB Clock */
1381
1382 static const char * const gxbb_vapb_parent_names[] = {
1383         "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1384 };
1385
1386 static struct clk_regmap gxbb_vapb_0_sel = {
1387         .data = &(struct clk_regmap_mux_data){
1388                 .offset = HHI_VAPBCLK_CNTL,
1389                 .mask = 0x3,
1390                 .shift = 9,
1391         },
1392         .hw.init = &(struct clk_init_data){
1393                 .name = "vapb_0_sel",
1394                 .ops = &clk_regmap_mux_ops,
1395                 /*
1396                  * bits 9:10 selects from 4 possible parents:
1397                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1398                  */
1399                 .parent_names = gxbb_vapb_parent_names,
1400                 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1401                 .flags = CLK_SET_RATE_NO_REPARENT,
1402         },
1403 };
1404
1405 static struct clk_regmap gxbb_vapb_0_div = {
1406         .data = &(struct clk_regmap_div_data){
1407                 .offset = HHI_VAPBCLK_CNTL,
1408                 .shift = 0,
1409                 .width = 7,
1410         },
1411         .hw.init = &(struct clk_init_data){
1412                 .name = "vapb_0_div",
1413                 .ops = &clk_regmap_divider_ops,
1414                 .parent_names = (const char *[]){ "vapb_0_sel" },
1415                 .num_parents = 1,
1416                 .flags = CLK_SET_RATE_PARENT,
1417         },
1418 };
1419
1420 static struct clk_regmap gxbb_vapb_0 = {
1421         .data = &(struct clk_regmap_gate_data){
1422                 .offset = HHI_VAPBCLK_CNTL,
1423                 .bit_idx = 8,
1424         },
1425         .hw.init = &(struct clk_init_data) {
1426                 .name = "vapb_0",
1427                 .ops = &clk_regmap_gate_ops,
1428                 .parent_names = (const char *[]){ "vapb_0_div" },
1429                 .num_parents = 1,
1430                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1431         },
1432 };
1433
1434 static struct clk_regmap gxbb_vapb_1_sel = {
1435         .data = &(struct clk_regmap_mux_data){
1436                 .offset = HHI_VAPBCLK_CNTL,
1437                 .mask = 0x3,
1438                 .shift = 25,
1439         },
1440         .hw.init = &(struct clk_init_data){
1441                 .name = "vapb_1_sel",
1442                 .ops = &clk_regmap_mux_ops,
1443                 /*
1444                  * bits 25:26 selects from 4 possible parents:
1445                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1446                  */
1447                 .parent_names = gxbb_vapb_parent_names,
1448                 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1449                 .flags = CLK_SET_RATE_NO_REPARENT,
1450         },
1451 };
1452
1453 static struct clk_regmap gxbb_vapb_1_div = {
1454         .data = &(struct clk_regmap_div_data){
1455                 .offset = HHI_VAPBCLK_CNTL,
1456                 .shift = 16,
1457                 .width = 7,
1458         },
1459         .hw.init = &(struct clk_init_data){
1460                 .name = "vapb_1_div",
1461                 .ops = &clk_regmap_divider_ops,
1462                 .parent_names = (const char *[]){ "vapb_1_sel" },
1463                 .num_parents = 1,
1464                 .flags = CLK_SET_RATE_PARENT,
1465         },
1466 };
1467
1468 static struct clk_regmap gxbb_vapb_1 = {
1469         .data = &(struct clk_regmap_gate_data){
1470                 .offset = HHI_VAPBCLK_CNTL,
1471                 .bit_idx = 24,
1472         },
1473         .hw.init = &(struct clk_init_data) {
1474                 .name = "vapb_1",
1475                 .ops = &clk_regmap_gate_ops,
1476                 .parent_names = (const char *[]){ "vapb_1_div" },
1477                 .num_parents = 1,
1478                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1479         },
1480 };
1481
1482 static struct clk_regmap gxbb_vapb_sel = {
1483         .data = &(struct clk_regmap_mux_data){
1484                 .offset = HHI_VAPBCLK_CNTL,
1485                 .mask = 1,
1486                 .shift = 31,
1487         },
1488         .hw.init = &(struct clk_init_data){
1489                 .name = "vapb_sel",
1490                 .ops = &clk_regmap_mux_ops,
1491                 /*
1492                  * bit 31 selects from 2 possible parents:
1493                  * vapb_0 or vapb_1
1494                  */
1495                 .parent_names = (const char *[]){ "vapb_0", "vapb_1" },
1496                 .num_parents = 2,
1497                 .flags = CLK_SET_RATE_NO_REPARENT,
1498         },
1499 };
1500
1501 static struct clk_regmap gxbb_vapb = {
1502         .data = &(struct clk_regmap_gate_data){
1503                 .offset = HHI_VAPBCLK_CNTL,
1504                 .bit_idx = 30,
1505         },
1506         .hw.init = &(struct clk_init_data) {
1507                 .name = "vapb",
1508                 .ops = &clk_regmap_gate_ops,
1509                 .parent_names = (const char *[]){ "vapb_sel" },
1510                 .num_parents = 1,
1511                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1512         },
1513 };
1514
1515 /* VDEC clocks */
1516
1517 static const char * const gxbb_vdec_parent_names[] = {
1518         "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1519 };
1520
1521 static struct clk_regmap gxbb_vdec_1_sel = {
1522         .data = &(struct clk_regmap_mux_data){
1523                 .offset = HHI_VDEC_CLK_CNTL,
1524                 .mask = 0x3,
1525                 .shift = 9,
1526                 .flags = CLK_MUX_ROUND_CLOSEST,
1527         },
1528         .hw.init = &(struct clk_init_data){
1529                 .name = "vdec_1_sel",
1530                 .ops = &clk_regmap_mux_ops,
1531                 .parent_names = gxbb_vdec_parent_names,
1532                 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
1533                 .flags = CLK_SET_RATE_PARENT,
1534         },
1535 };
1536
1537 static struct clk_regmap gxbb_vdec_1_div = {
1538         .data = &(struct clk_regmap_div_data){
1539                 .offset = HHI_VDEC_CLK_CNTL,
1540                 .shift = 0,
1541                 .width = 7,
1542         },
1543         .hw.init = &(struct clk_init_data){
1544                 .name = "vdec_1_div",
1545                 .ops = &clk_regmap_divider_ops,
1546                 .parent_names = (const char *[]){ "vdec_1_sel" },
1547                 .num_parents = 1,
1548                 .flags = CLK_SET_RATE_PARENT,
1549         },
1550 };
1551
1552 static struct clk_regmap gxbb_vdec_1 = {
1553         .data = &(struct clk_regmap_gate_data){
1554                 .offset = HHI_VDEC_CLK_CNTL,
1555                 .bit_idx = 8,
1556         },
1557         .hw.init = &(struct clk_init_data) {
1558                 .name = "vdec_1",
1559                 .ops = &clk_regmap_gate_ops,
1560                 .parent_names = (const char *[]){ "vdec_1_div" },
1561                 .num_parents = 1,
1562                 .flags = CLK_SET_RATE_PARENT,
1563         },
1564 };
1565
1566 static struct clk_regmap gxbb_vdec_hevc_sel = {
1567         .data = &(struct clk_regmap_mux_data){
1568                 .offset = HHI_VDEC2_CLK_CNTL,
1569                 .mask = 0x3,
1570                 .shift = 25,
1571                 .flags = CLK_MUX_ROUND_CLOSEST,
1572         },
1573         .hw.init = &(struct clk_init_data){
1574                 .name = "vdec_hevc_sel",
1575                 .ops = &clk_regmap_mux_ops,
1576                 .parent_names = gxbb_vdec_parent_names,
1577                 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
1578                 .flags = CLK_SET_RATE_PARENT,
1579         },
1580 };
1581
1582 static struct clk_regmap gxbb_vdec_hevc_div = {
1583         .data = &(struct clk_regmap_div_data){
1584                 .offset = HHI_VDEC2_CLK_CNTL,
1585                 .shift = 16,
1586                 .width = 7,
1587         },
1588         .hw.init = &(struct clk_init_data){
1589                 .name = "vdec_hevc_div",
1590                 .ops = &clk_regmap_divider_ops,
1591                 .parent_names = (const char *[]){ "vdec_hevc_sel" },
1592                 .num_parents = 1,
1593                 .flags = CLK_SET_RATE_PARENT,
1594         },
1595 };
1596
1597 static struct clk_regmap gxbb_vdec_hevc = {
1598         .data = &(struct clk_regmap_gate_data){
1599                 .offset = HHI_VDEC2_CLK_CNTL,
1600                 .bit_idx = 24,
1601         },
1602         .hw.init = &(struct clk_init_data) {
1603                 .name = "vdec_hevc",
1604                 .ops = &clk_regmap_gate_ops,
1605                 .parent_names = (const char *[]){ "vdec_hevc_div" },
1606                 .num_parents = 1,
1607                 .flags = CLK_SET_RATE_PARENT,
1608         },
1609 };
1610
1611 static u32 mux_table_gen_clk[]  = { 0, 4, 5, 6, 7, 8,
1612                                     9, 10, 11, 13, 14, };
1613 static const char * const gen_clk_parent_names[] = {
1614         "xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2",
1615         "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
1616 };
1617
1618 static struct clk_regmap gxbb_gen_clk_sel = {
1619         .data = &(struct clk_regmap_mux_data){
1620                 .offset = HHI_GEN_CLK_CNTL,
1621                 .mask = 0xf,
1622                 .shift = 12,
1623                 .table = mux_table_gen_clk,
1624         },
1625         .hw.init = &(struct clk_init_data){
1626                 .name = "gen_clk_sel",
1627                 .ops = &clk_regmap_mux_ops,
1628                 /*
1629                  * bits 15:12 selects from 14 possible parents:
1630                  * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
1631                  * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
1632                  * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
1633                  */
1634                 .parent_names = gen_clk_parent_names,
1635                 .num_parents = ARRAY_SIZE(gen_clk_parent_names),
1636         },
1637 };
1638
1639 static struct clk_regmap gxbb_gen_clk_div = {
1640         .data = &(struct clk_regmap_div_data){
1641                 .offset = HHI_GEN_CLK_CNTL,
1642                 .shift = 0,
1643                 .width = 11,
1644         },
1645         .hw.init = &(struct clk_init_data){
1646                 .name = "gen_clk_div",
1647                 .ops = &clk_regmap_divider_ops,
1648                 .parent_names = (const char *[]){ "gen_clk_sel" },
1649                 .num_parents = 1,
1650                 .flags = CLK_SET_RATE_PARENT,
1651         },
1652 };
1653
1654 static struct clk_regmap gxbb_gen_clk = {
1655         .data = &(struct clk_regmap_gate_data){
1656                 .offset = HHI_GEN_CLK_CNTL,
1657                 .bit_idx = 7,
1658         },
1659         .hw.init = &(struct clk_init_data){
1660                 .name = "gen_clk",
1661                 .ops = &clk_regmap_gate_ops,
1662                 .parent_names = (const char *[]){ "gen_clk_div" },
1663                 .num_parents = 1,
1664                 .flags = CLK_SET_RATE_PARENT,
1665         },
1666 };
1667
1668 /* Everything Else (EE) domain gates */
1669 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
1670 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
1671 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
1672 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
1673 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
1674 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
1675 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
1676 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
1677 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
1678 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
1679 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
1680 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
1681 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
1682 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
1683 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
1684 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
1685 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
1686 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
1687 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
1688 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
1689 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
1690 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
1691
1692 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
1693 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
1694 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
1695 static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
1696 static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
1697 static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
1698 static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
1699 static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
1700 static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
1701 static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
1702 static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
1703 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
1704 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
1705 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
1706 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
1707 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
1708 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
1709 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
1710 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
1711 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
1712 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
1713 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
1714 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
1715 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
1716 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
1717
1718 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1719 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1720 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
1721 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
1722 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
1723 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
1724 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
1725 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
1726 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
1727 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
1728 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
1729 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1730 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
1731
1732 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
1733 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
1734 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
1735 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
1736 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
1737 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
1738 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
1739 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
1740 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
1741 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
1742 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
1743 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
1744 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
1745 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
1746 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
1747 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
1748
1749 /* Always On (AO) domain gates */
1750
1751 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
1752 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
1753 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
1754 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
1755 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
1756
1757 /* Array of all clocks provided by this provider */
1758
1759 static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
1760         .hws = {
1761                 [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
1762                 [CLKID_HDMI_PLL]            = &gxbb_hdmi_pll.hw,
1763                 [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
1764                 [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
1765                 [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
1766                 [CLKID_FCLK_DIV4]           = &gxbb_fclk_div4.hw,
1767                 [CLKID_FCLK_DIV5]           = &gxbb_fclk_div5.hw,
1768                 [CLKID_FCLK_DIV7]           = &gxbb_fclk_div7.hw,
1769                 [CLKID_GP0_PLL]             = &gxbb_gp0_pll.hw,
1770                 [CLKID_MPEG_SEL]            = &gxbb_mpeg_clk_sel.hw,
1771                 [CLKID_MPEG_DIV]            = &gxbb_mpeg_clk_div.hw,
1772                 [CLKID_CLK81]               = &gxbb_clk81.hw,
1773                 [CLKID_MPLL0]               = &gxbb_mpll0.hw,
1774                 [CLKID_MPLL1]               = &gxbb_mpll1.hw,
1775                 [CLKID_MPLL2]               = &gxbb_mpll2.hw,
1776                 [CLKID_DDR]                 = &gxbb_ddr.hw,
1777                 [CLKID_DOS]                 = &gxbb_dos.hw,
1778                 [CLKID_ISA]                 = &gxbb_isa.hw,
1779                 [CLKID_PL301]               = &gxbb_pl301.hw,
1780                 [CLKID_PERIPHS]             = &gxbb_periphs.hw,
1781                 [CLKID_SPICC]               = &gxbb_spicc.hw,
1782                 [CLKID_I2C]                 = &gxbb_i2c.hw,
1783                 [CLKID_SAR_ADC]             = &gxbb_sar_adc.hw,
1784                 [CLKID_SMART_CARD]          = &gxbb_smart_card.hw,
1785                 [CLKID_RNG0]                = &gxbb_rng0.hw,
1786                 [CLKID_UART0]               = &gxbb_uart0.hw,
1787                 [CLKID_SDHC]                = &gxbb_sdhc.hw,
1788                 [CLKID_STREAM]              = &gxbb_stream.hw,
1789                 [CLKID_ASYNC_FIFO]          = &gxbb_async_fifo.hw,
1790                 [CLKID_SDIO]                = &gxbb_sdio.hw,
1791                 [CLKID_ABUF]                = &gxbb_abuf.hw,
1792                 [CLKID_HIU_IFACE]           = &gxbb_hiu_iface.hw,
1793                 [CLKID_ASSIST_MISC]         = &gxbb_assist_misc.hw,
1794                 [CLKID_SPI]                 = &gxbb_spi.hw,
1795                 [CLKID_I2S_SPDIF]           = &gxbb_i2s_spdif.hw,
1796                 [CLKID_ETH]                 = &gxbb_eth.hw,
1797                 [CLKID_DEMUX]               = &gxbb_demux.hw,
1798                 [CLKID_AIU_GLUE]            = &gxbb_aiu_glue.hw,
1799                 [CLKID_IEC958]              = &gxbb_iec958.hw,
1800                 [CLKID_I2S_OUT]             = &gxbb_i2s_out.hw,
1801                 [CLKID_AMCLK]               = &gxbb_amclk.hw,
1802                 [CLKID_AIFIFO2]             = &gxbb_aififo2.hw,
1803                 [CLKID_MIXER]               = &gxbb_mixer.hw,
1804                 [CLKID_MIXER_IFACE]         = &gxbb_mixer_iface.hw,
1805                 [CLKID_ADC]                 = &gxbb_adc.hw,
1806                 [CLKID_BLKMV]               = &gxbb_blkmv.hw,
1807                 [CLKID_AIU]                 = &gxbb_aiu.hw,
1808                 [CLKID_UART1]               = &gxbb_uart1.hw,
1809                 [CLKID_G2D]                 = &gxbb_g2d.hw,
1810                 [CLKID_USB0]                = &gxbb_usb0.hw,
1811                 [CLKID_USB1]                = &gxbb_usb1.hw,
1812                 [CLKID_RESET]               = &gxbb_reset.hw,
1813                 [CLKID_NAND]                = &gxbb_nand.hw,
1814                 [CLKID_DOS_PARSER]          = &gxbb_dos_parser.hw,
1815                 [CLKID_USB]                 = &gxbb_usb.hw,
1816                 [CLKID_VDIN1]               = &gxbb_vdin1.hw,
1817                 [CLKID_AHB_ARB0]            = &gxbb_ahb_arb0.hw,
1818                 [CLKID_EFUSE]               = &gxbb_efuse.hw,
1819                 [CLKID_BOOT_ROM]            = &gxbb_boot_rom.hw,
1820                 [CLKID_AHB_DATA_BUS]        = &gxbb_ahb_data_bus.hw,
1821                 [CLKID_AHB_CTRL_BUS]        = &gxbb_ahb_ctrl_bus.hw,
1822                 [CLKID_HDMI_INTR_SYNC]      = &gxbb_hdmi_intr_sync.hw,
1823                 [CLKID_HDMI_PCLK]           = &gxbb_hdmi_pclk.hw,
1824                 [CLKID_USB1_DDR_BRIDGE]     = &gxbb_usb1_ddr_bridge.hw,
1825                 [CLKID_USB0_DDR_BRIDGE]     = &gxbb_usb0_ddr_bridge.hw,
1826                 [CLKID_MMC_PCLK]            = &gxbb_mmc_pclk.hw,
1827                 [CLKID_DVIN]                = &gxbb_dvin.hw,
1828                 [CLKID_UART2]               = &gxbb_uart2.hw,
1829                 [CLKID_SANA]                = &gxbb_sana.hw,
1830                 [CLKID_VPU_INTR]            = &gxbb_vpu_intr.hw,
1831                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
1832                 [CLKID_CLK81_A53]           = &gxbb_clk81_a53.hw,
1833                 [CLKID_VCLK2_VENCI0]        = &gxbb_vclk2_venci0.hw,
1834                 [CLKID_VCLK2_VENCI1]        = &gxbb_vclk2_venci1.hw,
1835                 [CLKID_VCLK2_VENCP0]        = &gxbb_vclk2_vencp0.hw,
1836                 [CLKID_VCLK2_VENCP1]        = &gxbb_vclk2_vencp1.hw,
1837                 [CLKID_GCLK_VENCI_INT0]     = &gxbb_gclk_venci_int0.hw,
1838                 [CLKID_GCLK_VENCI_INT]      = &gxbb_gclk_vencp_int.hw,
1839                 [CLKID_DAC_CLK]             = &gxbb_dac_clk.hw,
1840                 [CLKID_AOCLK_GATE]          = &gxbb_aoclk_gate.hw,
1841                 [CLKID_IEC958_GATE]         = &gxbb_iec958_gate.hw,
1842                 [CLKID_ENC480P]             = &gxbb_enc480p.hw,
1843                 [CLKID_RNG1]                = &gxbb_rng1.hw,
1844                 [CLKID_GCLK_VENCI_INT1]     = &gxbb_gclk_venci_int1.hw,
1845                 [CLKID_VCLK2_VENCLMCC]      = &gxbb_vclk2_venclmcc.hw,
1846                 [CLKID_VCLK2_VENCL]         = &gxbb_vclk2_vencl.hw,
1847                 [CLKID_VCLK_OTHER]          = &gxbb_vclk_other.hw,
1848                 [CLKID_EDP]                 = &gxbb_edp.hw,
1849                 [CLKID_AO_MEDIA_CPU]        = &gxbb_ao_media_cpu.hw,
1850                 [CLKID_AO_AHB_SRAM]         = &gxbb_ao_ahb_sram.hw,
1851                 [CLKID_AO_AHB_BUS]          = &gxbb_ao_ahb_bus.hw,
1852                 [CLKID_AO_IFACE]            = &gxbb_ao_iface.hw,
1853                 [CLKID_AO_I2C]              = &gxbb_ao_i2c.hw,
1854                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
1855                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
1856                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
1857                 [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
1858                 [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
1859                 [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
1860                 [CLKID_MALI_0_SEL]          = &gxbb_mali_0_sel.hw,
1861                 [CLKID_MALI_0_DIV]          = &gxbb_mali_0_div.hw,
1862                 [CLKID_MALI_0]              = &gxbb_mali_0.hw,
1863                 [CLKID_MALI_1_SEL]          = &gxbb_mali_1_sel.hw,
1864                 [CLKID_MALI_1_DIV]          = &gxbb_mali_1_div.hw,
1865                 [CLKID_MALI_1]              = &gxbb_mali_1.hw,
1866                 [CLKID_MALI]                = &gxbb_mali.hw,
1867                 [CLKID_CTS_AMCLK]           = &gxbb_cts_amclk.hw,
1868                 [CLKID_CTS_AMCLK_SEL]       = &gxbb_cts_amclk_sel.hw,
1869                 [CLKID_CTS_AMCLK_DIV]       = &gxbb_cts_amclk_div.hw,
1870                 [CLKID_CTS_MCLK_I958]       = &gxbb_cts_mclk_i958.hw,
1871                 [CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
1872                 [CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
1873                 [CLKID_CTS_I958]            = &gxbb_cts_i958.hw,
1874                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
1875                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
1876                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
1877                 [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
1878                 [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
1879                 [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
1880                 [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
1881                 [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
1882                 [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
1883                 [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
1884                 [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
1885                 [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
1886                 [CLKID_VPU_0_SEL]           = &gxbb_vpu_0_sel.hw,
1887                 [CLKID_VPU_0_DIV]           = &gxbb_vpu_0_div.hw,
1888                 [CLKID_VPU_0]               = &gxbb_vpu_0.hw,
1889                 [CLKID_VPU_1_SEL]           = &gxbb_vpu_1_sel.hw,
1890                 [CLKID_VPU_1_DIV]           = &gxbb_vpu_1_div.hw,
1891                 [CLKID_VPU_1]               = &gxbb_vpu_1.hw,
1892                 [CLKID_VPU]                 = &gxbb_vpu.hw,
1893                 [CLKID_VAPB_0_SEL]          = &gxbb_vapb_0_sel.hw,
1894                 [CLKID_VAPB_0_DIV]          = &gxbb_vapb_0_div.hw,
1895                 [CLKID_VAPB_0]              = &gxbb_vapb_0.hw,
1896                 [CLKID_VAPB_1_SEL]          = &gxbb_vapb_1_sel.hw,
1897                 [CLKID_VAPB_1_DIV]          = &gxbb_vapb_1_div.hw,
1898                 [CLKID_VAPB_1]              = &gxbb_vapb_1.hw,
1899                 [CLKID_VAPB_SEL]            = &gxbb_vapb_sel.hw,
1900                 [CLKID_VAPB]                = &gxbb_vapb.hw,
1901                 [CLKID_HDMI_PLL_PRE_MULT]   = &gxbb_hdmi_pll_pre_mult.hw,
1902                 [CLKID_MPLL0_DIV]           = &gxbb_mpll0_div.hw,
1903                 [CLKID_MPLL1_DIV]           = &gxbb_mpll1_div.hw,
1904                 [CLKID_MPLL2_DIV]           = &gxbb_mpll2_div.hw,
1905                 [CLKID_MPLL_PREDIV]         = &gxbb_mpll_prediv.hw,
1906                 [CLKID_FCLK_DIV2_DIV]       = &gxbb_fclk_div2_div.hw,
1907                 [CLKID_FCLK_DIV3_DIV]       = &gxbb_fclk_div3_div.hw,
1908                 [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
1909                 [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
1910                 [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
1911                 [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
1912                 [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
1913                 [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
1914                 [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
1915                 [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
1916                 [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
1917                 [CLKID_GEN_CLK_SEL]         = &gxbb_gen_clk_sel.hw,
1918                 [CLKID_GEN_CLK_DIV]         = &gxbb_gen_clk_div.hw,
1919                 [CLKID_GEN_CLK]             = &gxbb_gen_clk.hw,
1920                 [CLKID_FIXED_PLL_DCO]       = &gxbb_fixed_pll_dco.hw,
1921                 [CLKID_HDMI_PLL_DCO]        = &gxbb_hdmi_pll_dco.hw,
1922                 [CLKID_HDMI_PLL_OD]         = &gxbb_hdmi_pll_od.hw,
1923                 [CLKID_HDMI_PLL_OD2]        = &gxbb_hdmi_pll_od2.hw,
1924                 [CLKID_SYS_PLL_DCO]         = &gxbb_sys_pll_dco.hw,
1925                 [CLKID_GP0_PLL_DCO]         = &gxbb_gp0_pll_dco.hw,
1926                 [NR_CLKS]                   = NULL,
1927         },
1928         .num = NR_CLKS,
1929 };
1930
1931 static struct clk_hw_onecell_data gxl_hw_onecell_data = {
1932         .hws = {
1933                 [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
1934                 [CLKID_HDMI_PLL]            = &gxl_hdmi_pll.hw,
1935                 [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
1936                 [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
1937                 [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
1938                 [CLKID_FCLK_DIV4]           = &gxbb_fclk_div4.hw,
1939                 [CLKID_FCLK_DIV5]           = &gxbb_fclk_div5.hw,
1940                 [CLKID_FCLK_DIV7]           = &gxbb_fclk_div7.hw,
1941                 [CLKID_GP0_PLL]             = &gxbb_gp0_pll.hw,
1942                 [CLKID_MPEG_SEL]            = &gxbb_mpeg_clk_sel.hw,
1943                 [CLKID_MPEG_DIV]            = &gxbb_mpeg_clk_div.hw,
1944                 [CLKID_CLK81]               = &gxbb_clk81.hw,
1945                 [CLKID_MPLL0]               = &gxbb_mpll0.hw,
1946                 [CLKID_MPLL1]               = &gxbb_mpll1.hw,
1947                 [CLKID_MPLL2]               = &gxbb_mpll2.hw,
1948                 [CLKID_DDR]                 = &gxbb_ddr.hw,
1949                 [CLKID_DOS]                 = &gxbb_dos.hw,
1950                 [CLKID_ISA]                 = &gxbb_isa.hw,
1951                 [CLKID_PL301]               = &gxbb_pl301.hw,
1952                 [CLKID_PERIPHS]             = &gxbb_periphs.hw,
1953                 [CLKID_SPICC]               = &gxbb_spicc.hw,
1954                 [CLKID_I2C]                 = &gxbb_i2c.hw,
1955                 [CLKID_SAR_ADC]             = &gxbb_sar_adc.hw,
1956                 [CLKID_SMART_CARD]          = &gxbb_smart_card.hw,
1957                 [CLKID_RNG0]                = &gxbb_rng0.hw,
1958                 [CLKID_UART0]               = &gxbb_uart0.hw,
1959                 [CLKID_SDHC]                = &gxbb_sdhc.hw,
1960                 [CLKID_STREAM]              = &gxbb_stream.hw,
1961                 [CLKID_ASYNC_FIFO]          = &gxbb_async_fifo.hw,
1962                 [CLKID_SDIO]                = &gxbb_sdio.hw,
1963                 [CLKID_ABUF]                = &gxbb_abuf.hw,
1964                 [CLKID_HIU_IFACE]           = &gxbb_hiu_iface.hw,
1965                 [CLKID_ASSIST_MISC]         = &gxbb_assist_misc.hw,
1966                 [CLKID_SPI]                 = &gxbb_spi.hw,
1967                 [CLKID_I2S_SPDIF]           = &gxbb_i2s_spdif.hw,
1968                 [CLKID_ETH]                 = &gxbb_eth.hw,
1969                 [CLKID_DEMUX]               = &gxbb_demux.hw,
1970                 [CLKID_AIU_GLUE]            = &gxbb_aiu_glue.hw,
1971                 [CLKID_IEC958]              = &gxbb_iec958.hw,
1972                 [CLKID_I2S_OUT]             = &gxbb_i2s_out.hw,
1973                 [CLKID_AMCLK]               = &gxbb_amclk.hw,
1974                 [CLKID_AIFIFO2]             = &gxbb_aififo2.hw,
1975                 [CLKID_MIXER]               = &gxbb_mixer.hw,
1976                 [CLKID_MIXER_IFACE]         = &gxbb_mixer_iface.hw,
1977                 [CLKID_ADC]                 = &gxbb_adc.hw,
1978                 [CLKID_BLKMV]               = &gxbb_blkmv.hw,
1979                 [CLKID_AIU]                 = &gxbb_aiu.hw,
1980                 [CLKID_UART1]               = &gxbb_uart1.hw,
1981                 [CLKID_G2D]                 = &gxbb_g2d.hw,
1982                 [CLKID_USB0]                = &gxbb_usb0.hw,
1983                 [CLKID_USB1]                = &gxbb_usb1.hw,
1984                 [CLKID_RESET]               = &gxbb_reset.hw,
1985                 [CLKID_NAND]                = &gxbb_nand.hw,
1986                 [CLKID_DOS_PARSER]          = &gxbb_dos_parser.hw,
1987                 [CLKID_USB]                 = &gxbb_usb.hw,
1988                 [CLKID_VDIN1]               = &gxbb_vdin1.hw,
1989                 [CLKID_AHB_ARB0]            = &gxbb_ahb_arb0.hw,
1990                 [CLKID_EFUSE]               = &gxbb_efuse.hw,
1991                 [CLKID_BOOT_ROM]            = &gxbb_boot_rom.hw,
1992                 [CLKID_AHB_DATA_BUS]        = &gxbb_ahb_data_bus.hw,
1993                 [CLKID_AHB_CTRL_BUS]        = &gxbb_ahb_ctrl_bus.hw,
1994                 [CLKID_HDMI_INTR_SYNC]      = &gxbb_hdmi_intr_sync.hw,
1995                 [CLKID_HDMI_PCLK]           = &gxbb_hdmi_pclk.hw,
1996                 [CLKID_USB1_DDR_BRIDGE]     = &gxbb_usb1_ddr_bridge.hw,
1997                 [CLKID_USB0_DDR_BRIDGE]     = &gxbb_usb0_ddr_bridge.hw,
1998                 [CLKID_MMC_PCLK]            = &gxbb_mmc_pclk.hw,
1999                 [CLKID_DVIN]                = &gxbb_dvin.hw,
2000                 [CLKID_UART2]               = &gxbb_uart2.hw,
2001                 [CLKID_SANA]                = &gxbb_sana.hw,
2002                 [CLKID_VPU_INTR]            = &gxbb_vpu_intr.hw,
2003                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2004                 [CLKID_CLK81_A53]           = &gxbb_clk81_a53.hw,
2005                 [CLKID_VCLK2_VENCI0]        = &gxbb_vclk2_venci0.hw,
2006                 [CLKID_VCLK2_VENCI1]        = &gxbb_vclk2_venci1.hw,
2007                 [CLKID_VCLK2_VENCP0]        = &gxbb_vclk2_vencp0.hw,
2008                 [CLKID_VCLK2_VENCP1]        = &gxbb_vclk2_vencp1.hw,
2009                 [CLKID_GCLK_VENCI_INT0]     = &gxbb_gclk_venci_int0.hw,
2010                 [CLKID_GCLK_VENCI_INT]      = &gxbb_gclk_vencp_int.hw,
2011                 [CLKID_DAC_CLK]             = &gxbb_dac_clk.hw,
2012                 [CLKID_AOCLK_GATE]          = &gxbb_aoclk_gate.hw,
2013                 [CLKID_IEC958_GATE]         = &gxbb_iec958_gate.hw,
2014                 [CLKID_ENC480P]             = &gxbb_enc480p.hw,
2015                 [CLKID_RNG1]                = &gxbb_rng1.hw,
2016                 [CLKID_GCLK_VENCI_INT1]     = &gxbb_gclk_venci_int1.hw,
2017                 [CLKID_VCLK2_VENCLMCC]      = &gxbb_vclk2_venclmcc.hw,
2018                 [CLKID_VCLK2_VENCL]         = &gxbb_vclk2_vencl.hw,
2019                 [CLKID_VCLK_OTHER]          = &gxbb_vclk_other.hw,
2020                 [CLKID_EDP]                 = &gxbb_edp.hw,
2021                 [CLKID_AO_MEDIA_CPU]        = &gxbb_ao_media_cpu.hw,
2022                 [CLKID_AO_AHB_SRAM]         = &gxbb_ao_ahb_sram.hw,
2023                 [CLKID_AO_AHB_BUS]          = &gxbb_ao_ahb_bus.hw,
2024                 [CLKID_AO_IFACE]            = &gxbb_ao_iface.hw,
2025                 [CLKID_AO_I2C]              = &gxbb_ao_i2c.hw,
2026                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
2027                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
2028                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
2029                 [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
2030                 [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
2031                 [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
2032                 [CLKID_MALI_0_SEL]          = &gxbb_mali_0_sel.hw,
2033                 [CLKID_MALI_0_DIV]          = &gxbb_mali_0_div.hw,
2034                 [CLKID_MALI_0]              = &gxbb_mali_0.hw,
2035                 [CLKID_MALI_1_SEL]          = &gxbb_mali_1_sel.hw,
2036                 [CLKID_MALI_1_DIV]          = &gxbb_mali_1_div.hw,
2037                 [CLKID_MALI_1]              = &gxbb_mali_1.hw,
2038                 [CLKID_MALI]                = &gxbb_mali.hw,
2039                 [CLKID_CTS_AMCLK]           = &gxbb_cts_amclk.hw,
2040                 [CLKID_CTS_AMCLK_SEL]       = &gxbb_cts_amclk_sel.hw,
2041                 [CLKID_CTS_AMCLK_DIV]       = &gxbb_cts_amclk_div.hw,
2042                 [CLKID_CTS_MCLK_I958]       = &gxbb_cts_mclk_i958.hw,
2043                 [CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
2044                 [CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
2045                 [CLKID_CTS_I958]            = &gxbb_cts_i958.hw,
2046                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
2047                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
2048                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
2049                 [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
2050                 [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
2051                 [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
2052                 [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
2053                 [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
2054                 [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
2055                 [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
2056                 [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
2057                 [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
2058                 [CLKID_VPU_0_SEL]           = &gxbb_vpu_0_sel.hw,
2059                 [CLKID_VPU_0_DIV]           = &gxbb_vpu_0_div.hw,
2060                 [CLKID_VPU_0]               = &gxbb_vpu_0.hw,
2061                 [CLKID_VPU_1_SEL]           = &gxbb_vpu_1_sel.hw,
2062                 [CLKID_VPU_1_DIV]           = &gxbb_vpu_1_div.hw,
2063                 [CLKID_VPU_1]               = &gxbb_vpu_1.hw,
2064                 [CLKID_VPU]                 = &gxbb_vpu.hw,
2065                 [CLKID_VAPB_0_SEL]          = &gxbb_vapb_0_sel.hw,
2066                 [CLKID_VAPB_0_DIV]          = &gxbb_vapb_0_div.hw,
2067                 [CLKID_VAPB_0]              = &gxbb_vapb_0.hw,
2068                 [CLKID_VAPB_1_SEL]          = &gxbb_vapb_1_sel.hw,
2069                 [CLKID_VAPB_1_DIV]          = &gxbb_vapb_1_div.hw,
2070                 [CLKID_VAPB_1]              = &gxbb_vapb_1.hw,
2071                 [CLKID_VAPB_SEL]            = &gxbb_vapb_sel.hw,
2072                 [CLKID_VAPB]                = &gxbb_vapb.hw,
2073                 [CLKID_MPLL0_DIV]           = &gxbb_mpll0_div.hw,
2074                 [CLKID_MPLL1_DIV]           = &gxbb_mpll1_div.hw,
2075                 [CLKID_MPLL2_DIV]           = &gxbb_mpll2_div.hw,
2076                 [CLKID_MPLL_PREDIV]         = &gxbb_mpll_prediv.hw,
2077                 [CLKID_FCLK_DIV2_DIV]       = &gxbb_fclk_div2_div.hw,
2078                 [CLKID_FCLK_DIV3_DIV]       = &gxbb_fclk_div3_div.hw,
2079                 [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
2080                 [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
2081                 [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
2082                 [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
2083                 [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
2084                 [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
2085                 [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
2086                 [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
2087                 [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
2088                 [CLKID_GEN_CLK_SEL]         = &gxbb_gen_clk_sel.hw,
2089                 [CLKID_GEN_CLK_DIV]         = &gxbb_gen_clk_div.hw,
2090                 [CLKID_GEN_CLK]             = &gxbb_gen_clk.hw,
2091                 [CLKID_FIXED_PLL_DCO]       = &gxbb_fixed_pll_dco.hw,
2092                 [CLKID_HDMI_PLL_DCO]        = &gxbb_hdmi_pll_dco.hw,
2093                 [CLKID_HDMI_PLL_OD]         = &gxl_hdmi_pll_od.hw,
2094                 [CLKID_HDMI_PLL_OD2]        = &gxl_hdmi_pll_od2.hw,
2095                 [CLKID_SYS_PLL_DCO]         = &gxbb_sys_pll_dco.hw,
2096                 [CLKID_GP0_PLL_DCO]         = &gxl_gp0_pll_dco.hw,
2097                 [NR_CLKS]                   = NULL,
2098         },
2099         .num = NR_CLKS,
2100 };
2101
2102 static struct clk_regmap *const gxbb_clk_regmaps[] = {
2103         &gxbb_gp0_pll_dco,
2104         &gxbb_hdmi_pll,
2105         &gxbb_hdmi_pll_od,
2106         &gxbb_hdmi_pll_od2,
2107 };
2108
2109 static struct clk_regmap *const gxl_clk_regmaps[] = {
2110         &gxl_gp0_pll_dco,
2111         &gxl_hdmi_pll,
2112         &gxl_hdmi_pll_od,
2113         &gxl_hdmi_pll_od2,
2114 };
2115
2116 static struct clk_regmap *const gx_clk_regmaps[] = {
2117         &gxbb_clk81,
2118         &gxbb_ddr,
2119         &gxbb_dos,
2120         &gxbb_isa,
2121         &gxbb_pl301,
2122         &gxbb_periphs,
2123         &gxbb_spicc,
2124         &gxbb_i2c,
2125         &gxbb_sar_adc,
2126         &gxbb_smart_card,
2127         &gxbb_rng0,
2128         &gxbb_uart0,
2129         &gxbb_sdhc,
2130         &gxbb_stream,
2131         &gxbb_async_fifo,
2132         &gxbb_sdio,
2133         &gxbb_abuf,
2134         &gxbb_hiu_iface,
2135         &gxbb_assist_misc,
2136         &gxbb_spi,
2137         &gxbb_i2s_spdif,
2138         &gxbb_eth,
2139         &gxbb_demux,
2140         &gxbb_aiu_glue,
2141         &gxbb_iec958,
2142         &gxbb_i2s_out,
2143         &gxbb_amclk,
2144         &gxbb_aififo2,
2145         &gxbb_mixer,
2146         &gxbb_mixer_iface,
2147         &gxbb_adc,
2148         &gxbb_blkmv,
2149         &gxbb_aiu,
2150         &gxbb_uart1,
2151         &gxbb_g2d,
2152         &gxbb_usb0,
2153         &gxbb_usb1,
2154         &gxbb_reset,
2155         &gxbb_nand,
2156         &gxbb_dos_parser,
2157         &gxbb_usb,
2158         &gxbb_vdin1,
2159         &gxbb_ahb_arb0,
2160         &gxbb_efuse,
2161         &gxbb_boot_rom,
2162         &gxbb_ahb_data_bus,
2163         &gxbb_ahb_ctrl_bus,
2164         &gxbb_hdmi_intr_sync,
2165         &gxbb_hdmi_pclk,
2166         &gxbb_usb1_ddr_bridge,
2167         &gxbb_usb0_ddr_bridge,
2168         &gxbb_mmc_pclk,
2169         &gxbb_dvin,
2170         &gxbb_uart2,
2171         &gxbb_sana,
2172         &gxbb_vpu_intr,
2173         &gxbb_sec_ahb_ahb3_bridge,
2174         &gxbb_clk81_a53,
2175         &gxbb_vclk2_venci0,
2176         &gxbb_vclk2_venci1,
2177         &gxbb_vclk2_vencp0,
2178         &gxbb_vclk2_vencp1,
2179         &gxbb_gclk_venci_int0,
2180         &gxbb_gclk_vencp_int,
2181         &gxbb_dac_clk,
2182         &gxbb_aoclk_gate,
2183         &gxbb_iec958_gate,
2184         &gxbb_enc480p,
2185         &gxbb_rng1,
2186         &gxbb_gclk_venci_int1,
2187         &gxbb_vclk2_venclmcc,
2188         &gxbb_vclk2_vencl,
2189         &gxbb_vclk_other,
2190         &gxbb_edp,
2191         &gxbb_ao_media_cpu,
2192         &gxbb_ao_ahb_sram,
2193         &gxbb_ao_ahb_bus,
2194         &gxbb_ao_iface,
2195         &gxbb_ao_i2c,
2196         &gxbb_emmc_a,
2197         &gxbb_emmc_b,
2198         &gxbb_emmc_c,
2199         &gxbb_sar_adc_clk,
2200         &gxbb_mali_0,
2201         &gxbb_mali_1,
2202         &gxbb_cts_amclk,
2203         &gxbb_cts_mclk_i958,
2204         &gxbb_32k_clk,
2205         &gxbb_sd_emmc_a_clk0,
2206         &gxbb_sd_emmc_b_clk0,
2207         &gxbb_sd_emmc_c_clk0,
2208         &gxbb_vpu_0,
2209         &gxbb_vpu_1,
2210         &gxbb_vapb_0,
2211         &gxbb_vapb_1,
2212         &gxbb_vapb,
2213         &gxbb_mpeg_clk_div,
2214         &gxbb_sar_adc_clk_div,
2215         &gxbb_mali_0_div,
2216         &gxbb_mali_1_div,
2217         &gxbb_cts_mclk_i958_div,
2218         &gxbb_32k_clk_div,
2219         &gxbb_sd_emmc_a_clk0_div,
2220         &gxbb_sd_emmc_b_clk0_div,
2221         &gxbb_sd_emmc_c_clk0_div,
2222         &gxbb_vpu_0_div,
2223         &gxbb_vpu_1_div,
2224         &gxbb_vapb_0_div,
2225         &gxbb_vapb_1_div,
2226         &gxbb_mpeg_clk_sel,
2227         &gxbb_sar_adc_clk_sel,
2228         &gxbb_mali_0_sel,
2229         &gxbb_mali_1_sel,
2230         &gxbb_mali,
2231         &gxbb_cts_amclk_sel,
2232         &gxbb_cts_mclk_i958_sel,
2233         &gxbb_cts_i958,
2234         &gxbb_32k_clk_sel,
2235         &gxbb_sd_emmc_a_clk0_sel,
2236         &gxbb_sd_emmc_b_clk0_sel,
2237         &gxbb_sd_emmc_c_clk0_sel,
2238         &gxbb_vpu_0_sel,
2239         &gxbb_vpu_1_sel,
2240         &gxbb_vpu,
2241         &gxbb_vapb_0_sel,
2242         &gxbb_vapb_1_sel,
2243         &gxbb_vapb_sel,
2244         &gxbb_mpll0,
2245         &gxbb_mpll1,
2246         &gxbb_mpll2,
2247         &gxbb_mpll0_div,
2248         &gxbb_mpll1_div,
2249         &gxbb_mpll2_div,
2250         &gxbb_cts_amclk_div,
2251         &gxbb_fixed_pll,
2252         &gxbb_sys_pll,
2253         &gxbb_mpll_prediv,
2254         &gxbb_fclk_div2,
2255         &gxbb_fclk_div3,
2256         &gxbb_fclk_div4,
2257         &gxbb_fclk_div5,
2258         &gxbb_fclk_div7,
2259         &gxbb_vdec_1_sel,
2260         &gxbb_vdec_1_div,
2261         &gxbb_vdec_1,
2262         &gxbb_vdec_hevc_sel,
2263         &gxbb_vdec_hevc_div,
2264         &gxbb_vdec_hevc,
2265         &gxbb_gen_clk_sel,
2266         &gxbb_gen_clk_div,
2267         &gxbb_gen_clk,
2268         &gxbb_fixed_pll_dco,
2269         &gxbb_hdmi_pll_dco,
2270         &gxbb_sys_pll_dco,
2271         &gxbb_gp0_pll,
2272 };
2273
2274 struct clkc_data {
2275         struct clk_regmap *const *regmap_clks;
2276         unsigned int regmap_clks_count;
2277         struct clk_hw_onecell_data *hw_onecell_data;
2278 };
2279
2280 static const struct clkc_data gxbb_clkc_data = {
2281         .regmap_clks = gxbb_clk_regmaps,
2282         .regmap_clks_count = ARRAY_SIZE(gxbb_clk_regmaps),
2283         .hw_onecell_data = &gxbb_hw_onecell_data,
2284 };
2285
2286 static const struct clkc_data gxl_clkc_data = {
2287         .regmap_clks = gxl_clk_regmaps,
2288         .regmap_clks_count = ARRAY_SIZE(gxl_clk_regmaps),
2289         .hw_onecell_data = &gxl_hw_onecell_data,
2290 };
2291
2292 static const struct of_device_id clkc_match_table[] = {
2293         { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
2294         { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
2295         {},
2296 };
2297
2298 static int gxbb_clkc_probe(struct platform_device *pdev)
2299 {
2300         const struct clkc_data *clkc_data;
2301         struct regmap *map;
2302         int ret, i;
2303         struct device *dev = &pdev->dev;
2304
2305         clkc_data = of_device_get_match_data(dev);
2306         if (!clkc_data)
2307                 return -EINVAL;
2308
2309         /* Get the hhi system controller node if available */
2310         map = syscon_node_to_regmap(of_get_parent(dev->of_node));
2311         if (IS_ERR(map)) {
2312                 dev_err(dev, "failed to get HHI regmap\n");
2313                 return PTR_ERR(map);
2314         }
2315
2316         /* Populate regmap for the common regmap backed clocks */
2317         for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++)
2318                 gx_clk_regmaps[i]->map = map;
2319
2320         /* Populate regmap for soc specific clocks */
2321         for (i = 0; i < clkc_data->regmap_clks_count; i++)
2322                 clkc_data->regmap_clks[i]->map = map;
2323
2324         /* Register all clks */
2325         for (i = 0; i < clkc_data->hw_onecell_data->num; i++) {
2326                 /* array might be sparse */
2327                 if (!clkc_data->hw_onecell_data->hws[i])
2328                         continue;
2329
2330                 ret = devm_clk_hw_register(dev,
2331                                            clkc_data->hw_onecell_data->hws[i]);
2332                 if (ret) {
2333                         dev_err(dev, "Clock registration failed\n");
2334                         return ret;
2335                 }
2336         }
2337
2338         return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
2339                                            clkc_data->hw_onecell_data);
2340 }
2341
2342 static struct platform_driver gxbb_driver = {
2343         .probe          = gxbb_clkc_probe,
2344         .driver         = {
2345                 .name   = "gxbb-clkc",
2346                 .of_match_table = clkc_match_table,
2347         },
2348 };
2349
2350 builtin_platform_driver(gxbb_driver);