drivers/clk/meson/g12a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Amlogic Meson-G12A Clock Controller Driver
   4  *
   5  * Copyright (c) 2016 Baylibre SAS.
   6  * Author: Michael Turquette <mturquette@baylibre.com>
   7  *
   8  * Copyright (c) 2018 Amlogic, inc.
   9  * Author: Qiufang Dai <qiufang.dai@amlogic.com>
  10  * Author: Jian Hu <jian.hu@amlogic.com>
  11  */
  12
  13 #include <linux/clk-provider.h>
  14 #include <linux/init.h>
  15 #include <linux/of_device.h>
  16 #include <linux/platform_device.h>
  17
  18 #include "clk-input.h"
  19 #include "clk-mpll.h"
  20 #include "clk-pll.h"
  21 #include "clk-regmap.h"
  22 #include "vid-pll-div.h"
  23 #include "meson-eeclk.h"
  24 #include "g12a.h"
  25
  26 static DEFINE_SPINLOCK(meson_clk_lock);
  27
  28 static struct clk_regmap g12a_fixed_pll_dco = {
  29         .data = &(struct meson_clk_pll_data){
  30                 .en = {
  31                         .reg_off = HHI_FIX_PLL_CNTL0,
  32                         .shift   = 28,
  33                         .width   = 1,
  34                 },
  35                 .m = {
  36                         .reg_off = HHI_FIX_PLL_CNTL0,
  37                         .shift   = 0,
  38                         .width   = 8,
  39                 },
  40                 .n = {
  41                         .reg_off = HHI_FIX_PLL_CNTL0,
  42                         .shift   = 10,
  43                         .width   = 5,
  44                 },
  45                 .frac = {
  46                         .reg_off = HHI_FIX_PLL_CNTL1,
  47                         .shift   = 0,
  48                         .width   = 17,
  49                 },
  50                 .l = {
  51                         .reg_off = HHI_FIX_PLL_CNTL0,
  52                         .shift   = 31,
  53                         .width   = 1,
  54                 },
  55                 .rst = {
  56                         .reg_off = HHI_FIX_PLL_CNTL0,
  57                         .shift   = 29,
  58                         .width   = 1,
  59                 },
  60         },
  61         .hw.init = &(struct clk_init_data){
  62                 .name = "fixed_pll_dco",
  63                 .ops = &meson_clk_pll_ro_ops,
  64                 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
  65                 .num_parents = 1,
  66         },
  67 };
  68
  69 static struct clk_regmap g12a_fixed_pll = {
  70         .data = &(struct clk_regmap_div_data){
  71                 .offset = HHI_FIX_PLL_CNTL0,
  72                 .shift = 16,
  73                 .width = 2,
  74                 .flags = CLK_DIVIDER_POWER_OF_TWO,
  75         },
  76         .hw.init = &(struct clk_init_data){
  77                 .name = "fixed_pll",
  78                 .ops = &clk_regmap_divider_ro_ops,
  79                 .parent_names = (const char *[]){ "fixed_pll_dco" },
  80                 .num_parents = 1,
  81                 /*
  82                  * This clock won't ever change at runtime so
  83                  * CLK_SET_RATE_PARENT is not required
  84                  */
  85         },
  86 };
  87
  88 /*
  89  * Internal sys pll emulation configuration parameters
  90  */
  91 static const struct reg_sequence g12a_sys_init_regs[] = {
  92         { .reg = HHI_SYS_PLL_CNTL1,     .def = 0x00000000 },
  93         { .reg = HHI_SYS_PLL_CNTL2,     .def = 0x00000000 },
  94         { .reg = HHI_SYS_PLL_CNTL3,     .def = 0x48681c00 },
  95         { .reg = HHI_SYS_PLL_CNTL4,     .def = 0x88770290 },
  96         { .reg = HHI_SYS_PLL_CNTL5,     .def = 0x39272000 },
  97         { .reg = HHI_SYS_PLL_CNTL6,     .def = 0x56540000 },
  98 };
  99
 100 static struct clk_regmap g12a_sys_pll_dco = {
 101         .data = &(struct meson_clk_pll_data){
 102                 .en = {
 103                         .reg_off = HHI_SYS_PLL_CNTL0,
 104                         .shift   = 28,
 105                         .width   = 1,
 106                 },
 107                 .m = {
 108                         .reg_off = HHI_SYS_PLL_CNTL0,
 109                         .shift   = 0,
 110                         .width   = 8,
 111                 },
 112                 .n = {
 113                         .reg_off = HHI_SYS_PLL_CNTL0,
 114                         .shift   = 10,
 115                         .width   = 5,
 116                 },
 117                 .l = {
 118                         .reg_off = HHI_SYS_PLL_CNTL0,
 119                         .shift   = 31,
 120                         .width   = 1,
 121                 },
 122                 .rst = {
 123                         .reg_off = HHI_SYS_PLL_CNTL0,
 124                         .shift   = 29,
 125                         .width   = 1,
 126                 },
 127                 .init_regs = g12a_sys_init_regs,
 128                 .init_count = ARRAY_SIZE(g12a_sys_init_regs),
 129         },
 130         .hw.init = &(struct clk_init_data){
 131                 .name = "sys_pll_dco",
 132                 .ops = &meson_clk_pll_ro_ops,
 133                 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
 134                 .num_parents = 1,
 135         },
 136 };
 137
 138 static struct clk_regmap g12a_sys_pll = {
 139         .data = &(struct clk_regmap_div_data){
 140                 .offset = HHI_SYS_PLL_CNTL0,
 141                 .shift = 16,
 142                 .width = 3,
 143                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 144         },
 145         .hw.init = &(struct clk_init_data){
 146                 .name = "sys_pll",
 147                 .ops = &clk_regmap_divider_ro_ops,
 148                 .parent_names = (const char *[]){ "sys_pll_dco" },
 149                 .num_parents = 1,
 150         },
 151 };
 152
 153 static struct clk_regmap g12a_sys_pll_div16_en = {
 154         .data = &(struct clk_regmap_gate_data){
 155                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 156                 .bit_idx = 24,
 157         },
 158         .hw.init = &(struct clk_init_data) {
 159                 .name = "sys_pll_div16_en",
 160                 .ops = &clk_regmap_gate_ro_ops,
 161                 .parent_names = (const char *[]){ "sys_pll" },
 162                 .num_parents = 1,
 163                 /*
 164                  * This clock is used to debug the sys_pll range
 165                  * Linux should not change it at runtime
 166                  */
 167         },
 168 };
 169
 170 static struct clk_fixed_factor g12a_sys_pll_div16 = {
 171         .mult = 1,
 172         .div = 16,
 173         .hw.init = &(struct clk_init_data){
 174                 .name = "sys_pll_div16",
 175                 .ops = &clk_fixed_factor_ops,
 176                 .parent_names = (const char *[]){ "sys_pll_div16_en" },
 177                 .num_parents = 1,
 178         },
 179 };
 180
 181 /* Datasheet names this field as "premux0" */
 182 static struct clk_regmap g12a_cpu_clk_premux0 = {
 183         .data = &(struct clk_regmap_mux_data){
 184                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 185                 .mask = 0x3,
 186                 .shift = 0,
 187         },
 188         .hw.init = &(struct clk_init_data){
 189                 .name = "cpu_clk_dyn0_sel",
 190                 .ops = &clk_regmap_mux_ro_ops,
 191                 .parent_names = (const char *[]){ IN_PREFIX "xtal",
 192                                                   "fclk_div2",
 193                                                   "fclk_div3" },
 194                 .num_parents = 3,
 195         },
 196 };
 197
 198 /* Datasheet names this field as "mux0_divn_tcnt" */
 199 static struct clk_regmap g12a_cpu_clk_mux0_div = {
 200         .data = &(struct clk_regmap_div_data){
 201                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 202                 .shift = 4,
 203                 .width = 6,
 204         },
 205         .hw.init = &(struct clk_init_data){
 206                 .name = "cpu_clk_dyn0_div",
 207                 .ops = &clk_regmap_divider_ro_ops,
 208                 .parent_names = (const char *[]){ "cpu_clk_dyn0_sel" },
 209                 .num_parents = 1,
 210         },
 211 };
 212
 213 /* Datasheet names this field as "postmux0" */
 214 static struct clk_regmap g12a_cpu_clk_postmux0 = {
 215         .data = &(struct clk_regmap_mux_data){
 216                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 217                 .mask = 0x1,
 218                 .shift = 2,
 219         },
 220         .hw.init = &(struct clk_init_data){
 221                 .name = "cpu_clk_dyn0",
 222                 .ops = &clk_regmap_mux_ro_ops,
 223                 .parent_names = (const char *[]){ "cpu_clk_dyn0_sel",
 224                                                   "cpu_clk_dyn0_div" },
 225                 .num_parents = 2,
 226         },
 227 };
 228
 229 /* Datasheet names this field as "premux1" */
 230 static struct clk_regmap g12a_cpu_clk_premux1 = {
 231         .data = &(struct clk_regmap_mux_data){
 232                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 233                 .mask = 0x3,
 234                 .shift = 16,
 235         },
 236         .hw.init = &(struct clk_init_data){
 237                 .name = "cpu_clk_dyn1_sel",
 238                 .ops = &clk_regmap_mux_ro_ops,
 239                 .parent_names = (const char *[]){ IN_PREFIX "xtal",
 240                                                   "fclk_div2",
 241                                                   "fclk_div3" },
 242                 .num_parents = 3,
 243         },
 244 };
 245
 246 /* Datasheet names this field as "Mux1_divn_tcnt" */
 247 static struct clk_regmap g12a_cpu_clk_mux1_div = {
 248         .data = &(struct clk_regmap_div_data){
 249                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 250                 .shift = 20,
 251                 .width = 6,
 252         },
 253         .hw.init = &(struct clk_init_data){
 254                 .name = "cpu_clk_dyn1_div",
 255                 .ops = &clk_regmap_divider_ro_ops,
 256                 .parent_names = (const char *[]){ "cpu_clk_dyn1_sel" },
 257                 .num_parents = 1,
 258         },
 259 };
 260
 261 /* Datasheet names this field as "postmux1" */
 262 static struct clk_regmap g12a_cpu_clk_postmux1 = {
 263         .data = &(struct clk_regmap_mux_data){
 264                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 265                 .mask = 0x1,
 266                 .shift = 18,
 267         },
 268         .hw.init = &(struct clk_init_data){
 269                 .name = "cpu_clk_dyn1",
 270                 .ops = &clk_regmap_mux_ro_ops,
 271                 .parent_names = (const char *[]){ "cpu_clk_dyn1_sel",
 272                                                   "cpu_clk_dyn1_div" },
 273                 .num_parents = 2,
 274         },
 275 };
 276
 277 /* Datasheet names this field as "Final_dyn_mux_sel" */
 278 static struct clk_regmap g12a_cpu_clk_dyn = {
 279         .data = &(struct clk_regmap_mux_data){
 280                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 281                 .mask = 0x1,
 282                 .shift = 10,
 283         },
 284         .hw.init = &(struct clk_init_data){
 285                 .name = "cpu_clk_dyn",
 286                 .ops = &clk_regmap_mux_ro_ops,
 287                 .parent_names = (const char *[]){ "cpu_clk_dyn0",
 288                                                   "cpu_clk_dyn1" },
 289                 .num_parents = 2,
 290         },
 291 };
 292
 293 /* Datasheet names this field as "Final_mux_sel" */
 294 static struct clk_regmap g12a_cpu_clk = {
 295         .data = &(struct clk_regmap_mux_data){
 296                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 297                 .mask = 0x1,
 298                 .shift = 11,
 299         },
 300         .hw.init = &(struct clk_init_data){
 301                 .name = "cpu_clk",
 302                 .ops = &clk_regmap_mux_ro_ops,
 303                 .parent_names = (const char *[]){ "cpu_clk_dyn",
 304                                                   "sys_pll" },
 305                 .num_parents = 2,
 306         },
 307 };
 308
 309 static struct clk_regmap g12a_cpu_clk_div16_en = {
 310         .data = &(struct clk_regmap_gate_data){
 311                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 312                 .bit_idx = 1,
 313         },
 314         .hw.init = &(struct clk_init_data) {
 315                 .name = "cpu_clk_div16_en",
 316                 .ops = &clk_regmap_gate_ro_ops,
 317                 .parent_names = (const char *[]){ "cpu_clk" },
 318                 .num_parents = 1,
 319                 /*
 320                  * This clock is used to debug the cpu_clk range
 321                  * Linux should not change it at runtime
 322                  */
 323         },
 324 };
 325
 326 static struct clk_fixed_factor g12a_cpu_clk_div16 = {
 327         .mult = 1,
 328         .div = 16,
 329         .hw.init = &(struct clk_init_data){
 330                 .name = "cpu_clk_div16",
 331                 .ops = &clk_fixed_factor_ops,
 332                 .parent_names = (const char *[]){ "cpu_clk_div16_en" },
 333                 .num_parents = 1,
 334         },
 335 };
 336
 337 static struct clk_regmap g12a_cpu_clk_apb_div = {
 338         .data = &(struct clk_regmap_div_data){
 339                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 340                 .shift = 3,
 341                 .width = 3,
 342                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 343         },
 344         .hw.init = &(struct clk_init_data){
 345                 .name = "cpu_clk_apb_div",
 346                 .ops = &clk_regmap_divider_ro_ops,
 347                 .parent_names = (const char *[]){ "cpu_clk" },
 348                 .num_parents = 1,
 349         },
 350 };
 351
 352 static struct clk_regmap g12a_cpu_clk_apb = {
 353         .data = &(struct clk_regmap_gate_data){
 354                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 355                 .bit_idx = 1,
 356         },
 357         .hw.init = &(struct clk_init_data) {
 358                 .name = "cpu_clk_apb",
 359                 .ops = &clk_regmap_gate_ro_ops,
 360                 .parent_names = (const char *[]){ "cpu_clk_apb_div" },
 361                 .num_parents = 1,
 362                 /*
 363                  * This clock is set by the ROM monitor code,
 364                  * Linux should not change it at runtime
 365                  */
 366         },
 367 };
 368
 369 static struct clk_regmap g12a_cpu_clk_atb_div = {
 370         .data = &(struct clk_regmap_div_data){
 371                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 372                 .shift = 6,
 373                 .width = 3,
 374                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 375         },
 376         .hw.init = &(struct clk_init_data){
 377                 .name = "cpu_clk_atb_div",
 378                 .ops = &clk_regmap_divider_ro_ops,
 379                 .parent_names = (const char *[]){ "cpu_clk" },
 380                 .num_parents = 1,
 381         },
 382 };
 383
 384 static struct clk_regmap g12a_cpu_clk_atb = {
 385         .data = &(struct clk_regmap_gate_data){
 386                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 387                 .bit_idx = 17,
 388         },
 389         .hw.init = &(struct clk_init_data) {
 390                 .name = "cpu_clk_atb",
 391                 .ops = &clk_regmap_gate_ro_ops,
 392                 .parent_names = (const char *[]){ "cpu_clk_atb_div" },
 393                 .num_parents = 1,
 394                 /*
 395                  * This clock is set by the ROM monitor code,
 396                  * Linux should not change it at runtime
 397                  */
 398         },
 399 };
 400
 401 static struct clk_regmap g12a_cpu_clk_axi_div = {
 402         .data = &(struct clk_regmap_div_data){
 403                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 404                 .shift = 9,
 405                 .width = 3,
 406                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 407         },
 408         .hw.init = &(struct clk_init_data){
 409                 .name = "cpu_clk_axi_div",
 410                 .ops = &clk_regmap_divider_ro_ops,
 411                 .parent_names = (const char *[]){ "cpu_clk" },
 412                 .num_parents = 1,
 413         },
 414 };
 415
 416 static struct clk_regmap g12a_cpu_clk_axi = {
 417         .data = &(struct clk_regmap_gate_data){
 418                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 419                 .bit_idx = 18,
 420         },
 421         .hw.init = &(struct clk_init_data) {
 422                 .name = "cpu_clk_axi",
 423                 .ops = &clk_regmap_gate_ro_ops,
 424                 .parent_names = (const char *[]){ "cpu_clk_axi_div" },
 425                 .num_parents = 1,
 426                 /*
 427                  * This clock is set by the ROM monitor code,
 428                  * Linux should not change it at runtime
 429                  */
 430         },
 431 };
 432
 433 static struct clk_regmap g12a_cpu_clk_trace_div = {
 434         .data = &(struct clk_regmap_div_data){
 435                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 436                 .shift = 20,
 437                 .width = 3,
 438                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 439         },
 440         .hw.init = &(struct clk_init_data){
 441                 .name = "cpu_clk_trace_div",
 442                 .ops = &clk_regmap_divider_ro_ops,
 443                 .parent_names = (const char *[]){ "cpu_clk" },
 444                 .num_parents = 1,
 445         },
 446 };
 447
 448 static struct clk_regmap g12a_cpu_clk_trace = {
 449         .data = &(struct clk_regmap_gate_data){
 450                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 451                 .bit_idx = 23,
 452         },
 453         .hw.init = &(struct clk_init_data) {
 454                 .name = "cpu_clk_trace",
 455                 .ops = &clk_regmap_gate_ro_ops,
 456                 .parent_names = (const char *[]){ "cpu_clk_trace_div" },
 457                 .num_parents = 1,
 458                 /*
 459                  * This clock is set by the ROM monitor code,
 460                  * Linux should not change it at runtime
 461                  */
 462         },
 463 };
 464
 465 static const struct pll_mult_range g12a_gp0_pll_mult_range = {
 466         .min = 55,
 467         .max = 255,
 468 };
 469
 470 /*
 471  * Internal gp0 pll emulation configuration parameters
 472  */
 473 static const struct reg_sequence g12a_gp0_init_regs[] = {
 474         { .reg = HHI_GP0_PLL_CNTL1,     .def = 0x00000000 },
 475         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0x00000000 },
 476         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x48681c00 },
 477         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0x33771290 },
 478         { .reg = HHI_GP0_PLL_CNTL5,     .def = 0x39272000 },
 479         { .reg = HHI_GP0_PLL_CNTL6,     .def = 0x56540000 },
 480 };
 481
 482 static struct clk_regmap g12a_gp0_pll_dco = {
 483         .data = &(struct meson_clk_pll_data){
 484                 .en = {
 485                         .reg_off = HHI_GP0_PLL_CNTL0,
 486                         .shift   = 28,
 487                         .width   = 1,
 488                 },
 489                 .m = {
 490                         .reg_off = HHI_GP0_PLL_CNTL0,
 491                         .shift   = 0,
 492                         .width   = 8,
 493                 },
 494                 .n = {
 495                         .reg_off = HHI_GP0_PLL_CNTL0,
 496                         .shift   = 10,
 497                         .width   = 5,
 498                 },
 499                 .frac = {
 500                         .reg_off = HHI_GP0_PLL_CNTL1,
 501                         .shift   = 0,
 502                         .width   = 17,
 503                 },
 504                 .l = {
 505                         .reg_off = HHI_GP0_PLL_CNTL0,
 506                         .shift   = 31,
 507                         .width   = 1,
 508                 },
 509                 .rst = {
 510                         .reg_off = HHI_GP0_PLL_CNTL0,
 511                         .shift   = 29,
 512                         .width   = 1,
 513                 },
 514                 .range = &g12a_gp0_pll_mult_range,
 515                 .init_regs = g12a_gp0_init_regs,
 516                 .init_count = ARRAY_SIZE(g12a_gp0_init_regs),
 517         },
 518         .hw.init = &(struct clk_init_data){
 519                 .name = "gp0_pll_dco",
 520                 .ops = &meson_clk_pll_ops,
 521                 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
 522                 .num_parents = 1,
 523         },
 524 };
 525
 526 static struct clk_regmap g12a_gp0_pll = {
 527         .data = &(struct clk_regmap_div_data){
 528                 .offset = HHI_GP0_PLL_CNTL0,
 529                 .shift = 16,
 530                 .width = 3,
 531                 .flags = (CLK_DIVIDER_POWER_OF_TWO |
 532                           CLK_DIVIDER_ROUND_CLOSEST),
 533         },
 534         .hw.init = &(struct clk_init_data){
 535                 .name = "gp0_pll",
 536                 .ops = &clk_regmap_divider_ops,
 537                 .parent_names = (const char *[]){ "gp0_pll_dco" },
 538                 .num_parents = 1,
 539                 .flags = CLK_SET_RATE_PARENT,
 540         },
 541 };
 542
 543 /*
 544  * Internal hifi pll emulation configuration parameters
 545  */
 546 static const struct reg_sequence g12a_hifi_init_regs[] = {
 547         { .reg = HHI_HIFI_PLL_CNTL1,    .def = 0x00000000 },
 548         { .reg = HHI_HIFI_PLL_CNTL2,    .def = 0x00000000 },
 549         { .reg = HHI_HIFI_PLL_CNTL3,    .def = 0x6a285c00 },
 550         { .reg = HHI_HIFI_PLL_CNTL4,    .def = 0x65771290 },
 551         { .reg = HHI_HIFI_PLL_CNTL5,    .def = 0x39272000 },
 552         { .reg = HHI_HIFI_PLL_CNTL6,    .def = 0x56540000 },
 553 };
 554
 555 static struct clk_regmap g12a_hifi_pll_dco = {
 556         .data = &(struct meson_clk_pll_data){
 557                 .en = {
 558                         .reg_off = HHI_HIFI_PLL_CNTL0,
 559                         .shift   = 28,
 560                         .width   = 1,
 561                 },
 562                 .m = {
 563                         .reg_off = HHI_HIFI_PLL_CNTL0,
 564                         .shift   = 0,
 565                         .width   = 8,
 566                 },
 567                 .n = {
 568                         .reg_off = HHI_HIFI_PLL_CNTL0,
 569                         .shift   = 10,
 570                         .width   = 5,
 571                 },
 572                 .frac = {
 573                         .reg_off = HHI_HIFI_PLL_CNTL1,
 574                         .shift   = 0,
 575                         .width   = 17,
 576                 },
 577                 .l = {
 578                         .reg_off = HHI_HIFI_PLL_CNTL0,
 579                         .shift   = 31,
 580                         .width   = 1,
 581                 },
 582                 .rst = {
 583                         .reg_off = HHI_HIFI_PLL_CNTL0,
 584                         .shift   = 29,
 585                         .width   = 1,
 586                 },
 587                 .range = &g12a_gp0_pll_mult_range,
 588                 .init_regs = g12a_hifi_init_regs,
 589                 .init_count = ARRAY_SIZE(g12a_hifi_init_regs),
 590                 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
 591         },
 592         .hw.init = &(struct clk_init_data){
 593                 .name = "hifi_pll_dco",
 594                 .ops = &meson_clk_pll_ops,
 595                 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
 596                 .num_parents = 1,
 597         },
 598 };
 599
 600 static struct clk_regmap g12a_hifi_pll = {
 601         .data = &(struct clk_regmap_div_data){
 602                 .offset = HHI_HIFI_PLL_CNTL0,
 603                 .shift = 16,
 604                 .width = 2,
 605                 .flags = (CLK_DIVIDER_POWER_OF_TWO |
 606                           CLK_DIVIDER_ROUND_CLOSEST),
 607         },
 608         .hw.init = &(struct clk_init_data){
 609                 .name = "hifi_pll",
 610                 .ops = &clk_regmap_divider_ops,
 611                 .parent_names = (const char *[]){ "hifi_pll_dco" },
 612                 .num_parents = 1,
 613                 .flags = CLK_SET_RATE_PARENT,
 614         },
 615 };
 616
 617 /*
 618  * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
 619  * 100MHz reference clock for the PCIe Analog PHY, and thus requires
 620  * a strict register sequence to enable the PLL.
 621  */
 622 static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
 623         { .reg = HHI_PCIE_PLL_CNTL0,    .def = 0x20090496 },
 624         { .reg = HHI_PCIE_PLL_CNTL0,    .def = 0x30090496 },
 625         { .reg = HHI_PCIE_PLL_CNTL1,    .def = 0x00000000 },
 626         { .reg = HHI_PCIE_PLL_CNTL2,    .def = 0x00001100 },
 627         { .reg = HHI_PCIE_PLL_CNTL3,    .def = 0x10058e00 },
 628         { .reg = HHI_PCIE_PLL_CNTL4,    .def = 0x000100c0 },
 629         { .reg = HHI_PCIE_PLL_CNTL5,    .def = 0x68000048 },
 630         { .reg = HHI_PCIE_PLL_CNTL5,    .def = 0x68000068, .delay_us = 20 },
 631         { .reg = HHI_PCIE_PLL_CNTL4,    .def = 0x008100c0, .delay_us = 10 },
 632         { .reg = HHI_PCIE_PLL_CNTL0,    .def = 0x34090496 },
 633         { .reg = HHI_PCIE_PLL_CNTL0,    .def = 0x14090496, .delay_us = 10 },
 634         { .reg = HHI_PCIE_PLL_CNTL2,    .def = 0x00001000 },
 635 };
 636
 637 /* Keep a single entry table for recalc/round_rate() ops */
 638 static const struct pll_params_table g12a_pcie_pll_table[] = {
 639         PLL_PARAMS(150, 1),
 640         {0, 0},
 641 };
 642
 643 static struct clk_regmap g12a_pcie_pll_dco = {
 644         .data = &(struct meson_clk_pll_data){
 645                 .en = {
 646                         .reg_off = HHI_PCIE_PLL_CNTL0,
 647                         .shift   = 28,
 648                         .width   = 1,
 649                 },
 650                 .m = {
 651                         .reg_off = HHI_PCIE_PLL_CNTL0,
 652                         .shift   = 0,
 653                         .width   = 8,
 654                 },
 655                 .n = {
 656                         .reg_off = HHI_PCIE_PLL_CNTL0,
 657                         .shift   = 10,
 658                         .width   = 5,
 659                 },
 660                 .frac = {
 661                         .reg_off = HHI_PCIE_PLL_CNTL1,
 662                         .shift   = 0,
 663                         .width   = 12,
 664                 },
 665                 .l = {
 666                         .reg_off = HHI_PCIE_PLL_CNTL0,
 667                         .shift   = 31,
 668                         .width   = 1,
 669                 },
 670                 .rst = {
 671                         .reg_off = HHI_PCIE_PLL_CNTL0,
 672                         .shift   = 29,
 673                         .width   = 1,
 674                 },
 675                 .table = g12a_pcie_pll_table,
 676                 .init_regs = g12a_pcie_pll_init_regs,
 677                 .init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
 678         },
 679         .hw.init = &(struct clk_init_data){
 680                 .name = "pcie_pll_dco",
 681                 .ops = &meson_clk_pcie_pll_ops,
 682                 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
 683                 .num_parents = 1,
 684         },
 685 };
 686
 687 static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
 688         .mult = 1,
 689         .div = 2,
 690         .hw.init = &(struct clk_init_data){
 691                 .name = "pcie_pll_dco_div2",
 692                 .ops = &clk_fixed_factor_ops,
 693                 .parent_names = (const char *[]){ "pcie_pll_dco" },
 694                 .num_parents = 1,
 695                 .flags = CLK_SET_RATE_PARENT,
 696         },
 697 };
 698
 699 static struct clk_regmap g12a_pcie_pll_od = {
 700         .data = &(struct clk_regmap_div_data){
 701                 .offset = HHI_PCIE_PLL_CNTL0,
 702                 .shift = 16,
 703                 .width = 5,
 704                 .flags = CLK_DIVIDER_ROUND_CLOSEST |
 705                          CLK_DIVIDER_ONE_BASED |
 706                          CLK_DIVIDER_ALLOW_ZERO,
 707         },
 708         .hw.init = &(struct clk_init_data){
 709                 .name = "pcie_pll_od",
 710                 .ops = &clk_regmap_divider_ops,
 711                 .parent_names = (const char *[]){ "pcie_pll_dco_div2" },
 712                 .num_parents = 1,
 713                 .flags = CLK_SET_RATE_PARENT,
 714         },
 715 };
 716
 717 static struct clk_fixed_factor g12a_pcie_pll = {
 718         .mult = 1,
 719         .div = 2,
 720         .hw.init = &(struct clk_init_data){
 721                 .name = "pcie_pll_pll",
 722                 .ops = &clk_fixed_factor_ops,
 723                 .parent_names = (const char *[]){ "pcie_pll_od" },
 724                 .num_parents = 1,
 725                 .flags = CLK_SET_RATE_PARENT,
 726         },
 727 };
 728
 729 static struct clk_regmap g12a_hdmi_pll_dco = {
 730         .data = &(struct meson_clk_pll_data){
 731                 .en = {
 732                         .reg_off = HHI_HDMI_PLL_CNTL0,
 733                         .shift   = 28,
 734                         .width   = 1,
 735                 },
 736                 .m = {
 737                         .reg_off = HHI_HDMI_PLL_CNTL0,
 738                         .shift   = 0,
 739                         .width   = 8,
 740                 },
 741                 .n = {
 742                         .reg_off = HHI_HDMI_PLL_CNTL0,
 743                         .shift   = 10,
 744                         .width   = 5,
 745                 },
 746                 .frac = {
 747                         .reg_off = HHI_HDMI_PLL_CNTL1,
 748                         .shift   = 0,
 749                         .width   = 16,
 750                 },
 751                 .l = {
 752                         .reg_off = HHI_HDMI_PLL_CNTL0,
 753                         .shift   = 30,
 754                         .width   = 1,
 755                 },
 756                 .rst = {
 757                         .reg_off = HHI_HDMI_PLL_CNTL0,
 758                         .shift   = 29,
 759                         .width   = 1,
 760                 },
 761         },
 762         .hw.init = &(struct clk_init_data){
 763                 .name = "hdmi_pll_dco",
 764                 .ops = &meson_clk_pll_ro_ops,
 765                 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
 766                 .num_parents = 1,
 767                 /*
 768                  * Display directly handle hdmi pll registers ATM, we need
 769                  * NOCACHE to keep our view of the clock as accurate as possible
 770                  */
 771                 .flags = CLK_GET_RATE_NOCACHE,
 772         },
 773 };
 774
 775 static struct clk_regmap g12a_hdmi_pll_od = {
 776         .data = &(struct clk_regmap_div_data){
 777                 .offset = HHI_HDMI_PLL_CNTL0,
 778                 .shift = 16,
 779                 .width = 2,
 780                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 781         },
 782         .hw.init = &(struct clk_init_data){
 783                 .name = "hdmi_pll_od",
 784                 .ops = &clk_regmap_divider_ro_ops,
 785                 .parent_names = (const char *[]){ "hdmi_pll_dco" },
 786                 .num_parents = 1,
 787                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 788         },
 789 };
 790
 791 static struct clk_regmap g12a_hdmi_pll_od2 = {
 792         .data = &(struct clk_regmap_div_data){
 793                 .offset = HHI_HDMI_PLL_CNTL0,
 794                 .shift = 18,
 795                 .width = 2,
 796                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 797         },
 798         .hw.init = &(struct clk_init_data){
 799                 .name = "hdmi_pll_od2",
 800                 .ops = &clk_regmap_divider_ro_ops,
 801                 .parent_names = (const char *[]){ "hdmi_pll_od" },
 802                 .num_parents = 1,
 803                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 804         },
 805 };
 806
 807 static struct clk_regmap g12a_hdmi_pll = {
 808         .data = &(struct clk_regmap_div_data){
 809                 .offset = HHI_HDMI_PLL_CNTL0,
 810                 .shift = 20,
 811                 .width = 2,
 812                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 813         },
 814         .hw.init = &(struct clk_init_data){
 815                 .name = "hdmi_pll",
 816                 .ops = &clk_regmap_divider_ro_ops,
 817                 .parent_names = (const char *[]){ "hdmi_pll_od2" },
 818                 .num_parents = 1,
 819                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 820         },
 821 };
 822
 823 static struct clk_fixed_factor g12a_fclk_div2_div = {
 824         .mult = 1,
 825         .div = 2,
 826         .hw.init = &(struct clk_init_data){
 827                 .name = "fclk_div2_div",
 828                 .ops = &clk_fixed_factor_ops,
 829                 .parent_names = (const char *[]){ "fixed_pll" },
 830                 .num_parents = 1,
 831         },
 832 };
 833
 834 static struct clk_regmap g12a_fclk_div2 = {
 835         .data = &(struct clk_regmap_gate_data){
 836                 .offset = HHI_FIX_PLL_CNTL1,
 837                 .bit_idx = 24,
 838         },
 839         .hw.init = &(struct clk_init_data){
 840                 .name = "fclk_div2",
 841                 .ops = &clk_regmap_gate_ops,
 842                 .parent_names = (const char *[]){ "fclk_div2_div" },
 843                 .num_parents = 1,
 844         },
 845 };
 846
 847 static struct clk_fixed_factor g12a_fclk_div3_div = {
 848         .mult = 1,
 849         .div = 3,
 850         .hw.init = &(struct clk_init_data){
 851                 .name = "fclk_div3_div",
 852                 .ops = &clk_fixed_factor_ops,
 853                 .parent_names = (const char *[]){ "fixed_pll" },
 854                 .num_parents = 1,
 855         },
 856 };
 857
 858 static struct clk_regmap g12a_fclk_div3 = {
 859         .data = &(struct clk_regmap_gate_data){
 860                 .offset = HHI_FIX_PLL_CNTL1,
 861                 .bit_idx = 20,
 862         },
 863         .hw.init = &(struct clk_init_data){
 864                 .name = "fclk_div3",
 865                 .ops = &clk_regmap_gate_ops,
 866                 .parent_names = (const char *[]){ "fclk_div3_div" },
 867                 .num_parents = 1,
 868         },
 869 };
 870
 871 static struct clk_fixed_factor g12a_fclk_div4_div = {
 872         .mult = 1,
 873         .div = 4,
 874         .hw.init = &(struct clk_init_data){
 875                 .name = "fclk_div4_div",
 876                 .ops = &clk_fixed_factor_ops,
 877                 .parent_names = (const char *[]){ "fixed_pll" },
 878                 .num_parents = 1,
 879         },
 880 };
 881
 882 static struct clk_regmap g12a_fclk_div4 = {
 883         .data = &(struct clk_regmap_gate_data){
 884                 .offset = HHI_FIX_PLL_CNTL1,
 885                 .bit_idx = 21,
 886         },
 887         .hw.init = &(struct clk_init_data){
 888                 .name = "fclk_div4",
 889                 .ops = &clk_regmap_gate_ops,
 890                 .parent_names = (const char *[]){ "fclk_div4_div" },
 891                 .num_parents = 1,
 892         },
 893 };
 894
 895 static struct clk_fixed_factor g12a_fclk_div5_div = {
 896         .mult = 1,
 897         .div = 5,
 898         .hw.init = &(struct clk_init_data){
 899                 .name = "fclk_div5_div",
 900                 .ops = &clk_fixed_factor_ops,
 901                 .parent_names = (const char *[]){ "fixed_pll" },
 902                 .num_parents = 1,
 903         },
 904 };
 905
 906 static struct clk_regmap g12a_fclk_div5 = {
 907         .data = &(struct clk_regmap_gate_data){
 908                 .offset = HHI_FIX_PLL_CNTL1,
 909                 .bit_idx = 22,
 910         },
 911         .hw.init = &(struct clk_init_data){
 912                 .name = "fclk_div5",
 913                 .ops = &clk_regmap_gate_ops,
 914                 .parent_names = (const char *[]){ "fclk_div5_div" },
 915                 .num_parents = 1,
 916         },
 917 };
 918
 919 static struct clk_fixed_factor g12a_fclk_div7_div = {
 920         .mult = 1,
 921         .div = 7,
 922         .hw.init = &(struct clk_init_data){
 923                 .name = "fclk_div7_div",
 924                 .ops = &clk_fixed_factor_ops,
 925                 .parent_names = (const char *[]){ "fixed_pll" },
 926                 .num_parents = 1,
 927         },
 928 };
 929
 930 static struct clk_regmap g12a_fclk_div7 = {
 931         .data = &(struct clk_regmap_gate_data){
 932                 .offset = HHI_FIX_PLL_CNTL1,
 933                 .bit_idx = 23,
 934         },
 935         .hw.init = &(struct clk_init_data){
 936                 .name = "fclk_div7",
 937                 .ops = &clk_regmap_gate_ops,
 938                 .parent_names = (const char *[]){ "fclk_div7_div" },
 939                 .num_parents = 1,
 940         },
 941 };
 942
 943 static struct clk_fixed_factor g12a_fclk_div2p5_div = {
 944         .mult = 1,
 945         .div = 5,
 946         .hw.init = &(struct clk_init_data){
 947                 .name = "fclk_div2p5_div",
 948                 .ops = &clk_fixed_factor_ops,
 949                 .parent_names = (const char *[]){ "fixed_pll_dco" },
 950                 .num_parents = 1,
 951         },
 952 };
 953
 954 static struct clk_regmap g12a_fclk_div2p5 = {
 955         .data = &(struct clk_regmap_gate_data){
 956                 .offset = HHI_FIX_PLL_CNTL1,
 957                 .bit_idx = 25,
 958         },
 959         .hw.init = &(struct clk_init_data){
 960                 .name = "fclk_div2p5",
 961                 .ops = &clk_regmap_gate_ops,
 962                 .parent_names = (const char *[]){ "fclk_div2p5_div" },
 963                 .num_parents = 1,
 964         },
 965 };
 966
 967 static struct clk_fixed_factor g12a_mpll_50m_div = {
 968         .mult = 1,
 969         .div = 80,
 970         .hw.init = &(struct clk_init_data){
 971                 .name = "mpll_50m_div",
 972                 .ops = &clk_fixed_factor_ops,
 973                 .parent_names = (const char *[]){ "fixed_pll_dco" },
 974                 .num_parents = 1,
 975         },
 976 };
 977
 978 static struct clk_regmap g12a_mpll_50m = {
 979         .data = &(struct clk_regmap_mux_data){
 980                 .offset = HHI_FIX_PLL_CNTL3,
 981                 .mask = 0x1,
 982                 .shift = 5,
 983         },
 984         .hw.init = &(struct clk_init_data){
 985                 .name = "mpll_50m",
 986                 .ops = &clk_regmap_mux_ro_ops,
 987                 .parent_names = (const char *[]){ IN_PREFIX "xtal",
 988                                                   "mpll_50m_div" },
 989                 .num_parents = 2,
 990         },
 991 };
 992
 993 static struct clk_fixed_factor g12a_mpll_prediv = {
 994         .mult = 1,
 995         .div = 2,
 996         .hw.init = &(struct clk_init_data){
 997                 .name = "mpll_prediv",
 998                 .ops = &clk_fixed_factor_ops,
 999                 .parent_names = (const char *[]){ "fixed_pll_dco" },
1000                 .num_parents = 1,
1001         },
1002 };
1003
1004 static struct clk_regmap g12a_mpll0_div = {
1005         .data = &(struct meson_clk_mpll_data){
1006                 .sdm = {
1007                         .reg_off = HHI_MPLL_CNTL1,
1008                         .shift   = 0,
1009                         .width   = 14,
1010                 },
1011                 .sdm_en = {
1012                         .reg_off = HHI_MPLL_CNTL1,
1013                         .shift   = 30,
1014                         .width   = 1,
1015                 },
1016                 .n2 = {
1017                         .reg_off = HHI_MPLL_CNTL1,
1018                         .shift   = 20,
1019                         .width   = 9,
1020                 },
1021                 .ssen = {
1022                         .reg_off = HHI_MPLL_CNTL1,
1023                         .shift   = 29,
1024                         .width   = 1,
1025                 },
1026                 .lock = &meson_clk_lock,
1027         },
1028         .hw.init = &(struct clk_init_data){
1029                 .name = "mpll0_div",
1030                 .ops = &meson_clk_mpll_ops,
1031                 .parent_names = (const char *[]){ "mpll_prediv" },
1032                 .num_parents = 1,
1033         },
1034 };
1035
1036 static struct clk_regmap g12a_mpll0 = {
1037         .data = &(struct clk_regmap_gate_data){
1038                 .offset = HHI_MPLL_CNTL1,
1039                 .bit_idx = 31,
1040         },
1041         .hw.init = &(struct clk_init_data){
1042                 .name = "mpll0",
1043                 .ops = &clk_regmap_gate_ops,
1044                 .parent_names = (const char *[]){ "mpll0_div" },
1045                 .num_parents = 1,
1046                 .flags = CLK_SET_RATE_PARENT,
1047         },
1048 };
1049
1050 static struct clk_regmap g12a_mpll1_div = {
1051         .data = &(struct meson_clk_mpll_data){
1052                 .sdm = {
1053                         .reg_off = HHI_MPLL_CNTL3,
1054                         .shift   = 0,
1055                         .width   = 14,
1056                 },
1057                 .sdm_en = {
1058                         .reg_off = HHI_MPLL_CNTL3,
1059                         .shift   = 30,
1060                         .width   = 1,
1061                 },
1062                 .n2 = {
1063                         .reg_off = HHI_MPLL_CNTL3,
1064                         .shift   = 20,
1065                         .width   = 9,
1066                 },
1067                 .ssen = {
1068                         .reg_off = HHI_MPLL_CNTL3,
1069                         .shift   = 29,
1070                         .width   = 1,
1071                 },
1072                 .lock = &meson_clk_lock,
1073         },
1074         .hw.init = &(struct clk_init_data){
1075                 .name = "mpll1_div",
1076                 .ops = &meson_clk_mpll_ops,
1077                 .parent_names = (const char *[]){ "mpll_prediv" },
1078                 .num_parents = 1,
1079         },
1080 };
1081
1082 static struct clk_regmap g12a_mpll1 = {
1083         .data = &(struct clk_regmap_gate_data){
1084                 .offset = HHI_MPLL_CNTL3,
1085                 .bit_idx = 31,
1086         },
1087         .hw.init = &(struct clk_init_data){
1088                 .name = "mpll1",
1089                 .ops = &clk_regmap_gate_ops,
1090                 .parent_names = (const char *[]){ "mpll1_div" },
1091                 .num_parents = 1,
1092                 .flags = CLK_SET_RATE_PARENT,
1093         },
1094 };
1095
1096 static struct clk_regmap g12a_mpll2_div = {
1097         .data = &(struct meson_clk_mpll_data){
1098                 .sdm = {
1099                         .reg_off = HHI_MPLL_CNTL5,
1100                         .shift   = 0,
1101                         .width   = 14,
1102                 },
1103                 .sdm_en = {
1104                         .reg_off = HHI_MPLL_CNTL5,
1105                         .shift   = 30,
1106                         .width   = 1,
1107                 },
1108                 .n2 = {
1109                         .reg_off = HHI_MPLL_CNTL5,
1110                         .shift   = 20,
1111                         .width   = 9,
1112                 },
1113                 .ssen = {
1114                         .reg_off = HHI_MPLL_CNTL5,
1115                         .shift   = 29,
1116                         .width   = 1,
1117                 },
1118                 .lock = &meson_clk_lock,
1119         },
1120         .hw.init = &(struct clk_init_data){
1121                 .name = "mpll2_div",
1122                 .ops = &meson_clk_mpll_ops,
1123                 .parent_names = (const char *[]){ "mpll_prediv" },
1124                 .num_parents = 1,
1125         },
1126 };
1127
1128 static struct clk_regmap g12a_mpll2 = {
1129         .data = &(struct clk_regmap_gate_data){
1130                 .offset = HHI_MPLL_CNTL5,
1131                 .bit_idx = 31,
1132         },
1133         .hw.init = &(struct clk_init_data){
1134                 .name = "mpll2",
1135                 .ops = &clk_regmap_gate_ops,
1136                 .parent_names = (const char *[]){ "mpll2_div" },
1137                 .num_parents = 1,
1138                 .flags = CLK_SET_RATE_PARENT,
1139         },
1140 };
1141
1142 static struct clk_regmap g12a_mpll3_div = {
1143         .data = &(struct meson_clk_mpll_data){
1144                 .sdm = {
1145                         .reg_off = HHI_MPLL_CNTL7,
1146                         .shift   = 0,
1147                         .width   = 14,
1148                 },
1149                 .sdm_en = {
1150                         .reg_off = HHI_MPLL_CNTL7,
1151                         .shift   = 30,
1152                         .width   = 1,
1153                 },
1154                 .n2 = {
1155                         .reg_off = HHI_MPLL_CNTL7,
1156                         .shift   = 20,
1157                         .width   = 9,
1158                 },
1159                 .ssen = {
1160                         .reg_off = HHI_MPLL_CNTL7,
1161                         .shift   = 29,
1162                         .width   = 1,
1163                 },
1164                 .lock = &meson_clk_lock,
1165         },
1166         .hw.init = &(struct clk_init_data){
1167                 .name = "mpll3_div",
1168                 .ops = &meson_clk_mpll_ops,
1169                 .parent_names = (const char *[]){ "mpll_prediv" },
1170                 .num_parents = 1,
1171         },
1172 };
1173
1174 static struct clk_regmap g12a_mpll3 = {
1175         .data = &(struct clk_regmap_gate_data){
1176                 .offset = HHI_MPLL_CNTL7,
1177                 .bit_idx = 31,
1178         },
1179         .hw.init = &(struct clk_init_data){
1180                 .name = "mpll3",
1181                 .ops = &clk_regmap_gate_ops,
1182                 .parent_names = (const char *[]){ "mpll3_div" },
1183                 .num_parents = 1,
1184                 .flags = CLK_SET_RATE_PARENT,
1185         },
1186 };
1187
1188 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
1189 static const char * const clk81_parent_names[] = {
1190         IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
1191         "fclk_div3", "fclk_div5"
1192 };
1193
1194 static struct clk_regmap g12a_mpeg_clk_sel = {
1195         .data = &(struct clk_regmap_mux_data){
1196                 .offset = HHI_MPEG_CLK_CNTL,
1197                 .mask = 0x7,
1198                 .shift = 12,
1199                 .table = mux_table_clk81,
1200         },
1201         .hw.init = &(struct clk_init_data){
1202                 .name = "mpeg_clk_sel",
1203                 .ops = &clk_regmap_mux_ro_ops,
1204                 .parent_names = clk81_parent_names,
1205                 .num_parents = ARRAY_SIZE(clk81_parent_names),
1206         },
1207 };
1208
1209 static struct clk_regmap g12a_mpeg_clk_div = {
1210         .data = &(struct clk_regmap_div_data){
1211                 .offset = HHI_MPEG_CLK_CNTL,
1212                 .shift = 0,
1213                 .width = 7,
1214         },
1215         .hw.init = &(struct clk_init_data){
1216                 .name = "mpeg_clk_div",
1217                 .ops = &clk_regmap_divider_ops,
1218                 .parent_names = (const char *[]){ "mpeg_clk_sel" },
1219                 .num_parents = 1,
1220                 .flags = CLK_SET_RATE_PARENT,
1221         },
1222 };
1223
1224 static struct clk_regmap g12a_clk81 = {
1225         .data = &(struct clk_regmap_gate_data){
1226                 .offset = HHI_MPEG_CLK_CNTL,
1227                 .bit_idx = 7,
1228         },
1229         .hw.init = &(struct clk_init_data){
1230                 .name = "clk81",
1231                 .ops = &clk_regmap_gate_ops,
1232                 .parent_names = (const char *[]){ "mpeg_clk_div" },
1233                 .num_parents = 1,
1234                 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
1235         },
1236 };
1237
1238 static const char * const g12a_sd_emmc_clk0_parent_names[] = {
1239         IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
1240
1241         /*
1242          * Following these parent clocks, we should also have had mpll2, mpll3
1243          * and gp0_pll but these clocks are too precious to be used here. All
1244          * the necessary rates for MMC and NAND operation can be acheived using
1245          * g12a_ee_core or fclk_div clocks
1246          */
1247 };
1248
1249 /* SDIO clock */
1250 static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {
1251         .data = &(struct clk_regmap_mux_data){
1252                 .offset = HHI_SD_EMMC_CLK_CNTL,
1253                 .mask = 0x7,
1254                 .shift = 9,
1255         },
1256         .hw.init = &(struct clk_init_data) {
1257                 .name = "sd_emmc_a_clk0_sel",
1258                 .ops = &clk_regmap_mux_ops,
1259                 .parent_names = g12a_sd_emmc_clk0_parent_names,
1260                 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),
1261                 .flags = CLK_SET_RATE_PARENT,
1262         },
1263 };
1264
1265 static struct clk_regmap g12a_sd_emmc_a_clk0_div = {
1266         .data = &(struct clk_regmap_div_data){
1267                 .offset = HHI_SD_EMMC_CLK_CNTL,
1268                 .shift = 0,
1269                 .width = 7,
1270         },
1271         .hw.init = &(struct clk_init_data) {
1272                 .name = "sd_emmc_a_clk0_div",
1273                 .ops = &clk_regmap_divider_ops,
1274                 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
1275                 .num_parents = 1,
1276                 .flags = CLK_SET_RATE_PARENT,
1277         },
1278 };
1279
1280 static struct clk_regmap g12a_sd_emmc_a_clk0 = {
1281         .data = &(struct clk_regmap_gate_data){
1282                 .offset = HHI_SD_EMMC_CLK_CNTL,
1283                 .bit_idx = 7,
1284         },
1285         .hw.init = &(struct clk_init_data){
1286                 .name = "sd_emmc_a_clk0",
1287                 .ops = &clk_regmap_gate_ops,
1288                 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
1289                 .num_parents = 1,
1290                 .flags = CLK_SET_RATE_PARENT,
1291         },
1292 };
1293
1294 /* SDcard clock */
1295 static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {
1296         .data = &(struct clk_regmap_mux_data){
1297                 .offset = HHI_SD_EMMC_CLK_CNTL,
1298                 .mask = 0x7,
1299                 .shift = 25,
1300         },
1301         .hw.init = &(struct clk_init_data) {
1302                 .name = "sd_emmc_b_clk0_sel",
1303                 .ops = &clk_regmap_mux_ops,
1304                 .parent_names = g12a_sd_emmc_clk0_parent_names,
1305                 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),
1306                 .flags = CLK_SET_RATE_PARENT,
1307         },
1308 };
1309
1310 static struct clk_regmap g12a_sd_emmc_b_clk0_div = {
1311         .data = &(struct clk_regmap_div_data){
1312                 .offset = HHI_SD_EMMC_CLK_CNTL,
1313                 .shift = 16,
1314                 .width = 7,
1315         },
1316         .hw.init = &(struct clk_init_data) {
1317                 .name = "sd_emmc_b_clk0_div",
1318                 .ops = &clk_regmap_divider_ops,
1319                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
1320                 .num_parents = 1,
1321                 .flags = CLK_SET_RATE_PARENT,
1322         },
1323 };
1324
1325 static struct clk_regmap g12a_sd_emmc_b_clk0 = {
1326         .data = &(struct clk_regmap_gate_data){
1327                 .offset = HHI_SD_EMMC_CLK_CNTL,
1328                 .bit_idx = 23,
1329         },
1330         .hw.init = &(struct clk_init_data){
1331                 .name = "sd_emmc_b_clk0",
1332                 .ops = &clk_regmap_gate_ops,
1333                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
1334                 .num_parents = 1,
1335                 .flags = CLK_SET_RATE_PARENT,
1336         },
1337 };
1338
1339 /* EMMC/NAND clock */
1340 static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {
1341         .data = &(struct clk_regmap_mux_data){
1342                 .offset = HHI_NAND_CLK_CNTL,
1343                 .mask = 0x7,
1344                 .shift = 9,
1345         },
1346         .hw.init = &(struct clk_init_data) {
1347                 .name = "sd_emmc_c_clk0_sel",
1348                 .ops = &clk_regmap_mux_ops,
1349                 .parent_names = g12a_sd_emmc_clk0_parent_names,
1350                 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),
1351                 .flags = CLK_SET_RATE_PARENT,
1352         },
1353 };
1354
1355 static struct clk_regmap g12a_sd_emmc_c_clk0_div = {
1356         .data = &(struct clk_regmap_div_data){
1357                 .offset = HHI_NAND_CLK_CNTL,
1358                 .shift = 0,
1359                 .width = 7,
1360         },
1361         .hw.init = &(struct clk_init_data) {
1362                 .name = "sd_emmc_c_clk0_div",
1363                 .ops = &clk_regmap_divider_ops,
1364                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
1365                 .num_parents = 1,
1366                 .flags = CLK_SET_RATE_PARENT,
1367         },
1368 };
1369
1370 static struct clk_regmap g12a_sd_emmc_c_clk0 = {
1371         .data = &(struct clk_regmap_gate_data){
1372                 .offset = HHI_NAND_CLK_CNTL,
1373                 .bit_idx = 7,
1374         },
1375         .hw.init = &(struct clk_init_data){
1376                 .name = "sd_emmc_c_clk0",
1377                 .ops = &clk_regmap_gate_ops,
1378                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
1379                 .num_parents = 1,
1380                 .flags = CLK_SET_RATE_PARENT,
1381         },
1382 };
1383
1384 /* VPU Clock */
1385
1386 static const char * const g12a_vpu_parent_names[] = {
1387         "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
1388         "mpll1", "vid_pll", "hifi_pll", "gp0_pll",
1389 };
1390
1391 static struct clk_regmap g12a_vpu_0_sel = {
1392         .data = &(struct clk_regmap_mux_data){
1393                 .offset = HHI_VPU_CLK_CNTL,
1394                 .mask = 0x7,
1395                 .shift = 9,
1396         },
1397         .hw.init = &(struct clk_init_data){
1398                 .name = "vpu_0_sel",
1399                 .ops = &clk_regmap_mux_ops,
1400                 .parent_names = g12a_vpu_parent_names,
1401                 .num_parents = ARRAY_SIZE(g12a_vpu_parent_names),
1402                 .flags = CLK_SET_RATE_NO_REPARENT,
1403         },
1404 };
1405
1406 static struct clk_regmap g12a_vpu_0_div = {
1407         .data = &(struct clk_regmap_div_data){
1408                 .offset = HHI_VPU_CLK_CNTL,
1409                 .shift = 0,
1410                 .width = 7,
1411         },
1412         .hw.init = &(struct clk_init_data){
1413                 .name = "vpu_0_div",
1414                 .ops = &clk_regmap_divider_ops,
1415                 .parent_names = (const char *[]){ "vpu_0_sel" },
1416                 .num_parents = 1,
1417                 .flags = CLK_SET_RATE_PARENT,
1418         },
1419 };
1420
1421 static struct clk_regmap g12a_vpu_0 = {
1422         .data = &(struct clk_regmap_gate_data){
1423                 .offset = HHI_VPU_CLK_CNTL,
1424                 .bit_idx = 8,
1425         },
1426         .hw.init = &(struct clk_init_data) {
1427                 .name = "vpu_0",
1428                 .ops = &clk_regmap_gate_ops,
1429                 .parent_names = (const char *[]){ "vpu_0_div" },
1430                 .num_parents = 1,
1431                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1432         },
1433 };
1434
1435 static struct clk_regmap g12a_vpu_1_sel = {
1436         .data = &(struct clk_regmap_mux_data){
1437                 .offset = HHI_VPU_CLK_CNTL,
1438                 .mask = 0x7,
1439                 .shift = 25,
1440         },
1441         .hw.init = &(struct clk_init_data){
1442                 .name = "vpu_1_sel",
1443                 .ops = &clk_regmap_mux_ops,
1444                 .parent_names = g12a_vpu_parent_names,
1445                 .num_parents = ARRAY_SIZE(g12a_vpu_parent_names),
1446                 .flags = CLK_SET_RATE_NO_REPARENT,
1447         },
1448 };
1449
1450 static struct clk_regmap g12a_vpu_1_div = {
1451         .data = &(struct clk_regmap_div_data){
1452                 .offset = HHI_VPU_CLK_CNTL,
1453                 .shift = 16,
1454                 .width = 7,
1455         },
1456         .hw.init = &(struct clk_init_data){
1457                 .name = "vpu_1_div",
1458                 .ops = &clk_regmap_divider_ops,
1459                 .parent_names = (const char *[]){ "vpu_1_sel" },
1460                 .num_parents = 1,
1461                 .flags = CLK_SET_RATE_PARENT,
1462         },
1463 };
1464
1465 static struct clk_regmap g12a_vpu_1 = {
1466         .data = &(struct clk_regmap_gate_data){
1467                 .offset = HHI_VPU_CLK_CNTL,
1468                 .bit_idx = 24,
1469         },
1470         .hw.init = &(struct clk_init_data) {
1471                 .name = "vpu_1",
1472                 .ops = &clk_regmap_gate_ops,
1473                 .parent_names = (const char *[]){ "vpu_1_div" },
1474                 .num_parents = 1,
1475                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1476         },
1477 };
1478
1479 static struct clk_regmap g12a_vpu = {
1480         .data = &(struct clk_regmap_mux_data){
1481                 .offset = HHI_VPU_CLK_CNTL,
1482                 .mask = 1,
1483                 .shift = 31,
1484         },
1485         .hw.init = &(struct clk_init_data){
1486                 .name = "vpu",
1487                 .ops = &clk_regmap_mux_ops,
1488                 /*
1489                  * bit 31 selects from 2 possible parents:
1490                  * vpu_0 or vpu_1
1491                  */
1492                 .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
1493                 .num_parents = 2,
1494                 .flags = CLK_SET_RATE_NO_REPARENT,
1495         },
1496 };
1497
1498 /* VDEC clocks */
1499
1500 static const char * const g12a_vdec_parent_names[] = {
1501         "fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
1502         "hifi_pll", "gp0_pll",
1503 };
1504
1505 static struct clk_regmap g12a_vdec_1_sel = {
1506         .data = &(struct clk_regmap_mux_data){
1507                 .offset = HHI_VDEC_CLK_CNTL,
1508                 .mask = 0x7,
1509                 .shift = 9,
1510                 .flags = CLK_MUX_ROUND_CLOSEST,
1511         },
1512         .hw.init = &(struct clk_init_data){
1513                 .name = "vdec_1_sel",
1514                 .ops = &clk_regmap_mux_ops,
1515                 .parent_names = g12a_vdec_parent_names,
1516                 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
1517                 .flags = CLK_SET_RATE_PARENT,
1518         },
1519 };
1520
1521 static struct clk_regmap g12a_vdec_1_div = {
1522         .data = &(struct clk_regmap_div_data){
1523                 .offset = HHI_VDEC_CLK_CNTL,
1524                 .shift = 0,
1525                 .width = 7,
1526                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1527         },
1528         .hw.init = &(struct clk_init_data){
1529                 .name = "vdec_1_div",
1530                 .ops = &clk_regmap_divider_ops,
1531                 .parent_names = (const char *[]){ "vdec_1_sel" },
1532                 .num_parents = 1,
1533                 .flags = CLK_SET_RATE_PARENT,
1534         },
1535 };
1536
1537 static struct clk_regmap g12a_vdec_1 = {
1538         .data = &(struct clk_regmap_gate_data){
1539                 .offset = HHI_VDEC_CLK_CNTL,
1540                 .bit_idx = 8,
1541         },
1542         .hw.init = &(struct clk_init_data) {
1543                 .name = "vdec_1",
1544                 .ops = &clk_regmap_gate_ops,
1545                 .parent_names = (const char *[]){ "vdec_1_div" },
1546                 .num_parents = 1,
1547                 .flags = CLK_SET_RATE_PARENT,
1548         },
1549 };
1550
1551 static struct clk_regmap g12a_vdec_hevcf_sel = {
1552         .data = &(struct clk_regmap_mux_data){
1553                 .offset = HHI_VDEC2_CLK_CNTL,
1554                 .mask = 0x7,
1555                 .shift = 9,
1556                 .flags = CLK_MUX_ROUND_CLOSEST,
1557         },
1558         .hw.init = &(struct clk_init_data){
1559                 .name = "vdec_hevcf_sel",
1560                 .ops = &clk_regmap_mux_ops,
1561                 .parent_names = g12a_vdec_parent_names,
1562                 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
1563                 .flags = CLK_SET_RATE_PARENT,
1564         },
1565 };
1566
1567 static struct clk_regmap g12a_vdec_hevcf_div = {
1568         .data = &(struct clk_regmap_div_data){
1569                 .offset = HHI_VDEC2_CLK_CNTL,
1570                 .shift = 0,
1571                 .width = 7,
1572                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1573         },
1574         .hw.init = &(struct clk_init_data){
1575                 .name = "vdec_hevcf_div",
1576                 .ops = &clk_regmap_divider_ops,
1577                 .parent_names = (const char *[]){ "vdec_hevcf_sel" },
1578                 .num_parents = 1,
1579                 .flags = CLK_SET_RATE_PARENT,
1580         },
1581 };
1582
1583 static struct clk_regmap g12a_vdec_hevcf = {
1584         .data = &(struct clk_regmap_gate_data){
1585                 .offset = HHI_VDEC2_CLK_CNTL,
1586                 .bit_idx = 8,
1587         },
1588         .hw.init = &(struct clk_init_data) {
1589                 .name = "vdec_hevcf",
1590                 .ops = &clk_regmap_gate_ops,
1591                 .parent_names = (const char *[]){ "vdec_hevcf_div" },
1592                 .num_parents = 1,
1593                 .flags = CLK_SET_RATE_PARENT,
1594         },
1595 };
1596
1597 static struct clk_regmap g12a_vdec_hevc_sel = {
1598         .data = &(struct clk_regmap_mux_data){
1599                 .offset = HHI_VDEC2_CLK_CNTL,
1600                 .mask = 0x7,
1601                 .shift = 25,
1602                 .flags = CLK_MUX_ROUND_CLOSEST,
1603         },
1604         .hw.init = &(struct clk_init_data){
1605                 .name = "vdec_hevc_sel",
1606                 .ops = &clk_regmap_mux_ops,
1607                 .parent_names = g12a_vdec_parent_names,
1608                 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
1609                 .flags = CLK_SET_RATE_PARENT,
1610         },
1611 };
1612
1613 static struct clk_regmap g12a_vdec_hevc_div = {
1614         .data = &(struct clk_regmap_div_data){
1615                 .offset = HHI_VDEC2_CLK_CNTL,
1616                 .shift = 16,
1617                 .width = 7,
1618                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1619         },
1620         .hw.init = &(struct clk_init_data){
1621                 .name = "vdec_hevc_div",
1622                 .ops = &clk_regmap_divider_ops,
1623                 .parent_names = (const char *[]){ "vdec_hevc_sel" },
1624                 .num_parents = 1,
1625                 .flags = CLK_SET_RATE_PARENT,
1626         },
1627 };
1628
1629 static struct clk_regmap g12a_vdec_hevc = {
1630         .data = &(struct clk_regmap_gate_data){
1631                 .offset = HHI_VDEC2_CLK_CNTL,
1632                 .bit_idx = 24,
1633         },
1634         .hw.init = &(struct clk_init_data) {
1635                 .name = "vdec_hevc",
1636                 .ops = &clk_regmap_gate_ops,
1637                 .parent_names = (const char *[]){ "vdec_hevc_div" },
1638                 .num_parents = 1,
1639                 .flags = CLK_SET_RATE_PARENT,
1640         },
1641 };
1642
1643 /* VAPB Clock */
1644
1645 static const char * const g12a_vapb_parent_names[] = {
1646         "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7",
1647         "mpll1", "vid_pll", "mpll2", "fclk_div2p5",
1648 };
1649
1650 static struct clk_regmap g12a_vapb_0_sel = {
1651         .data = &(struct clk_regmap_mux_data){
1652                 .offset = HHI_VAPBCLK_CNTL,
1653                 .mask = 0x3,
1654                 .shift = 9,
1655         },
1656         .hw.init = &(struct clk_init_data){
1657                 .name = "vapb_0_sel",
1658                 .ops = &clk_regmap_mux_ops,
1659                 .parent_names = g12a_vapb_parent_names,
1660                 .num_parents = ARRAY_SIZE(g12a_vapb_parent_names),
1661                 .flags = CLK_SET_RATE_NO_REPARENT,
1662         },
1663 };
1664
1665 static struct clk_regmap g12a_vapb_0_div = {
1666         .data = &(struct clk_regmap_div_data){
1667                 .offset = HHI_VAPBCLK_CNTL,
1668                 .shift = 0,
1669                 .width = 7,
1670         },
1671         .hw.init = &(struct clk_init_data){
1672                 .name = "vapb_0_div",
1673                 .ops = &clk_regmap_divider_ops,
1674                 .parent_names = (const char *[]){ "vapb_0_sel" },
1675                 .num_parents = 1,
1676                 .flags = CLK_SET_RATE_PARENT,
1677         },
1678 };
1679
1680 static struct clk_regmap g12a_vapb_0 = {
1681         .data = &(struct clk_regmap_gate_data){
1682                 .offset = HHI_VAPBCLK_CNTL,
1683                 .bit_idx = 8,
1684         },
1685         .hw.init = &(struct clk_init_data) {
1686                 .name = "vapb_0",
1687                 .ops = &clk_regmap_gate_ops,
1688                 .parent_names = (const char *[]){ "vapb_0_div" },
1689                 .num_parents = 1,
1690                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1691         },
1692 };
1693
1694 static struct clk_regmap g12a_vapb_1_sel = {
1695         .data = &(struct clk_regmap_mux_data){
1696                 .offset = HHI_VAPBCLK_CNTL,
1697                 .mask = 0x3,
1698                 .shift = 25,
1699         },
1700         .hw.init = &(struct clk_init_data){
1701                 .name = "vapb_1_sel",
1702                 .ops = &clk_regmap_mux_ops,
1703                 .parent_names = g12a_vapb_parent_names,
1704                 .num_parents = ARRAY_SIZE(g12a_vapb_parent_names),
1705                 .flags = CLK_SET_RATE_NO_REPARENT,
1706         },
1707 };
1708
1709 static struct clk_regmap g12a_vapb_1_div = {
1710         .data = &(struct clk_regmap_div_data){
1711                 .offset = HHI_VAPBCLK_CNTL,
1712                 .shift = 16,
1713                 .width = 7,
1714         },
1715         .hw.init = &(struct clk_init_data){
1716                 .name = "vapb_1_div",
1717                 .ops = &clk_regmap_divider_ops,
1718                 .parent_names = (const char *[]){ "vapb_1_sel" },
1719                 .num_parents = 1,
1720                 .flags = CLK_SET_RATE_PARENT,
1721         },
1722 };
1723
1724 static struct clk_regmap g12a_vapb_1 = {
1725         .data = &(struct clk_regmap_gate_data){
1726                 .offset = HHI_VAPBCLK_CNTL,
1727                 .bit_idx = 24,
1728         },
1729         .hw.init = &(struct clk_init_data) {
1730                 .name = "vapb_1",
1731                 .ops = &clk_regmap_gate_ops,
1732                 .parent_names = (const char *[]){ "vapb_1_div" },
1733                 .num_parents = 1,
1734                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1735         },
1736 };
1737
1738 static struct clk_regmap g12a_vapb_sel = {
1739         .data = &(struct clk_regmap_mux_data){
1740                 .offset = HHI_VAPBCLK_CNTL,
1741                 .mask = 1,
1742                 .shift = 31,
1743         },
1744         .hw.init = &(struct clk_init_data){
1745                 .name = "vapb_sel",
1746                 .ops = &clk_regmap_mux_ops,
1747                 /*
1748                  * bit 31 selects from 2 possible parents:
1749                  * vapb_0 or vapb_1
1750                  */
1751                 .parent_names = (const char *[]){ "vapb_0", "vapb_1" },
1752                 .num_parents = 2,
1753                 .flags = CLK_SET_RATE_NO_REPARENT,
1754         },
1755 };
1756
1757 static struct clk_regmap g12a_vapb = {
1758         .data = &(struct clk_regmap_gate_data){
1759                 .offset = HHI_VAPBCLK_CNTL,
1760                 .bit_idx = 30,
1761         },
1762         .hw.init = &(struct clk_init_data) {
1763                 .name = "vapb",
1764                 .ops = &clk_regmap_gate_ops,
1765                 .parent_names = (const char *[]){ "vapb_sel" },
1766                 .num_parents = 1,
1767                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1768         },
1769 };
1770
1771 /* Video Clocks */
1772
1773 static struct clk_regmap g12a_vid_pll_div = {
1774         .data = &(struct meson_vid_pll_div_data){
1775                 .val = {
1776                         .reg_off = HHI_VID_PLL_CLK_DIV,
1777                         .shift   = 0,
1778                         .width   = 15,
1779                 },
1780                 .sel = {
1781                         .reg_off = HHI_VID_PLL_CLK_DIV,
1782                         .shift   = 16,
1783                         .width   = 2,
1784                 },
1785         },
1786         .hw.init = &(struct clk_init_data) {
1787                 .name = "vid_pll_div",
1788                 .ops = &meson_vid_pll_div_ro_ops,
1789                 .parent_names = (const char *[]){ "hdmi_pll" },
1790                 .num_parents = 1,
1791                 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1792         },
1793 };
1794
1795 static const char * const g12a_vid_pll_parent_names[] = { "vid_pll_div",
1796                                                           "hdmi_pll" };
1797
1798 static struct clk_regmap g12a_vid_pll_sel = {
1799         .data = &(struct clk_regmap_mux_data){
1800                 .offset = HHI_VID_PLL_CLK_DIV,
1801                 .mask = 0x1,
1802                 .shift = 18,
1803         },
1804         .hw.init = &(struct clk_init_data){
1805                 .name = "vid_pll_sel",
1806                 .ops = &clk_regmap_mux_ops,
1807                 /*
1808                  * bit 18 selects from 2 possible parents:
1809                  * vid_pll_div or hdmi_pll
1810                  */
1811                 .parent_names = g12a_vid_pll_parent_names,
1812                 .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_names),
1813                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1814         },
1815 };
1816
1817 static struct clk_regmap g12a_vid_pll = {
1818         .data = &(struct clk_regmap_gate_data){
1819                 .offset = HHI_VID_PLL_CLK_DIV,
1820                 .bit_idx = 19,
1821         },
1822         .hw.init = &(struct clk_init_data) {
1823                 .name = "vid_pll",
1824                 .ops = &clk_regmap_gate_ops,
1825                 .parent_names = (const char *[]){ "vid_pll_sel" },
1826                 .num_parents = 1,
1827                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1828         },
1829 };
1830
1831 static const char * const g12a_vclk_parent_names[] = {
1832         "vid_pll", "gp0_pll", "hifi_pll", "mpll1", "fclk_div3", "fclk_div4",
1833         "fclk_div5", "fclk_div7"
1834 };
1835
1836 static struct clk_regmap g12a_vclk_sel = {
1837         .data = &(struct clk_regmap_mux_data){
1838                 .offset = HHI_VID_CLK_CNTL,
1839                 .mask = 0x7,
1840                 .shift = 16,
1841         },
1842         .hw.init = &(struct clk_init_data){
1843                 .name = "vclk_sel",
1844                 .ops = &clk_regmap_mux_ops,
1845                 .parent_names = g12a_vclk_parent_names,
1846                 .num_parents = ARRAY_SIZE(g12a_vclk_parent_names),
1847                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1848         },
1849 };
1850
1851 static struct clk_regmap g12a_vclk2_sel = {
1852         .data = &(struct clk_regmap_mux_data){
1853                 .offset = HHI_VIID_CLK_CNTL,
1854                 .mask = 0x7,
1855                 .shift = 16,
1856         },
1857         .hw.init = &(struct clk_init_data){
1858                 .name = "vclk2_sel",
1859                 .ops = &clk_regmap_mux_ops,
1860                 .parent_names = g12a_vclk_parent_names,
1861                 .num_parents = ARRAY_SIZE(g12a_vclk_parent_names),
1862                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1863         },
1864 };
1865
1866 static struct clk_regmap g12a_vclk_input = {
1867         .data = &(struct clk_regmap_gate_data){
1868                 .offset = HHI_VID_CLK_DIV,
1869                 .bit_idx = 16,
1870         },
1871         .hw.init = &(struct clk_init_data) {
1872                 .name = "vclk_input",
1873                 .ops = &clk_regmap_gate_ops,
1874                 .parent_names = (const char *[]){ "vclk_sel" },
1875                 .num_parents = 1,
1876                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1877         },
1878 };
1879
1880 static struct clk_regmap g12a_vclk2_input = {
1881         .data = &(struct clk_regmap_gate_data){
1882                 .offset = HHI_VIID_CLK_DIV,
1883                 .bit_idx = 16,
1884         },
1885         .hw.init = &(struct clk_init_data) {
1886                 .name = "vclk2_input",
1887                 .ops = &clk_regmap_gate_ops,
1888                 .parent_names = (const char *[]){ "vclk2_sel" },
1889                 .num_parents = 1,
1890                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1891         },
1892 };
1893
1894 static struct clk_regmap g12a_vclk_div = {
1895         .data = &(struct clk_regmap_div_data){
1896                 .offset = HHI_VID_CLK_DIV,
1897                 .shift = 0,
1898                 .width = 8,
1899         },
1900         .hw.init = &(struct clk_init_data){
1901                 .name = "vclk_div",
1902                 .ops = &clk_regmap_divider_ops,
1903                 .parent_names = (const char *[]){ "vclk_input" },
1904                 .num_parents = 1,
1905                 .flags = CLK_GET_RATE_NOCACHE,
1906         },
1907 };
1908
1909 static struct clk_regmap g12a_vclk2_div = {
1910         .data = &(struct clk_regmap_div_data){
1911                 .offset = HHI_VIID_CLK_DIV,
1912                 .shift = 0,
1913                 .width = 8,
1914         },
1915         .hw.init = &(struct clk_init_data){
1916                 .name = "vclk2_div",
1917                 .ops = &clk_regmap_divider_ops,
1918                 .parent_names = (const char *[]){ "vclk2_input" },
1919                 .num_parents = 1,
1920                 .flags = CLK_GET_RATE_NOCACHE,
1921         },
1922 };
1923
1924 static struct clk_regmap g12a_vclk = {
1925         .data = &(struct clk_regmap_gate_data){
1926                 .offset = HHI_VID_CLK_CNTL,
1927                 .bit_idx = 19,
1928         },
1929         .hw.init = &(struct clk_init_data) {
1930                 .name = "vclk",
1931                 .ops = &clk_regmap_gate_ops,
1932                 .parent_names = (const char *[]){ "vclk_div" },
1933                 .num_parents = 1,
1934                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1935         },
1936 };
1937
1938 static struct clk_regmap g12a_vclk2 = {
1939         .data = &(struct clk_regmap_gate_data){
1940                 .offset = HHI_VIID_CLK_CNTL,
1941                 .bit_idx = 19,
1942         },
1943         .hw.init = &(struct clk_init_data) {
1944                 .name = "vclk2",
1945                 .ops = &clk_regmap_gate_ops,
1946                 .parent_names = (const char *[]){ "vclk2_div" },
1947                 .num_parents = 1,
1948                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1949         },
1950 };
1951
1952 static struct clk_regmap g12a_vclk_div1 = {
1953         .data = &(struct clk_regmap_gate_data){
1954                 .offset = HHI_VID_CLK_CNTL,
1955                 .bit_idx = 0,
1956         },
1957         .hw.init = &(struct clk_init_data) {
1958                 .name = "vclk_div1",
1959                 .ops = &clk_regmap_gate_ops,
1960                 .parent_names = (const char *[]){ "vclk" },
1961                 .num_parents = 1,
1962                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1963         },
1964 };
1965
1966 static struct clk_regmap g12a_vclk_div2_en = {
1967         .data = &(struct clk_regmap_gate_data){
1968                 .offset = HHI_VID_CLK_CNTL,
1969                 .bit_idx = 1,
1970         },
1971         .hw.init = &(struct clk_init_data) {
1972                 .name = "vclk_div2_en",
1973                 .ops = &clk_regmap_gate_ops,
1974                 .parent_names = (const char *[]){ "vclk" },
1975                 .num_parents = 1,
1976                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1977         },
1978 };
1979
1980 static struct clk_regmap g12a_vclk_div4_en = {
1981         .data = &(struct clk_regmap_gate_data){
1982                 .offset = HHI_VID_CLK_CNTL,
1983                 .bit_idx = 2,
1984         },
1985         .hw.init = &(struct clk_init_data) {
1986                 .name = "vclk_div4_en",
1987                 .ops = &clk_regmap_gate_ops,
1988                 .parent_names = (const char *[]){ "vclk" },
1989                 .num_parents = 1,
1990                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1991         },
1992 };
1993
1994 static struct clk_regmap g12a_vclk_div6_en = {
1995         .data = &(struct clk_regmap_gate_data){
1996                 .offset = HHI_VID_CLK_CNTL,
1997                 .bit_idx = 3,
1998         },
1999         .hw.init = &(struct clk_init_data) {
2000                 .name = "vclk_div6_en",
2001                 .ops = &clk_regmap_gate_ops,
2002                 .parent_names = (const char *[]){ "vclk" },
2003                 .num_parents = 1,
2004                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2005         },
2006 };
2007
2008 static struct clk_regmap g12a_vclk_div12_en = {
2009         .data = &(struct clk_regmap_gate_data){
2010                 .offset = HHI_VID_CLK_CNTL,
2011                 .bit_idx = 4,
2012         },
2013         .hw.init = &(struct clk_init_data) {
2014                 .name = "vclk_div12_en",
2015                 .ops = &clk_regmap_gate_ops,
2016                 .parent_names = (const char *[]){ "vclk" },
2017                 .num_parents = 1,
2018                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2019         },
2020 };
2021
2022 static struct clk_regmap g12a_vclk2_div1 = {
2023         .data = &(struct clk_regmap_gate_data){
2024                 .offset = HHI_VIID_CLK_CNTL,
2025                 .bit_idx = 0,
2026         },
2027         .hw.init = &(struct clk_init_data) {
2028                 .name = "vclk2_div1",
2029                 .ops = &clk_regmap_gate_ops,
2030                 .parent_names = (const char *[]){ "vclk2" },
2031                 .num_parents = 1,
2032                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2033         },
2034 };
2035
2036 static struct clk_regmap g12a_vclk2_div2_en = {
2037         .data = &(struct clk_regmap_gate_data){
2038                 .offset = HHI_VIID_CLK_CNTL,
2039                 .bit_idx = 1,
2040         },
2041         .hw.init = &(struct clk_init_data) {
2042                 .name = "vclk2_div2_en",
2043                 .ops = &clk_regmap_gate_ops,
2044                 .parent_names = (const char *[]){ "vclk2" },
2045                 .num_parents = 1,
2046                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2047         },
2048 };
2049
2050 static struct clk_regmap g12a_vclk2_div4_en = {
2051         .data = &(struct clk_regmap_gate_data){
2052                 .offset = HHI_VIID_CLK_CNTL,
2053                 .bit_idx = 2,
2054         },
2055         .hw.init = &(struct clk_init_data) {
2056                 .name = "vclk2_div4_en",
2057                 .ops = &clk_regmap_gate_ops,
2058                 .parent_names = (const char *[]){ "vclk2" },
2059                 .num_parents = 1,
2060                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2061         },
2062 };
2063
2064 static struct clk_regmap g12a_vclk2_div6_en = {
2065         .data = &(struct clk_regmap_gate_data){
2066                 .offset = HHI_VIID_CLK_CNTL,
2067                 .bit_idx = 3,
2068         },
2069         .hw.init = &(struct clk_init_data) {
2070                 .name = "vclk2_div6_en",
2071                 .ops = &clk_regmap_gate_ops,
2072                 .parent_names = (const char *[]){ "vclk2" },
2073                 .num_parents = 1,
2074                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2075         },
2076 };
2077
2078 static struct clk_regmap g12a_vclk2_div12_en = {
2079         .data = &(struct clk_regmap_gate_data){
2080                 .offset = HHI_VIID_CLK_CNTL,
2081                 .bit_idx = 4,
2082         },
2083         .hw.init = &(struct clk_init_data) {
2084                 .name = "vclk2_div12_en",
2085                 .ops = &clk_regmap_gate_ops,
2086                 .parent_names = (const char *[]){ "vclk2" },
2087                 .num_parents = 1,
2088                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2089         },
2090 };
2091
2092 static struct clk_fixed_factor g12a_vclk_div2 = {
2093         .mult = 1,
2094         .div = 2,
2095         .hw.init = &(struct clk_init_data){
2096                 .name = "vclk_div2",
2097                 .ops = &clk_fixed_factor_ops,
2098                 .parent_names = (const char *[]){ "vclk_div2_en" },
2099                 .num_parents = 1,
2100         },
2101 };
2102
2103 static struct clk_fixed_factor g12a_vclk_div4 = {
2104         .mult = 1,
2105         .div = 4,
2106         .hw.init = &(struct clk_init_data){
2107                 .name = "vclk_div4",
2108                 .ops = &clk_fixed_factor_ops,
2109                 .parent_names = (const char *[]){ "vclk_div4_en" },
2110                 .num_parents = 1,
2111         },
2112 };
2113
2114 static struct clk_fixed_factor g12a_vclk_div6 = {
2115         .mult = 1,
2116         .div = 6,
2117         .hw.init = &(struct clk_init_data){
2118                 .name = "vclk_div6",
2119                 .ops = &clk_fixed_factor_ops,
2120                 .parent_names = (const char *[]){ "vclk_div6_en" },
2121                 .num_parents = 1,
2122         },
2123 };
2124
2125 static struct clk_fixed_factor g12a_vclk_div12 = {
2126         .mult = 1,
2127         .div = 12,
2128         .hw.init = &(struct clk_init_data){
2129                 .name = "vclk_div12",
2130                 .ops = &clk_fixed_factor_ops,
2131                 .parent_names = (const char *[]){ "vclk_div12_en" },
2132                 .num_parents = 1,
2133         },
2134 };
2135
2136 static struct clk_fixed_factor g12a_vclk2_div2 = {
2137         .mult = 1,
2138         .div = 2,
2139         .hw.init = &(struct clk_init_data){
2140                 .name = "vclk2_div2",
2141                 .ops = &clk_fixed_factor_ops,
2142                 .parent_names = (const char *[]){ "vclk2_div2_en" },
2143                 .num_parents = 1,
2144         },
2145 };
2146
2147 static struct clk_fixed_factor g12a_vclk2_div4 = {
2148         .mult = 1,
2149         .div = 4,
2150         .hw.init = &(struct clk_init_data){
2151                 .name = "vclk2_div4",
2152                 .ops = &clk_fixed_factor_ops,
2153                 .parent_names = (const char *[]){ "vclk2_div4_en" },
2154                 .num_parents = 1,
2155         },
2156 };
2157
2158 static struct clk_fixed_factor g12a_vclk2_div6 = {
2159         .mult = 1,
2160         .div = 6,
2161         .hw.init = &(struct clk_init_data){
2162                 .name = "vclk2_div6",
2163                 .ops = &clk_fixed_factor_ops,
2164                 .parent_names = (const char *[]){ "vclk2_div6_en" },
2165                 .num_parents = 1,
2166         },
2167 };
2168
2169 static struct clk_fixed_factor g12a_vclk2_div12 = {
2170         .mult = 1,
2171         .div = 12,
2172         .hw.init = &(struct clk_init_data){
2173                 .name = "vclk2_div12",
2174                 .ops = &clk_fixed_factor_ops,
2175                 .parent_names = (const char *[]){ "vclk2_div12_en" },
2176                 .num_parents = 1,
2177         },
2178 };
2179
2180 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2181 static const char * const g12a_cts_parent_names[] = {
2182         "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
2183         "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
2184         "vclk2_div6", "vclk2_div12"
2185 };
2186
2187 static struct clk_regmap g12a_cts_enci_sel = {
2188         .data = &(struct clk_regmap_mux_data){
2189                 .offset = HHI_VID_CLK_DIV,
2190                 .mask = 0xf,
2191                 .shift = 28,
2192                 .table = mux_table_cts_sel,
2193         },
2194         .hw.init = &(struct clk_init_data){
2195                 .name = "cts_enci_sel",
2196                 .ops = &clk_regmap_mux_ops,
2197                 .parent_names = g12a_cts_parent_names,
2198                 .num_parents = ARRAY_SIZE(g12a_cts_parent_names),
2199                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2200         },
2201 };
2202
2203 static struct clk_regmap g12a_cts_encp_sel = {
2204         .data = &(struct clk_regmap_mux_data){
2205                 .offset = HHI_VID_CLK_DIV,
2206                 .mask = 0xf,
2207                 .shift = 20,
2208                 .table = mux_table_cts_sel,
2209         },
2210         .hw.init = &(struct clk_init_data){
2211                 .name = "cts_encp_sel",
2212                 .ops = &clk_regmap_mux_ops,
2213                 .parent_names = g12a_cts_parent_names,
2214                 .num_parents = ARRAY_SIZE(g12a_cts_parent_names),
2215                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2216         },
2217 };
2218
2219 static struct clk_regmap g12a_cts_vdac_sel = {
2220         .data = &(struct clk_regmap_mux_data){
2221                 .offset = HHI_VIID_CLK_DIV,
2222                 .mask = 0xf,
2223                 .shift = 28,
2224                 .table = mux_table_cts_sel,
2225         },
2226         .hw.init = &(struct clk_init_data){
2227                 .name = "cts_vdac_sel",
2228                 .ops = &clk_regmap_mux_ops,
2229                 .parent_names = g12a_cts_parent_names,
2230                 .num_parents = ARRAY_SIZE(g12a_cts_parent_names),
2231                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2232         },
2233 };
2234
2235 /* TOFIX: add support for cts_tcon */
2236 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2237 static const char * const g12a_cts_hdmi_tx_parent_names[] = {
2238         "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
2239         "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
2240         "vclk2_div6", "vclk2_div12"
2241 };
2242
2243 static struct clk_regmap g12a_hdmi_tx_sel = {
2244         .data = &(struct clk_regmap_mux_data){
2245                 .offset = HHI_HDMI_CLK_CNTL,
2246                 .mask = 0xf,
2247                 .shift = 16,
2248                 .table = mux_table_hdmi_tx_sel,
2249         },
2250         .hw.init = &(struct clk_init_data){
2251                 .name = "hdmi_tx_sel",
2252                 .ops = &clk_regmap_mux_ops,
2253                 .parent_names = g12a_cts_hdmi_tx_parent_names,
2254                 .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_names),
2255                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2256         },
2257 };
2258
2259 static struct clk_regmap g12a_cts_enci = {
2260         .data = &(struct clk_regmap_gate_data){
2261                 .offset = HHI_VID_CLK_CNTL2,
2262                 .bit_idx = 0,
2263         },
2264         .hw.init = &(struct clk_init_data) {
2265                 .name = "cts_enci",
2266                 .ops = &clk_regmap_gate_ops,
2267                 .parent_names = (const char *[]){ "cts_enci_sel" },
2268                 .num_parents = 1,
2269                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2270         },
2271 };
2272
2273 static struct clk_regmap g12a_cts_encp = {
2274         .data = &(struct clk_regmap_gate_data){
2275                 .offset = HHI_VID_CLK_CNTL2,
2276                 .bit_idx = 2,
2277         },
2278         .hw.init = &(struct clk_init_data) {
2279                 .name = "cts_encp",
2280                 .ops = &clk_regmap_gate_ops,
2281                 .parent_names = (const char *[]){ "cts_encp_sel" },
2282                 .num_parents = 1,
2283                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2284         },
2285 };
2286
2287 static struct clk_regmap g12a_cts_vdac = {
2288         .data = &(struct clk_regmap_gate_data){
2289                 .offset = HHI_VID_CLK_CNTL2,
2290                 .bit_idx = 4,
2291         },
2292         .hw.init = &(struct clk_init_data) {
2293                 .name = "cts_vdac",
2294                 .ops = &clk_regmap_gate_ops,
2295                 .parent_names = (const char *[]){ "cts_vdac_sel" },
2296                 .num_parents = 1,
2297                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2298         },
2299 };
2300
2301 static struct clk_regmap g12a_hdmi_tx = {
2302         .data = &(struct clk_regmap_gate_data){
2303                 .offset = HHI_VID_CLK_CNTL2,
2304                 .bit_idx = 5,
2305         },
2306         .hw.init = &(struct clk_init_data) {
2307                 .name = "hdmi_tx",
2308                 .ops = &clk_regmap_gate_ops,
2309                 .parent_names = (const char *[]){ "hdmi_tx_sel" },
2310                 .num_parents = 1,
2311                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2312         },
2313 };
2314
2315 /* HDMI Clocks */
2316
2317 static const char * const g12a_hdmi_parent_names[] = {
2318         IN_PREFIX "xtal", "fclk_div4", "fclk_div3", "fclk_div5"
2319 };
2320
2321 static struct clk_regmap g12a_hdmi_sel = {
2322         .data = &(struct clk_regmap_mux_data){
2323                 .offset = HHI_HDMI_CLK_CNTL,
2324                 .mask = 0x3,
2325                 .shift = 9,
2326                 .flags = CLK_MUX_ROUND_CLOSEST,
2327         },
2328         .hw.init = &(struct clk_init_data){
2329                 .name = "hdmi_sel",
2330                 .ops = &clk_regmap_mux_ops,
2331                 .parent_names = g12a_hdmi_parent_names,
2332                 .num_parents = ARRAY_SIZE(g12a_hdmi_parent_names),
2333                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2334         },
2335 };
2336
2337 static struct clk_regmap g12a_hdmi_div = {
2338         .data = &(struct clk_regmap_div_data){
2339                 .offset = HHI_HDMI_CLK_CNTL,
2340                 .shift = 0,
2341                 .width = 7,
2342         },
2343         .hw.init = &(struct clk_init_data){
2344                 .name = "hdmi_div",
2345                 .ops = &clk_regmap_divider_ops,
2346                 .parent_names = (const char *[]){ "hdmi_sel" },
2347                 .num_parents = 1,
2348                 .flags = CLK_GET_RATE_NOCACHE,
2349         },
2350 };
2351
2352 static struct clk_regmap g12a_hdmi = {
2353         .data = &(struct clk_regmap_gate_data){
2354                 .offset = HHI_HDMI_CLK_CNTL,
2355                 .bit_idx = 8,
2356         },
2357         .hw.init = &(struct clk_init_data) {
2358                 .name = "hdmi",
2359                 .ops = &clk_regmap_gate_ops,
2360                 .parent_names = (const char *[]){ "hdmi_div" },
2361                 .num_parents = 1,
2362                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2363         },
2364 };
2365
2366 /*
2367  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
2368  * muxed by a glitch-free switch.
2369  */
2370
2371 static const char * const g12a_mali_0_1_parent_names[] = {
2372         IN_PREFIX "xtal", "gp0_pll", "hihi_pll", "fclk_div2p5",
2373         "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7"
2374 };
2375
2376 static struct clk_regmap g12a_mali_0_sel = {
2377         .data = &(struct clk_regmap_mux_data){
2378                 .offset = HHI_MALI_CLK_CNTL,
2379                 .mask = 0x7,
2380                 .shift = 9,
2381         },
2382         .hw.init = &(struct clk_init_data){
2383                 .name = "mali_0_sel",
2384                 .ops = &clk_regmap_mux_ops,
2385                 .parent_names = g12a_mali_0_1_parent_names,
2386                 .num_parents = 8,
2387                 .flags = CLK_SET_RATE_NO_REPARENT,
2388         },
2389 };
2390
2391 static struct clk_regmap g12a_mali_0_div = {
2392         .data = &(struct clk_regmap_div_data){
2393                 .offset = HHI_MALI_CLK_CNTL,
2394                 .shift = 0,
2395                 .width = 7,
2396         },
2397         .hw.init = &(struct clk_init_data){
2398                 .name = "mali_0_div",
2399                 .ops = &clk_regmap_divider_ops,
2400                 .parent_names = (const char *[]){ "mali_0_sel" },
2401                 .num_parents = 1,
2402                 .flags = CLK_SET_RATE_NO_REPARENT,
2403         },
2404 };
2405
2406 static struct clk_regmap g12a_mali_0 = {
2407         .data = &(struct clk_regmap_gate_data){
2408                 .offset = HHI_MALI_CLK_CNTL,
2409                 .bit_idx = 8,
2410         },
2411         .hw.init = &(struct clk_init_data){
2412                 .name = "mali_0",
2413                 .ops = &clk_regmap_gate_ops,
2414                 .parent_names = (const char *[]){ "mali_0_div" },
2415                 .num_parents = 1,
2416                 .flags = CLK_SET_RATE_PARENT,
2417         },
2418 };
2419
2420 static struct clk_regmap g12a_mali_1_sel = {
2421         .data = &(struct clk_regmap_mux_data){
2422                 .offset = HHI_MALI_CLK_CNTL,
2423                 .mask = 0x7,
2424                 .shift = 25,
2425         },
2426         .hw.init = &(struct clk_init_data){
2427                 .name = "mali_1_sel",
2428                 .ops = &clk_regmap_mux_ops,
2429                 .parent_names = g12a_mali_0_1_parent_names,
2430                 .num_parents = 8,
2431                 .flags = CLK_SET_RATE_NO_REPARENT,
2432         },
2433 };
2434
2435 static struct clk_regmap g12a_mali_1_div = {
2436         .data = &(struct clk_regmap_div_data){
2437                 .offset = HHI_MALI_CLK_CNTL,
2438                 .shift = 16,
2439                 .width = 7,
2440         },
2441         .hw.init = &(struct clk_init_data){
2442                 .name = "mali_1_div",
2443                 .ops = &clk_regmap_divider_ops,
2444                 .parent_names = (const char *[]){ "mali_1_sel" },
2445                 .num_parents = 1,
2446                 .flags = CLK_SET_RATE_NO_REPARENT,
2447         },
2448 };
2449
2450 static struct clk_regmap g12a_mali_1 = {
2451         .data = &(struct clk_regmap_gate_data){
2452                 .offset = HHI_MALI_CLK_CNTL,
2453                 .bit_idx = 24,
2454         },
2455         .hw.init = &(struct clk_init_data){
2456                 .name = "mali_1",
2457                 .ops = &clk_regmap_gate_ops,
2458                 .parent_names = (const char *[]){ "mali_1_div" },
2459                 .num_parents = 1,
2460                 .flags = CLK_SET_RATE_PARENT,
2461         },
2462 };
2463
2464 static const char * const g12a_mali_parent_names[] = {
2465         "mali_0", "mali_1"
2466 };
2467
2468 static struct clk_regmap g12a_mali = {
2469         .data = &(struct clk_regmap_mux_data){
2470                 .offset = HHI_MALI_CLK_CNTL,
2471                 .mask = 1,
2472                 .shift = 31,
2473         },
2474         .hw.init = &(struct clk_init_data){
2475                 .name = "mali",
2476                 .ops = &clk_regmap_mux_ops,
2477                 .parent_names = g12a_mali_parent_names,
2478                 .num_parents = 2,
2479                 .flags = CLK_SET_RATE_NO_REPARENT,
2480         },
2481 };
2482
2483 /* Everything Else (EE) domain gates */
2484 static MESON_GATE(g12a_ddr,                     HHI_GCLK_MPEG0, 0);
2485 static MESON_GATE(g12a_dos,                     HHI_GCLK_MPEG0, 1);
2486 static MESON_GATE(g12a_audio_locker,            HHI_GCLK_MPEG0, 2);
2487 static MESON_GATE(g12a_mipi_dsi_host,           HHI_GCLK_MPEG0, 3);
2488 static MESON_GATE(g12a_eth_phy,                 HHI_GCLK_MPEG0, 4);
2489 static MESON_GATE(g12a_isa,                     HHI_GCLK_MPEG0, 5);
2490 static MESON_GATE(g12a_pl301,                   HHI_GCLK_MPEG0, 6);
2491 static MESON_GATE(g12a_periphs,                 HHI_GCLK_MPEG0, 7);
2492 static MESON_GATE(g12a_spicc_0,                 HHI_GCLK_MPEG0, 8);
2493 static MESON_GATE(g12a_i2c,                     HHI_GCLK_MPEG0, 9);
2494 static MESON_GATE(g12a_sana,                    HHI_GCLK_MPEG0, 10);
2495 static MESON_GATE(g12a_sd,                      HHI_GCLK_MPEG0, 11);
2496 static MESON_GATE(g12a_rng0,                    HHI_GCLK_MPEG0, 12);
2497 static MESON_GATE(g12a_uart0,                   HHI_GCLK_MPEG0, 13);
2498 static MESON_GATE(g12a_spicc_1,                 HHI_GCLK_MPEG0, 14);
2499 static MESON_GATE(g12a_hiu_reg,                 HHI_GCLK_MPEG0, 19);
2500 static MESON_GATE(g12a_mipi_dsi_phy,            HHI_GCLK_MPEG0, 20);
2501 static MESON_GATE(g12a_assist_misc,             HHI_GCLK_MPEG0, 23);
2502 static MESON_GATE(g12a_emmc_a,                  HHI_GCLK_MPEG0, 4);
2503 static MESON_GATE(g12a_emmc_b,                  HHI_GCLK_MPEG0, 25);
2504 static MESON_GATE(g12a_emmc_c,                  HHI_GCLK_MPEG0, 26);
2505 static MESON_GATE(g12a_audio_codec,             HHI_GCLK_MPEG0, 28);
2506
2507 static MESON_GATE(g12a_audio,                   HHI_GCLK_MPEG1, 0);
2508 static MESON_GATE(g12a_eth_core,                HHI_GCLK_MPEG1, 3);
2509 static MESON_GATE(g12a_demux,                   HHI_GCLK_MPEG1, 4);
2510 static MESON_GATE(g12a_audio_ififo,             HHI_GCLK_MPEG1, 11);
2511 static MESON_GATE(g12a_adc,                     HHI_GCLK_MPEG1, 13);
2512 static MESON_GATE(g12a_uart1,                   HHI_GCLK_MPEG1, 16);
2513 static MESON_GATE(g12a_g2d,                     HHI_GCLK_MPEG1, 20);
2514 static MESON_GATE(g12a_reset,                   HHI_GCLK_MPEG1, 23);
2515 static MESON_GATE(g12a_pcie_comb,               HHI_GCLK_MPEG1, 24);
2516 static MESON_GATE(g12a_parser,                  HHI_GCLK_MPEG1, 25);
2517 static MESON_GATE(g12a_usb_general,             HHI_GCLK_MPEG1, 26);
2518 static MESON_GATE(g12a_pcie_phy,                HHI_GCLK_MPEG1, 27);
2519 static MESON_GATE(g12a_ahb_arb0,                HHI_GCLK_MPEG1, 29);
2520
2521 static MESON_GATE(g12a_ahb_data_bus,            HHI_GCLK_MPEG2, 1);
2522 static MESON_GATE(g12a_ahb_ctrl_bus,            HHI_GCLK_MPEG2, 2);
2523 static MESON_GATE(g12a_htx_hdcp22,              HHI_GCLK_MPEG2, 3);
2524 static MESON_GATE(g12a_htx_pclk,                HHI_GCLK_MPEG2, 4);
2525 static MESON_GATE(g12a_bt656,                   HHI_GCLK_MPEG2, 6);
2526 static MESON_GATE(g12a_usb1_to_ddr,             HHI_GCLK_MPEG2, 8);
2527 static MESON_GATE(g12a_mmc_pclk,                HHI_GCLK_MPEG2, 11);
2528 static MESON_GATE(g12a_uart2,                   HHI_GCLK_MPEG2, 15);
2529 static MESON_GATE(g12a_vpu_intr,                HHI_GCLK_MPEG2, 25);
2530 static MESON_GATE(g12a_gic,                     HHI_GCLK_MPEG2, 30);
2531
2532 static MESON_GATE(g12a_vclk2_venci0,            HHI_GCLK_OTHER, 1);
2533 static MESON_GATE(g12a_vclk2_venci1,            HHI_GCLK_OTHER, 2);
2534 static MESON_GATE(g12a_vclk2_vencp0,            HHI_GCLK_OTHER, 3);
2535 static MESON_GATE(g12a_vclk2_vencp1,            HHI_GCLK_OTHER, 4);
2536 static MESON_GATE(g12a_vclk2_venct0,            HHI_GCLK_OTHER, 5);
2537 static MESON_GATE(g12a_vclk2_venct1,            HHI_GCLK_OTHER, 6);
2538 static MESON_GATE(g12a_vclk2_other,             HHI_GCLK_OTHER, 7);
2539 static MESON_GATE(g12a_vclk2_enci,              HHI_GCLK_OTHER, 8);
2540 static MESON_GATE(g12a_vclk2_encp,              HHI_GCLK_OTHER, 9);
2541 static MESON_GATE(g12a_dac_clk,                 HHI_GCLK_OTHER, 10);
2542 static MESON_GATE(g12a_aoclk_gate,              HHI_GCLK_OTHER, 14);
2543 static MESON_GATE(g12a_iec958_gate,             HHI_GCLK_OTHER, 16);
2544 static MESON_GATE(g12a_enc480p,                 HHI_GCLK_OTHER, 20);
2545 static MESON_GATE(g12a_rng1,                    HHI_GCLK_OTHER, 21);
2546 static MESON_GATE(g12a_vclk2_enct,              HHI_GCLK_OTHER, 22);
2547 static MESON_GATE(g12a_vclk2_encl,              HHI_GCLK_OTHER, 23);
2548 static MESON_GATE(g12a_vclk2_venclmmc,          HHI_GCLK_OTHER, 24);
2549 static MESON_GATE(g12a_vclk2_vencl,             HHI_GCLK_OTHER, 25);
2550 static MESON_GATE(g12a_vclk2_other1,            HHI_GCLK_OTHER, 26);
2551
2552 static MESON_GATE_RO(g12a_dma,                  HHI_GCLK_OTHER2, 0);
2553 static MESON_GATE_RO(g12a_efuse,                HHI_GCLK_OTHER2, 1);
2554 static MESON_GATE_RO(g12a_rom_boot,             HHI_GCLK_OTHER2, 2);
2555 static MESON_GATE_RO(g12a_reset_sec,            HHI_GCLK_OTHER2, 3);
2556 static MESON_GATE_RO(g12a_sec_ahb_apb3,         HHI_GCLK_OTHER2, 4);
2557
2558 /* Array of all clocks provided by this provider */
2559 static struct clk_hw_onecell_data g12a_hw_onecell_data = {
2560         .hws = {
2561                 [CLKID_SYS_PLL]                 = &g12a_sys_pll.hw,
2562                 [CLKID_FIXED_PLL]               = &g12a_fixed_pll.hw,
2563                 [CLKID_FCLK_DIV2]               = &g12a_fclk_div2.hw,
2564                 [CLKID_FCLK_DIV3]               = &g12a_fclk_div3.hw,
2565                 [CLKID_FCLK_DIV4]               = &g12a_fclk_div4.hw,
2566                 [CLKID_FCLK_DIV5]               = &g12a_fclk_div5.hw,
2567                 [CLKID_FCLK_DIV7]               = &g12a_fclk_div7.hw,
2568                 [CLKID_FCLK_DIV2P5]             = &g12a_fclk_div2p5.hw,
2569                 [CLKID_GP0_PLL]                 = &g12a_gp0_pll.hw,
2570                 [CLKID_MPEG_SEL]                = &g12a_mpeg_clk_sel.hw,
2571                 [CLKID_MPEG_DIV]                = &g12a_mpeg_clk_div.hw,
2572                 [CLKID_CLK81]                   = &g12a_clk81.hw,
2573                 [CLKID_MPLL0]                   = &g12a_mpll0.hw,
2574                 [CLKID_MPLL1]                   = &g12a_mpll1.hw,
2575                 [CLKID_MPLL2]                   = &g12a_mpll2.hw,
2576                 [CLKID_MPLL3]                   = &g12a_mpll3.hw,
2577                 [CLKID_DDR]                     = &g12a_ddr.hw,
2578                 [CLKID_DOS]                     = &g12a_dos.hw,
2579                 [CLKID_AUDIO_LOCKER]            = &g12a_audio_locker.hw,
2580                 [CLKID_MIPI_DSI_HOST]           = &g12a_mipi_dsi_host.hw,
2581                 [CLKID_ETH_PHY]                 = &g12a_eth_phy.hw,
2582                 [CLKID_ISA]                     = &g12a_isa.hw,
2583                 [CLKID_PL301]                   = &g12a_pl301.hw,
2584                 [CLKID_PERIPHS]                 = &g12a_periphs.hw,
2585                 [CLKID_SPICC0]                  = &g12a_spicc_0.hw,
2586                 [CLKID_I2C]                     = &g12a_i2c.hw,
2587                 [CLKID_SANA]                    = &g12a_sana.hw,
2588                 [CLKID_SD]                      = &g12a_sd.hw,
2589                 [CLKID_RNG0]                    = &g12a_rng0.hw,
2590                 [CLKID_UART0]                   = &g12a_uart0.hw,
2591                 [CLKID_SPICC1]                  = &g12a_spicc_1.hw,
2592                 [CLKID_HIU_IFACE]               = &g12a_hiu_reg.hw,
2593                 [CLKID_MIPI_DSI_PHY]            = &g12a_mipi_dsi_phy.hw,
2594                 [CLKID_ASSIST_MISC]             = &g12a_assist_misc.hw,
2595                 [CLKID_SD_EMMC_A]               = &g12a_emmc_a.hw,
2596                 [CLKID_SD_EMMC_B]               = &g12a_emmc_b.hw,
2597                 [CLKID_SD_EMMC_C]               = &g12a_emmc_c.hw,
2598                 [CLKID_AUDIO_CODEC]             = &g12a_audio_codec.hw,
2599                 [CLKID_AUDIO]                   = &g12a_audio.hw,
2600                 [CLKID_ETH]                     = &g12a_eth_core.hw,
2601                 [CLKID_DEMUX]                   = &g12a_demux.hw,
2602                 [CLKID_AUDIO_IFIFO]             = &g12a_audio_ififo.hw,
2603                 [CLKID_ADC]                     = &g12a_adc.hw,
2604                 [CLKID_UART1]                   = &g12a_uart1.hw,
2605                 [CLKID_G2D]                     = &g12a_g2d.hw,
2606                 [CLKID_RESET]                   = &g12a_reset.hw,
2607                 [CLKID_PCIE_COMB]               = &g12a_pcie_comb.hw,
2608                 [CLKID_PARSER]                  = &g12a_parser.hw,
2609                 [CLKID_USB]                     = &g12a_usb_general.hw,
2610                 [CLKID_PCIE_PHY]                = &g12a_pcie_phy.hw,
2611                 [CLKID_AHB_ARB0]                = &g12a_ahb_arb0.hw,
2612                 [CLKID_AHB_DATA_BUS]            = &g12a_ahb_data_bus.hw,
2613                 [CLKID_AHB_CTRL_BUS]            = &g12a_ahb_ctrl_bus.hw,
2614                 [CLKID_HTX_HDCP22]              = &g12a_htx_hdcp22.hw,
2615                 [CLKID_HTX_PCLK]                = &g12a_htx_pclk.hw,
2616                 [CLKID_BT656]                   = &g12a_bt656.hw,
2617                 [CLKID_USB1_DDR_BRIDGE]         = &g12a_usb1_to_ddr.hw,
2618                 [CLKID_MMC_PCLK]                = &g12a_mmc_pclk.hw,
2619                 [CLKID_UART2]                   = &g12a_uart2.hw,
2620                 [CLKID_VPU_INTR]                = &g12a_vpu_intr.hw,
2621                 [CLKID_GIC]                     = &g12a_gic.hw,
2622                 [CLKID_SD_EMMC_A_CLK0_SEL]      = &g12a_sd_emmc_a_clk0_sel.hw,
2623                 [CLKID_SD_EMMC_A_CLK0_DIV]      = &g12a_sd_emmc_a_clk0_div.hw,
2624                 [CLKID_SD_EMMC_A_CLK0]          = &g12a_sd_emmc_a_clk0.hw,
2625                 [CLKID_SD_EMMC_B_CLK0_SEL]      = &g12a_sd_emmc_b_clk0_sel.hw,
2626                 [CLKID_SD_EMMC_B_CLK0_DIV]      = &g12a_sd_emmc_b_clk0_div.hw,
2627                 [CLKID_SD_EMMC_B_CLK0]          = &g12a_sd_emmc_b_clk0.hw,
2628                 [CLKID_SD_EMMC_C_CLK0_SEL]      = &g12a_sd_emmc_c_clk0_sel.hw,
2629                 [CLKID_SD_EMMC_C_CLK0_DIV]      = &g12a_sd_emmc_c_clk0_div.hw,
2630                 [CLKID_SD_EMMC_C_CLK0]          = &g12a_sd_emmc_c_clk0.hw,
2631                 [CLKID_MPLL0_DIV]               = &g12a_mpll0_div.hw,
2632                 [CLKID_MPLL1_DIV]               = &g12a_mpll1_div.hw,
2633                 [CLKID_MPLL2_DIV]               = &g12a_mpll2_div.hw,
2634                 [CLKID_MPLL3_DIV]               = &g12a_mpll3_div.hw,
2635                 [CLKID_FCLK_DIV2_DIV]           = &g12a_fclk_div2_div.hw,
2636                 [CLKID_FCLK_DIV3_DIV]           = &g12a_fclk_div3_div.hw,
2637                 [CLKID_FCLK_DIV4_DIV]           = &g12a_fclk_div4_div.hw,
2638                 [CLKID_FCLK_DIV5_DIV]           = &g12a_fclk_div5_div.hw,
2639                 [CLKID_FCLK_DIV7_DIV]           = &g12a_fclk_div7_div.hw,
2640                 [CLKID_FCLK_DIV2P5_DIV]         = &g12a_fclk_div2p5_div.hw,
2641                 [CLKID_HIFI_PLL]                = &g12a_hifi_pll.hw,
2642                 [CLKID_VCLK2_VENCI0]            = &g12a_vclk2_venci0.hw,
2643                 [CLKID_VCLK2_VENCI1]            = &g12a_vclk2_venci1.hw,
2644                 [CLKID_VCLK2_VENCP0]            = &g12a_vclk2_vencp0.hw,
2645                 [CLKID_VCLK2_VENCP1]            = &g12a_vclk2_vencp1.hw,
2646                 [CLKID_VCLK2_VENCT0]            = &g12a_vclk2_venct0.hw,
2647                 [CLKID_VCLK2_VENCT1]            = &g12a_vclk2_venct1.hw,
2648                 [CLKID_VCLK2_OTHER]             = &g12a_vclk2_other.hw,
2649                 [CLKID_VCLK2_ENCI]              = &g12a_vclk2_enci.hw,
2650                 [CLKID_VCLK2_ENCP]              = &g12a_vclk2_encp.hw,
2651                 [CLKID_DAC_CLK]                 = &g12a_dac_clk.hw,
2652                 [CLKID_AOCLK]                   = &g12a_aoclk_gate.hw,
2653                 [CLKID_IEC958]                  = &g12a_iec958_gate.hw,
2654                 [CLKID_ENC480P]                 = &g12a_enc480p.hw,
2655                 [CLKID_RNG1]                    = &g12a_rng1.hw,
2656                 [CLKID_VCLK2_ENCT]              = &g12a_vclk2_enct.hw,
2657                 [CLKID_VCLK2_ENCL]              = &g12a_vclk2_encl.hw,
2658                 [CLKID_VCLK2_VENCLMMC]          = &g12a_vclk2_venclmmc.hw,
2659                 [CLKID_VCLK2_VENCL]             = &g12a_vclk2_vencl.hw,
2660                 [CLKID_VCLK2_OTHER1]            = &g12a_vclk2_other1.hw,
2661                 [CLKID_FIXED_PLL_DCO]           = &g12a_fixed_pll_dco.hw,
2662                 [CLKID_SYS_PLL_DCO]             = &g12a_sys_pll_dco.hw,
2663                 [CLKID_GP0_PLL_DCO]             = &g12a_gp0_pll_dco.hw,
2664                 [CLKID_HIFI_PLL_DCO]            = &g12a_hifi_pll_dco.hw,
2665                 [CLKID_DMA]                     = &g12a_dma.hw,
2666                 [CLKID_EFUSE]                   = &g12a_efuse.hw,
2667                 [CLKID_ROM_BOOT]                = &g12a_rom_boot.hw,
2668                 [CLKID_RESET_SEC]               = &g12a_reset_sec.hw,
2669                 [CLKID_SEC_AHB_APB3]            = &g12a_sec_ahb_apb3.hw,
2670                 [CLKID_MPLL_PREDIV]             = &g12a_mpll_prediv.hw,
2671                 [CLKID_VPU_0_SEL]               = &g12a_vpu_0_sel.hw,
2672                 [CLKID_VPU_0_DIV]               = &g12a_vpu_0_div.hw,
2673                 [CLKID_VPU_0]                   = &g12a_vpu_0.hw,
2674                 [CLKID_VPU_1_SEL]               = &g12a_vpu_1_sel.hw,
2675                 [CLKID_VPU_1_DIV]               = &g12a_vpu_1_div.hw,
2676                 [CLKID_VPU_1]                   = &g12a_vpu_1.hw,
2677                 [CLKID_VPU]                     = &g12a_vpu.hw,
2678                 [CLKID_VAPB_0_SEL]              = &g12a_vapb_0_sel.hw,
2679                 [CLKID_VAPB_0_DIV]              = &g12a_vapb_0_div.hw,
2680                 [CLKID_VAPB_0]                  = &g12a_vapb_0.hw,
2681                 [CLKID_VAPB_1_SEL]              = &g12a_vapb_1_sel.hw,
2682                 [CLKID_VAPB_1_DIV]              = &g12a_vapb_1_div.hw,
2683                 [CLKID_VAPB_1]                  = &g12a_vapb_1.hw,
2684                 [CLKID_VAPB_SEL]                = &g12a_vapb_sel.hw,
2685                 [CLKID_VAPB]                    = &g12a_vapb.hw,
2686                 [CLKID_HDMI_PLL_DCO]            = &g12a_hdmi_pll_dco.hw,
2687                 [CLKID_HDMI_PLL_OD]             = &g12a_hdmi_pll_od.hw,
2688                 [CLKID_HDMI_PLL_OD2]            = &g12a_hdmi_pll_od2.hw,
2689                 [CLKID_HDMI_PLL]                = &g12a_hdmi_pll.hw,
2690                 [CLKID_VID_PLL]                 = &g12a_vid_pll_div.hw,
2691                 [CLKID_VID_PLL_SEL]             = &g12a_vid_pll_sel.hw,
2692                 [CLKID_VID_PLL_DIV]             = &g12a_vid_pll.hw,
2693                 [CLKID_VCLK_SEL]                = &g12a_vclk_sel.hw,
2694                 [CLKID_VCLK2_SEL]               = &g12a_vclk2_sel.hw,
2695                 [CLKID_VCLK_INPUT]              = &g12a_vclk_input.hw,
2696                 [CLKID_VCLK2_INPUT]             = &g12a_vclk2_input.hw,
2697                 [CLKID_VCLK_DIV]                = &g12a_vclk_div.hw,
2698                 [CLKID_VCLK2_DIV]               = &g12a_vclk2_div.hw,
2699                 [CLKID_VCLK]                    = &g12a_vclk.hw,
2700                 [CLKID_VCLK2]                   = &g12a_vclk2.hw,
2701                 [CLKID_VCLK_DIV1]               = &g12a_vclk_div1.hw,
2702                 [CLKID_VCLK_DIV2_EN]            = &g12a_vclk_div2_en.hw,
2703                 [CLKID_VCLK_DIV4_EN]            = &g12a_vclk_div4_en.hw,
2704                 [CLKID_VCLK_DIV6_EN]            = &g12a_vclk_div6_en.hw,
2705                 [CLKID_VCLK_DIV12_EN]           = &g12a_vclk_div12_en.hw,
2706                 [CLKID_VCLK2_DIV1]              = &g12a_vclk2_div1.hw,
2707                 [CLKID_VCLK2_DIV2_EN]           = &g12a_vclk2_div2_en.hw,
2708                 [CLKID_VCLK2_DIV4_EN]           = &g12a_vclk2_div4_en.hw,
2709                 [CLKID_VCLK2_DIV6_EN]           = &g12a_vclk2_div6_en.hw,
2710                 [CLKID_VCLK2_DIV12_EN]          = &g12a_vclk2_div12_en.hw,
2711                 [CLKID_VCLK_DIV2]               = &g12a_vclk_div2.hw,
2712                 [CLKID_VCLK_DIV4]               = &g12a_vclk_div4.hw,
2713                 [CLKID_VCLK_DIV6]               = &g12a_vclk_div6.hw,
2714                 [CLKID_VCLK_DIV12]              = &g12a_vclk_div12.hw,
2715                 [CLKID_VCLK2_DIV2]              = &g12a_vclk2_div2.hw,
2716                 [CLKID_VCLK2_DIV4]              = &g12a_vclk2_div4.hw,
2717                 [CLKID_VCLK2_DIV6]              = &g12a_vclk2_div6.hw,
2718                 [CLKID_VCLK2_DIV12]             = &g12a_vclk2_div12.hw,
2719                 [CLKID_CTS_ENCI_SEL]            = &g12a_cts_enci_sel.hw,
2720                 [CLKID_CTS_ENCP_SEL]            = &g12a_cts_encp_sel.hw,
2721                 [CLKID_CTS_VDAC_SEL]            = &g12a_cts_vdac_sel.hw,
2722                 [CLKID_HDMI_TX_SEL]             = &g12a_hdmi_tx_sel.hw,
2723                 [CLKID_CTS_ENCI]                = &g12a_cts_enci.hw,
2724                 [CLKID_CTS_ENCP]                = &g12a_cts_encp.hw,
2725                 [CLKID_CTS_VDAC]                = &g12a_cts_vdac.hw,
2726                 [CLKID_HDMI_TX]                 = &g12a_hdmi_tx.hw,
2727                 [CLKID_HDMI_SEL]                = &g12a_hdmi_sel.hw,
2728                 [CLKID_HDMI_DIV]                = &g12a_hdmi_div.hw,
2729                 [CLKID_HDMI]                    = &g12a_hdmi.hw,
2730                 [CLKID_MALI_0_SEL]              = &g12a_mali_0_sel.hw,
2731                 [CLKID_MALI_0_DIV]              = &g12a_mali_0_div.hw,
2732                 [CLKID_MALI_0]                  = &g12a_mali_0.hw,
2733                 [CLKID_MALI_1_SEL]              = &g12a_mali_1_sel.hw,
2734                 [CLKID_MALI_1_DIV]              = &g12a_mali_1_div.hw,
2735                 [CLKID_MALI_1]                  = &g12a_mali_1.hw,
2736                 [CLKID_MALI]                    = &g12a_mali.hw,
2737                 [CLKID_MPLL_5OM_DIV]            = &g12a_mpll_50m_div.hw,
2738                 [CLKID_MPLL_5OM]                = &g12a_mpll_50m.hw,
2739                 [CLKID_SYS_PLL_DIV16_EN]        = &g12a_sys_pll_div16_en.hw,
2740                 [CLKID_SYS_PLL_DIV16]           = &g12a_sys_pll_div16.hw,
2741                 [CLKID_CPU_CLK_DYN0_SEL]        = &g12a_cpu_clk_premux0.hw,
2742                 [CLKID_CPU_CLK_DYN0_DIV]        = &g12a_cpu_clk_mux0_div.hw,
2743                 [CLKID_CPU_CLK_DYN0]            = &g12a_cpu_clk_postmux0.hw,
2744                 [CLKID_CPU_CLK_DYN1_SEL]        = &g12a_cpu_clk_premux1.hw,
2745                 [CLKID_CPU_CLK_DYN1_DIV]        = &g12a_cpu_clk_mux1_div.hw,
2746                 [CLKID_CPU_CLK_DYN1]            = &g12a_cpu_clk_postmux1.hw,
2747                 [CLKID_CPU_CLK_DYN]             = &g12a_cpu_clk_dyn.hw,
2748                 [CLKID_CPU_CLK]                 = &g12a_cpu_clk.hw,
2749                 [CLKID_CPU_CLK_DIV16_EN]        = &g12a_cpu_clk_div16_en.hw,
2750                 [CLKID_CPU_CLK_DIV16]           = &g12a_cpu_clk_div16.hw,
2751                 [CLKID_CPU_CLK_APB_DIV]         = &g12a_cpu_clk_apb_div.hw,
2752                 [CLKID_CPU_CLK_APB]             = &g12a_cpu_clk_apb.hw,
2753                 [CLKID_CPU_CLK_ATB_DIV]         = &g12a_cpu_clk_atb_div.hw,
2754                 [CLKID_CPU_CLK_ATB]             = &g12a_cpu_clk_atb.hw,
2755                 [CLKID_CPU_CLK_AXI_DIV]         = &g12a_cpu_clk_axi_div.hw,
2756                 [CLKID_CPU_CLK_AXI]             = &g12a_cpu_clk_axi.hw,
2757                 [CLKID_CPU_CLK_TRACE_DIV]       = &g12a_cpu_clk_trace_div.hw,
2758                 [CLKID_CPU_CLK_TRACE]           = &g12a_cpu_clk_trace.hw,
2759                 [CLKID_PCIE_PLL_DCO]            = &g12a_pcie_pll_dco.hw,
2760                 [CLKID_PCIE_PLL_DCO_DIV2]       = &g12a_pcie_pll_dco_div2.hw,
2761                 [CLKID_PCIE_PLL_OD]             = &g12a_pcie_pll_od.hw,
2762                 [CLKID_PCIE_PLL]                = &g12a_pcie_pll.hw,
2763                 [CLKID_VDEC_1_SEL]              = &g12a_vdec_1_sel.hw,
2764                 [CLKID_VDEC_1_DIV]              = &g12a_vdec_1_div.hw,
2765                 [CLKID_VDEC_1]                  = &g12a_vdec_1.hw,
2766                 [CLKID_VDEC_HEVC_SEL]           = &g12a_vdec_hevc_sel.hw,
2767                 [CLKID_VDEC_HEVC_DIV]           = &g12a_vdec_hevc_div.hw,
2768                 [CLKID_VDEC_HEVC]               = &g12a_vdec_hevc.hw,
2769                 [CLKID_VDEC_HEVCF_SEL]          = &g12a_vdec_hevcf_sel.hw,
2770                 [CLKID_VDEC_HEVCF_DIV]          = &g12a_vdec_hevcf_div.hw,
2771                 [CLKID_VDEC_HEVCF]              = &g12a_vdec_hevcf.hw,
2772                 [NR_CLKS]                       = NULL,
2773         },
2774         .num = NR_CLKS,
2775 };
2776
2777 /* Convenience table to populate regmap in .probe */
2778 static struct clk_regmap *const g12a_clk_regmaps[] = {
2779         &g12a_clk81,
2780         &g12a_dos,
2781         &g12a_ddr,
2782         &g12a_audio_locker,
2783         &g12a_mipi_dsi_host,
2784         &g12a_eth_phy,
2785         &g12a_isa,
2786         &g12a_pl301,
2787         &g12a_periphs,
2788         &g12a_spicc_0,
2789         &g12a_i2c,
2790         &g12a_sana,
2791         &g12a_sd,
2792         &g12a_rng0,
2793         &g12a_uart0,
2794         &g12a_spicc_1,
2795         &g12a_hiu_reg,
2796         &g12a_mipi_dsi_phy,
2797         &g12a_assist_misc,
2798         &g12a_emmc_a,
2799         &g12a_emmc_b,
2800         &g12a_emmc_c,
2801         &g12a_audio_codec,
2802         &g12a_audio,
2803         &g12a_eth_core,
2804         &g12a_demux,
2805         &g12a_audio_ififo,
2806         &g12a_adc,
2807         &g12a_uart1,
2808         &g12a_g2d,
2809         &g12a_reset,
2810         &g12a_pcie_comb,
2811         &g12a_parser,
2812         &g12a_usb_general,
2813         &g12a_pcie_phy,
2814         &g12a_ahb_arb0,
2815         &g12a_ahb_data_bus,
2816         &g12a_ahb_ctrl_bus,
2817         &g12a_htx_hdcp22,
2818         &g12a_htx_pclk,
2819         &g12a_bt656,
2820         &g12a_usb1_to_ddr,
2821         &g12a_mmc_pclk,
2822         &g12a_vpu_intr,
2823         &g12a_gic,
2824         &g12a_sd_emmc_a_clk0,
2825         &g12a_sd_emmc_b_clk0,
2826         &g12a_sd_emmc_c_clk0,
2827         &g12a_mpeg_clk_div,
2828         &g12a_sd_emmc_a_clk0_div,
2829         &g12a_sd_emmc_b_clk0_div,
2830         &g12a_sd_emmc_c_clk0_div,
2831         &g12a_mpeg_clk_sel,
2832         &g12a_sd_emmc_a_clk0_sel,
2833         &g12a_sd_emmc_b_clk0_sel,
2834         &g12a_sd_emmc_c_clk0_sel,
2835         &g12a_mpll0,
2836         &g12a_mpll1,
2837         &g12a_mpll2,
2838         &g12a_mpll3,
2839         &g12a_mpll0_div,
2840         &g12a_mpll1_div,
2841         &g12a_mpll2_div,
2842         &g12a_mpll3_div,
2843         &g12a_fixed_pll,
2844         &g12a_sys_pll,
2845         &g12a_gp0_pll,
2846         &g12a_hifi_pll,
2847         &g12a_vclk2_venci0,
2848         &g12a_vclk2_venci1,
2849         &g12a_vclk2_vencp0,
2850         &g12a_vclk2_vencp1,
2851         &g12a_vclk2_venct0,
2852         &g12a_vclk2_venct1,
2853         &g12a_vclk2_other,
2854         &g12a_vclk2_enci,
2855         &g12a_vclk2_encp,
2856         &g12a_dac_clk,
2857         &g12a_aoclk_gate,
2858         &g12a_iec958_gate,
2859         &g12a_enc480p,
2860         &g12a_rng1,
2861         &g12a_vclk2_enct,
2862         &g12a_vclk2_encl,
2863         &g12a_vclk2_venclmmc,
2864         &g12a_vclk2_vencl,
2865         &g12a_vclk2_other1,
2866         &g12a_fixed_pll_dco,
2867         &g12a_sys_pll_dco,
2868         &g12a_gp0_pll_dco,
2869         &g12a_hifi_pll_dco,
2870         &g12a_fclk_div2,
2871         &g12a_fclk_div3,
2872         &g12a_fclk_div4,
2873         &g12a_fclk_div5,
2874         &g12a_fclk_div7,
2875         &g12a_fclk_div2p5,
2876         &g12a_dma,
2877         &g12a_efuse,
2878         &g12a_rom_boot,
2879         &g12a_reset_sec,
2880         &g12a_sec_ahb_apb3,
2881         &g12a_vpu_0_sel,
2882         &g12a_vpu_0_div,
2883         &g12a_vpu_0,
2884         &g12a_vpu_1_sel,
2885         &g12a_vpu_1_div,
2886         &g12a_vpu_1,
2887         &g12a_vpu,
2888         &g12a_vapb_0_sel,
2889         &g12a_vapb_0_div,
2890         &g12a_vapb_0,
2891         &g12a_vapb_1_sel,
2892         &g12a_vapb_1_div,
2893         &g12a_vapb_1,
2894         &g12a_vapb_sel,
2895         &g12a_vapb,
2896         &g12a_hdmi_pll_dco,
2897         &g12a_hdmi_pll_od,
2898         &g12a_hdmi_pll_od2,
2899         &g12a_hdmi_pll,
2900         &g12a_vid_pll_div,
2901         &g12a_vid_pll_sel,
2902         &g12a_vid_pll,
2903         &g12a_vclk_sel,
2904         &g12a_vclk2_sel,
2905         &g12a_vclk_input,
2906         &g12a_vclk2_input,
2907         &g12a_vclk_div,
2908         &g12a_vclk2_div,
2909         &g12a_vclk,
2910         &g12a_vclk2,
2911         &g12a_vclk_div1,
2912         &g12a_vclk_div2_en,
2913         &g12a_vclk_div4_en,
2914         &g12a_vclk_div6_en,
2915         &g12a_vclk_div12_en,
2916         &g12a_vclk2_div1,
2917         &g12a_vclk2_div2_en,
2918         &g12a_vclk2_div4_en,
2919         &g12a_vclk2_div6_en,
2920         &g12a_vclk2_div12_en,
2921         &g12a_cts_enci_sel,
2922         &g12a_cts_encp_sel,
2923         &g12a_cts_vdac_sel,
2924         &g12a_hdmi_tx_sel,
2925         &g12a_cts_enci,
2926         &g12a_cts_encp,
2927         &g12a_cts_vdac,
2928         &g12a_hdmi_tx,
2929         &g12a_hdmi_sel,
2930         &g12a_hdmi_div,
2931         &g12a_hdmi,
2932         &g12a_mali_0_sel,
2933         &g12a_mali_0_div,
2934         &g12a_mali_0,
2935         &g12a_mali_1_sel,
2936         &g12a_mali_1_div,
2937         &g12a_mali_1,
2938         &g12a_mali,
2939         &g12a_mpll_50m,
2940         &g12a_sys_pll_div16_en,
2941         &g12a_cpu_clk_premux0,
2942         &g12a_cpu_clk_mux0_div,
2943         &g12a_cpu_clk_postmux0,
2944         &g12a_cpu_clk_premux1,
2945         &g12a_cpu_clk_mux1_div,
2946         &g12a_cpu_clk_postmux1,
2947         &g12a_cpu_clk_dyn,
2948         &g12a_cpu_clk,
2949         &g12a_cpu_clk_div16_en,
2950         &g12a_cpu_clk_apb_div,
2951         &g12a_cpu_clk_apb,
2952         &g12a_cpu_clk_atb_div,
2953         &g12a_cpu_clk_atb,
2954         &g12a_cpu_clk_axi_div,
2955         &g12a_cpu_clk_axi,
2956         &g12a_cpu_clk_trace_div,
2957         &g12a_cpu_clk_trace,
2958         &g12a_pcie_pll_od,
2959         &g12a_pcie_pll_dco,
2960         &g12a_vdec_1_sel,
2961         &g12a_vdec_1_div,
2962         &g12a_vdec_1,
2963         &g12a_vdec_hevc_sel,
2964         &g12a_vdec_hevc_div,
2965         &g12a_vdec_hevc,
2966         &g12a_vdec_hevcf_sel,
2967         &g12a_vdec_hevcf_div,
2968         &g12a_vdec_hevcf,
2969 };
2970
2971 static const struct meson_eeclkc_data g12a_clkc_data = {
2972         .regmap_clks = g12a_clk_regmaps,
2973         .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
2974         .hw_onecell_data = &g12a_hw_onecell_data
2975 };
2976
2977 static const struct of_device_id clkc_match_table[] = {
2978         { .compatible = "amlogic,g12a-clkc", .data = &g12a_clkc_data },
2979         {}
2980 };
2981
2982 static struct platform_driver g12a_driver = {
2983         .probe          = meson_eeclkc_probe,
2984         .driver         = {
2985                 .name   = "g12a-clkc",
2986                 .of_match_table = clkc_match_table,
2987         },
2988 };
2989
2990 builtin_platform_driver(g12a_driver);