drivers/clk/meson/axg.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * AmLogic Meson-AXG Clock Controller Driver
   4  *
   5  * Copyright (c) 2016 Baylibre SAS.
   6  * Author: Michael Turquette <mturquette@baylibre.com>
   7  *
   8  * Copyright (c) 2017 Amlogic, inc.
   9  * Author: Qiufang Dai <qiufang.dai@amlogic.com>
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/init.h>
  15 #include <linux/of_device.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regmap.h>
  19
  20 #include "clkc.h"
  21 #include "axg.h"
  22
  23 static DEFINE_SPINLOCK(meson_clk_lock);
  24
  25 static struct clk_regmap axg_fixed_pll = {
  26         .data = &(struct meson_clk_pll_data){
  27                 .m = {
  28                         .reg_off = HHI_MPLL_CNTL,
  29                         .shift   = 0,
  30                         .width   = 9,
  31                 },
  32                 .n = {
  33                         .reg_off = HHI_MPLL_CNTL,
  34                         .shift   = 9,
  35                         .width   = 5,
  36                 },
  37                 .od = {
  38                         .reg_off = HHI_MPLL_CNTL,
  39                         .shift   = 16,
  40                         .width   = 2,
  41                 },
  42                 .frac = {
  43                         .reg_off = HHI_MPLL_CNTL2,
  44                         .shift   = 0,
  45                         .width   = 12,
  46                 },
  47                 .l = {
  48                         .reg_off = HHI_MPLL_CNTL,
  49                         .shift   = 31,
  50                         .width   = 1,
  51                 },
  52                 .rst = {
  53                         .reg_off = HHI_MPLL_CNTL,
  54                         .shift   = 29,
  55                         .width   = 1,
  56                 },
  57         },
  58         .hw.init = &(struct clk_init_data){
  59                 .name = "fixed_pll",
  60                 .ops = &meson_clk_pll_ro_ops,
  61                 .parent_names = (const char *[]){ "xtal" },
  62                 .num_parents = 1,
  63         },
  64 };
  65
  66 static struct clk_regmap axg_sys_pll = {
  67         .data = &(struct meson_clk_pll_data){
  68                 .m = {
  69                         .reg_off = HHI_SYS_PLL_CNTL,
  70                         .shift   = 0,
  71                         .width   = 9,
  72                 },
  73                 .n = {
  74                         .reg_off = HHI_SYS_PLL_CNTL,
  75                         .shift   = 9,
  76                         .width   = 5,
  77                 },
  78                 .od = {
  79                         .reg_off = HHI_SYS_PLL_CNTL,
  80                         .shift   = 16,
  81                         .width   = 2,
  82                 },
  83                 .l = {
  84                         .reg_off = HHI_SYS_PLL_CNTL,
  85                         .shift   = 31,
  86                         .width   = 1,
  87                 },
  88                 .rst = {
  89                         .reg_off = HHI_SYS_PLL_CNTL,
  90                         .shift   = 29,
  91                         .width   = 1,
  92                 },
  93         },
  94         .hw.init = &(struct clk_init_data){
  95                 .name = "sys_pll",
  96                 .ops = &meson_clk_pll_ro_ops,
  97                 .parent_names = (const char *[]){ "xtal" },
  98                 .num_parents = 1,
  99                 .flags = CLK_GET_RATE_NOCACHE,
 100         },
 101 };
 102
 103 static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
 104         PLL_RATE(240000000, 40, 1, 2),
 105         PLL_RATE(246000000, 41, 1, 2),
 106         PLL_RATE(252000000, 42, 1, 2),
 107         PLL_RATE(258000000, 43, 1, 2),
 108         PLL_RATE(264000000, 44, 1, 2),
 109         PLL_RATE(270000000, 45, 1, 2),
 110         PLL_RATE(276000000, 46, 1, 2),
 111         PLL_RATE(282000000, 47, 1, 2),
 112         PLL_RATE(288000000, 48, 1, 2),
 113         PLL_RATE(294000000, 49, 1, 2),
 114         PLL_RATE(300000000, 50, 1, 2),
 115         PLL_RATE(306000000, 51, 1, 2),
 116         PLL_RATE(312000000, 52, 1, 2),
 117         PLL_RATE(318000000, 53, 1, 2),
 118         PLL_RATE(324000000, 54, 1, 2),
 119         PLL_RATE(330000000, 55, 1, 2),
 120         PLL_RATE(336000000, 56, 1, 2),
 121         PLL_RATE(342000000, 57, 1, 2),
 122         PLL_RATE(348000000, 58, 1, 2),
 123         PLL_RATE(354000000, 59, 1, 2),
 124         PLL_RATE(360000000, 60, 1, 2),
 125         PLL_RATE(366000000, 61, 1, 2),
 126         PLL_RATE(372000000, 62, 1, 2),
 127         PLL_RATE(378000000, 63, 1, 2),
 128         PLL_RATE(384000000, 64, 1, 2),
 129         PLL_RATE(390000000, 65, 1, 3),
 130         PLL_RATE(396000000, 66, 1, 3),
 131         PLL_RATE(402000000, 67, 1, 3),
 132         PLL_RATE(408000000, 68, 1, 3),
 133         PLL_RATE(480000000, 40, 1, 1),
 134         PLL_RATE(492000000, 41, 1, 1),
 135         PLL_RATE(504000000, 42, 1, 1),
 136         PLL_RATE(516000000, 43, 1, 1),
 137         PLL_RATE(528000000, 44, 1, 1),
 138         PLL_RATE(540000000, 45, 1, 1),
 139         PLL_RATE(552000000, 46, 1, 1),
 140         PLL_RATE(564000000, 47, 1, 1),
 141         PLL_RATE(576000000, 48, 1, 1),
 142         PLL_RATE(588000000, 49, 1, 1),
 143         PLL_RATE(600000000, 50, 1, 1),
 144         PLL_RATE(612000000, 51, 1, 1),
 145         PLL_RATE(624000000, 52, 1, 1),
 146         PLL_RATE(636000000, 53, 1, 1),
 147         PLL_RATE(648000000, 54, 1, 1),
 148         PLL_RATE(660000000, 55, 1, 1),
 149         PLL_RATE(672000000, 56, 1, 1),
 150         PLL_RATE(684000000, 57, 1, 1),
 151         PLL_RATE(696000000, 58, 1, 1),
 152         PLL_RATE(708000000, 59, 1, 1),
 153         PLL_RATE(720000000, 60, 1, 1),
 154         PLL_RATE(732000000, 61, 1, 1),
 155         PLL_RATE(744000000, 62, 1, 1),
 156         PLL_RATE(756000000, 63, 1, 1),
 157         PLL_RATE(768000000, 64, 1, 1),
 158         PLL_RATE(780000000, 65, 1, 1),
 159         PLL_RATE(792000000, 66, 1, 1),
 160         PLL_RATE(804000000, 67, 1, 1),
 161         PLL_RATE(816000000, 68, 1, 1),
 162         PLL_RATE(960000000, 40, 1, 0),
 163         PLL_RATE(984000000, 41, 1, 0),
 164         PLL_RATE(1008000000, 42, 1, 0),
 165         PLL_RATE(1032000000, 43, 1, 0),
 166         PLL_RATE(1056000000, 44, 1, 0),
 167         PLL_RATE(1080000000, 45, 1, 0),
 168         PLL_RATE(1104000000, 46, 1, 0),
 169         PLL_RATE(1128000000, 47, 1, 0),
 170         PLL_RATE(1152000000, 48, 1, 0),
 171         PLL_RATE(1176000000, 49, 1, 0),
 172         PLL_RATE(1200000000, 50, 1, 0),
 173         PLL_RATE(1224000000, 51, 1, 0),
 174         PLL_RATE(1248000000, 52, 1, 0),
 175         PLL_RATE(1272000000, 53, 1, 0),
 176         PLL_RATE(1296000000, 54, 1, 0),
 177         PLL_RATE(1320000000, 55, 1, 0),
 178         PLL_RATE(1344000000, 56, 1, 0),
 179         PLL_RATE(1368000000, 57, 1, 0),
 180         PLL_RATE(1392000000, 58, 1, 0),
 181         PLL_RATE(1416000000, 59, 1, 0),
 182         PLL_RATE(1440000000, 60, 1, 0),
 183         PLL_RATE(1464000000, 61, 1, 0),
 184         PLL_RATE(1488000000, 62, 1, 0),
 185         PLL_RATE(1512000000, 63, 1, 0),
 186         PLL_RATE(1536000000, 64, 1, 0),
 187         PLL_RATE(1560000000, 65, 1, 0),
 188         PLL_RATE(1584000000, 66, 1, 0),
 189         PLL_RATE(1608000000, 67, 1, 0),
 190         PLL_RATE(1632000000, 68, 1, 0),
 191         { /* sentinel */ },
 192 };
 193
 194 static const struct reg_sequence axg_gp0_init_regs[] = {
 195         { .reg = HHI_GP0_PLL_CNTL1,     .def = 0xc084b000 },
 196         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0xb75020be },
 197         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a59a288 },
 198         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0xc000004d },
 199         { .reg = HHI_GP0_PLL_CNTL5,     .def = 0x00078000 },
 200         { .reg = HHI_GP0_PLL_CNTL,      .def = 0x40010250 },
 201 };
 202
 203 static struct clk_regmap axg_gp0_pll = {
 204         .data = &(struct meson_clk_pll_data){
 205                 .m = {
 206                         .reg_off = HHI_GP0_PLL_CNTL,
 207                         .shift   = 0,
 208                         .width   = 9,
 209                 },
 210                 .n = {
 211                         .reg_off = HHI_GP0_PLL_CNTL,
 212                         .shift   = 9,
 213                         .width   = 5,
 214                 },
 215                 .od = {
 216                         .reg_off = HHI_GP0_PLL_CNTL,
 217                         .shift   = 16,
 218                         .width   = 2,
 219                 },
 220                 .frac = {
 221                         .reg_off = HHI_GP0_PLL_CNTL1,
 222                         .shift   = 0,
 223                         .width   = 10,
 224                 },
 225                 .l = {
 226                         .reg_off = HHI_GP0_PLL_CNTL,
 227                         .shift   = 31,
 228                         .width   = 1,
 229                 },
 230                 .rst = {
 231                         .reg_off = HHI_GP0_PLL_CNTL,
 232                         .shift   = 29,
 233                         .width   = 1,
 234                 },
 235                 .table = axg_gp0_pll_rate_table,
 236                 .init_regs = axg_gp0_init_regs,
 237                 .init_count = ARRAY_SIZE(axg_gp0_init_regs),
 238         },
 239         .hw.init = &(struct clk_init_data){
 240                 .name = "gp0_pll",
 241                 .ops = &meson_clk_pll_ops,
 242                 .parent_names = (const char *[]){ "xtal" },
 243                 .num_parents = 1,
 244         },
 245 };
 246
 247 static const struct reg_sequence axg_hifi_init_regs[] = {
 248         { .reg = HHI_HIFI_PLL_CNTL1,    .def = 0xc084b000 },
 249         { .reg = HHI_HIFI_PLL_CNTL2,    .def = 0xb75020be },
 250         { .reg = HHI_HIFI_PLL_CNTL3,    .def = 0x0a6a3a88 },
 251         { .reg = HHI_HIFI_PLL_CNTL4,    .def = 0xc000004d },
 252         { .reg = HHI_HIFI_PLL_CNTL5,    .def = 0x00058000 },
 253         { .reg = HHI_HIFI_PLL_CNTL,     .def = 0x40010250 },
 254 };
 255
 256 static struct clk_regmap axg_hifi_pll = {
 257         .data = &(struct meson_clk_pll_data){
 258                 .m = {
 259                         .reg_off = HHI_HIFI_PLL_CNTL,
 260                         .shift   = 0,
 261                         .width   = 9,
 262                 },
 263                 .n = {
 264                         .reg_off = HHI_HIFI_PLL_CNTL,
 265                         .shift   = 9,
 266                         .width   = 5,
 267                 },
 268                 .od = {
 269                         .reg_off = HHI_HIFI_PLL_CNTL,
 270                         .shift   = 16,
 271                         .width   = 2,
 272                 },
 273                 .frac = {
 274                         .reg_off = HHI_HIFI_PLL_CNTL5,
 275                         .shift   = 0,
 276                         .width   = 13,
 277                 },
 278                 .l = {
 279                         .reg_off = HHI_HIFI_PLL_CNTL,
 280                         .shift   = 31,
 281                         .width   = 1,
 282                 },
 283                 .rst = {
 284                         .reg_off = HHI_HIFI_PLL_CNTL,
 285                         .shift   = 29,
 286                         .width   = 1,
 287                 },
 288                 .table = axg_gp0_pll_rate_table,
 289                 .init_regs = axg_hifi_init_regs,
 290                 .init_count = ARRAY_SIZE(axg_hifi_init_regs),
 291                 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
 292         },
 293         .hw.init = &(struct clk_init_data){
 294                 .name = "hifi_pll",
 295                 .ops = &meson_clk_pll_ops,
 296                 .parent_names = (const char *[]){ "xtal" },
 297                 .num_parents = 1,
 298         },
 299 };
 300
 301 static struct clk_fixed_factor axg_fclk_div2_div = {
 302         .mult = 1,
 303         .div = 2,
 304         .hw.init = &(struct clk_init_data){
 305                 .name = "fclk_div2_div",
 306                 .ops = &clk_fixed_factor_ops,
 307                 .parent_names = (const char *[]){ "fixed_pll" },
 308                 .num_parents = 1,
 309         },
 310 };
 311
 312 static struct clk_regmap axg_fclk_div2 = {
 313         .data = &(struct clk_regmap_gate_data){
 314                 .offset = HHI_MPLL_CNTL6,
 315                 .bit_idx = 27,
 316         },
 317         .hw.init = &(struct clk_init_data){
 318                 .name = "fclk_div2",
 319                 .ops = &clk_regmap_gate_ops,
 320                 .parent_names = (const char *[]){ "fclk_div2_div" },
 321                 .num_parents = 1,
 322         },
 323 };
 324
 325 static struct clk_fixed_factor axg_fclk_div3_div = {
 326         .mult = 1,
 327         .div = 3,
 328         .hw.init = &(struct clk_init_data){
 329                 .name = "fclk_div3_div",
 330                 .ops = &clk_fixed_factor_ops,
 331                 .parent_names = (const char *[]){ "fixed_pll" },
 332                 .num_parents = 1,
 333         },
 334 };
 335
 336 static struct clk_regmap axg_fclk_div3 = {
 337         .data = &(struct clk_regmap_gate_data){
 338                 .offset = HHI_MPLL_CNTL6,
 339                 .bit_idx = 28,
 340         },
 341         .hw.init = &(struct clk_init_data){
 342                 .name = "fclk_div3",
 343                 .ops = &clk_regmap_gate_ops,
 344                 .parent_names = (const char *[]){ "fclk_div3_div" },
 345                 .num_parents = 1,
 346         },
 347 };
 348
 349 static struct clk_fixed_factor axg_fclk_div4_div = {
 350         .mult = 1,
 351         .div = 4,
 352         .hw.init = &(struct clk_init_data){
 353                 .name = "fclk_div4_div",
 354                 .ops = &clk_fixed_factor_ops,
 355                 .parent_names = (const char *[]){ "fixed_pll" },
 356                 .num_parents = 1,
 357         },
 358 };
 359
 360 static struct clk_regmap axg_fclk_div4 = {
 361         .data = &(struct clk_regmap_gate_data){
 362                 .offset = HHI_MPLL_CNTL6,
 363                 .bit_idx = 29,
 364         },
 365         .hw.init = &(struct clk_init_data){
 366                 .name = "fclk_div4",
 367                 .ops = &clk_regmap_gate_ops,
 368                 .parent_names = (const char *[]){ "fclk_div4_div" },
 369                 .num_parents = 1,
 370         },
 371 };
 372
 373 static struct clk_fixed_factor axg_fclk_div5_div = {
 374         .mult = 1,
 375         .div = 5,
 376         .hw.init = &(struct clk_init_data){
 377                 .name = "fclk_div5_div",
 378                 .ops = &clk_fixed_factor_ops,
 379                 .parent_names = (const char *[]){ "fixed_pll" },
 380                 .num_parents = 1,
 381         },
 382 };
 383
 384 static struct clk_regmap axg_fclk_div5 = {
 385         .data = &(struct clk_regmap_gate_data){
 386                 .offset = HHI_MPLL_CNTL6,
 387                 .bit_idx = 30,
 388         },
 389         .hw.init = &(struct clk_init_data){
 390                 .name = "fclk_div5",
 391                 .ops = &clk_regmap_gate_ops,
 392                 .parent_names = (const char *[]){ "fclk_div5_div" },
 393                 .num_parents = 1,
 394         },
 395 };
 396
 397 static struct clk_fixed_factor axg_fclk_div7_div = {
 398         .mult = 1,
 399         .div = 7,
 400         .hw.init = &(struct clk_init_data){
 401                 .name = "fclk_div7_div",
 402                 .ops = &clk_fixed_factor_ops,
 403                 .parent_names = (const char *[]){ "fixed_pll" },
 404                 .num_parents = 1,
 405         },
 406 };
 407
 408 static struct clk_regmap axg_fclk_div7 = {
 409         .data = &(struct clk_regmap_gate_data){
 410                 .offset = HHI_MPLL_CNTL6,
 411                 .bit_idx = 31,
 412         },
 413         .hw.init = &(struct clk_init_data){
 414                 .name = "fclk_div7",
 415                 .ops = &clk_regmap_gate_ops,
 416                 .parent_names = (const char *[]){ "fclk_div7_div" },
 417                 .num_parents = 1,
 418         },
 419 };
 420
 421 static struct clk_regmap axg_mpll_prediv = {
 422         .data = &(struct clk_regmap_div_data){
 423                 .offset = HHI_MPLL_CNTL5,
 424                 .shift = 12,
 425                 .width = 1,
 426         },
 427         .hw.init = &(struct clk_init_data){
 428                 .name = "mpll_prediv",
 429                 .ops = &clk_regmap_divider_ro_ops,
 430                 .parent_names = (const char *[]){ "fixed_pll" },
 431                 .num_parents = 1,
 432         },
 433 };
 434
 435 static struct clk_regmap axg_mpll0_div = {
 436         .data = &(struct meson_clk_mpll_data){
 437                 .sdm = {
 438                         .reg_off = HHI_MPLL_CNTL7,
 439                         .shift   = 0,
 440                         .width   = 14,
 441                 },
 442                 .sdm_en = {
 443                         .reg_off = HHI_MPLL_CNTL7,
 444                         .shift   = 15,
 445                         .width   = 1,
 446                 },
 447                 .n2 = {
 448                         .reg_off = HHI_MPLL_CNTL7,
 449                         .shift   = 16,
 450                         .width   = 9,
 451                 },
 452                 .ssen = {
 453                         .reg_off = HHI_MPLL_CNTL,
 454                         .shift   = 25,
 455                         .width   = 1,
 456                 },
 457                 .misc = {
 458                         .reg_off = HHI_PLL_TOP_MISC,
 459                         .shift   = 0,
 460                         .width   = 1,
 461                 },
 462                 .lock = &meson_clk_lock,
 463                 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 464         },
 465         .hw.init = &(struct clk_init_data){
 466                 .name = "mpll0_div",
 467                 .ops = &meson_clk_mpll_ops,
 468                 .parent_names = (const char *[]){ "mpll_prediv" },
 469                 .num_parents = 1,
 470         },
 471 };
 472
 473 static struct clk_regmap axg_mpll0 = {
 474         .data = &(struct clk_regmap_gate_data){
 475                 .offset = HHI_MPLL_CNTL7,
 476                 .bit_idx = 14,
 477         },
 478         .hw.init = &(struct clk_init_data){
 479                 .name = "mpll0",
 480                 .ops = &clk_regmap_gate_ops,
 481                 .parent_names = (const char *[]){ "mpll0_div" },
 482                 .num_parents = 1,
 483                 .flags = CLK_SET_RATE_PARENT,
 484         },
 485 };
 486
 487 static struct clk_regmap axg_mpll1_div = {
 488         .data = &(struct meson_clk_mpll_data){
 489                 .sdm = {
 490                         .reg_off = HHI_MPLL_CNTL8,
 491                         .shift   = 0,
 492                         .width   = 14,
 493                 },
 494                 .sdm_en = {
 495                         .reg_off = HHI_MPLL_CNTL8,
 496                         .shift   = 15,
 497                         .width   = 1,
 498                 },
 499                 .n2 = {
 500                         .reg_off = HHI_MPLL_CNTL8,
 501                         .shift   = 16,
 502                         .width   = 9,
 503                 },
 504                 .misc = {
 505                         .reg_off = HHI_PLL_TOP_MISC,
 506                         .shift   = 1,
 507                         .width   = 1,
 508                 },
 509                 .lock = &meson_clk_lock,
 510                 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 511         },
 512         .hw.init = &(struct clk_init_data){
 513                 .name = "mpll1_div",
 514                 .ops = &meson_clk_mpll_ops,
 515                 .parent_names = (const char *[]){ "mpll_prediv" },
 516                 .num_parents = 1,
 517         },
 518 };
 519
 520 static struct clk_regmap axg_mpll1 = {
 521         .data = &(struct clk_regmap_gate_data){
 522                 .offset = HHI_MPLL_CNTL8,
 523                 .bit_idx = 14,
 524         },
 525         .hw.init = &(struct clk_init_data){
 526                 .name = "mpll1",
 527                 .ops = &clk_regmap_gate_ops,
 528                 .parent_names = (const char *[]){ "mpll1_div" },
 529                 .num_parents = 1,
 530                 .flags = CLK_SET_RATE_PARENT,
 531         },
 532 };
 533
 534 static struct clk_regmap axg_mpll2_div = {
 535         .data = &(struct meson_clk_mpll_data){
 536                 .sdm = {
 537                         .reg_off = HHI_MPLL_CNTL9,
 538                         .shift   = 0,
 539                         .width   = 14,
 540                 },
 541                 .sdm_en = {
 542                         .reg_off = HHI_MPLL_CNTL9,
 543                         .shift   = 15,
 544                         .width   = 1,
 545                 },
 546                 .n2 = {
 547                         .reg_off = HHI_MPLL_CNTL9,
 548                         .shift   = 16,
 549                         .width   = 9,
 550                 },
 551                 .misc = {
 552                         .reg_off = HHI_PLL_TOP_MISC,
 553                         .shift   = 2,
 554                         .width   = 1,
 555                 },
 556                 .lock = &meson_clk_lock,
 557                 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 558         },
 559         .hw.init = &(struct clk_init_data){
 560                 .name = "mpll2_div",
 561                 .ops = &meson_clk_mpll_ops,
 562                 .parent_names = (const char *[]){ "mpll_prediv" },
 563                 .num_parents = 1,
 564         },
 565 };
 566
 567 static struct clk_regmap axg_mpll2 = {
 568         .data = &(struct clk_regmap_gate_data){
 569                 .offset = HHI_MPLL_CNTL9,
 570                 .bit_idx = 14,
 571         },
 572         .hw.init = &(struct clk_init_data){
 573                 .name = "mpll2",
 574                 .ops = &clk_regmap_gate_ops,
 575                 .parent_names = (const char *[]){ "mpll2_div" },
 576                 .num_parents = 1,
 577                 .flags = CLK_SET_RATE_PARENT,
 578         },
 579 };
 580
 581 static struct clk_regmap axg_mpll3_div = {
 582         .data = &(struct meson_clk_mpll_data){
 583                 .sdm = {
 584                         .reg_off = HHI_MPLL3_CNTL0,
 585                         .shift   = 12,
 586                         .width   = 14,
 587                 },
 588                 .sdm_en = {
 589                         .reg_off = HHI_MPLL3_CNTL0,
 590                         .shift   = 11,
 591                         .width   = 1,
 592                 },
 593                 .n2 = {
 594                         .reg_off = HHI_MPLL3_CNTL0,
 595                         .shift   = 2,
 596                         .width   = 9,
 597                 },
 598                 .misc = {
 599                         .reg_off = HHI_PLL_TOP_MISC,
 600                         .shift   = 3,
 601                         .width   = 1,
 602                 },
 603                 .lock = &meson_clk_lock,
 604                 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 605         },
 606         .hw.init = &(struct clk_init_data){
 607                 .name = "mpll3_div",
 608                 .ops = &meson_clk_mpll_ops,
 609                 .parent_names = (const char *[]){ "mpll_prediv" },
 610                 .num_parents = 1,
 611         },
 612 };
 613
 614 static struct clk_regmap axg_mpll3 = {
 615         .data = &(struct clk_regmap_gate_data){
 616                 .offset = HHI_MPLL3_CNTL0,
 617                 .bit_idx = 0,
 618         },
 619         .hw.init = &(struct clk_init_data){
 620                 .name = "mpll3",
 621                 .ops = &clk_regmap_gate_ops,
 622                 .parent_names = (const char *[]){ "mpll3_div" },
 623                 .num_parents = 1,
 624                 .flags = CLK_SET_RATE_PARENT,
 625         },
 626 };
 627
 628 static const struct pll_rate_table axg_pcie_pll_rate_table[] = {
 629         {
 630                 .rate   = 100000000,
 631                 .m      = 200,
 632                 .n      = 3,
 633                 .od     = 1,
 634                 .od2    = 3,
 635         },
 636         { /* sentinel */ },
 637 };
 638
 639 static const struct reg_sequence axg_pcie_init_regs[] = {
 640         { .reg = HHI_PCIE_PLL_CNTL,     .def = 0x400106c8 },
 641         { .reg = HHI_PCIE_PLL_CNTL1,    .def = 0x0084a2aa },
 642         { .reg = HHI_PCIE_PLL_CNTL2,    .def = 0xb75020be },
 643         { .reg = HHI_PCIE_PLL_CNTL3,    .def = 0x0a47488e },
 644         { .reg = HHI_PCIE_PLL_CNTL4,    .def = 0xc000004d },
 645         { .reg = HHI_PCIE_PLL_CNTL5,    .def = 0x00078000 },
 646         { .reg = HHI_PCIE_PLL_CNTL6,    .def = 0x002323c6 },
 647 };
 648
 649 static struct clk_regmap axg_pcie_pll = {
 650         .data = &(struct meson_clk_pll_data){
 651                 .m = {
 652                         .reg_off = HHI_PCIE_PLL_CNTL,
 653                         .shift   = 0,
 654                         .width   = 9,
 655                 },
 656                 .n = {
 657                         .reg_off = HHI_PCIE_PLL_CNTL,
 658                         .shift   = 9,
 659                         .width   = 5,
 660                 },
 661                 .od = {
 662                         .reg_off = HHI_PCIE_PLL_CNTL,
 663                         .shift   = 16,
 664                         .width   = 2,
 665                 },
 666                 .od2 = {
 667                         .reg_off = HHI_PCIE_PLL_CNTL6,
 668                         .shift   = 6,
 669                         .width   = 2,
 670                 },
 671                 .frac = {
 672                         .reg_off = HHI_PCIE_PLL_CNTL1,
 673                         .shift   = 0,
 674                         .width   = 12,
 675                 },
 676                 .l = {
 677                         .reg_off = HHI_PCIE_PLL_CNTL,
 678                         .shift   = 31,
 679                         .width   = 1,
 680                 },
 681                 .rst = {
 682                         .reg_off = HHI_PCIE_PLL_CNTL,
 683                         .shift   = 29,
 684                         .width   = 1,
 685                 },
 686                 .table = axg_pcie_pll_rate_table,
 687                 .init_regs = axg_pcie_init_regs,
 688                 .init_count = ARRAY_SIZE(axg_pcie_init_regs),
 689         },
 690         .hw.init = &(struct clk_init_data){
 691                 .name = "pcie_pll",
 692                 .ops = &meson_clk_pll_ops,
 693                 .parent_names = (const char *[]){ "xtal" },
 694                 .num_parents = 1,
 695         },
 696 };
 697
 698 static struct clk_regmap axg_pcie_mux = {
 699         .data = &(struct clk_regmap_mux_data){
 700                 .offset = HHI_PCIE_PLL_CNTL6,
 701                 .mask = 0x1,
 702                 .shift = 2,
 703         },
 704         .hw.init = &(struct clk_init_data){
 705                 .name = "pcie_mux",
 706                 .ops = &clk_regmap_mux_ops,
 707                 .parent_names = (const char *[]){ "mpll3", "pcie_pll" },
 708                 .num_parents = 2,
 709                 .flags = CLK_SET_RATE_PARENT,
 710         },
 711 };
 712
 713 static struct clk_regmap axg_pcie_ref = {
 714         .data = &(struct clk_regmap_mux_data){
 715                 .offset = HHI_PCIE_PLL_CNTL6,
 716                 .mask = 0x1,
 717                 .shift = 1,
 718                 /* skip the parent 0, reserved for debug */
 719                 .table = (u32[]){ 1 },
 720         },
 721         .hw.init = &(struct clk_init_data){
 722                 .name = "pcie_ref",
 723                 .ops = &clk_regmap_mux_ops,
 724                 .parent_names = (const char *[]){ "pcie_mux" },
 725                 .num_parents = 1,
 726                 .flags = CLK_SET_RATE_PARENT,
 727         },
 728 };
 729
 730 static struct clk_regmap axg_pcie_cml_en0 = {
 731         .data = &(struct clk_regmap_gate_data){
 732                 .offset = HHI_PCIE_PLL_CNTL6,
 733                 .bit_idx = 4,
 734         },
 735         .hw.init = &(struct clk_init_data) {
 736                 .name = "pcie_cml_en0",
 737                 .ops = &clk_regmap_gate_ops,
 738                 .parent_names = (const char *[]){ "pcie_ref" },
 739                 .num_parents = 1,
 740                 .flags = CLK_SET_RATE_PARENT,
 741
 742         },
 743 };
 744
 745 static struct clk_regmap axg_pcie_cml_en1 = {
 746         .data = &(struct clk_regmap_gate_data){
 747                 .offset = HHI_PCIE_PLL_CNTL6,
 748                 .bit_idx = 3,
 749         },
 750         .hw.init = &(struct clk_init_data) {
 751                 .name = "pcie_cml_en1",
 752                 .ops = &clk_regmap_gate_ops,
 753                 .parent_names = (const char *[]){ "pcie_ref" },
 754                 .num_parents = 1,
 755                 .flags = CLK_SET_RATE_PARENT,
 756         },
 757 };
 758
 759 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
 760 static const char * const clk81_parent_names[] = {
 761         "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
 762         "fclk_div3", "fclk_div5"
 763 };
 764
 765 static struct clk_regmap axg_mpeg_clk_sel = {
 766         .data = &(struct clk_regmap_mux_data){
 767                 .offset = HHI_MPEG_CLK_CNTL,
 768                 .mask = 0x7,
 769                 .shift = 12,
 770                 .table = mux_table_clk81,
 771         },
 772         .hw.init = &(struct clk_init_data){
 773                 .name = "mpeg_clk_sel",
 774                 .ops = &clk_regmap_mux_ro_ops,
 775                 .parent_names = clk81_parent_names,
 776                 .num_parents = ARRAY_SIZE(clk81_parent_names),
 777         },
 778 };
 779
 780 static struct clk_regmap axg_mpeg_clk_div = {
 781         .data = &(struct clk_regmap_div_data){
 782                 .offset = HHI_MPEG_CLK_CNTL,
 783                 .shift = 0,
 784                 .width = 7,
 785         },
 786         .hw.init = &(struct clk_init_data){
 787                 .name = "mpeg_clk_div",
 788                 .ops = &clk_regmap_divider_ops,
 789                 .parent_names = (const char *[]){ "mpeg_clk_sel" },
 790                 .num_parents = 1,
 791                 .flags = CLK_SET_RATE_PARENT,
 792         },
 793 };
 794
 795 static struct clk_regmap axg_clk81 = {
 796         .data = &(struct clk_regmap_gate_data){
 797                 .offset = HHI_MPEG_CLK_CNTL,
 798                 .bit_idx = 7,
 799         },
 800         .hw.init = &(struct clk_init_data){
 801                 .name = "clk81",
 802                 .ops = &clk_regmap_gate_ops,
 803                 .parent_names = (const char *[]){ "mpeg_clk_div" },
 804                 .num_parents = 1,
 805                 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
 806         },
 807 };
 808
 809 static const char * const axg_sd_emmc_clk0_parent_names[] = {
 810         "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
 811
 812         /*
 813          * Following these parent clocks, we should also have had mpll2, mpll3
 814          * and gp0_pll but these clocks are too precious to be used here. All
 815          * the necessary rates for MMC and NAND operation can be acheived using
 816          * xtal or fclk_div clocks
 817          */
 818 };
 819
 820 /* SDcard clock */
 821 static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
 822         .data = &(struct clk_regmap_mux_data){
 823                 .offset = HHI_SD_EMMC_CLK_CNTL,
 824                 .mask = 0x7,
 825                 .shift = 25,
 826         },
 827         .hw.init = &(struct clk_init_data) {
 828                 .name = "sd_emmc_b_clk0_sel",
 829                 .ops = &clk_regmap_mux_ops,
 830                 .parent_names = axg_sd_emmc_clk0_parent_names,
 831                 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
 832                 .flags = CLK_SET_RATE_PARENT,
 833         },
 834 };
 835
 836 static struct clk_regmap axg_sd_emmc_b_clk0_div = {
 837         .data = &(struct clk_regmap_div_data){
 838                 .offset = HHI_SD_EMMC_CLK_CNTL,
 839                 .shift = 16,
 840                 .width = 7,
 841                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
 842         },
 843         .hw.init = &(struct clk_init_data) {
 844                 .name = "sd_emmc_b_clk0_div",
 845                 .ops = &clk_regmap_divider_ops,
 846                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
 847                 .num_parents = 1,
 848                 .flags = CLK_SET_RATE_PARENT,
 849         },
 850 };
 851
 852 static struct clk_regmap axg_sd_emmc_b_clk0 = {
 853         .data = &(struct clk_regmap_gate_data){
 854                 .offset = HHI_SD_EMMC_CLK_CNTL,
 855                 .bit_idx = 23,
 856         },
 857         .hw.init = &(struct clk_init_data){
 858                 .name = "sd_emmc_b_clk0",
 859                 .ops = &clk_regmap_gate_ops,
 860                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
 861                 .num_parents = 1,
 862                 .flags = CLK_SET_RATE_PARENT,
 863         },
 864 };
 865
 866 /* EMMC/NAND clock */
 867 static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
 868         .data = &(struct clk_regmap_mux_data){
 869                 .offset = HHI_NAND_CLK_CNTL,
 870                 .mask = 0x7,
 871                 .shift = 9,
 872         },
 873         .hw.init = &(struct clk_init_data) {
 874                 .name = "sd_emmc_c_clk0_sel",
 875                 .ops = &clk_regmap_mux_ops,
 876                 .parent_names = axg_sd_emmc_clk0_parent_names,
 877                 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
 878                 .flags = CLK_SET_RATE_PARENT,
 879         },
 880 };
 881
 882 static struct clk_regmap axg_sd_emmc_c_clk0_div = {
 883         .data = &(struct clk_regmap_div_data){
 884                 .offset = HHI_NAND_CLK_CNTL,
 885                 .shift = 0,
 886                 .width = 7,
 887                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
 888         },
 889         .hw.init = &(struct clk_init_data) {
 890                 .name = "sd_emmc_c_clk0_div",
 891                 .ops = &clk_regmap_divider_ops,
 892                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
 893                 .num_parents = 1,
 894                 .flags = CLK_SET_RATE_PARENT,
 895         },
 896 };
 897
 898 static struct clk_regmap axg_sd_emmc_c_clk0 = {
 899         .data = &(struct clk_regmap_gate_data){
 900                 .offset = HHI_NAND_CLK_CNTL,
 901                 .bit_idx = 7,
 902         },
 903         .hw.init = &(struct clk_init_data){
 904                 .name = "sd_emmc_c_clk0",
 905                 .ops = &clk_regmap_gate_ops,
 906                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
 907                 .num_parents = 1,
 908                 .flags = CLK_SET_RATE_PARENT,
 909         },
 910 };
 911
 912 static u32 mux_table_gen_clk[]  = { 0, 4, 5, 6, 7, 8,
 913                                     9, 10, 11, 13, 14, };
 914 static const char * const gen_clk_parent_names[] = {
 915         "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3",
 916         "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
 917 };
 918
 919 static struct clk_regmap axg_gen_clk_sel = {
 920         .data = &(struct clk_regmap_mux_data){
 921                 .offset = HHI_GEN_CLK_CNTL,
 922                 .mask = 0xf,
 923                 .shift = 12,
 924                 .table = mux_table_gen_clk,
 925         },
 926         .hw.init = &(struct clk_init_data){
 927                 .name = "gen_clk_sel",
 928                 .ops = &clk_regmap_mux_ops,
 929                 /*
 930                  * bits 15:12 selects from 14 possible parents:
 931                  * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
 932                  * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
 933                  * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
 934                  */
 935                 .parent_names = gen_clk_parent_names,
 936                 .num_parents = ARRAY_SIZE(gen_clk_parent_names),
 937         },
 938 };
 939
 940 static struct clk_regmap axg_gen_clk_div = {
 941         .data = &(struct clk_regmap_div_data){
 942                 .offset = HHI_GEN_CLK_CNTL,
 943                 .shift = 0,
 944                 .width = 11,
 945         },
 946         .hw.init = &(struct clk_init_data){
 947                 .name = "gen_clk_div",
 948                 .ops = &clk_regmap_divider_ops,
 949                 .parent_names = (const char *[]){ "gen_clk_sel" },
 950                 .num_parents = 1,
 951                 .flags = CLK_SET_RATE_PARENT,
 952         },
 953 };
 954
 955 static struct clk_regmap axg_gen_clk = {
 956         .data = &(struct clk_regmap_gate_data){
 957                 .offset = HHI_GEN_CLK_CNTL,
 958                 .bit_idx = 7,
 959         },
 960         .hw.init = &(struct clk_init_data){
 961                 .name = "gen_clk",
 962                 .ops = &clk_regmap_gate_ops,
 963                 .parent_names = (const char *[]){ "gen_clk_div" },
 964                 .num_parents = 1,
 965                 .flags = CLK_SET_RATE_PARENT,
 966         },
 967 };
 968
 969 /* Everything Else (EE) domain gates */
 970 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
 971 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
 972 static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
 973 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
 974 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
 975 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
 976 static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
 977 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
 978 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
 979 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
 980 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
 981 static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
 982 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
 983 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
 984 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
 985 static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
 986 static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
 987 static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
 988 static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
 989 static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
 990
 991 static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
 992 static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
 993 static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
 994 static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
 995 static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
 996 static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
 997 static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
 998 static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
 999 static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
1000 static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
1001 static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
1002
1003 static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1004 static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1005 static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
1006 static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
1007 static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
1008 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
1009 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1010 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
1011 static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29);
1012
1013 /* Always On (AO) domain gates */
1014
1015 static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
1016 static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
1017 static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
1018 static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
1019 static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
1020
1021 /* Array of all clocks provided by this provider */
1022
1023 static struct clk_hw_onecell_data axg_hw_onecell_data = {
1024         .hws = {
1025                 [CLKID_SYS_PLL]                 = &axg_sys_pll.hw,
1026                 [CLKID_FIXED_PLL]               = &axg_fixed_pll.hw,
1027                 [CLKID_FCLK_DIV2]               = &axg_fclk_div2.hw,
1028                 [CLKID_FCLK_DIV3]               = &axg_fclk_div3.hw,
1029                 [CLKID_FCLK_DIV4]               = &axg_fclk_div4.hw,
1030                 [CLKID_FCLK_DIV5]               = &axg_fclk_div5.hw,
1031                 [CLKID_FCLK_DIV7]               = &axg_fclk_div7.hw,
1032                 [CLKID_GP0_PLL]                 = &axg_gp0_pll.hw,
1033                 [CLKID_MPEG_SEL]                = &axg_mpeg_clk_sel.hw,
1034                 [CLKID_MPEG_DIV]                = &axg_mpeg_clk_div.hw,
1035                 [CLKID_CLK81]                   = &axg_clk81.hw,
1036                 [CLKID_MPLL0]                   = &axg_mpll0.hw,
1037                 [CLKID_MPLL1]                   = &axg_mpll1.hw,
1038                 [CLKID_MPLL2]                   = &axg_mpll2.hw,
1039                 [CLKID_MPLL3]                   = &axg_mpll3.hw,
1040                 [CLKID_DDR]                     = &axg_ddr.hw,
1041                 [CLKID_AUDIO_LOCKER]            = &axg_audio_locker.hw,
1042                 [CLKID_MIPI_DSI_HOST]           = &axg_mipi_dsi_host.hw,
1043                 [CLKID_ISA]                     = &axg_isa.hw,
1044                 [CLKID_PL301]                   = &axg_pl301.hw,
1045                 [CLKID_PERIPHS]                 = &axg_periphs.hw,
1046                 [CLKID_SPICC0]                  = &axg_spicc_0.hw,
1047                 [CLKID_I2C]                     = &axg_i2c.hw,
1048                 [CLKID_RNG0]                    = &axg_rng0.hw,
1049                 [CLKID_UART0]                   = &axg_uart0.hw,
1050                 [CLKID_MIPI_DSI_PHY]            = &axg_mipi_dsi_phy.hw,
1051                 [CLKID_SPICC1]                  = &axg_spicc_1.hw,
1052                 [CLKID_PCIE_A]                  = &axg_pcie_a.hw,
1053                 [CLKID_PCIE_B]                  = &axg_pcie_b.hw,
1054                 [CLKID_HIU_IFACE]               = &axg_hiu_reg.hw,
1055                 [CLKID_ASSIST_MISC]             = &axg_assist_misc.hw,
1056                 [CLKID_SD_EMMC_B]               = &axg_emmc_b.hw,
1057                 [CLKID_SD_EMMC_C]               = &axg_emmc_c.hw,
1058                 [CLKID_DMA]                     = &axg_dma.hw,
1059                 [CLKID_SPI]                     = &axg_spi.hw,
1060                 [CLKID_AUDIO]                   = &axg_audio.hw,
1061                 [CLKID_ETH]                     = &axg_eth_core.hw,
1062                 [CLKID_UART1]                   = &axg_uart1.hw,
1063                 [CLKID_G2D]                     = &axg_g2d.hw,
1064                 [CLKID_USB0]                    = &axg_usb0.hw,
1065                 [CLKID_USB1]                    = &axg_usb1.hw,
1066                 [CLKID_RESET]                   = &axg_reset.hw,
1067                 [CLKID_USB]                     = &axg_usb_general.hw,
1068                 [CLKID_AHB_ARB0]                = &axg_ahb_arb0.hw,
1069                 [CLKID_EFUSE]                   = &axg_efuse.hw,
1070                 [CLKID_BOOT_ROM]                = &axg_boot_rom.hw,
1071                 [CLKID_AHB_DATA_BUS]            = &axg_ahb_data_bus.hw,
1072                 [CLKID_AHB_CTRL_BUS]            = &axg_ahb_ctrl_bus.hw,
1073                 [CLKID_USB1_DDR_BRIDGE]         = &axg_usb1_to_ddr.hw,
1074                 [CLKID_USB0_DDR_BRIDGE]         = &axg_usb0_to_ddr.hw,
1075                 [CLKID_MMC_PCLK]                = &axg_mmc_pclk.hw,
1076                 [CLKID_VPU_INTR]                = &axg_vpu_intr.hw,
1077                 [CLKID_SEC_AHB_AHB3_BRIDGE]     = &axg_sec_ahb_ahb3_bridge.hw,
1078                 [CLKID_GIC]                     = &axg_gic.hw,
1079                 [CLKID_AO_MEDIA_CPU]            = &axg_ao_media_cpu.hw,
1080                 [CLKID_AO_AHB_SRAM]             = &axg_ao_ahb_sram.hw,
1081                 [CLKID_AO_AHB_BUS]              = &axg_ao_ahb_bus.hw,
1082                 [CLKID_AO_IFACE]                = &axg_ao_iface.hw,
1083                 [CLKID_AO_I2C]                  = &axg_ao_i2c.hw,
1084                 [CLKID_SD_EMMC_B_CLK0_SEL]      = &axg_sd_emmc_b_clk0_sel.hw,
1085                 [CLKID_SD_EMMC_B_CLK0_DIV]      = &axg_sd_emmc_b_clk0_div.hw,
1086                 [CLKID_SD_EMMC_B_CLK0]          = &axg_sd_emmc_b_clk0.hw,
1087                 [CLKID_SD_EMMC_C_CLK0_SEL]      = &axg_sd_emmc_c_clk0_sel.hw,
1088                 [CLKID_SD_EMMC_C_CLK0_DIV]      = &axg_sd_emmc_c_clk0_div.hw,
1089                 [CLKID_SD_EMMC_C_CLK0]          = &axg_sd_emmc_c_clk0.hw,
1090                 [CLKID_MPLL0_DIV]               = &axg_mpll0_div.hw,
1091                 [CLKID_MPLL1_DIV]               = &axg_mpll1_div.hw,
1092                 [CLKID_MPLL2_DIV]               = &axg_mpll2_div.hw,
1093                 [CLKID_MPLL3_DIV]               = &axg_mpll3_div.hw,
1094                 [CLKID_HIFI_PLL]                = &axg_hifi_pll.hw,
1095                 [CLKID_MPLL_PREDIV]             = &axg_mpll_prediv.hw,
1096                 [CLKID_FCLK_DIV2_DIV]           = &axg_fclk_div2_div.hw,
1097                 [CLKID_FCLK_DIV3_DIV]           = &axg_fclk_div3_div.hw,
1098                 [CLKID_FCLK_DIV4_DIV]           = &axg_fclk_div4_div.hw,
1099                 [CLKID_FCLK_DIV5_DIV]           = &axg_fclk_div5_div.hw,
1100                 [CLKID_FCLK_DIV7_DIV]           = &axg_fclk_div7_div.hw,
1101                 [CLKID_PCIE_PLL]                = &axg_pcie_pll.hw,
1102                 [CLKID_PCIE_MUX]                = &axg_pcie_mux.hw,
1103                 [CLKID_PCIE_REF]                = &axg_pcie_ref.hw,
1104                 [CLKID_PCIE_CML_EN0]            = &axg_pcie_cml_en0.hw,
1105                 [CLKID_PCIE_CML_EN1]            = &axg_pcie_cml_en1.hw,
1106                 [CLKID_MIPI_ENABLE]             = &axg_mipi_enable.hw,
1107                 [CLKID_GEN_CLK_SEL]             = &axg_gen_clk_sel.hw,
1108                 [CLKID_GEN_CLK_DIV]             = &axg_gen_clk_div.hw,
1109                 [CLKID_GEN_CLK]                 = &axg_gen_clk.hw,
1110                 [NR_CLKS]                       = NULL,
1111         },
1112         .num = NR_CLKS,
1113 };
1114
1115 /* Convenience table to populate regmap in .probe */
1116 static struct clk_regmap *const axg_clk_regmaps[] = {
1117         &axg_clk81,
1118         &axg_ddr,
1119         &axg_audio_locker,
1120         &axg_mipi_dsi_host,
1121         &axg_isa,
1122         &axg_pl301,
1123         &axg_periphs,
1124         &axg_spicc_0,
1125         &axg_i2c,
1126         &axg_rng0,
1127         &axg_uart0,
1128         &axg_mipi_dsi_phy,
1129         &axg_spicc_1,
1130         &axg_pcie_a,
1131         &axg_pcie_b,
1132         &axg_hiu_reg,
1133         &axg_assist_misc,
1134         &axg_emmc_b,
1135         &axg_emmc_c,
1136         &axg_dma,
1137         &axg_spi,
1138         &axg_audio,
1139         &axg_eth_core,
1140         &axg_uart1,
1141         &axg_g2d,
1142         &axg_usb0,
1143         &axg_usb1,
1144         &axg_reset,
1145         &axg_usb_general,
1146         &axg_ahb_arb0,
1147         &axg_efuse,
1148         &axg_boot_rom,
1149         &axg_ahb_data_bus,
1150         &axg_ahb_ctrl_bus,
1151         &axg_usb1_to_ddr,
1152         &axg_usb0_to_ddr,
1153         &axg_mmc_pclk,
1154         &axg_vpu_intr,
1155         &axg_sec_ahb_ahb3_bridge,
1156         &axg_gic,
1157         &axg_ao_media_cpu,
1158         &axg_ao_ahb_sram,
1159         &axg_ao_ahb_bus,
1160         &axg_ao_iface,
1161         &axg_ao_i2c,
1162         &axg_sd_emmc_b_clk0,
1163         &axg_sd_emmc_c_clk0,
1164         &axg_mpeg_clk_div,
1165         &axg_sd_emmc_b_clk0_div,
1166         &axg_sd_emmc_c_clk0_div,
1167         &axg_mpeg_clk_sel,
1168         &axg_sd_emmc_b_clk0_sel,
1169         &axg_sd_emmc_c_clk0_sel,
1170         &axg_mpll0,
1171         &axg_mpll1,
1172         &axg_mpll2,
1173         &axg_mpll3,
1174         &axg_mpll0_div,
1175         &axg_mpll1_div,
1176         &axg_mpll2_div,
1177         &axg_mpll3_div,
1178         &axg_fixed_pll,
1179         &axg_sys_pll,
1180         &axg_gp0_pll,
1181         &axg_hifi_pll,
1182         &axg_mpll_prediv,
1183         &axg_fclk_div2,
1184         &axg_fclk_div3,
1185         &axg_fclk_div4,
1186         &axg_fclk_div5,
1187         &axg_fclk_div7,
1188         &axg_pcie_pll,
1189         &axg_pcie_mux,
1190         &axg_pcie_ref,
1191         &axg_pcie_cml_en0,
1192         &axg_pcie_cml_en1,
1193         &axg_mipi_enable,
1194         &axg_gen_clk_sel,
1195         &axg_gen_clk_div,
1196         &axg_gen_clk,
1197 };
1198
1199 static const struct of_device_id clkc_match_table[] = {
1200         { .compatible = "amlogic,axg-clkc" },
1201         {}
1202 };
1203
1204 static int axg_clkc_probe(struct platform_device *pdev)
1205 {
1206         struct device *dev = &pdev->dev;
1207         struct regmap *map;
1208         int ret, i;
1209
1210         /* Get the hhi system controller node if available */
1211         map = syscon_node_to_regmap(of_get_parent(dev->of_node));
1212         if (IS_ERR(map)) {
1213                 dev_err(dev, "failed to get HHI regmap\n");
1214                 return PTR_ERR(map);
1215         }
1216
1217         /* Populate regmap for the regmap backed clocks */
1218         for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++)
1219                 axg_clk_regmaps[i]->map = map;
1220
1221         for (i = 0; i < axg_hw_onecell_data.num; i++) {
1222                 /* array might be sparse */
1223                 if (!axg_hw_onecell_data.hws[i])
1224                         continue;
1225
1226                 ret = devm_clk_hw_register(dev, axg_hw_onecell_data.hws[i]);
1227                 if (ret) {
1228                         dev_err(dev, "Clock registration failed\n");
1229                         return ret;
1230                 }
1231         }
1232
1233         return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1234                                            &axg_hw_onecell_data);
1235 }
1236
1237 static struct platform_driver axg_driver = {
1238         .probe          = axg_clkc_probe,
1239         .driver         = {
1240                 .name   = "axg-clkc",
1241                 .of_match_table = clkc_match_table,
1242         },
1243 };
1244
1245 builtin_platform_driver(axg_driver);