1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
8 * Copyright (c) 2017 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/init.h>
15 #include <linux/of_device.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
23 static DEFINE_SPINLOCK(meson_clk_lock);
25 static struct clk_regmap axg_fixed_pll_dco = {
26 .data = &(struct meson_clk_pll_data){
28 .reg_off = HHI_MPLL_CNTL,
33 .reg_off = HHI_MPLL_CNTL,
38 .reg_off = HHI_MPLL_CNTL,
43 .reg_off = HHI_MPLL_CNTL2,
48 .reg_off = HHI_MPLL_CNTL,
53 .reg_off = HHI_MPLL_CNTL,
58 .hw.init = &(struct clk_init_data){
59 .name = "fixed_pll_dco",
60 .ops = &meson_clk_pll_ro_ops,
61 .parent_names = (const char *[]){ "xtal" },
66 static struct clk_regmap axg_fixed_pll = {
67 .data = &(struct clk_regmap_div_data){
68 .offset = HHI_MPLL_CNTL,
71 .flags = CLK_DIVIDER_POWER_OF_TWO,
73 .hw.init = &(struct clk_init_data){
75 .ops = &clk_regmap_divider_ro_ops,
76 .parent_names = (const char *[]){ "fixed_pll_dco" },
79 * This clock won't ever change at runtime so
80 * CLK_SET_RATE_PARENT is not required
85 static struct clk_regmap axg_sys_pll_dco = {
86 .data = &(struct meson_clk_pll_data){
88 .reg_off = HHI_SYS_PLL_CNTL,
93 .reg_off = HHI_SYS_PLL_CNTL,
98 .reg_off = HHI_SYS_PLL_CNTL,
103 .reg_off = HHI_SYS_PLL_CNTL,
108 .reg_off = HHI_SYS_PLL_CNTL,
113 .hw.init = &(struct clk_init_data){
114 .name = "sys_pll_dco",
115 .ops = &meson_clk_pll_ro_ops,
116 .parent_names = (const char *[]){ "xtal" },
121 static struct clk_regmap axg_sys_pll = {
122 .data = &(struct clk_regmap_div_data){
123 .offset = HHI_SYS_PLL_CNTL,
126 .flags = CLK_DIVIDER_POWER_OF_TWO,
128 .hw.init = &(struct clk_init_data){
130 .ops = &clk_regmap_divider_ro_ops,
131 .parent_names = (const char *[]){ "sys_pll_dco" },
133 .flags = CLK_SET_RATE_PARENT,
137 static const struct pll_params_table axg_gp0_pll_params_table[] = {
170 static const struct reg_sequence axg_gp0_init_regs[] = {
171 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
172 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
173 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
174 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
175 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
178 static struct clk_regmap axg_gp0_pll_dco = {
179 .data = &(struct meson_clk_pll_data){
181 .reg_off = HHI_GP0_PLL_CNTL,
186 .reg_off = HHI_GP0_PLL_CNTL,
191 .reg_off = HHI_GP0_PLL_CNTL,
196 .reg_off = HHI_GP0_PLL_CNTL1,
201 .reg_off = HHI_GP0_PLL_CNTL,
206 .reg_off = HHI_GP0_PLL_CNTL,
210 .table = axg_gp0_pll_params_table,
211 .init_regs = axg_gp0_init_regs,
212 .init_count = ARRAY_SIZE(axg_gp0_init_regs),
214 .hw.init = &(struct clk_init_data){
215 .name = "gp0_pll_dco",
216 .ops = &meson_clk_pll_ops,
217 .parent_names = (const char *[]){ "xtal" },
222 static struct clk_regmap axg_gp0_pll = {
223 .data = &(struct clk_regmap_div_data){
224 .offset = HHI_GP0_PLL_CNTL,
227 .flags = CLK_DIVIDER_POWER_OF_TWO,
229 .hw.init = &(struct clk_init_data){
231 .ops = &clk_regmap_divider_ops,
232 .parent_names = (const char *[]){ "gp0_pll_dco" },
234 .flags = CLK_SET_RATE_PARENT,
238 static const struct reg_sequence axg_hifi_init_regs[] = {
239 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 },
240 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be },
241 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 },
242 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d },
243 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 },
246 static struct clk_regmap axg_hifi_pll_dco = {
247 .data = &(struct meson_clk_pll_data){
249 .reg_off = HHI_HIFI_PLL_CNTL,
254 .reg_off = HHI_HIFI_PLL_CNTL,
259 .reg_off = HHI_HIFI_PLL_CNTL,
264 .reg_off = HHI_HIFI_PLL_CNTL5,
269 .reg_off = HHI_HIFI_PLL_CNTL,
274 .reg_off = HHI_HIFI_PLL_CNTL,
278 .table = axg_gp0_pll_params_table,
279 .init_regs = axg_hifi_init_regs,
280 .init_count = ARRAY_SIZE(axg_hifi_init_regs),
281 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
283 .hw.init = &(struct clk_init_data){
284 .name = "hifi_pll_dco",
285 .ops = &meson_clk_pll_ops,
286 .parent_names = (const char *[]){ "xtal" },
291 static struct clk_regmap axg_hifi_pll = {
292 .data = &(struct clk_regmap_div_data){
293 .offset = HHI_HIFI_PLL_CNTL,
296 .flags = CLK_DIVIDER_POWER_OF_TWO,
298 .hw.init = &(struct clk_init_data){
300 .ops = &clk_regmap_divider_ops,
301 .parent_names = (const char *[]){ "hifi_pll_dco" },
303 .flags = CLK_SET_RATE_PARENT,
307 static struct clk_fixed_factor axg_fclk_div2_div = {
310 .hw.init = &(struct clk_init_data){
311 .name = "fclk_div2_div",
312 .ops = &clk_fixed_factor_ops,
313 .parent_names = (const char *[]){ "fixed_pll" },
318 static struct clk_regmap axg_fclk_div2 = {
319 .data = &(struct clk_regmap_gate_data){
320 .offset = HHI_MPLL_CNTL6,
323 .hw.init = &(struct clk_init_data){
325 .ops = &clk_regmap_gate_ops,
326 .parent_names = (const char *[]){ "fclk_div2_div" },
331 static struct clk_fixed_factor axg_fclk_div3_div = {
334 .hw.init = &(struct clk_init_data){
335 .name = "fclk_div3_div",
336 .ops = &clk_fixed_factor_ops,
337 .parent_names = (const char *[]){ "fixed_pll" },
342 static struct clk_regmap axg_fclk_div3 = {
343 .data = &(struct clk_regmap_gate_data){
344 .offset = HHI_MPLL_CNTL6,
347 .hw.init = &(struct clk_init_data){
349 .ops = &clk_regmap_gate_ops,
350 .parent_names = (const char *[]){ "fclk_div3_div" },
355 static struct clk_fixed_factor axg_fclk_div4_div = {
358 .hw.init = &(struct clk_init_data){
359 .name = "fclk_div4_div",
360 .ops = &clk_fixed_factor_ops,
361 .parent_names = (const char *[]){ "fixed_pll" },
366 static struct clk_regmap axg_fclk_div4 = {
367 .data = &(struct clk_regmap_gate_data){
368 .offset = HHI_MPLL_CNTL6,
371 .hw.init = &(struct clk_init_data){
373 .ops = &clk_regmap_gate_ops,
374 .parent_names = (const char *[]){ "fclk_div4_div" },
379 static struct clk_fixed_factor axg_fclk_div5_div = {
382 .hw.init = &(struct clk_init_data){
383 .name = "fclk_div5_div",
384 .ops = &clk_fixed_factor_ops,
385 .parent_names = (const char *[]){ "fixed_pll" },
390 static struct clk_regmap axg_fclk_div5 = {
391 .data = &(struct clk_regmap_gate_data){
392 .offset = HHI_MPLL_CNTL6,
395 .hw.init = &(struct clk_init_data){
397 .ops = &clk_regmap_gate_ops,
398 .parent_names = (const char *[]){ "fclk_div5_div" },
403 static struct clk_fixed_factor axg_fclk_div7_div = {
406 .hw.init = &(struct clk_init_data){
407 .name = "fclk_div7_div",
408 .ops = &clk_fixed_factor_ops,
409 .parent_names = (const char *[]){ "fixed_pll" },
414 static struct clk_regmap axg_fclk_div7 = {
415 .data = &(struct clk_regmap_gate_data){
416 .offset = HHI_MPLL_CNTL6,
419 .hw.init = &(struct clk_init_data){
421 .ops = &clk_regmap_gate_ops,
422 .parent_names = (const char *[]){ "fclk_div7_div" },
427 static struct clk_regmap axg_mpll_prediv = {
428 .data = &(struct clk_regmap_div_data){
429 .offset = HHI_MPLL_CNTL5,
433 .hw.init = &(struct clk_init_data){
434 .name = "mpll_prediv",
435 .ops = &clk_regmap_divider_ro_ops,
436 .parent_names = (const char *[]){ "fixed_pll" },
441 static struct clk_regmap axg_mpll0_div = {
442 .data = &(struct meson_clk_mpll_data){
444 .reg_off = HHI_MPLL_CNTL7,
449 .reg_off = HHI_MPLL_CNTL7,
454 .reg_off = HHI_MPLL_CNTL7,
459 .reg_off = HHI_MPLL_CNTL,
464 .reg_off = HHI_PLL_TOP_MISC,
468 .lock = &meson_clk_lock,
469 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
471 .hw.init = &(struct clk_init_data){
473 .ops = &meson_clk_mpll_ops,
474 .parent_names = (const char *[]){ "mpll_prediv" },
479 static struct clk_regmap axg_mpll0 = {
480 .data = &(struct clk_regmap_gate_data){
481 .offset = HHI_MPLL_CNTL7,
484 .hw.init = &(struct clk_init_data){
486 .ops = &clk_regmap_gate_ops,
487 .parent_names = (const char *[]){ "mpll0_div" },
489 .flags = CLK_SET_RATE_PARENT,
493 static struct clk_regmap axg_mpll1_div = {
494 .data = &(struct meson_clk_mpll_data){
496 .reg_off = HHI_MPLL_CNTL8,
501 .reg_off = HHI_MPLL_CNTL8,
506 .reg_off = HHI_MPLL_CNTL8,
511 .reg_off = HHI_PLL_TOP_MISC,
515 .lock = &meson_clk_lock,
516 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
518 .hw.init = &(struct clk_init_data){
520 .ops = &meson_clk_mpll_ops,
521 .parent_names = (const char *[]){ "mpll_prediv" },
526 static struct clk_regmap axg_mpll1 = {
527 .data = &(struct clk_regmap_gate_data){
528 .offset = HHI_MPLL_CNTL8,
531 .hw.init = &(struct clk_init_data){
533 .ops = &clk_regmap_gate_ops,
534 .parent_names = (const char *[]){ "mpll1_div" },
536 .flags = CLK_SET_RATE_PARENT,
540 static struct clk_regmap axg_mpll2_div = {
541 .data = &(struct meson_clk_mpll_data){
543 .reg_off = HHI_MPLL_CNTL9,
548 .reg_off = HHI_MPLL_CNTL9,
553 .reg_off = HHI_MPLL_CNTL9,
558 .reg_off = HHI_PLL_TOP_MISC,
562 .lock = &meson_clk_lock,
563 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
565 .hw.init = &(struct clk_init_data){
567 .ops = &meson_clk_mpll_ops,
568 .parent_names = (const char *[]){ "mpll_prediv" },
573 static struct clk_regmap axg_mpll2 = {
574 .data = &(struct clk_regmap_gate_data){
575 .offset = HHI_MPLL_CNTL9,
578 .hw.init = &(struct clk_init_data){
580 .ops = &clk_regmap_gate_ops,
581 .parent_names = (const char *[]){ "mpll2_div" },
583 .flags = CLK_SET_RATE_PARENT,
587 static struct clk_regmap axg_mpll3_div = {
588 .data = &(struct meson_clk_mpll_data){
590 .reg_off = HHI_MPLL3_CNTL0,
595 .reg_off = HHI_MPLL3_CNTL0,
600 .reg_off = HHI_MPLL3_CNTL0,
605 .reg_off = HHI_PLL_TOP_MISC,
609 .lock = &meson_clk_lock,
610 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
612 .hw.init = &(struct clk_init_data){
614 .ops = &meson_clk_mpll_ops,
615 .parent_names = (const char *[]){ "mpll_prediv" },
620 static struct clk_regmap axg_mpll3 = {
621 .data = &(struct clk_regmap_gate_data){
622 .offset = HHI_MPLL3_CNTL0,
625 .hw.init = &(struct clk_init_data){
627 .ops = &clk_regmap_gate_ops,
628 .parent_names = (const char *[]){ "mpll3_div" },
630 .flags = CLK_SET_RATE_PARENT,
634 static const struct pll_params_table axg_pcie_pll_params_table[] = {
642 static const struct reg_sequence axg_pcie_init_regs[] = {
643 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa },
644 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be },
645 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e },
646 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d },
647 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 },
648 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 },
649 { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 },
652 static struct clk_regmap axg_pcie_pll_dco = {
653 .data = &(struct meson_clk_pll_data){
655 .reg_off = HHI_PCIE_PLL_CNTL,
660 .reg_off = HHI_PCIE_PLL_CNTL,
665 .reg_off = HHI_PCIE_PLL_CNTL,
670 .reg_off = HHI_PCIE_PLL_CNTL1,
675 .reg_off = HHI_PCIE_PLL_CNTL,
680 .reg_off = HHI_PCIE_PLL_CNTL,
684 .table = axg_pcie_pll_params_table,
685 .init_regs = axg_pcie_init_regs,
686 .init_count = ARRAY_SIZE(axg_pcie_init_regs),
688 .hw.init = &(struct clk_init_data){
689 .name = "pcie_pll_dco",
690 .ops = &meson_clk_pll_ops,
691 .parent_names = (const char *[]){ "xtal" },
696 static struct clk_regmap axg_pcie_pll_od = {
697 .data = &(struct clk_regmap_div_data){
698 .offset = HHI_PCIE_PLL_CNTL,
701 .flags = CLK_DIVIDER_POWER_OF_TWO,
703 .hw.init = &(struct clk_init_data){
704 .name = "pcie_pll_od",
705 .ops = &clk_regmap_divider_ops,
706 .parent_names = (const char *[]){ "pcie_pll_dco" },
708 .flags = CLK_SET_RATE_PARENT,
712 static struct clk_regmap axg_pcie_pll = {
713 .data = &(struct clk_regmap_div_data){
714 .offset = HHI_PCIE_PLL_CNTL6,
717 .flags = CLK_DIVIDER_POWER_OF_TWO,
719 .hw.init = &(struct clk_init_data){
721 .ops = &clk_regmap_divider_ops,
722 .parent_names = (const char *[]){ "pcie_pll_od" },
724 .flags = CLK_SET_RATE_PARENT,
728 static struct clk_regmap axg_pcie_mux = {
729 .data = &(struct clk_regmap_mux_data){
730 .offset = HHI_PCIE_PLL_CNTL6,
733 /* skip the parent mpll3, reserved for debug */
734 .table = (u32[]){ 1 },
736 .hw.init = &(struct clk_init_data){
738 .ops = &clk_regmap_mux_ops,
739 .parent_names = (const char *[]){ "pcie_pll" },
741 .flags = CLK_SET_RATE_PARENT,
745 static struct clk_regmap axg_pcie_ref = {
746 .data = &(struct clk_regmap_mux_data){
747 .offset = HHI_PCIE_PLL_CNTL6,
750 /* skip the parent 0, reserved for debug */
751 .table = (u32[]){ 1 },
753 .hw.init = &(struct clk_init_data){
755 .ops = &clk_regmap_mux_ops,
756 .parent_names = (const char *[]){ "pcie_mux" },
758 .flags = CLK_SET_RATE_PARENT,
762 static struct clk_regmap axg_pcie_cml_en0 = {
763 .data = &(struct clk_regmap_gate_data){
764 .offset = HHI_PCIE_PLL_CNTL6,
767 .hw.init = &(struct clk_init_data) {
768 .name = "pcie_cml_en0",
769 .ops = &clk_regmap_gate_ops,
770 .parent_names = (const char *[]){ "pcie_ref" },
772 .flags = CLK_SET_RATE_PARENT,
777 static struct clk_regmap axg_pcie_cml_en1 = {
778 .data = &(struct clk_regmap_gate_data){
779 .offset = HHI_PCIE_PLL_CNTL6,
782 .hw.init = &(struct clk_init_data) {
783 .name = "pcie_cml_en1",
784 .ops = &clk_regmap_gate_ops,
785 .parent_names = (const char *[]){ "pcie_ref" },
787 .flags = CLK_SET_RATE_PARENT,
791 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
792 static const char * const clk81_parent_names[] = {
793 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
794 "fclk_div3", "fclk_div5"
797 static struct clk_regmap axg_mpeg_clk_sel = {
798 .data = &(struct clk_regmap_mux_data){
799 .offset = HHI_MPEG_CLK_CNTL,
802 .table = mux_table_clk81,
804 .hw.init = &(struct clk_init_data){
805 .name = "mpeg_clk_sel",
806 .ops = &clk_regmap_mux_ro_ops,
807 .parent_names = clk81_parent_names,
808 .num_parents = ARRAY_SIZE(clk81_parent_names),
812 static struct clk_regmap axg_mpeg_clk_div = {
813 .data = &(struct clk_regmap_div_data){
814 .offset = HHI_MPEG_CLK_CNTL,
818 .hw.init = &(struct clk_init_data){
819 .name = "mpeg_clk_div",
820 .ops = &clk_regmap_divider_ops,
821 .parent_names = (const char *[]){ "mpeg_clk_sel" },
823 .flags = CLK_SET_RATE_PARENT,
827 static struct clk_regmap axg_clk81 = {
828 .data = &(struct clk_regmap_gate_data){
829 .offset = HHI_MPEG_CLK_CNTL,
832 .hw.init = &(struct clk_init_data){
834 .ops = &clk_regmap_gate_ops,
835 .parent_names = (const char *[]){ "mpeg_clk_div" },
837 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
841 static const char * const axg_sd_emmc_clk0_parent_names[] = {
842 "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
845 * Following these parent clocks, we should also have had mpll2, mpll3
846 * and gp0_pll but these clocks are too precious to be used here. All
847 * the necessary rates for MMC and NAND operation can be acheived using
848 * xtal or fclk_div clocks
853 static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
854 .data = &(struct clk_regmap_mux_data){
855 .offset = HHI_SD_EMMC_CLK_CNTL,
859 .hw.init = &(struct clk_init_data) {
860 .name = "sd_emmc_b_clk0_sel",
861 .ops = &clk_regmap_mux_ops,
862 .parent_names = axg_sd_emmc_clk0_parent_names,
863 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
864 .flags = CLK_SET_RATE_PARENT,
868 static struct clk_regmap axg_sd_emmc_b_clk0_div = {
869 .data = &(struct clk_regmap_div_data){
870 .offset = HHI_SD_EMMC_CLK_CNTL,
873 .flags = CLK_DIVIDER_ROUND_CLOSEST,
875 .hw.init = &(struct clk_init_data) {
876 .name = "sd_emmc_b_clk0_div",
877 .ops = &clk_regmap_divider_ops,
878 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
880 .flags = CLK_SET_RATE_PARENT,
884 static struct clk_regmap axg_sd_emmc_b_clk0 = {
885 .data = &(struct clk_regmap_gate_data){
886 .offset = HHI_SD_EMMC_CLK_CNTL,
889 .hw.init = &(struct clk_init_data){
890 .name = "sd_emmc_b_clk0",
891 .ops = &clk_regmap_gate_ops,
892 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
894 .flags = CLK_SET_RATE_PARENT,
898 /* EMMC/NAND clock */
899 static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
900 .data = &(struct clk_regmap_mux_data){
901 .offset = HHI_NAND_CLK_CNTL,
905 .hw.init = &(struct clk_init_data) {
906 .name = "sd_emmc_c_clk0_sel",
907 .ops = &clk_regmap_mux_ops,
908 .parent_names = axg_sd_emmc_clk0_parent_names,
909 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
910 .flags = CLK_SET_RATE_PARENT,
914 static struct clk_regmap axg_sd_emmc_c_clk0_div = {
915 .data = &(struct clk_regmap_div_data){
916 .offset = HHI_NAND_CLK_CNTL,
919 .flags = CLK_DIVIDER_ROUND_CLOSEST,
921 .hw.init = &(struct clk_init_data) {
922 .name = "sd_emmc_c_clk0_div",
923 .ops = &clk_regmap_divider_ops,
924 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
926 .flags = CLK_SET_RATE_PARENT,
930 static struct clk_regmap axg_sd_emmc_c_clk0 = {
931 .data = &(struct clk_regmap_gate_data){
932 .offset = HHI_NAND_CLK_CNTL,
935 .hw.init = &(struct clk_init_data){
936 .name = "sd_emmc_c_clk0",
937 .ops = &clk_regmap_gate_ops,
938 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
940 .flags = CLK_SET_RATE_PARENT,
944 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
945 9, 10, 11, 13, 14, };
946 static const char * const gen_clk_parent_names[] = {
947 "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3",
948 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
951 static struct clk_regmap axg_gen_clk_sel = {
952 .data = &(struct clk_regmap_mux_data){
953 .offset = HHI_GEN_CLK_CNTL,
956 .table = mux_table_gen_clk,
958 .hw.init = &(struct clk_init_data){
959 .name = "gen_clk_sel",
960 .ops = &clk_regmap_mux_ops,
962 * bits 15:12 selects from 14 possible parents:
963 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
964 * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
965 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
967 .parent_names = gen_clk_parent_names,
968 .num_parents = ARRAY_SIZE(gen_clk_parent_names),
972 static struct clk_regmap axg_gen_clk_div = {
973 .data = &(struct clk_regmap_div_data){
974 .offset = HHI_GEN_CLK_CNTL,
978 .hw.init = &(struct clk_init_data){
979 .name = "gen_clk_div",
980 .ops = &clk_regmap_divider_ops,
981 .parent_names = (const char *[]){ "gen_clk_sel" },
983 .flags = CLK_SET_RATE_PARENT,
987 static struct clk_regmap axg_gen_clk = {
988 .data = &(struct clk_regmap_gate_data){
989 .offset = HHI_GEN_CLK_CNTL,
992 .hw.init = &(struct clk_init_data){
994 .ops = &clk_regmap_gate_ops,
995 .parent_names = (const char *[]){ "gen_clk_div" },
997 .flags = CLK_SET_RATE_PARENT,
1001 /* Everything Else (EE) domain gates */
1002 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
1003 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
1004 static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
1005 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
1006 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
1007 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
1008 static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
1009 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
1010 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
1011 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
1012 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
1013 static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
1014 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
1015 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
1016 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
1017 static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
1018 static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
1019 static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
1020 static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
1021 static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
1023 static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
1024 static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
1025 static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
1026 static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
1027 static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
1028 static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
1029 static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
1030 static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
1031 static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
1032 static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
1033 static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
1035 static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1036 static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1037 static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
1038 static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
1039 static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
1040 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
1041 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1042 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
1043 static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29);
1045 /* Always On (AO) domain gates */
1047 static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
1048 static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
1049 static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
1050 static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
1051 static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
1053 /* Array of all clocks provided by this provider */
1055 static struct clk_hw_onecell_data axg_hw_onecell_data = {
1057 [CLKID_SYS_PLL] = &axg_sys_pll.hw,
1058 [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
1059 [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
1060 [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
1061 [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
1062 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
1063 [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
1064 [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
1065 [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
1066 [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
1067 [CLKID_CLK81] = &axg_clk81.hw,
1068 [CLKID_MPLL0] = &axg_mpll0.hw,
1069 [CLKID_MPLL1] = &axg_mpll1.hw,
1070 [CLKID_MPLL2] = &axg_mpll2.hw,
1071 [CLKID_MPLL3] = &axg_mpll3.hw,
1072 [CLKID_DDR] = &axg_ddr.hw,
1073 [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
1074 [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
1075 [CLKID_ISA] = &axg_isa.hw,
1076 [CLKID_PL301] = &axg_pl301.hw,
1077 [CLKID_PERIPHS] = &axg_periphs.hw,
1078 [CLKID_SPICC0] = &axg_spicc_0.hw,
1079 [CLKID_I2C] = &axg_i2c.hw,
1080 [CLKID_RNG0] = &axg_rng0.hw,
1081 [CLKID_UART0] = &axg_uart0.hw,
1082 [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
1083 [CLKID_SPICC1] = &axg_spicc_1.hw,
1084 [CLKID_PCIE_A] = &axg_pcie_a.hw,
1085 [CLKID_PCIE_B] = &axg_pcie_b.hw,
1086 [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
1087 [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
1088 [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
1089 [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
1090 [CLKID_DMA] = &axg_dma.hw,
1091 [CLKID_SPI] = &axg_spi.hw,
1092 [CLKID_AUDIO] = &axg_audio.hw,
1093 [CLKID_ETH] = &axg_eth_core.hw,
1094 [CLKID_UART1] = &axg_uart1.hw,
1095 [CLKID_G2D] = &axg_g2d.hw,
1096 [CLKID_USB0] = &axg_usb0.hw,
1097 [CLKID_USB1] = &axg_usb1.hw,
1098 [CLKID_RESET] = &axg_reset.hw,
1099 [CLKID_USB] = &axg_usb_general.hw,
1100 [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
1101 [CLKID_EFUSE] = &axg_efuse.hw,
1102 [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
1103 [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
1104 [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
1105 [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
1106 [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
1107 [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
1108 [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
1109 [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
1110 [CLKID_GIC] = &axg_gic.hw,
1111 [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
1112 [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
1113 [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
1114 [CLKID_AO_IFACE] = &axg_ao_iface.hw,
1115 [CLKID_AO_I2C] = &axg_ao_i2c.hw,
1116 [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
1117 [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
1118 [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
1119 [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
1120 [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
1121 [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
1122 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
1123 [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
1124 [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
1125 [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
1126 [CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
1127 [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
1128 [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
1129 [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
1130 [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
1131 [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
1132 [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
1133 [CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
1134 [CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
1135 [CLKID_PCIE_REF] = &axg_pcie_ref.hw,
1136 [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
1137 [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
1138 [CLKID_MIPI_ENABLE] = &axg_mipi_enable.hw,
1139 [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
1140 [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
1141 [CLKID_GEN_CLK] = &axg_gen_clk.hw,
1142 [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
1143 [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
1144 [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
1145 [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
1146 [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
1147 [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
1153 /* Convenience table to populate regmap in .probe */
1154 static struct clk_regmap *const axg_clk_regmaps[] = {
1193 &axg_sec_ahb_ahb3_bridge,
1200 &axg_sd_emmc_b_clk0,
1201 &axg_sd_emmc_c_clk0,
1203 &axg_sd_emmc_b_clk0_div,
1204 &axg_sd_emmc_c_clk0_div,
1206 &axg_sd_emmc_b_clk0_sel,
1207 &axg_sd_emmc_c_clk0_sel,
1245 static const struct of_device_id clkc_match_table[] = {
1246 { .compatible = "amlogic,axg-clkc" },
1250 static int axg_clkc_probe(struct platform_device *pdev)
1252 struct device *dev = &pdev->dev;
1256 /* Get the hhi system controller node if available */
1257 map = syscon_node_to_regmap(of_get_parent(dev->of_node));
1259 dev_err(dev, "failed to get HHI regmap\n");
1260 return PTR_ERR(map);
1263 /* Populate regmap for the regmap backed clocks */
1264 for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++)
1265 axg_clk_regmaps[i]->map = map;
1267 for (i = 0; i < axg_hw_onecell_data.num; i++) {
1268 /* array might be sparse */
1269 if (!axg_hw_onecell_data.hws[i])
1272 ret = devm_clk_hw_register(dev, axg_hw_onecell_data.hws[i]);
1274 dev_err(dev, "Clock registration failed\n");
1279 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1280 &axg_hw_onecell_data);
1283 static struct platform_driver axg_driver = {
1284 .probe = axg_clkc_probe,
1287 .of_match_table = clkc_match_table,
1291 builtin_platform_driver(axg_driver);