drivers/clk/imx/clk-pll14xx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2017-2018 NXP.
   4  */
   5
   6 #include <linux/bitops.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/err.h>
   9 #include <linux/io.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/slab.h>
  12 #include <linux/jiffies.h>
  13
  14 #include "clk.h"
  15
  16 #define GNRL_CTL        0x0
  17 #define DIV_CTL         0x4
  18 #define LOCK_STATUS     BIT(31)
  19 #define LOCK_SEL_MASK   BIT(29)
  20 #define CLKE_MASK       BIT(11)
  21 #define RST_MASK        BIT(9)
  22 #define BYPASS_MASK     BIT(4)
  23 #define MDIV_SHIFT      12
  24 #define MDIV_MASK       GENMASK(21, 12)
  25 #define PDIV_SHIFT      4
  26 #define PDIV_MASK       GENMASK(9, 4)
  27 #define SDIV_SHIFT      0
  28 #define SDIV_MASK       GENMASK(2, 0)
  29 #define KDIV_SHIFT      0
  30 #define KDIV_MASK       GENMASK(15, 0)
  31
  32 #define LOCK_TIMEOUT_US         10000
  33
  34 struct clk_pll14xx {
  35         struct clk_hw                   hw;
  36         void __iomem                    *base;
  37         enum imx_pll14xx_type           type;
  38         const struct imx_pll14xx_rate_table *rate_table;
  39         int rate_count;
  40 };
  41
  42 #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw)
  43
  44 static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
  45                 struct clk_pll14xx *pll, unsigned long rate)
  46 {
  47         const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
  48         int i;
  49
  50         for (i = 0; i < pll->rate_count; i++)
  51                 if (rate == rate_table[i].rate)
  52                         return &rate_table[i];
  53
  54         return NULL;
  55 }
  56
  57 static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate,
  58                         unsigned long *prate)
  59 {
  60         struct clk_pll14xx *pll = to_clk_pll14xx(hw);
  61         const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
  62         int i;
  63
  64         /* Assumming rate_table is in descending order */
  65         for (i = 0; i < pll->rate_count; i++)
  66                 if (rate >= rate_table[i].rate)
  67                         return rate_table[i].rate;
  68
  69         /* return minimum supported value */
  70         return rate_table[i - 1].rate;
  71 }
  72
  73 static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw,
  74                                                   unsigned long parent_rate)
  75 {
  76         struct clk_pll14xx *pll = to_clk_pll14xx(hw);
  77         u32 mdiv, pdiv, sdiv, pll_gnrl, pll_div;
  78         u64 fvco = parent_rate;
  79
  80         pll_gnrl = readl_relaxed(pll->base);
  81         pll_div = readl_relaxed(pll->base + 4);
  82         mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
  83         pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
  84         sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
  85
  86         fvco *= mdiv;
  87         do_div(fvco, pdiv << sdiv);
  88
  89         return fvco;
  90 }
  91
  92 static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw,
  93                                                   unsigned long parent_rate)
  94 {
  95         struct clk_pll14xx *pll = to_clk_pll14xx(hw);
  96         u32 mdiv, pdiv, sdiv, pll_gnrl, pll_div_ctl0, pll_div_ctl1;
  97         short int kdiv;
  98         u64 fvco = parent_rate;
  99
 100         pll_gnrl = readl_relaxed(pll->base);
 101         pll_div_ctl0 = readl_relaxed(pll->base + 4);
 102         pll_div_ctl1 = readl_relaxed(pll->base + 8);
 103         mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
 104         pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
 105         sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
 106         kdiv = pll_div_ctl1 & KDIV_MASK;
 107
 108         /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
 109         fvco *= (mdiv * 65536 + kdiv);
 110         pdiv *= 65536;
 111
 112         do_div(fvco, pdiv << sdiv);
 113
 114         return fvco;
 115 }
 116
 117 static inline bool clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table *rate,
 118                                           u32 pll_div)
 119 {
 120         u32 old_mdiv, old_pdiv;
 121
 122         old_mdiv = (pll_div >> MDIV_SHIFT) & MDIV_MASK;
 123         old_pdiv = (pll_div >> PDIV_SHIFT) & PDIV_MASK;
 124
 125         return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
 126 }
 127
 128 static inline bool clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table *rate,
 129                                           u32 pll_div_ctl0, u32 pll_div_ctl1)
 130 {
 131         u32 old_mdiv, old_pdiv, old_kdiv;
 132
 133         old_mdiv = (pll_div_ctl0 >> MDIV_SHIFT) & MDIV_MASK;
 134         old_pdiv = (pll_div_ctl0 >> PDIV_SHIFT) & PDIV_MASK;
 135         old_kdiv = (pll_div_ctl1 >> KDIV_SHIFT) & KDIV_MASK;
 136
 137         return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
 138                 rate->kdiv != old_kdiv;
 139 }
 140
 141 static inline bool clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table *rate,
 142                                           u32 pll_div_ctl0, u32 pll_div_ctl1)
 143 {
 144         u32 old_mdiv, old_pdiv, old_kdiv;
 145
 146         old_mdiv = (pll_div_ctl0 >> MDIV_SHIFT) & MDIV_MASK;
 147         old_pdiv = (pll_div_ctl0 >> PDIV_SHIFT) & PDIV_MASK;
 148         old_kdiv = (pll_div_ctl1 >> KDIV_SHIFT) & KDIV_MASK;
 149
 150         return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
 151                 rate->kdiv != old_kdiv;
 152 }
 153
 154 static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
 155 {
 156         u32 val;
 157
 158         return readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US, 0,
 159                         LOCK_TIMEOUT_US);
 160 }
 161
 162 static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
 163                                  unsigned long prate)
 164 {
 165         struct clk_pll14xx *pll = to_clk_pll14xx(hw);
 166         const struct imx_pll14xx_rate_table *rate;
 167         u32 tmp, div_val;
 168         int ret;
 169
 170         rate = imx_get_pll_settings(pll, drate);
 171         if (!rate) {
 172                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 173                        drate, clk_hw_get_name(hw));
 174                 return -EINVAL;
 175         }
 176
 177         tmp = readl_relaxed(pll->base + 4);
 178
 179         if (!clk_pll1416x_mp_change(rate, tmp)) {
 180                 tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
 181                 tmp |= rate->sdiv << SDIV_SHIFT;
 182                 writel_relaxed(tmp, pll->base + 4);
 183
 184                 return 0;
 185         }
 186
 187         /* Bypass clock and set lock to pll output lock */
 188         tmp = readl_relaxed(pll->base);
 189         tmp |= LOCK_SEL_MASK;
 190         writel_relaxed(tmp, pll->base);
 191
 192         /* Enable RST */
 193         tmp &= ~RST_MASK;
 194         writel_relaxed(tmp, pll->base);
 195
 196         div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
 197                 (rate->sdiv << SDIV_SHIFT);
 198         writel_relaxed(div_val, pll->base + 0x4);
 199
 200         /*
 201          * According to SPEC, t3 - t2 need to be greater than
 202          * 1us and 1/FREF, respectively.
 203          * FREF is FIN / Prediv, the prediv is [1, 63], so choose
 204          * 3us.
 205          */
 206         udelay(3);
 207
 208         /* Disable RST */
 209         tmp |= RST_MASK;
 210         writel_relaxed(tmp, pll->base);
 211
 212         /* Wait Lock */
 213         ret = clk_pll14xx_wait_lock(pll);
 214         if (ret)
 215                 return ret;
 216
 217         /* Bypass */
 218         tmp &= ~BYPASS_MASK;
 219         writel_relaxed(tmp, pll->base);
 220
 221         return 0;
 222 }
 223
 224 static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
 225                                  unsigned long prate)
 226 {
 227         struct clk_pll14xx *pll = to_clk_pll14xx(hw);
 228         const struct imx_pll14xx_rate_table *rate;
 229         u32 tmp, div_val;
 230         int ret;
 231
 232         rate = imx_get_pll_settings(pll, drate);
 233         if (!rate) {
 234                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 235                         drate, clk_hw_get_name(hw));
 236                 return -EINVAL;
 237         }
 238
 239         tmp = readl_relaxed(pll->base + 4);
 240         div_val = readl_relaxed(pll->base + 8);
 241
 242         if (!clk_pll1443x_mpk_change(rate, tmp, div_val)) {
 243                 tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
 244                 tmp |= rate->sdiv << SDIV_SHIFT;
 245                 writel_relaxed(tmp, pll->base + 4);
 246
 247                 return 0;
 248         }
 249
 250         /* Enable RST */
 251         tmp = readl_relaxed(pll->base);
 252         tmp &= ~RST_MASK;
 253         writel_relaxed(tmp, pll->base);
 254
 255         div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
 256                 (rate->sdiv << SDIV_SHIFT);
 257         writel_relaxed(div_val, pll->base + 0x4);
 258         writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);
 259
 260         /*
 261          * According to SPEC, t3 - t2 need to be greater than
 262          * 1us and 1/FREF, respectively.
 263          * FREF is FIN / Prediv, the prediv is [1, 63], so choose
 264          * 3us.
 265          */
 266         udelay(3);
 267
 268         /* Disable RST */
 269         tmp |= RST_MASK;
 270         writel_relaxed(tmp, pll->base);
 271
 272         /* Wait Lock*/
 273         ret = clk_pll14xx_wait_lock(pll);
 274         if (ret)
 275                 return ret;
 276
 277         /* Bypass */
 278         tmp &= ~BYPASS_MASK;
 279         writel_relaxed(tmp, pll->base);
 280
 281         return 0;
 282 }
 283
 284 static int clk_pll14xx_prepare(struct clk_hw *hw)
 285 {
 286         struct clk_pll14xx *pll = to_clk_pll14xx(hw);
 287         u32 val;
 288
 289         /*
 290          * RESETB = 1 from 0, PLL starts its normal
 291          * operation after lock time
 292          */
 293         val = readl_relaxed(pll->base + GNRL_CTL);
 294         val |= RST_MASK;
 295         writel_relaxed(val, pll->base + GNRL_CTL);
 296
 297         return clk_pll14xx_wait_lock(pll);
 298 }
 299
 300 static int clk_pll14xx_is_prepared(struct clk_hw *hw)
 301 {
 302         struct clk_pll14xx *pll = to_clk_pll14xx(hw);
 303         u32 val;
 304
 305         val = readl_relaxed(pll->base + GNRL_CTL);
 306
 307         return (val & RST_MASK) ? 1 : 0;
 308 }
 309
 310 static void clk_pll14xx_unprepare(struct clk_hw *hw)
 311 {
 312         struct clk_pll14xx *pll = to_clk_pll14xx(hw);
 313         u32 val;
 314
 315         /*
 316          * Set RST to 0, power down mode is enabled and
 317          * every digital block is reset
 318          */
 319         val = readl_relaxed(pll->base + GNRL_CTL);
 320         val &= ~RST_MASK;
 321         writel_relaxed(val, pll->base + GNRL_CTL);
 322 }
 323
 324 static const struct clk_ops clk_pll1416x_ops = {
 325         .prepare        = clk_pll14xx_prepare,
 326         .unprepare      = clk_pll14xx_unprepare,
 327         .is_prepared    = clk_pll14xx_is_prepared,
 328         .recalc_rate    = clk_pll1416x_recalc_rate,
 329         .round_rate     = clk_pll14xx_round_rate,
 330         .set_rate       = clk_pll1416x_set_rate,
 331 };
 332
 333 static const struct clk_ops clk_pll1416x_min_ops = {
 334         .recalc_rate    = clk_pll1416x_recalc_rate,
 335 };
 336
 337 static const struct clk_ops clk_pll1443x_ops = {
 338         .prepare        = clk_pll14xx_prepare,
 339         .unprepare      = clk_pll14xx_unprepare,
 340         .is_prepared    = clk_pll14xx_is_prepared,
 341         .recalc_rate    = clk_pll1443x_recalc_rate,
 342         .round_rate     = clk_pll14xx_round_rate,
 343         .set_rate       = clk_pll1443x_set_rate,
 344 };
 345
 346 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
 347                             void __iomem *base,
 348                             const struct imx_pll14xx_clk *pll_clk)
 349 {
 350         struct clk_pll14xx *pll;
 351         struct clk *clk;
 352         struct clk_init_data init;
 353
 354         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 355         if (!pll)
 356                 return ERR_PTR(-ENOMEM);
 357
 358         init.name = name;
 359         init.flags = pll_clk->flags;
 360         init.parent_names = &parent_name;
 361         init.num_parents = 1;
 362
 363         switch (pll_clk->type) {
 364         case PLL_1416X:
 365                 if (!pll_clk->rate_table)
 366                         init.ops = &clk_pll1416x_min_ops;
 367                 else
 368                         init.ops = &clk_pll1416x_ops;
 369                 break;
 370         case PLL_1443X:
 371                 init.ops = &clk_pll1443x_ops;
 372                 break;
 373         default:
 374                 pr_err("%s: Unknown pll type for pll clk %s\n",
 375                        __func__, name);
 376         };
 377
 378         pll->base = base;
 379         pll->hw.init = &init;
 380         pll->type = pll_clk->type;
 381         pll->rate_table = pll_clk->rate_table;
 382         pll->rate_count = pll_clk->rate_count;
 383
 384         clk = clk_register(NULL, &pll->hw);
 385         if (IS_ERR(clk)) {
 386                 pr_err("%s: failed to register pll %s %lu\n",
 387                         __func__, name, PTR_ERR(clk));
 388                 kfree(pll);
 389         }
 390
 391         return clk;
 392 }