1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 #include <linux/clk-provider.h>
7 #include <linux/clkdev.h>
8 #include <linux/clk/at91_pmc.h>
9 #include <linux/delay.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/regmap.h>
15 #define SLOW_CLOCK_FREQ 32768
17 #define MAINFRDY_TIMEOUT (((MAINF_DIV + 1) * USEC_PER_SEC) / \
19 #define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ)
20 #define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT
22 #define MOR_KEY_MASK (0xff << 16)
26 struct regmap *regmap;
29 #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)
31 struct clk_main_rc_osc {
33 struct regmap *regmap;
34 unsigned long frequency;
35 unsigned long accuracy;
38 #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)
40 struct clk_rm9200_main {
42 struct regmap *regmap;
45 #define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw)
47 struct clk_sam9x5_main {
49 struct regmap *regmap;
53 #define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw)
55 static inline bool clk_main_osc_ready(struct regmap *regmap)
59 regmap_read(regmap, AT91_PMC_SR, &status);
61 return status & AT91_PMC_MOSCS;
64 static int clk_main_osc_prepare(struct clk_hw *hw)
66 struct clk_main_osc *osc = to_clk_main_osc(hw);
67 struct regmap *regmap = osc->regmap;
70 regmap_read(regmap, AT91_CKGR_MOR, &tmp);
73 if (tmp & AT91_PMC_OSCBYPASS)
76 if (!(tmp & AT91_PMC_MOSCEN)) {
77 tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY;
78 regmap_write(regmap, AT91_CKGR_MOR, tmp);
81 while (!clk_main_osc_ready(regmap))
87 static void clk_main_osc_unprepare(struct clk_hw *hw)
89 struct clk_main_osc *osc = to_clk_main_osc(hw);
90 struct regmap *regmap = osc->regmap;
93 regmap_read(regmap, AT91_CKGR_MOR, &tmp);
94 if (tmp & AT91_PMC_OSCBYPASS)
97 if (!(tmp & AT91_PMC_MOSCEN))
100 tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN);
101 regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_KEY);
104 static int clk_main_osc_is_prepared(struct clk_hw *hw)
106 struct clk_main_osc *osc = to_clk_main_osc(hw);
107 struct regmap *regmap = osc->regmap;
110 regmap_read(regmap, AT91_CKGR_MOR, &tmp);
111 if (tmp & AT91_PMC_OSCBYPASS)
114 regmap_read(regmap, AT91_PMC_SR, &status);
116 return (status & AT91_PMC_MOSCS) && (tmp & AT91_PMC_MOSCEN);
119 static const struct clk_ops main_osc_ops = {
120 .prepare = clk_main_osc_prepare,
121 .unprepare = clk_main_osc_unprepare,
122 .is_prepared = clk_main_osc_is_prepared,
125 struct clk_hw * __init
126 at91_clk_register_main_osc(struct regmap *regmap,
128 const char *parent_name,
131 struct clk_main_osc *osc;
132 struct clk_init_data init;
136 if (!name || !parent_name)
137 return ERR_PTR(-EINVAL);
139 osc = kzalloc(sizeof(*osc), GFP_KERNEL);
141 return ERR_PTR(-ENOMEM);
144 init.ops = &main_osc_ops;
145 init.parent_names = &parent_name;
146 init.num_parents = 1;
147 init.flags = CLK_IGNORE_UNUSED;
149 osc->hw.init = &init;
150 osc->regmap = regmap;
153 regmap_update_bits(regmap,
154 AT91_CKGR_MOR, MOR_KEY_MASK |
156 AT91_PMC_OSCBYPASS | AT91_PMC_KEY);
159 ret = clk_hw_register(NULL, &osc->hw);
168 static bool clk_main_rc_osc_ready(struct regmap *regmap)
172 regmap_read(regmap, AT91_PMC_SR, &status);
174 return status & AT91_PMC_MOSCRCS;
177 static int clk_main_rc_osc_prepare(struct clk_hw *hw)
179 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
180 struct regmap *regmap = osc->regmap;
183 regmap_read(regmap, AT91_CKGR_MOR, &mor);
185 if (!(mor & AT91_PMC_MOSCRCEN))
186 regmap_update_bits(regmap, AT91_CKGR_MOR,
187 MOR_KEY_MASK | AT91_PMC_MOSCRCEN,
188 AT91_PMC_MOSCRCEN | AT91_PMC_KEY);
190 while (!clk_main_rc_osc_ready(regmap))
196 static void clk_main_rc_osc_unprepare(struct clk_hw *hw)
198 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
199 struct regmap *regmap = osc->regmap;
202 regmap_read(regmap, AT91_CKGR_MOR, &mor);
204 if (!(mor & AT91_PMC_MOSCRCEN))
207 regmap_update_bits(regmap, AT91_CKGR_MOR,
208 MOR_KEY_MASK | AT91_PMC_MOSCRCEN, AT91_PMC_KEY);
211 static int clk_main_rc_osc_is_prepared(struct clk_hw *hw)
213 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
214 struct regmap *regmap = osc->regmap;
215 unsigned int mor, status;
217 regmap_read(regmap, AT91_CKGR_MOR, &mor);
218 regmap_read(regmap, AT91_PMC_SR, &status);
220 return (mor & AT91_PMC_MOSCRCEN) && (status & AT91_PMC_MOSCRCS);
223 static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw,
224 unsigned long parent_rate)
226 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
228 return osc->frequency;
231 static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw,
232 unsigned long parent_acc)
234 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
236 return osc->accuracy;
239 static const struct clk_ops main_rc_osc_ops = {
240 .prepare = clk_main_rc_osc_prepare,
241 .unprepare = clk_main_rc_osc_unprepare,
242 .is_prepared = clk_main_rc_osc_is_prepared,
243 .recalc_rate = clk_main_rc_osc_recalc_rate,
244 .recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
247 struct clk_hw * __init
248 at91_clk_register_main_rc_osc(struct regmap *regmap,
250 u32 frequency, u32 accuracy)
252 struct clk_main_rc_osc *osc;
253 struct clk_init_data init;
257 if (!name || !frequency)
258 return ERR_PTR(-EINVAL);
260 osc = kzalloc(sizeof(*osc), GFP_KERNEL);
262 return ERR_PTR(-ENOMEM);
265 init.ops = &main_rc_osc_ops;
266 init.parent_names = NULL;
267 init.num_parents = 0;
268 init.flags = CLK_IGNORE_UNUSED;
270 osc->hw.init = &init;
271 osc->regmap = regmap;
272 osc->frequency = frequency;
273 osc->accuracy = accuracy;
276 ret = clk_hw_register(NULL, hw);
285 static int clk_main_probe_frequency(struct regmap *regmap)
287 unsigned long prep_time, timeout;
290 timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
293 regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
294 if (mcfr & AT91_PMC_MAINRDY)
296 usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
297 } while (time_before(prep_time, timeout));
302 static unsigned long clk_main_recalc_rate(struct regmap *regmap,
303 unsigned long parent_rate)
310 pr_warn("Main crystal frequency not set, using approximate value\n");
311 regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
312 if (!(mcfr & AT91_PMC_MAINRDY))
315 return ((mcfr & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV;
318 static int clk_rm9200_main_prepare(struct clk_hw *hw)
320 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
322 return clk_main_probe_frequency(clkmain->regmap);
325 static int clk_rm9200_main_is_prepared(struct clk_hw *hw)
327 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
330 regmap_read(clkmain->regmap, AT91_CKGR_MCFR, &status);
332 return status & AT91_PMC_MAINRDY ? 1 : 0;
335 static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw,
336 unsigned long parent_rate)
338 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
340 return clk_main_recalc_rate(clkmain->regmap, parent_rate);
343 static const struct clk_ops rm9200_main_ops = {
344 .prepare = clk_rm9200_main_prepare,
345 .is_prepared = clk_rm9200_main_is_prepared,
346 .recalc_rate = clk_rm9200_main_recalc_rate,
349 struct clk_hw * __init
350 at91_clk_register_rm9200_main(struct regmap *regmap,
352 const char *parent_name)
354 struct clk_rm9200_main *clkmain;
355 struct clk_init_data init;
360 return ERR_PTR(-EINVAL);
363 return ERR_PTR(-EINVAL);
365 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
367 return ERR_PTR(-ENOMEM);
370 init.ops = &rm9200_main_ops;
371 init.parent_names = &parent_name;
372 init.num_parents = 1;
375 clkmain->hw.init = &init;
376 clkmain->regmap = regmap;
379 ret = clk_hw_register(NULL, &clkmain->hw);
388 static inline bool clk_sam9x5_main_ready(struct regmap *regmap)
392 regmap_read(regmap, AT91_PMC_SR, &status);
394 return status & AT91_PMC_MOSCSELS ? 1 : 0;
397 static int clk_sam9x5_main_prepare(struct clk_hw *hw)
399 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
400 struct regmap *regmap = clkmain->regmap;
402 while (!clk_sam9x5_main_ready(regmap))
405 return clk_main_probe_frequency(regmap);
408 static int clk_sam9x5_main_is_prepared(struct clk_hw *hw)
410 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
412 return clk_sam9x5_main_ready(clkmain->regmap);
415 static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw,
416 unsigned long parent_rate)
418 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
420 return clk_main_recalc_rate(clkmain->regmap, parent_rate);
423 static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index)
425 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
426 struct regmap *regmap = clkmain->regmap;
432 regmap_read(regmap, AT91_CKGR_MOR, &tmp);
433 tmp &= ~MOR_KEY_MASK;
435 if (index && !(tmp & AT91_PMC_MOSCSEL))
436 regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL);
437 else if (!index && (tmp & AT91_PMC_MOSCSEL))
438 regmap_write(regmap, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL);
440 while (!clk_sam9x5_main_ready(regmap))
446 static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
448 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
451 regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
453 return status & AT91_PMC_MOSCEN ? 1 : 0;
456 static const struct clk_ops sam9x5_main_ops = {
457 .prepare = clk_sam9x5_main_prepare,
458 .is_prepared = clk_sam9x5_main_is_prepared,
459 .recalc_rate = clk_sam9x5_main_recalc_rate,
460 .set_parent = clk_sam9x5_main_set_parent,
461 .get_parent = clk_sam9x5_main_get_parent,
464 struct clk_hw * __init
465 at91_clk_register_sam9x5_main(struct regmap *regmap,
467 const char **parent_names,
470 struct clk_sam9x5_main *clkmain;
471 struct clk_init_data init;
477 return ERR_PTR(-EINVAL);
479 if (!parent_names || !num_parents)
480 return ERR_PTR(-EINVAL);
482 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
484 return ERR_PTR(-ENOMEM);
487 init.ops = &sam9x5_main_ops;
488 init.parent_names = parent_names;
489 init.num_parents = num_parents;
490 init.flags = CLK_SET_PARENT_GATE;
492 clkmain->hw.init = &init;
493 clkmain->regmap = regmap;
494 regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
495 clkmain->parent = status & AT91_PMC_MOSCEN ? 1 : 0;
498 ret = clk_hw_register(NULL, &clkmain->hw);