drivers/char/synclinkmp.c

   1 /*
   2  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/module.h>
  38 #include <linux/errno.h>
  39 #include <linux/signal.h>
  40 #include <linux/sched.h>
  41 #include <linux/timer.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/tty.h>
  45 #include <linux/tty_flip.h>
  46 #include <linux/serial.h>
  47 #include <linux/major.h>
  48 #include <linux/string.h>
  49 #include <linux/fcntl.h>
  50 #include <linux/ptrace.h>
  51 #include <linux/ioport.h>
  52 #include <linux/mm.h>
  53 #include <linux/seq_file.h>
  54 #include <linux/slab.h>
  55 #include <linux/smp_lock.h>
  56 #include <linux/netdevice.h>
  57 #include <linux/vmalloc.h>
  58 #include <linux/init.h>
  59 #include <linux/delay.h>
  60 #include <linux/ioctl.h>
  61
  62 #include <asm/system.h>
  63 #include <asm/io.h>
  64 #include <asm/irq.h>
  65 #include <asm/dma.h>
  66 #include <linux/bitops.h>
  67 #include <asm/types.h>
  68 #include <linux/termios.h>
  69 #include <linux/workqueue.h>
  70 #include <linux/hdlc.h>
  71 #include <linux/synclink.h>
  72
  73 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
  74 #define SYNCLINK_GENERIC_HDLC 1
  75 #else
  76 #define SYNCLINK_GENERIC_HDLC 0
  77 #endif
  78
  79 #define GET_USER(error,value,addr) error = get_user(value,addr)
  80 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  81 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  82 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  83
  84 #include <asm/uaccess.h>
  85
  86 static MGSL_PARAMS default_params = {
  87         MGSL_MODE_HDLC,                 /* unsigned long mode */
  88         0,                              /* unsigned char loopback; */
  89         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  90         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  91         0,                              /* unsigned long clock_speed; */
  92         0xff,                           /* unsigned char addr_filter; */
  93         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  94         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  95         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  96         9600,                           /* unsigned long data_rate; */
  97         8,                              /* unsigned char data_bits; */
  98         1,                              /* unsigned char stop_bits; */
  99         ASYNC_PARITY_NONE               /* unsigned char parity; */
 100 };
 101
 102 /* size in bytes of DMA data buffers */
 103 #define SCABUFSIZE      1024
 104 #define SCA_MEM_SIZE    0x40000
 105 #define SCA_BASE_SIZE   512
 106 #define SCA_REG_SIZE    16
 107 #define SCA_MAX_PORTS   4
 108 #define SCAMAXDESC      128
 109
 110 #define BUFFERLISTSIZE  4096
 111
 112 /* SCA-I style DMA buffer descriptor */
 113 typedef struct _SCADESC
 114 {
 115         u16     next;           /* lower l6 bits of next descriptor addr */
 116         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 117         u8      buf_base;       /* upper 8 bits of buffer addr */
 118         u8      pad1;
 119         u16     length;         /* length of buffer */
 120         u8      status;         /* status of buffer */
 121         u8      pad2;
 122 } SCADESC, *PSCADESC;
 123
 124 typedef struct _SCADESC_EX
 125 {
 126         /* device driver bookkeeping section */
 127         char    *virt_addr;     /* virtual address of data buffer */
 128         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 129 } SCADESC_EX, *PSCADESC_EX;
 130
 131 /* The queue of BH actions to be performed */
 132
 133 #define BH_RECEIVE  1
 134 #define BH_TRANSMIT 2
 135 #define BH_STATUS   4
 136
 137 #define IO_PIN_SHUTDOWN_LIMIT 100
 138
 139 struct  _input_signal_events {
 140         int     ri_up;
 141         int     ri_down;
 142         int     dsr_up;
 143         int     dsr_down;
 144         int     dcd_up;
 145         int     dcd_down;
 146         int     cts_up;
 147         int     cts_down;
 148 };
 149
 150 /*
 151  * Device instance data structure
 152  */
 153 typedef struct _synclinkmp_info {
 154         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 155         int                     magic;
 156         struct tty_port         port;
 157         int                     line;
 158         unsigned short          close_delay;
 159         unsigned short          closing_wait;   /* time to wait before closing */
 160
 161         struct mgsl_icount      icount;
 162
 163         int                     timeout;
 164         int                     x_char;         /* xon/xoff character */
 165         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 166         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 167         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 168         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 169         unsigned char           *tx_buf;
 170         int                     tx_put;
 171         int                     tx_get;
 172         int                     tx_count;
 173
 174         wait_queue_head_t       status_event_wait_q;
 175         wait_queue_head_t       event_wait_q;
 176         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 177         struct _synclinkmp_info *next_device;   /* device list link */
 178         struct timer_list       status_timer;   /* input signal status check timer */
 179
 180         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 181         struct work_struct task;                        /* task structure for scheduling bh */
 182
 183         u32 max_frame_size;                     /* as set by device config */
 184
 185         u32 pending_bh;
 186
 187         bool bh_running;                                /* Protection from multiple */
 188         int isr_overflow;
 189         bool bh_requested;
 190
 191         int dcd_chkcount;                       /* check counts to prevent */
 192         int cts_chkcount;                       /* too many IRQs if a signal */
 193         int dsr_chkcount;                       /* is floating */
 194         int ri_chkcount;
 195
 196         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 197         unsigned long buffer_list_phys;
 198
 199         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 200         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 201         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 202         unsigned int current_rx_buf;
 203
 204         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 205         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 206         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 207         unsigned int last_tx_buf;
 208
 209         unsigned char *tmp_rx_buf;
 210         unsigned int tmp_rx_buf_count;
 211
 212         bool rx_enabled;
 213         bool rx_overflow;
 214
 215         bool tx_enabled;
 216         bool tx_active;
 217         u32 idle_mode;
 218
 219         unsigned char ie0_value;
 220         unsigned char ie1_value;
 221         unsigned char ie2_value;
 222         unsigned char ctrlreg_value;
 223         unsigned char old_signals;
 224
 225         char device_name[25];                   /* device instance name */
 226
 227         int port_count;
 228         int adapter_num;
 229         int port_num;
 230
 231         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 232
 233         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 234
 235         unsigned int irq_level;                 /* interrupt level */
 236         unsigned long irq_flags;
 237         bool irq_requested;                     /* true if IRQ requested */
 238
 239         MGSL_PARAMS params;                     /* communications parameters */
 240
 241         unsigned char serial_signals;           /* current serial signal states */
 242
 243         bool irq_occurred;                      /* for diagnostics use */
 244         unsigned int init_error;                /* Initialization startup error */
 245
 246         u32 last_mem_alloc;
 247         unsigned char* memory_base;             /* shared memory address (PCI only) */
 248         u32 phys_memory_base;
 249         int shared_mem_requested;
 250
 251         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 252         u32 phys_sca_base;
 253         u32 sca_offset;
 254         bool sca_base_requested;
 255
 256         unsigned char* lcr_base;                /* local config registers (PCI only) */
 257         u32 phys_lcr_base;
 258         u32 lcr_offset;
 259         int lcr_mem_requested;
 260
 261         unsigned char* statctrl_base;           /* status/control register memory */
 262         u32 phys_statctrl_base;
 263         u32 statctrl_offset;
 264         bool sca_statctrl_requested;
 265
 266         u32 misc_ctrl_value;
 267         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 268         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 269         bool drop_rts_on_tx_done;
 270
 271         struct  _input_signal_events    input_signal_events;
 272
 273         /* SPPP/Cisco HDLC device parts */
 274         int netcount;
 275         spinlock_t netlock;
 276
 277 #if SYNCLINK_GENERIC_HDLC
 278         struct net_device *netdev;
 279 #endif
 280
 281 } SLMP_INFO;
 282
 283 #define MGSL_MAGIC 0x5401
 284
 285 /*
 286  * define serial signal status change macros
 287  */
 288 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 289 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 290 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 291 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 292
 293 /* Common Register macros */
 294 #define LPR     0x00
 295 #define PABR0   0x02
 296 #define PABR1   0x03
 297 #define WCRL    0x04
 298 #define WCRM    0x05
 299 #define WCRH    0x06
 300 #define DPCR    0x08
 301 #define DMER    0x09
 302 #define ISR0    0x10
 303 #define ISR1    0x11
 304 #define ISR2    0x12
 305 #define IER0    0x14
 306 #define IER1    0x15
 307 #define IER2    0x16
 308 #define ITCR    0x18
 309 #define INTVR   0x1a
 310 #define IMVR    0x1c
 311
 312 /* MSCI Register macros */
 313 #define TRB     0x20
 314 #define TRBL    0x20
 315 #define TRBH    0x21
 316 #define SR0     0x22
 317 #define SR1     0x23
 318 #define SR2     0x24
 319 #define SR3     0x25
 320 #define FST     0x26
 321 #define IE0     0x28
 322 #define IE1     0x29
 323 #define IE2     0x2a
 324 #define FIE     0x2b
 325 #define CMD     0x2c
 326 #define MD0     0x2e
 327 #define MD1     0x2f
 328 #define MD2     0x30
 329 #define CTL     0x31
 330 #define SA0     0x32
 331 #define SA1     0x33
 332 #define IDL     0x34
 333 #define TMC     0x35
 334 #define RXS     0x36
 335 #define TXS     0x37
 336 #define TRC0    0x38
 337 #define TRC1    0x39
 338 #define RRC     0x3a
 339 #define CST0    0x3c
 340 #define CST1    0x3d
 341
 342 /* Timer Register Macros */
 343 #define TCNT    0x60
 344 #define TCNTL   0x60
 345 #define TCNTH   0x61
 346 #define TCONR   0x62
 347 #define TCONRL  0x62
 348 #define TCONRH  0x63
 349 #define TMCS    0x64
 350 #define TEPR    0x65
 351
 352 /* DMA Controller Register macros */
 353 #define DARL    0x80
 354 #define DARH    0x81
 355 #define DARB    0x82
 356 #define BAR     0x80
 357 #define BARL    0x80
 358 #define BARH    0x81
 359 #define BARB    0x82
 360 #define SAR     0x84
 361 #define SARL    0x84
 362 #define SARH    0x85
 363 #define SARB    0x86
 364 #define CPB     0x86
 365 #define CDA     0x88
 366 #define CDAL    0x88
 367 #define CDAH    0x89
 368 #define EDA     0x8a
 369 #define EDAL    0x8a
 370 #define EDAH    0x8b
 371 #define BFL     0x8c
 372 #define BFLL    0x8c
 373 #define BFLH    0x8d
 374 #define BCR     0x8e
 375 #define BCRL    0x8e
 376 #define BCRH    0x8f
 377 #define DSR     0x90
 378 #define DMR     0x91
 379 #define FCT     0x93
 380 #define DIR     0x94
 381 #define DCMD    0x95
 382
 383 /* combine with timer or DMA register address */
 384 #define TIMER0  0x00
 385 #define TIMER1  0x08
 386 #define TIMER2  0x10
 387 #define TIMER3  0x18
 388 #define RXDMA   0x00
 389 #define TXDMA   0x20
 390
 391 /* SCA Command Codes */
 392 #define NOOP            0x00
 393 #define TXRESET         0x01
 394 #define TXENABLE        0x02
 395 #define TXDISABLE       0x03
 396 #define TXCRCINIT       0x04
 397 #define TXCRCEXCL       0x05
 398 #define TXEOM           0x06
 399 #define TXABORT         0x07
 400 #define MPON            0x08
 401 #define TXBUFCLR        0x09
 402 #define RXRESET         0x11
 403 #define RXENABLE        0x12
 404 #define RXDISABLE       0x13
 405 #define RXCRCINIT       0x14
 406 #define RXREJECT        0x15
 407 #define SEARCHMP        0x16
 408 #define RXCRCEXCL       0x17
 409 #define RXCRCCALC       0x18
 410 #define CHRESET         0x21
 411 #define HUNT            0x31
 412
 413 /* DMA command codes */
 414 #define SWABORT         0x01
 415 #define FEICLEAR        0x02
 416
 417 /* IE0 */
 418 #define TXINTE          BIT7
 419 #define RXINTE          BIT6
 420 #define TXRDYE          BIT1
 421 #define RXRDYE          BIT0
 422
 423 /* IE1 & SR1 */
 424 #define UDRN    BIT7
 425 #define IDLE    BIT6
 426 #define SYNCD   BIT4
 427 #define FLGD    BIT4
 428 #define CCTS    BIT3
 429 #define CDCD    BIT2
 430 #define BRKD    BIT1
 431 #define ABTD    BIT1
 432 #define GAPD    BIT1
 433 #define BRKE    BIT0
 434 #define IDLD    BIT0
 435
 436 /* IE2 & SR2 */
 437 #define EOM     BIT7
 438 #define PMP     BIT6
 439 #define SHRT    BIT6
 440 #define PE      BIT5
 441 #define ABT     BIT5
 442 #define FRME    BIT4
 443 #define RBIT    BIT4
 444 #define OVRN    BIT3
 445 #define CRCE    BIT2
 446
 447
 448 /*
 449  * Global linked list of SyncLink devices
 450  */
 451 static SLMP_INFO *synclinkmp_device_list = NULL;
 452 static int synclinkmp_adapter_count = -1;
 453 static int synclinkmp_device_count = 0;
 454
 455 /*
 456  * Set this param to non-zero to load eax with the
 457  * .text section address and breakpoint on module load.
 458  * This is useful for use with gdb and add-symbol-file command.
 459  */
 460 static int break_on_load = 0;
 461
 462 /*
 463  * Driver major number, defaults to zero to get auto
 464  * assigned major number. May be forced as module parameter.
 465  */
 466 static int ttymajor = 0;
 467
 468 /*
 469  * Array of user specified options for ISA adapters.
 470  */
 471 static int debug_level = 0;
 472 static int maxframe[MAX_DEVICES] = {0,};
 473
 474 module_param(break_on_load, bool, 0);
 475 module_param(ttymajor, int, 0);
 476 module_param(debug_level, int, 0);
 477 module_param_array(maxframe, int, NULL, 0);
 478
 479 static char *driver_name = "SyncLink MultiPort driver";
 480 static char *driver_version = "$Revision: 4.38 $";
 481
 482 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 483 static void synclinkmp_remove_one(struct pci_dev *dev);
 484
 485 static struct pci_device_id synclinkmp_pci_tbl[] = {
 486         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 487         { 0, }, /* terminate list */
 488 };
 489 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 490
 491 MODULE_LICENSE("GPL");
 492
 493 static struct pci_driver synclinkmp_pci_driver = {
 494         .name           = "synclinkmp",
 495         .id_table       = synclinkmp_pci_tbl,
 496         .probe          = synclinkmp_init_one,
 497         .remove         = __devexit_p(synclinkmp_remove_one),
 498 };
 499
 500
 501 static struct tty_driver *serial_driver;
 502
 503 /* number of characters left in xmit buffer before we ask for more */
 504 #define WAKEUP_CHARS 256
 505
 506
 507 /* tty callbacks */
 508
 509 static int  open(struct tty_struct *tty, struct file * filp);
 510 static void close(struct tty_struct *tty, struct file * filp);
 511 static void hangup(struct tty_struct *tty);
 512 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 513
 514 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 515 static int put_char(struct tty_struct *tty, unsigned char ch);
 516 static void send_xchar(struct tty_struct *tty, char ch);
 517 static void wait_until_sent(struct tty_struct *tty, int timeout);
 518 static int  write_room(struct tty_struct *tty);
 519 static void flush_chars(struct tty_struct *tty);
 520 static void flush_buffer(struct tty_struct *tty);
 521 static void tx_hold(struct tty_struct *tty);
 522 static void tx_release(struct tty_struct *tty);
 523
 524 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 525 static int  chars_in_buffer(struct tty_struct *tty);
 526 static void throttle(struct tty_struct * tty);
 527 static void unthrottle(struct tty_struct * tty);
 528 static int set_break(struct tty_struct *tty, int break_state);
 529
 530 #if SYNCLINK_GENERIC_HDLC
 531 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 532 static void hdlcdev_tx_done(SLMP_INFO *info);
 533 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 534 static int  hdlcdev_init(SLMP_INFO *info);
 535 static void hdlcdev_exit(SLMP_INFO *info);
 536 #endif
 537
 538 /* ioctl handlers */
 539
 540 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 541 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 542 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 543 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 544 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 545 static int  tx_enable(SLMP_INFO *info, int enable);
 546 static int  tx_abort(SLMP_INFO *info);
 547 static int  rx_enable(SLMP_INFO *info, int enable);
 548 static int  modem_input_wait(SLMP_INFO *info,int arg);
 549 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 550 static int  tiocmget(struct tty_struct *tty, struct file *file);
 551 static int  tiocmset(struct tty_struct *tty, struct file *file,
 552                      unsigned int set, unsigned int clear);
 553 static int  set_break(struct tty_struct *tty, int break_state);
 554
 555 static void add_device(SLMP_INFO *info);
 556 static void device_init(int adapter_num, struct pci_dev *pdev);
 557 static int  claim_resources(SLMP_INFO *info);
 558 static void release_resources(SLMP_INFO *info);
 559
 560 static int  startup(SLMP_INFO *info);
 561 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 562 static int carrier_raised(struct tty_port *port);
 563 static void shutdown(SLMP_INFO *info);
 564 static void program_hw(SLMP_INFO *info);
 565 static void change_params(SLMP_INFO *info);
 566
 567 static bool init_adapter(SLMP_INFO *info);
 568 static bool register_test(SLMP_INFO *info);
 569 static bool irq_test(SLMP_INFO *info);
 570 static bool loopback_test(SLMP_INFO *info);
 571 static int  adapter_test(SLMP_INFO *info);
 572 static bool memory_test(SLMP_INFO *info);
 573
 574 static void reset_adapter(SLMP_INFO *info);
 575 static void reset_port(SLMP_INFO *info);
 576 static void async_mode(SLMP_INFO *info);
 577 static void hdlc_mode(SLMP_INFO *info);
 578
 579 static void rx_stop(SLMP_INFO *info);
 580 static void rx_start(SLMP_INFO *info);
 581 static void rx_reset_buffers(SLMP_INFO *info);
 582 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 583 static bool rx_get_frame(SLMP_INFO *info);
 584
 585 static void tx_start(SLMP_INFO *info);
 586 static void tx_stop(SLMP_INFO *info);
 587 static void tx_load_fifo(SLMP_INFO *info);
 588 static void tx_set_idle(SLMP_INFO *info);
 589 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 590
 591 static void get_signals(SLMP_INFO *info);
 592 static void set_signals(SLMP_INFO *info);
 593 static void enable_loopback(SLMP_INFO *info, int enable);
 594 static void set_rate(SLMP_INFO *info, u32 data_rate);
 595
 596 static int  bh_action(SLMP_INFO *info);
 597 static void bh_handler(struct work_struct *work);
 598 static void bh_receive(SLMP_INFO *info);
 599 static void bh_transmit(SLMP_INFO *info);
 600 static void bh_status(SLMP_INFO *info);
 601 static void isr_timer(SLMP_INFO *info);
 602 static void isr_rxint(SLMP_INFO *info);
 603 static void isr_rxrdy(SLMP_INFO *info);
 604 static void isr_txint(SLMP_INFO *info);
 605 static void isr_txrdy(SLMP_INFO *info);
 606 static void isr_rxdmaok(SLMP_INFO *info);
 607 static void isr_rxdmaerror(SLMP_INFO *info);
 608 static void isr_txdmaok(SLMP_INFO *info);
 609 static void isr_txdmaerror(SLMP_INFO *info);
 610 static void isr_io_pin(SLMP_INFO *info, u16 status);
 611
 612 static int  alloc_dma_bufs(SLMP_INFO *info);
 613 static void free_dma_bufs(SLMP_INFO *info);
 614 static int  alloc_buf_list(SLMP_INFO *info);
 615 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 616 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 617 static void free_tmp_rx_buf(SLMP_INFO *info);
 618
 619 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 620 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 621 static void tx_timeout(unsigned long context);
 622 static void status_timeout(unsigned long context);
 623
 624 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 625 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 626 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 627 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 628 static unsigned char read_status_reg(SLMP_INFO * info);
 629 static void write_control_reg(SLMP_INFO * info);
 630
 631
 632 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 633 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 634 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 635
 636 static u32 misc_ctrl_value = 0x007e4040;
 637 static u32 lcr1_brdr_value = 0x00800028;
 638
 639 static u32 read_ahead_count = 8;
 640
 641 /* DPCR, DMA Priority Control
 642  *
 643  * 07..05  Not used, must be 0
 644  * 04      BRC, bus release condition: 0=all transfers complete
 645  *              1=release after 1 xfer on all channels
 646  * 03      CCC, channel change condition: 0=every cycle
 647  *              1=after each channel completes all xfers
 648  * 02..00  PR<2..0>, priority 100=round robin
 649  *
 650  * 00000100 = 0x00
 651  */
 652 static unsigned char dma_priority = 0x04;
 653
 654 // Number of bytes that can be written to shared RAM
 655 // in a single write operation
 656 static u32 sca_pci_load_interval = 64;
 657
 658 /*
 659  * 1st function defined in .text section. Calling this function in
 660  * init_module() followed by a breakpoint allows a remote debugger
 661  * (gdb) to get the .text address for the add-symbol-file command.
 662  * This allows remote debugging of dynamically loadable modules.
 663  */
 664 static void* synclinkmp_get_text_ptr(void);
 665 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 666
 667 static inline int sanity_check(SLMP_INFO *info,
 668                                char *name, const char *routine)
 669 {
 670 #ifdef SANITY_CHECK
 671         static const char *badmagic =
 672                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 673         static const char *badinfo =
 674                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 675
 676         if (!info) {
 677                 printk(badinfo, name, routine);
 678                 return 1;
 679         }
 680         if (info->magic != MGSL_MAGIC) {
 681                 printk(badmagic, name, routine);
 682                 return 1;
 683         }
 684 #else
 685         if (!info)
 686                 return 1;
 687 #endif
 688         return 0;
 689 }
 690
 691 /**
 692  * line discipline callback wrappers
 693  *
 694  * The wrappers maintain line discipline references
 695  * while calling into the line discipline.
 696  *
 697  * ldisc_receive_buf  - pass receive data to line discipline
 698  */
 699
 700 static void ldisc_receive_buf(struct tty_struct *tty,
 701                               const __u8 *data, char *flags, int count)
 702 {
 703         struct tty_ldisc *ld;
 704         if (!tty)
 705                 return;
 706         ld = tty_ldisc_ref(tty);
 707         if (ld) {
 708                 if (ld->ops->receive_buf)
 709                         ld->ops->receive_buf(tty, data, flags, count);
 710                 tty_ldisc_deref(ld);
 711         }
 712 }
 713
 714 /* tty callbacks */
 715
 716 /* Called when a port is opened.  Init and enable port.
 717  */
 718 static int open(struct tty_struct *tty, struct file *filp)
 719 {
 720         SLMP_INFO *info;
 721         int retval, line;
 722         unsigned long flags;
 723
 724         line = tty->index;
 725         if ((line < 0) || (line >= synclinkmp_device_count)) {
 726                 printk("%s(%d): open with invalid line #%d.\n",
 727                         __FILE__,__LINE__,line);
 728                 return -ENODEV;
 729         }
 730
 731         info = synclinkmp_device_list;
 732         while(info && info->line != line)
 733                 info = info->next_device;
 734         if (sanity_check(info, tty->name, "open"))
 735                 return -ENODEV;
 736         if ( info->init_error ) {
 737                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 738                         __FILE__,__LINE__,info->device_name,info->init_error);
 739                 return -ENODEV;
 740         }
 741
 742         tty->driver_data = info;
 743         info->port.tty = tty;
 744
 745         if (debug_level >= DEBUG_LEVEL_INFO)
 746                 printk("%s(%d):%s open(), old ref count = %d\n",
 747                          __FILE__,__LINE__,tty->driver->name, info->port.count);
 748
 749         /* If port is closing, signal caller to try again */
 750         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 751                 if (info->port.flags & ASYNC_CLOSING)
 752                         interruptible_sleep_on(&info->port.close_wait);
 753                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 754                         -EAGAIN : -ERESTARTSYS);
 755                 goto cleanup;
 756         }
 757
 758         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 759
 760         spin_lock_irqsave(&info->netlock, flags);
 761         if (info->netcount) {
 762                 retval = -EBUSY;
 763                 spin_unlock_irqrestore(&info->netlock, flags);
 764                 goto cleanup;
 765         }
 766         info->port.count++;
 767         spin_unlock_irqrestore(&info->netlock, flags);
 768
 769         if (info->port.count == 1) {
 770                 /* 1st open on this device, init hardware */
 771                 retval = startup(info);
 772                 if (retval < 0)
 773                         goto cleanup;
 774         }
 775
 776         retval = block_til_ready(tty, filp, info);
 777         if (retval) {
 778                 if (debug_level >= DEBUG_LEVEL_INFO)
 779                         printk("%s(%d):%s block_til_ready() returned %d\n",
 780                                  __FILE__,__LINE__, info->device_name, retval);
 781                 goto cleanup;
 782         }
 783
 784         if (debug_level >= DEBUG_LEVEL_INFO)
 785                 printk("%s(%d):%s open() success\n",
 786                          __FILE__,__LINE__, info->device_name);
 787         retval = 0;
 788
 789 cleanup:
 790         if (retval) {
 791                 if (tty->count == 1)
 792                         info->port.tty = NULL; /* tty layer will release tty struct */
 793                 if(info->port.count)
 794                         info->port.count--;
 795         }
 796
 797         return retval;
 798 }
 799
 800 /* Called when port is closed. Wait for remaining data to be
 801  * sent. Disable port and free resources.
 802  */
 803 static void close(struct tty_struct *tty, struct file *filp)
 804 {
 805         SLMP_INFO * info = tty->driver_data;
 806
 807         if (sanity_check(info, tty->name, "close"))
 808                 return;
 809
 810         if (debug_level >= DEBUG_LEVEL_INFO)
 811                 printk("%s(%d):%s close() entry, count=%d\n",
 812                          __FILE__,__LINE__, info->device_name, info->port.count);
 813
 814         if (tty_port_close_start(&info->port, tty, filp) == 0)
 815                 goto cleanup;
 816
 817         if (info->port.flags & ASYNC_INITIALIZED)
 818                 wait_until_sent(tty, info->timeout);
 819
 820         flush_buffer(tty);
 821         tty_ldisc_flush(tty);
 822         shutdown(info);
 823
 824         tty_port_close_end(&info->port, tty);
 825         info->port.tty = NULL;
 826 cleanup:
 827         if (debug_level >= DEBUG_LEVEL_INFO)
 828                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 829                         tty->driver->name, info->port.count);
 830 }
 831
 832 /* Called by tty_hangup() when a hangup is signaled.
 833  * This is the same as closing all open descriptors for the port.
 834  */
 835 static void hangup(struct tty_struct *tty)
 836 {
 837         SLMP_INFO *info = tty->driver_data;
 838
 839         if (debug_level >= DEBUG_LEVEL_INFO)
 840                 printk("%s(%d):%s hangup()\n",
 841                          __FILE__,__LINE__, info->device_name );
 842
 843         if (sanity_check(info, tty->name, "hangup"))
 844                 return;
 845
 846         flush_buffer(tty);
 847         shutdown(info);
 848
 849         info->port.count = 0;
 850         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 851         info->port.tty = NULL;
 852
 853         wake_up_interruptible(&info->port.open_wait);
 854 }
 855
 856 /* Set new termios settings
 857  */
 858 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 859 {
 860         SLMP_INFO *info = tty->driver_data;
 861         unsigned long flags;
 862
 863         if (debug_level >= DEBUG_LEVEL_INFO)
 864                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 865                         tty->driver->name );
 866
 867         change_params(info);
 868
 869         /* Handle transition to B0 status */
 870         if (old_termios->c_cflag & CBAUD &&
 871             !(tty->termios->c_cflag & CBAUD)) {
 872                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 873                 spin_lock_irqsave(&info->lock,flags);
 874                 set_signals(info);
 875                 spin_unlock_irqrestore(&info->lock,flags);
 876         }
 877
 878         /* Handle transition away from B0 status */
 879         if (!(old_termios->c_cflag & CBAUD) &&
 880             tty->termios->c_cflag & CBAUD) {
 881                 info->serial_signals |= SerialSignal_DTR;
 882                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 883                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 884                         info->serial_signals |= SerialSignal_RTS;
 885                 }
 886                 spin_lock_irqsave(&info->lock,flags);
 887                 set_signals(info);
 888                 spin_unlock_irqrestore(&info->lock,flags);
 889         }
 890
 891         /* Handle turning off CRTSCTS */
 892         if (old_termios->c_cflag & CRTSCTS &&
 893             !(tty->termios->c_cflag & CRTSCTS)) {
 894                 tty->hw_stopped = 0;
 895                 tx_release(tty);
 896         }
 897 }
 898
 899 /* Send a block of data
 900  *
 901  * Arguments:
 902  *
 903  *      tty             pointer to tty information structure
 904  *      buf             pointer to buffer containing send data
 905  *      count           size of send data in bytes
 906  *
 907  * Return Value:        number of characters written
 908  */
 909 static int write(struct tty_struct *tty,
 910                  const unsigned char *buf, int count)
 911 {
 912         int     c, ret = 0;
 913         SLMP_INFO *info = tty->driver_data;
 914         unsigned long flags;
 915
 916         if (debug_level >= DEBUG_LEVEL_INFO)
 917                 printk("%s(%d):%s write() count=%d\n",
 918                        __FILE__,__LINE__,info->device_name,count);
 919
 920         if (sanity_check(info, tty->name, "write"))
 921                 goto cleanup;
 922
 923         if (!info->tx_buf)
 924                 goto cleanup;
 925
 926         if (info->params.mode == MGSL_MODE_HDLC) {
 927                 if (count > info->max_frame_size) {
 928                         ret = -EIO;
 929                         goto cleanup;
 930                 }
 931                 if (info->tx_active)
 932                         goto cleanup;
 933                 if (info->tx_count) {
 934                         /* send accumulated data from send_char() calls */
 935                         /* as frame and wait before accepting more data. */
 936                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 937                         goto start;
 938                 }
 939                 ret = info->tx_count = count;
 940                 tx_load_dma_buffer(info, buf, count);
 941                 goto start;
 942         }
 943
 944         for (;;) {
 945                 c = min_t(int, count,
 946                         min(info->max_frame_size - info->tx_count - 1,
 947                             info->max_frame_size - info->tx_put));
 948                 if (c <= 0)
 949                         break;
 950
 951                 memcpy(info->tx_buf + info->tx_put, buf, c);
 952
 953                 spin_lock_irqsave(&info->lock,flags);
 954                 info->tx_put += c;
 955                 if (info->tx_put >= info->max_frame_size)
 956                         info->tx_put -= info->max_frame_size;
 957                 info->tx_count += c;
 958                 spin_unlock_irqrestore(&info->lock,flags);
 959
 960                 buf += c;
 961                 count -= c;
 962                 ret += c;
 963         }
 964
 965         if (info->params.mode == MGSL_MODE_HDLC) {
 966                 if (count) {
 967                         ret = info->tx_count = 0;
 968                         goto cleanup;
 969                 }
 970                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 971         }
 972 start:
 973         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 974                 spin_lock_irqsave(&info->lock,flags);
 975                 if (!info->tx_active)
 976                         tx_start(info);
 977                 spin_unlock_irqrestore(&info->lock,flags);
 978         }
 979
 980 cleanup:
 981         if (debug_level >= DEBUG_LEVEL_INFO)
 982                 printk( "%s(%d):%s write() returning=%d\n",
 983                         __FILE__,__LINE__,info->device_name,ret);
 984         return ret;
 985 }
 986
 987 /* Add a character to the transmit buffer.
 988  */
 989 static int put_char(struct tty_struct *tty, unsigned char ch)
 990 {
 991         SLMP_INFO *info = tty->driver_data;
 992         unsigned long flags;
 993         int ret = 0;
 994
 995         if ( debug_level >= DEBUG_LEVEL_INFO ) {
 996                 printk( "%s(%d):%s put_char(%d)\n",
 997                         __FILE__,__LINE__,info->device_name,ch);
 998         }
 999
1000         if (sanity_check(info, tty->name, "put_char"))
1001                 return 0;
1002
1003         if (!info->tx_buf)
1004                 return 0;
1005
1006         spin_lock_irqsave(&info->lock,flags);
1007
1008         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1009              !info->tx_active ) {
1010
1011                 if (info->tx_count < info->max_frame_size - 1) {
1012                         info->tx_buf[info->tx_put++] = ch;
1013                         if (info->tx_put >= info->max_frame_size)
1014                                 info->tx_put -= info->max_frame_size;
1015                         info->tx_count++;
1016                         ret = 1;
1017                 }
1018         }
1019
1020         spin_unlock_irqrestore(&info->lock,flags);
1021         return ret;
1022 }
1023
1024 /* Send a high-priority XON/XOFF character
1025  */
1026 static void send_xchar(struct tty_struct *tty, char ch)
1027 {
1028         SLMP_INFO *info = tty->driver_data;
1029         unsigned long flags;
1030
1031         if (debug_level >= DEBUG_LEVEL_INFO)
1032                 printk("%s(%d):%s send_xchar(%d)\n",
1033                          __FILE__,__LINE__, info->device_name, ch );
1034
1035         if (sanity_check(info, tty->name, "send_xchar"))
1036                 return;
1037
1038         info->x_char = ch;
1039         if (ch) {
1040                 /* Make sure transmit interrupts are on */
1041                 spin_lock_irqsave(&info->lock,flags);
1042                 if (!info->tx_enabled)
1043                         tx_start(info);
1044                 spin_unlock_irqrestore(&info->lock,flags);
1045         }
1046 }
1047
1048 /* Wait until the transmitter is empty.
1049  */
1050 static void wait_until_sent(struct tty_struct *tty, int timeout)
1051 {
1052         SLMP_INFO * info = tty->driver_data;
1053         unsigned long orig_jiffies, char_time;
1054
1055         if (!info )
1056                 return;
1057
1058         if (debug_level >= DEBUG_LEVEL_INFO)
1059                 printk("%s(%d):%s wait_until_sent() entry\n",
1060                          __FILE__,__LINE__, info->device_name );
1061
1062         if (sanity_check(info, tty->name, "wait_until_sent"))
1063                 return;
1064
1065         lock_kernel();
1066
1067         if (!(info->port.flags & ASYNC_INITIALIZED))
1068                 goto exit;
1069
1070         orig_jiffies = jiffies;
1071
1072         /* Set check interval to 1/5 of estimated time to
1073          * send a character, and make it at least 1. The check
1074          * interval should also be less than the timeout.
1075          * Note: use tight timings here to satisfy the NIST-PCTS.
1076          */
1077
1078         if ( info->params.data_rate ) {
1079                 char_time = info->timeout/(32 * 5);
1080                 if (!char_time)
1081                         char_time++;
1082         } else
1083                 char_time = 1;
1084
1085         if (timeout)
1086                 char_time = min_t(unsigned long, char_time, timeout);
1087
1088         if ( info->params.mode == MGSL_MODE_HDLC ) {
1089                 while (info->tx_active) {
1090                         msleep_interruptible(jiffies_to_msecs(char_time));
1091                         if (signal_pending(current))
1092                                 break;
1093                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1094                                 break;
1095                 }
1096         } else {
1097                 //TODO: determine if there is something similar to USC16C32
1098                 //      TXSTATUS_ALL_SENT status
1099                 while ( info->tx_active && info->tx_enabled) {
1100                         msleep_interruptible(jiffies_to_msecs(char_time));
1101                         if (signal_pending(current))
1102                                 break;
1103                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1104                                 break;
1105                 }
1106         }
1107
1108 exit:
1109         unlock_kernel();
1110         if (debug_level >= DEBUG_LEVEL_INFO)
1111                 printk("%s(%d):%s wait_until_sent() exit\n",
1112                          __FILE__,__LINE__, info->device_name );
1113 }
1114
1115 /* Return the count of free bytes in transmit buffer
1116  */
1117 static int write_room(struct tty_struct *tty)
1118 {
1119         SLMP_INFO *info = tty->driver_data;
1120         int ret;
1121
1122         if (sanity_check(info, tty->name, "write_room"))
1123                 return 0;
1124
1125         lock_kernel();
1126         if (info->params.mode == MGSL_MODE_HDLC) {
1127                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1128         } else {
1129                 ret = info->max_frame_size - info->tx_count - 1;
1130                 if (ret < 0)
1131                         ret = 0;
1132         }
1133         unlock_kernel();
1134
1135         if (debug_level >= DEBUG_LEVEL_INFO)
1136                 printk("%s(%d):%s write_room()=%d\n",
1137                        __FILE__, __LINE__, info->device_name, ret);
1138
1139         return ret;
1140 }
1141
1142 /* enable transmitter and send remaining buffered characters
1143  */
1144 static void flush_chars(struct tty_struct *tty)
1145 {
1146         SLMP_INFO *info = tty->driver_data;
1147         unsigned long flags;
1148
1149         if ( debug_level >= DEBUG_LEVEL_INFO )
1150                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1151                         __FILE__,__LINE__,info->device_name,info->tx_count);
1152
1153         if (sanity_check(info, tty->name, "flush_chars"))
1154                 return;
1155
1156         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1157             !info->tx_buf)
1158                 return;
1159
1160         if ( debug_level >= DEBUG_LEVEL_INFO )
1161                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1162                         __FILE__,__LINE__,info->device_name );
1163
1164         spin_lock_irqsave(&info->lock,flags);
1165
1166         if (!info->tx_active) {
1167                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1168                         info->tx_count ) {
1169                         /* operating in synchronous (frame oriented) mode */
1170                         /* copy data from circular tx_buf to */
1171                         /* transmit DMA buffer. */
1172                         tx_load_dma_buffer(info,
1173                                  info->tx_buf,info->tx_count);
1174                 }
1175                 tx_start(info);
1176         }
1177
1178         spin_unlock_irqrestore(&info->lock,flags);
1179 }
1180
1181 /* Discard all data in the send buffer
1182  */
1183 static void flush_buffer(struct tty_struct *tty)
1184 {
1185         SLMP_INFO *info = tty->driver_data;
1186         unsigned long flags;
1187
1188         if (debug_level >= DEBUG_LEVEL_INFO)
1189                 printk("%s(%d):%s flush_buffer() entry\n",
1190                          __FILE__,__LINE__, info->device_name );
1191
1192         if (sanity_check(info, tty->name, "flush_buffer"))
1193                 return;
1194
1195         spin_lock_irqsave(&info->lock,flags);
1196         info->tx_count = info->tx_put = info->tx_get = 0;
1197         del_timer(&info->tx_timer);
1198         spin_unlock_irqrestore(&info->lock,flags);
1199
1200         tty_wakeup(tty);
1201 }
1202
1203 /* throttle (stop) transmitter
1204  */
1205 static void tx_hold(struct tty_struct *tty)
1206 {
1207         SLMP_INFO *info = tty->driver_data;
1208         unsigned long flags;
1209
1210         if (sanity_check(info, tty->name, "tx_hold"))
1211                 return;
1212
1213         if ( debug_level >= DEBUG_LEVEL_INFO )
1214                 printk("%s(%d):%s tx_hold()\n",
1215                         __FILE__,__LINE__,info->device_name);
1216
1217         spin_lock_irqsave(&info->lock,flags);
1218         if (info->tx_enabled)
1219                 tx_stop(info);
1220         spin_unlock_irqrestore(&info->lock,flags);
1221 }
1222
1223 /* release (start) transmitter
1224  */
1225 static void tx_release(struct tty_struct *tty)
1226 {
1227         SLMP_INFO *info = tty->driver_data;
1228         unsigned long flags;
1229
1230         if (sanity_check(info, tty->name, "tx_release"))
1231                 return;
1232
1233         if ( debug_level >= DEBUG_LEVEL_INFO )
1234                 printk("%s(%d):%s tx_release()\n",
1235                         __FILE__,__LINE__,info->device_name);
1236
1237         spin_lock_irqsave(&info->lock,flags);
1238         if (!info->tx_enabled)
1239                 tx_start(info);
1240         spin_unlock_irqrestore(&info->lock,flags);
1241 }
1242
1243 /* Service an IOCTL request
1244  *
1245  * Arguments:
1246  *
1247  *      tty     pointer to tty instance data
1248  *      file    pointer to associated file object for device
1249  *      cmd     IOCTL command code
1250  *      arg     command argument/context
1251  *
1252  * Return Value:        0 if success, otherwise error code
1253  */
1254 static int do_ioctl(struct tty_struct *tty, struct file *file,
1255                  unsigned int cmd, unsigned long arg)
1256 {
1257         SLMP_INFO *info = tty->driver_data;
1258         int error;
1259         struct mgsl_icount cnow;        /* kernel counter temps */
1260         struct serial_icounter_struct __user *p_cuser;  /* user space */
1261         unsigned long flags;
1262         void __user *argp = (void __user *)arg;
1263
1264         if (debug_level >= DEBUG_LEVEL_INFO)
1265                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1266                         info->device_name, cmd );
1267
1268         if (sanity_check(info, tty->name, "ioctl"))
1269                 return -ENODEV;
1270
1271         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1272             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1273                 if (tty->flags & (1 << TTY_IO_ERROR))
1274                     return -EIO;
1275         }
1276
1277         switch (cmd) {
1278         case MGSL_IOCGPARAMS:
1279                 return get_params(info, argp);
1280         case MGSL_IOCSPARAMS:
1281                 return set_params(info, argp);
1282         case MGSL_IOCGTXIDLE:
1283                 return get_txidle(info, argp);
1284         case MGSL_IOCSTXIDLE:
1285                 return set_txidle(info, (int)arg);
1286         case MGSL_IOCTXENABLE:
1287                 return tx_enable(info, (int)arg);
1288         case MGSL_IOCRXENABLE:
1289                 return rx_enable(info, (int)arg);
1290         case MGSL_IOCTXABORT:
1291                 return tx_abort(info);
1292         case MGSL_IOCGSTATS:
1293                 return get_stats(info, argp);
1294         case MGSL_IOCWAITEVENT:
1295                 return wait_mgsl_event(info, argp);
1296         case MGSL_IOCLOOPTXDONE:
1297                 return 0; // TODO: Not supported, need to document
1298                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1299                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1300                  */
1301         case TIOCMIWAIT:
1302                 return modem_input_wait(info,(int)arg);
1303
1304                 /*
1305                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1306                  * Return: write counters to the user passed counter struct
1307                  * NB: both 1->0 and 0->1 transitions are counted except for
1308                  *     RI where only 0->1 is counted.
1309                  */
1310         case TIOCGICOUNT:
1311                 spin_lock_irqsave(&info->lock,flags);
1312                 cnow = info->icount;
1313                 spin_unlock_irqrestore(&info->lock,flags);
1314                 p_cuser = argp;
1315                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1316                 if (error) return error;
1317                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1318                 if (error) return error;
1319                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1320                 if (error) return error;
1321                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1322                 if (error) return error;
1323                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1324                 if (error) return error;
1325                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1326                 if (error) return error;
1327                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1328                 if (error) return error;
1329                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1330                 if (error) return error;
1331                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1332                 if (error) return error;
1333                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1334                 if (error) return error;
1335                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1336                 if (error) return error;
1337                 return 0;
1338         default:
1339                 return -ENOIOCTLCMD;
1340         }
1341         return 0;
1342 }
1343
1344 static int ioctl(struct tty_struct *tty, struct file *file,
1345                  unsigned int cmd, unsigned long arg)
1346 {
1347         int ret;
1348         lock_kernel();
1349         ret = do_ioctl(tty, file, cmd, arg);
1350         unlock_kernel();
1351         return ret;
1352 }
1353
1354 /*
1355  * /proc fs routines....
1356  */
1357
1358 static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1359 {
1360         char    stat_buf[30];
1361         unsigned long flags;
1362
1363         seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1364                        "\tIRQ=%d MaxFrameSize=%u\n",
1365                 info->device_name,
1366                 info->phys_sca_base,
1367                 info->phys_memory_base,
1368                 info->phys_statctrl_base,
1369                 info->phys_lcr_base,
1370                 info->irq_level,
1371                 info->max_frame_size );
1372
1373         /* output current serial signal states */
1374         spin_lock_irqsave(&info->lock,flags);
1375         get_signals(info);
1376         spin_unlock_irqrestore(&info->lock,flags);
1377
1378         stat_buf[0] = 0;
1379         stat_buf[1] = 0;
1380         if (info->serial_signals & SerialSignal_RTS)
1381                 strcat(stat_buf, "|RTS");
1382         if (info->serial_signals & SerialSignal_CTS)
1383                 strcat(stat_buf, "|CTS");
1384         if (info->serial_signals & SerialSignal_DTR)
1385                 strcat(stat_buf, "|DTR");
1386         if (info->serial_signals & SerialSignal_DSR)
1387                 strcat(stat_buf, "|DSR");
1388         if (info->serial_signals & SerialSignal_DCD)
1389                 strcat(stat_buf, "|CD");
1390         if (info->serial_signals & SerialSignal_RI)
1391                 strcat(stat_buf, "|RI");
1392
1393         if (info->params.mode == MGSL_MODE_HDLC) {
1394                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1395                               info->icount.txok, info->icount.rxok);
1396                 if (info->icount.txunder)
1397                         seq_printf(m, " txunder:%d", info->icount.txunder);
1398                 if (info->icount.txabort)
1399                         seq_printf(m, " txabort:%d", info->icount.txabort);
1400                 if (info->icount.rxshort)
1401                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1402                 if (info->icount.rxlong)
1403                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1404                 if (info->icount.rxover)
1405                         seq_printf(m, " rxover:%d", info->icount.rxover);
1406                 if (info->icount.rxcrc)
1407                         seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1408         } else {
1409                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1410                               info->icount.tx, info->icount.rx);
1411                 if (info->icount.frame)
1412                         seq_printf(m, " fe:%d", info->icount.frame);
1413                 if (info->icount.parity)
1414                         seq_printf(m, " pe:%d", info->icount.parity);
1415                 if (info->icount.brk)
1416                         seq_printf(m, " brk:%d", info->icount.brk);
1417                 if (info->icount.overrun)
1418                         seq_printf(m, " oe:%d", info->icount.overrun);
1419         }
1420
1421         /* Append serial signal status to end */
1422         seq_printf(m, " %s\n", stat_buf+1);
1423
1424         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1425          info->tx_active,info->bh_requested,info->bh_running,
1426          info->pending_bh);
1427 }
1428
1429 /* Called to print information about devices
1430  */
1431 static int synclinkmp_proc_show(struct seq_file *m, void *v)
1432 {
1433         SLMP_INFO *info;
1434
1435         seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1436
1437         info = synclinkmp_device_list;
1438         while( info ) {
1439                 line_info(m, info);
1440                 info = info->next_device;
1441         }
1442         return 0;
1443 }
1444
1445 static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1446 {
1447         return single_open(file, synclinkmp_proc_show, NULL);
1448 }
1449
1450 static const struct file_operations synclinkmp_proc_fops = {
1451         .owner          = THIS_MODULE,
1452         .open           = synclinkmp_proc_open,
1453         .read           = seq_read,
1454         .llseek         = seq_lseek,
1455         .release        = single_release,
1456 };
1457
1458 /* Return the count of bytes in transmit buffer
1459  */
1460 static int chars_in_buffer(struct tty_struct *tty)
1461 {
1462         SLMP_INFO *info = tty->driver_data;
1463
1464         if (sanity_check(info, tty->name, "chars_in_buffer"))
1465                 return 0;
1466
1467         if (debug_level >= DEBUG_LEVEL_INFO)
1468                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1469                        __FILE__, __LINE__, info->device_name, info->tx_count);
1470
1471         return info->tx_count;
1472 }
1473
1474 /* Signal remote device to throttle send data (our receive data)
1475  */
1476 static void throttle(struct tty_struct * tty)
1477 {
1478         SLMP_INFO *info = tty->driver_data;
1479         unsigned long flags;
1480
1481         if (debug_level >= DEBUG_LEVEL_INFO)
1482                 printk("%s(%d):%s throttle() entry\n",
1483                          __FILE__,__LINE__, info->device_name );
1484
1485         if (sanity_check(info, tty->name, "throttle"))
1486                 return;
1487
1488         if (I_IXOFF(tty))
1489                 send_xchar(tty, STOP_CHAR(tty));
1490
1491         if (tty->termios->c_cflag & CRTSCTS) {
1492                 spin_lock_irqsave(&info->lock,flags);
1493                 info->serial_signals &= ~SerialSignal_RTS;
1494                 set_signals(info);
1495                 spin_unlock_irqrestore(&info->lock,flags);
1496         }
1497 }
1498
1499 /* Signal remote device to stop throttling send data (our receive data)
1500  */
1501 static void unthrottle(struct tty_struct * tty)
1502 {
1503         SLMP_INFO *info = tty->driver_data;
1504         unsigned long flags;
1505
1506         if (debug_level >= DEBUG_LEVEL_INFO)
1507                 printk("%s(%d):%s unthrottle() entry\n",
1508                          __FILE__,__LINE__, info->device_name );
1509
1510         if (sanity_check(info, tty->name, "unthrottle"))
1511                 return;
1512
1513         if (I_IXOFF(tty)) {
1514                 if (info->x_char)
1515                         info->x_char = 0;
1516                 else
1517                         send_xchar(tty, START_CHAR(tty));
1518         }
1519
1520         if (tty->termios->c_cflag & CRTSCTS) {
1521                 spin_lock_irqsave(&info->lock,flags);
1522                 info->serial_signals |= SerialSignal_RTS;
1523                 set_signals(info);
1524                 spin_unlock_irqrestore(&info->lock,flags);
1525         }
1526 }
1527
1528 /* set or clear transmit break condition
1529  * break_state  -1=set break condition, 0=clear
1530  */
1531 static int set_break(struct tty_struct *tty, int break_state)
1532 {
1533         unsigned char RegValue;
1534         SLMP_INFO * info = tty->driver_data;
1535         unsigned long flags;
1536
1537         if (debug_level >= DEBUG_LEVEL_INFO)
1538                 printk("%s(%d):%s set_break(%d)\n",
1539                          __FILE__,__LINE__, info->device_name, break_state);
1540
1541         if (sanity_check(info, tty->name, "set_break"))
1542                 return -EINVAL;
1543
1544         spin_lock_irqsave(&info->lock,flags);
1545         RegValue = read_reg(info, CTL);
1546         if (break_state == -1)
1547                 RegValue |= BIT3;
1548         else
1549                 RegValue &= ~BIT3;
1550         write_reg(info, CTL, RegValue);
1551         spin_unlock_irqrestore(&info->lock,flags);
1552         return 0;
1553 }
1554
1555 #if SYNCLINK_GENERIC_HDLC
1556
1557 /**
1558  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1559  * set encoding and frame check sequence (FCS) options
1560  *
1561  * dev       pointer to network device structure
1562  * encoding  serial encoding setting
1563  * parity    FCS setting
1564  *
1565  * returns 0 if success, otherwise error code
1566  */
1567 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1568                           unsigned short parity)
1569 {
1570         SLMP_INFO *info = dev_to_port(dev);
1571         unsigned char  new_encoding;
1572         unsigned short new_crctype;
1573
1574         /* return error if TTY interface open */
1575         if (info->port.count)
1576                 return -EBUSY;
1577
1578         switch (encoding)
1579         {
1580         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1581         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1582         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1583         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1584         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1585         default: return -EINVAL;
1586         }
1587
1588         switch (parity)
1589         {
1590         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1591         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1592         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1593         default: return -EINVAL;
1594         }
1595
1596         info->params.encoding = new_encoding;
1597         info->params.crc_type = new_crctype;
1598
1599         /* if network interface up, reprogram hardware */
1600         if (info->netcount)
1601                 program_hw(info);
1602
1603         return 0;
1604 }
1605
1606 /**
1607  * called by generic HDLC layer to send frame
1608  *
1609  * skb  socket buffer containing HDLC frame
1610  * dev  pointer to network device structure
1611  */
1612 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1613                                       struct net_device *dev)
1614 {
1615         SLMP_INFO *info = dev_to_port(dev);
1616         unsigned long flags;
1617
1618         if (debug_level >= DEBUG_LEVEL_INFO)
1619                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1620
1621         /* stop sending until this frame completes */
1622         netif_stop_queue(dev);
1623
1624         /* copy data to device buffers */
1625         info->tx_count = skb->len;
1626         tx_load_dma_buffer(info, skb->data, skb->len);
1627
1628         /* update network statistics */
1629         dev->stats.tx_packets++;
1630         dev->stats.tx_bytes += skb->len;
1631
1632         /* done with socket buffer, so free it */
1633         dev_kfree_skb(skb);
1634
1635         /* save start time for transmit timeout detection */
1636         dev->trans_start = jiffies;
1637
1638         /* start hardware transmitter if necessary */
1639         spin_lock_irqsave(&info->lock,flags);
1640         if (!info->tx_active)
1641                 tx_start(info);
1642         spin_unlock_irqrestore(&info->lock,flags);
1643
1644         return NETDEV_TX_OK;
1645 }
1646
1647 /**
1648  * called by network layer when interface enabled
1649  * claim resources and initialize hardware
1650  *
1651  * dev  pointer to network device structure
1652  *
1653  * returns 0 if success, otherwise error code
1654  */
1655 static int hdlcdev_open(struct net_device *dev)
1656 {
1657         SLMP_INFO *info = dev_to_port(dev);
1658         int rc;
1659         unsigned long flags;
1660
1661         if (debug_level >= DEBUG_LEVEL_INFO)
1662                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1663
1664         /* generic HDLC layer open processing */
1665         if ((rc = hdlc_open(dev)))
1666                 return rc;
1667
1668         /* arbitrate between network and tty opens */
1669         spin_lock_irqsave(&info->netlock, flags);
1670         if (info->port.count != 0 || info->netcount != 0) {
1671                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1672                 spin_unlock_irqrestore(&info->netlock, flags);
1673                 return -EBUSY;
1674         }
1675         info->netcount=1;
1676         spin_unlock_irqrestore(&info->netlock, flags);
1677
1678         /* claim resources and init adapter */
1679         if ((rc = startup(info)) != 0) {
1680                 spin_lock_irqsave(&info->netlock, flags);
1681                 info->netcount=0;
1682                 spin_unlock_irqrestore(&info->netlock, flags);
1683                 return rc;
1684         }
1685
1686         /* assert DTR and RTS, apply hardware settings */
1687         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1688         program_hw(info);
1689
1690         /* enable network layer transmit */
1691         dev->trans_start = jiffies;
1692         netif_start_queue(dev);
1693
1694         /* inform generic HDLC layer of current DCD status */
1695         spin_lock_irqsave(&info->lock, flags);
1696         get_signals(info);
1697         spin_unlock_irqrestore(&info->lock, flags);
1698         if (info->serial_signals & SerialSignal_DCD)
1699                 netif_carrier_on(dev);
1700         else
1701                 netif_carrier_off(dev);
1702         return 0;
1703 }
1704
1705 /**
1706  * called by network layer when interface is disabled
1707  * shutdown hardware and release resources
1708  *
1709  * dev  pointer to network device structure
1710  *
1711  * returns 0 if success, otherwise error code
1712  */
1713 static int hdlcdev_close(struct net_device *dev)
1714 {
1715         SLMP_INFO *info = dev_to_port(dev);
1716         unsigned long flags;
1717
1718         if (debug_level >= DEBUG_LEVEL_INFO)
1719                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1720
1721         netif_stop_queue(dev);
1722
1723         /* shutdown adapter and release resources */
1724         shutdown(info);
1725
1726         hdlc_close(dev);
1727
1728         spin_lock_irqsave(&info->netlock, flags);
1729         info->netcount=0;
1730         spin_unlock_irqrestore(&info->netlock, flags);
1731
1732         return 0;
1733 }
1734
1735 /**
1736  * called by network layer to process IOCTL call to network device
1737  *
1738  * dev  pointer to network device structure
1739  * ifr  pointer to network interface request structure
1740  * cmd  IOCTL command code
1741  *
1742  * returns 0 if success, otherwise error code
1743  */
1744 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1745 {
1746         const size_t size = sizeof(sync_serial_settings);
1747         sync_serial_settings new_line;
1748         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1749         SLMP_INFO *info = dev_to_port(dev);
1750         unsigned int flags;
1751
1752         if (debug_level >= DEBUG_LEVEL_INFO)
1753                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1754
1755         /* return error if TTY interface open */
1756         if (info->port.count)
1757                 return -EBUSY;
1758
1759         if (cmd != SIOCWANDEV)
1760                 return hdlc_ioctl(dev, ifr, cmd);
1761
1762         switch(ifr->ifr_settings.type) {
1763         case IF_GET_IFACE: /* return current sync_serial_settings */
1764
1765                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1766                 if (ifr->ifr_settings.size < size) {
1767                         ifr->ifr_settings.size = size; /* data size wanted */
1768                         return -ENOBUFS;
1769                 }
1770
1771                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1772                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1773                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1774                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1775
1776                 switch (flags){
1777                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1778                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1779                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1780                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1781                 default: new_line.clock_type = CLOCK_DEFAULT;
1782                 }
1783
1784                 new_line.clock_rate = info->params.clock_speed;
1785                 new_line.loopback   = info->params.loopback ? 1:0;
1786
1787                 if (copy_to_user(line, &new_line, size))
1788                         return -EFAULT;
1789                 return 0;
1790
1791         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1792
1793                 if(!capable(CAP_NET_ADMIN))
1794                         return -EPERM;
1795                 if (copy_from_user(&new_line, line, size))
1796                         return -EFAULT;
1797
1798                 switch (new_line.clock_type)
1799                 {
1800                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1801                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1802                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1803                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1804                 case CLOCK_DEFAULT:  flags = info->params.flags &
1805                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1806                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1807                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1808                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1809                 default: return -EINVAL;
1810                 }
1811
1812                 if (new_line.loopback != 0 && new_line.loopback != 1)
1813                         return -EINVAL;
1814
1815                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1816                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1817                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1818                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1819                 info->params.flags |= flags;
1820
1821                 info->params.loopback = new_line.loopback;
1822
1823                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1824                         info->params.clock_speed = new_line.clock_rate;
1825                 else
1826                         info->params.clock_speed = 0;
1827
1828                 /* if network interface up, reprogram hardware */
1829                 if (info->netcount)
1830                         program_hw(info);
1831                 return 0;
1832
1833         default:
1834                 return hdlc_ioctl(dev, ifr, cmd);
1835         }
1836 }
1837
1838 /**
1839  * called by network layer when transmit timeout is detected
1840  *
1841  * dev  pointer to network device structure
1842  */
1843 static void hdlcdev_tx_timeout(struct net_device *dev)
1844 {
1845         SLMP_INFO *info = dev_to_port(dev);
1846         unsigned long flags;
1847
1848         if (debug_level >= DEBUG_LEVEL_INFO)
1849                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1850
1851         dev->stats.tx_errors++;
1852         dev->stats.tx_aborted_errors++;
1853
1854         spin_lock_irqsave(&info->lock,flags);
1855         tx_stop(info);
1856         spin_unlock_irqrestore(&info->lock,flags);
1857
1858         netif_wake_queue(dev);
1859 }
1860
1861 /**
1862  * called by device driver when transmit completes
1863  * reenable network layer transmit if stopped
1864  *
1865  * info  pointer to device instance information
1866  */
1867 static void hdlcdev_tx_done(SLMP_INFO *info)
1868 {
1869         if (netif_queue_stopped(info->netdev))
1870                 netif_wake_queue(info->netdev);
1871 }
1872
1873 /**
1874  * called by device driver when frame received
1875  * pass frame to network layer
1876  *
1877  * info  pointer to device instance information
1878  * buf   pointer to buffer contianing frame data
1879  * size  count of data bytes in buf
1880  */
1881 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1882 {
1883         struct sk_buff *skb = dev_alloc_skb(size);
1884         struct net_device *dev = info->netdev;
1885
1886         if (debug_level >= DEBUG_LEVEL_INFO)
1887                 printk("hdlcdev_rx(%s)\n",dev->name);
1888
1889         if (skb == NULL) {
1890                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1891                        dev->name);
1892                 dev->stats.rx_dropped++;
1893                 return;
1894         }
1895
1896         memcpy(skb_put(skb, size), buf, size);
1897
1898         skb->protocol = hdlc_type_trans(skb, dev);
1899
1900         dev->stats.rx_packets++;
1901         dev->stats.rx_bytes += size;
1902
1903         netif_rx(skb);
1904 }
1905
1906 static const struct net_device_ops hdlcdev_ops = {
1907         .ndo_open       = hdlcdev_open,
1908         .ndo_stop       = hdlcdev_close,
1909         .ndo_change_mtu = hdlc_change_mtu,
1910         .ndo_start_xmit = hdlc_start_xmit,
1911         .ndo_do_ioctl   = hdlcdev_ioctl,
1912         .ndo_tx_timeout = hdlcdev_tx_timeout,
1913 };
1914
1915 /**
1916  * called by device driver when adding device instance
1917  * do generic HDLC initialization
1918  *
1919  * info  pointer to device instance information
1920  *
1921  * returns 0 if success, otherwise error code
1922  */
1923 static int hdlcdev_init(SLMP_INFO *info)
1924 {
1925         int rc;
1926         struct net_device *dev;
1927         hdlc_device *hdlc;
1928
1929         /* allocate and initialize network and HDLC layer objects */
1930
1931         if (!(dev = alloc_hdlcdev(info))) {
1932                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1933                 return -ENOMEM;
1934         }
1935
1936         /* for network layer reporting purposes only */
1937         dev->mem_start = info->phys_sca_base;
1938         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1939         dev->irq       = info->irq_level;
1940
1941         /* network layer callbacks and settings */
1942         dev->netdev_ops     = &hdlcdev_ops;
1943         dev->watchdog_timeo = 10 * HZ;
1944         dev->tx_queue_len   = 50;
1945
1946         /* generic HDLC layer callbacks and settings */
1947         hdlc         = dev_to_hdlc(dev);
1948         hdlc->attach = hdlcdev_attach;
1949         hdlc->xmit   = hdlcdev_xmit;
1950
1951         /* register objects with HDLC layer */
1952         if ((rc = register_hdlc_device(dev))) {
1953                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1954                 free_netdev(dev);
1955                 return rc;
1956         }
1957
1958         info->netdev = dev;
1959         return 0;
1960 }
1961
1962 /**
1963  * called by device driver when removing device instance
1964  * do generic HDLC cleanup
1965  *
1966  * info  pointer to device instance information
1967  */
1968 static void hdlcdev_exit(SLMP_INFO *info)
1969 {
1970         unregister_hdlc_device(info->netdev);
1971         free_netdev(info->netdev);
1972         info->netdev = NULL;
1973 }
1974
1975 #endif /* CONFIG_HDLC */
1976
1977
1978 /* Return next bottom half action to perform.
1979  * Return Value:        BH action code or 0 if nothing to do.
1980  */
1981 static int bh_action(SLMP_INFO *info)
1982 {
1983         unsigned long flags;
1984         int rc = 0;
1985
1986         spin_lock_irqsave(&info->lock,flags);
1987
1988         if (info->pending_bh & BH_RECEIVE) {
1989                 info->pending_bh &= ~BH_RECEIVE;
1990                 rc = BH_RECEIVE;
1991         } else if (info->pending_bh & BH_TRANSMIT) {
1992                 info->pending_bh &= ~BH_TRANSMIT;
1993                 rc = BH_TRANSMIT;
1994         } else if (info->pending_bh & BH_STATUS) {
1995                 info->pending_bh &= ~BH_STATUS;
1996                 rc = BH_STATUS;
1997         }
1998
1999         if (!rc) {
2000                 /* Mark BH routine as complete */
2001                 info->bh_running = false;
2002                 info->bh_requested = false;
2003         }
2004
2005         spin_unlock_irqrestore(&info->lock,flags);
2006
2007         return rc;
2008 }
2009
2010 /* Perform bottom half processing of work items queued by ISR.
2011  */
2012 static void bh_handler(struct work_struct *work)
2013 {
2014         SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2015         int action;
2016
2017         if (!info)
2018                 return;
2019
2020         if ( debug_level >= DEBUG_LEVEL_BH )
2021                 printk( "%s(%d):%s bh_handler() entry\n",
2022                         __FILE__,__LINE__,info->device_name);
2023
2024         info->bh_running = true;
2025
2026         while((action = bh_action(info)) != 0) {
2027
2028                 /* Process work item */
2029                 if ( debug_level >= DEBUG_LEVEL_BH )
2030                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2031                                 __FILE__,__LINE__,info->device_name, action);
2032
2033                 switch (action) {
2034
2035                 case BH_RECEIVE:
2036                         bh_receive(info);
2037                         break;
2038                 case BH_TRANSMIT:
2039                         bh_transmit(info);
2040                         break;
2041                 case BH_STATUS:
2042                         bh_status(info);
2043                         break;
2044                 default:
2045                         /* unknown work item ID */
2046                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2047                                 __FILE__,__LINE__,info->device_name,action);
2048                         break;
2049                 }
2050         }
2051
2052         if ( debug_level >= DEBUG_LEVEL_BH )
2053                 printk( "%s(%d):%s bh_handler() exit\n",
2054                         __FILE__,__LINE__,info->device_name);
2055 }
2056
2057 static void bh_receive(SLMP_INFO *info)
2058 {
2059         if ( debug_level >= DEBUG_LEVEL_BH )
2060                 printk( "%s(%d):%s bh_receive()\n",
2061                         __FILE__,__LINE__,info->device_name);
2062
2063         while( rx_get_frame(info) );
2064 }
2065
2066 static void bh_transmit(SLMP_INFO *info)
2067 {
2068         struct tty_struct *tty = info->port.tty;
2069
2070         if ( debug_level >= DEBUG_LEVEL_BH )
2071                 printk( "%s(%d):%s bh_transmit() entry\n",
2072                         __FILE__,__LINE__,info->device_name);
2073
2074         if (tty)
2075                 tty_wakeup(tty);
2076 }
2077
2078 static void bh_status(SLMP_INFO *info)
2079 {
2080         if ( debug_level >= DEBUG_LEVEL_BH )
2081                 printk( "%s(%d):%s bh_status() entry\n",
2082                         __FILE__,__LINE__,info->device_name);
2083
2084         info->ri_chkcount = 0;
2085         info->dsr_chkcount = 0;
2086         info->dcd_chkcount = 0;
2087         info->cts_chkcount = 0;
2088 }
2089
2090 static void isr_timer(SLMP_INFO * info)
2091 {
2092         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2093
2094         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2095         write_reg(info, IER2, 0);
2096
2097         /* TMCS, Timer Control/Status Register
2098          *
2099          * 07      CMF, Compare match flag (read only) 1=match
2100          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2101          * 05      Reserved, must be 0
2102          * 04      TME, Timer Enable
2103          * 03..00  Reserved, must be 0
2104          *
2105          * 0000 0000
2106          */
2107         write_reg(info, (unsigned char)(timer + TMCS), 0);
2108
2109         info->irq_occurred = true;
2110
2111         if ( debug_level >= DEBUG_LEVEL_ISR )
2112                 printk("%s(%d):%s isr_timer()\n",
2113                         __FILE__,__LINE__,info->device_name);
2114 }
2115
2116 static void isr_rxint(SLMP_INFO * info)
2117 {
2118         struct tty_struct *tty = info->port.tty;
2119         struct  mgsl_icount *icount = &info->icount;
2120         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2121         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2122
2123         /* clear status bits */
2124         if (status)
2125                 write_reg(info, SR1, status);
2126
2127         if (status2)
2128                 write_reg(info, SR2, status2);
2129
2130         if ( debug_level >= DEBUG_LEVEL_ISR )
2131                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2132                         __FILE__,__LINE__,info->device_name,status,status2);
2133
2134         if (info->params.mode == MGSL_MODE_ASYNC) {
2135                 if (status & BRKD) {
2136                         icount->brk++;
2137
2138                         /* process break detection if tty control
2139                          * is not set to ignore it
2140                          */
2141                         if ( tty ) {
2142                                 if (!(status & info->ignore_status_mask1)) {
2143                                         if (info->read_status_mask1 & BRKD) {
2144                                                 tty_insert_flip_char(tty, 0, TTY_BREAK);
2145                                                 if (info->port.flags & ASYNC_SAK)
2146                                                         do_SAK(tty);
2147                                         }
2148                                 }
2149                         }
2150                 }
2151         }
2152         else {
2153                 if (status & (FLGD|IDLD)) {
2154                         if (status & FLGD)
2155                                 info->icount.exithunt++;
2156                         else if (status & IDLD)
2157                                 info->icount.rxidle++;
2158                         wake_up_interruptible(&info->event_wait_q);
2159                 }
2160         }
2161
2162         if (status & CDCD) {
2163                 /* simulate a common modem status change interrupt
2164                  * for our handler
2165                  */
2166                 get_signals( info );
2167                 isr_io_pin(info,
2168                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2169         }
2170 }
2171
2172 /*
2173  * handle async rx data interrupts
2174  */
2175 static void isr_rxrdy(SLMP_INFO * info)
2176 {
2177         u16 status;
2178         unsigned char DataByte;
2179         struct tty_struct *tty = info->port.tty;
2180         struct  mgsl_icount *icount = &info->icount;
2181
2182         if ( debug_level >= DEBUG_LEVEL_ISR )
2183                 printk("%s(%d):%s isr_rxrdy\n",
2184                         __FILE__,__LINE__,info->device_name);
2185
2186         while((status = read_reg(info,CST0)) & BIT0)
2187         {
2188                 int flag = 0;
2189                 bool over = false;
2190                 DataByte = read_reg(info,TRB);
2191
2192                 icount->rx++;
2193
2194                 if ( status & (PE + FRME + OVRN) ) {
2195                         printk("%s(%d):%s rxerr=%04X\n",
2196                                 __FILE__,__LINE__,info->device_name,status);
2197
2198                         /* update error statistics */
2199                         if (status & PE)
2200                                 icount->parity++;
2201                         else if (status & FRME)
2202                                 icount->frame++;
2203                         else if (status & OVRN)
2204                                 icount->overrun++;
2205
2206                         /* discard char if tty control flags say so */
2207                         if (status & info->ignore_status_mask2)
2208                                 continue;
2209
2210                         status &= info->read_status_mask2;
2211
2212                         if ( tty ) {
2213                                 if (status & PE)
2214                                         flag = TTY_PARITY;
2215                                 else if (status & FRME)
2216                                         flag = TTY_FRAME;
2217                                 if (status & OVRN) {
2218                                         /* Overrun is special, since it's
2219                                          * reported immediately, and doesn't
2220                                          * affect the current character
2221                                          */
2222                                         over = true;
2223                                 }
2224                         }
2225                 }       /* end of if (error) */
2226
2227                 if ( tty ) {
2228                         tty_insert_flip_char(tty, DataByte, flag);
2229                         if (over)
2230                                 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2231                 }
2232         }
2233
2234         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2235                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2236                         __FILE__,__LINE__,info->device_name,
2237                         icount->rx,icount->brk,icount->parity,
2238                         icount->frame,icount->overrun);
2239         }
2240
2241         if ( tty )
2242                 tty_flip_buffer_push(tty);
2243 }
2244
2245 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2246 {
2247         if ( debug_level >= DEBUG_LEVEL_ISR )
2248                 printk("%s(%d):%s isr_txeom status=%02x\n",
2249                         __FILE__,__LINE__,info->device_name,status);
2250
2251         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2252         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2253         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2254
2255         if (status & UDRN) {
2256                 write_reg(info, CMD, TXRESET);
2257                 write_reg(info, CMD, TXENABLE);
2258         } else
2259                 write_reg(info, CMD, TXBUFCLR);
2260
2261         /* disable and clear tx interrupts */
2262         info->ie0_value &= ~TXRDYE;
2263         info->ie1_value &= ~(IDLE + UDRN);
2264         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2265         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2266
2267         if ( info->tx_active ) {
2268                 if (info->params.mode != MGSL_MODE_ASYNC) {
2269                         if (status & UDRN)
2270                                 info->icount.txunder++;
2271                         else if (status & IDLE)
2272                                 info->icount.txok++;
2273                 }
2274
2275                 info->tx_active = false;
2276                 info->tx_count = info->tx_put = info->tx_get = 0;
2277
2278                 del_timer(&info->tx_timer);
2279
2280                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2281                         info->serial_signals &= ~SerialSignal_RTS;
2282                         info->drop_rts_on_tx_done = false;
2283                         set_signals(info);
2284                 }
2285
2286 #if SYNCLINK_GENERIC_HDLC
2287                 if (info->netcount)
2288                         hdlcdev_tx_done(info);
2289                 else
2290 #endif
2291                 {
2292                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2293                                 tx_stop(info);
2294                                 return;
2295                         }
2296                         info->pending_bh |= BH_TRANSMIT;
2297                 }
2298         }
2299 }
2300
2301
2302 /*
2303  * handle tx status interrupts
2304  */
2305 static void isr_txint(SLMP_INFO * info)
2306 {
2307         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2308
2309         /* clear status bits */
2310         write_reg(info, SR1, status);
2311
2312         if ( debug_level >= DEBUG_LEVEL_ISR )
2313                 printk("%s(%d):%s isr_txint status=%02x\n",
2314                         __FILE__,__LINE__,info->device_name,status);
2315
2316         if (status & (UDRN + IDLE))
2317                 isr_txeom(info, status);
2318
2319         if (status & CCTS) {
2320                 /* simulate a common modem status change interrupt
2321                  * for our handler
2322                  */
2323                 get_signals( info );
2324                 isr_io_pin(info,
2325                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2326
2327         }
2328 }
2329
2330 /*
2331  * handle async tx data interrupts
2332  */
2333 static void isr_txrdy(SLMP_INFO * info)
2334 {
2335         if ( debug_level >= DEBUG_LEVEL_ISR )
2336                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2337                         __FILE__,__LINE__,info->device_name,info->tx_count);
2338
2339         if (info->params.mode != MGSL_MODE_ASYNC) {
2340                 /* disable TXRDY IRQ, enable IDLE IRQ */
2341                 info->ie0_value &= ~TXRDYE;
2342                 info->ie1_value |= IDLE;
2343                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2344                 return;
2345         }
2346
2347         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2348                 tx_stop(info);
2349                 return;
2350         }
2351
2352         if ( info->tx_count )
2353                 tx_load_fifo( info );
2354         else {
2355                 info->tx_active = false;
2356                 info->ie0_value &= ~TXRDYE;
2357                 write_reg(info, IE0, info->ie0_value);
2358         }
2359
2360         if (info->tx_count < WAKEUP_CHARS)
2361                 info->pending_bh |= BH_TRANSMIT;
2362 }
2363
2364 static void isr_rxdmaok(SLMP_INFO * info)
2365 {
2366         /* BIT7 = EOT (end of transfer)
2367          * BIT6 = EOM (end of message/frame)
2368          */
2369         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2370
2371         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2372         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2373
2374         if ( debug_level >= DEBUG_LEVEL_ISR )
2375                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2376                         __FILE__,__LINE__,info->device_name,status);
2377
2378         info->pending_bh |= BH_RECEIVE;
2379 }
2380
2381 static void isr_rxdmaerror(SLMP_INFO * info)
2382 {
2383         /* BIT5 = BOF (buffer overflow)
2384          * BIT4 = COF (counter overflow)
2385          */
2386         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2387
2388         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2389         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2390
2391         if ( debug_level >= DEBUG_LEVEL_ISR )
2392                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2393                         __FILE__,__LINE__,info->device_name,status);
2394
2395         info->rx_overflow = true;
2396         info->pending_bh |= BH_RECEIVE;
2397 }
2398
2399 static void isr_txdmaok(SLMP_INFO * info)
2400 {
2401         unsigned char status_reg1 = read_reg(info, SR1);
2402
2403         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2404         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2405         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2406
2407         if ( debug_level >= DEBUG_LEVEL_ISR )
2408                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2409                         __FILE__,__LINE__,info->device_name,status_reg1);
2410
2411         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2412         write_reg16(info, TRC0, 0);
2413         info->ie0_value |= TXRDYE;
2414         write_reg(info, IE0, info->ie0_value);
2415 }
2416
2417 static void isr_txdmaerror(SLMP_INFO * info)
2418 {
2419         /* BIT5 = BOF (buffer overflow)
2420          * BIT4 = COF (counter overflow)
2421          */
2422         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2423
2424         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2425         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2426
2427         if ( debug_level >= DEBUG_LEVEL_ISR )
2428                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2429                         __FILE__,__LINE__,info->device_name,status);
2430 }
2431
2432 /* handle input serial signal changes
2433  */
2434 static void isr_io_pin( SLMP_INFO *info, u16 status )
2435 {
2436         struct  mgsl_icount *icount;
2437
2438         if ( debug_level >= DEBUG_LEVEL_ISR )
2439                 printk("%s(%d):isr_io_pin status=%04X\n",
2440                         __FILE__,__LINE__,status);
2441
2442         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2443                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2444                 icount = &info->icount;
2445                 /* update input line counters */
2446                 if (status & MISCSTATUS_RI_LATCHED) {
2447                         icount->rng++;
2448                         if ( status & SerialSignal_RI )
2449                                 info->input_signal_events.ri_up++;
2450                         else
2451                                 info->input_signal_events.ri_down++;
2452                 }
2453                 if (status & MISCSTATUS_DSR_LATCHED) {
2454                         icount->dsr++;
2455                         if ( status & SerialSignal_DSR )
2456                                 info->input_signal_events.dsr_up++;
2457                         else
2458                                 info->input_signal_events.dsr_down++;
2459                 }
2460                 if (status & MISCSTATUS_DCD_LATCHED) {
2461                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2462                                 info->ie1_value &= ~CDCD;
2463                                 write_reg(info, IE1, info->ie1_value);
2464                         }
2465                         icount->dcd++;
2466                         if (status & SerialSignal_DCD) {
2467                                 info->input_signal_events.dcd_up++;
2468                         } else
2469                                 info->input_signal_events.dcd_down++;
2470 #if SYNCLINK_GENERIC_HDLC
2471                         if (info->netcount) {
2472                                 if (status & SerialSignal_DCD)
2473                                         netif_carrier_on(info->netdev);
2474                                 else
2475                                         netif_carrier_off(info->netdev);
2476                         }
2477 #endif
2478                 }
2479                 if (status & MISCSTATUS_CTS_LATCHED)
2480                 {
2481                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2482                                 info->ie1_value &= ~CCTS;
2483                                 write_reg(info, IE1, info->ie1_value);
2484                         }
2485                         icount->cts++;
2486                         if ( status & SerialSignal_CTS )
2487                                 info->input_signal_events.cts_up++;
2488                         else
2489                                 info->input_signal_events.cts_down++;
2490                 }
2491                 wake_up_interruptible(&info->status_event_wait_q);
2492                 wake_up_interruptible(&info->event_wait_q);
2493
2494                 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2495                      (status & MISCSTATUS_DCD_LATCHED) ) {
2496                         if ( debug_level >= DEBUG_LEVEL_ISR )
2497                                 printk("%s CD now %s...", info->device_name,
2498                                        (status & SerialSignal_DCD) ? "on" : "off");
2499                         if (status & SerialSignal_DCD)
2500                                 wake_up_interruptible(&info->port.open_wait);
2501                         else {
2502                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2503                                         printk("doing serial hangup...");
2504                                 if (info->port.tty)
2505                                         tty_hangup(info->port.tty);
2506                         }
2507                 }
2508
2509                 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
2510                      (status & MISCSTATUS_CTS_LATCHED) ) {
2511                         if ( info->port.tty ) {
2512                                 if (info->port.tty->hw_stopped) {
2513                                         if (status & SerialSignal_CTS) {
2514                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2515                                                         printk("CTS tx start...");
2516                                                 info->port.tty->hw_stopped = 0;
2517                                                 tx_start(info);
2518                                                 info->pending_bh |= BH_TRANSMIT;
2519                                                 return;
2520                                         }
2521                                 } else {
2522                                         if (!(status & SerialSignal_CTS)) {
2523                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2524                                                         printk("CTS tx stop...");
2525                                                 info->port.tty->hw_stopped = 1;
2526                                                 tx_stop(info);
2527                                         }
2528                                 }
2529                         }
2530                 }
2531         }
2532
2533         info->pending_bh |= BH_STATUS;
2534 }
2535
2536 /* Interrupt service routine entry point.
2537  *
2538  * Arguments:
2539  *      irq             interrupt number that caused interrupt
2540  *      dev_id          device ID supplied during interrupt registration
2541  *      regs            interrupted processor context
2542  */
2543 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2544 {
2545         SLMP_INFO *info = dev_id;
2546         unsigned char status, status0, status1=0;
2547         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2548         unsigned char timerstatus0, timerstatus1=0;
2549         unsigned char shift;
2550         unsigned int i;
2551         unsigned short tmp;
2552
2553         if ( debug_level >= DEBUG_LEVEL_ISR )
2554                 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2555                         __FILE__, __LINE__, info->irq_level);
2556
2557         spin_lock(&info->lock);
2558
2559         for(;;) {
2560
2561                 /* get status for SCA0 (ports 0-1) */
2562                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2563                 status0 = (unsigned char)tmp;
2564                 dmastatus0 = (unsigned char)(tmp>>8);
2565                 timerstatus0 = read_reg(info, ISR2);
2566
2567                 if ( debug_level >= DEBUG_LEVEL_ISR )
2568                         printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2569                                 __FILE__, __LINE__, info->device_name,
2570                                 status0, dmastatus0, timerstatus0);
2571
2572                 if (info->port_count == 4) {
2573                         /* get status for SCA1 (ports 2-3) */
2574                         tmp = read_reg16(info->port_array[2], ISR0);
2575                         status1 = (unsigned char)tmp;
2576                         dmastatus1 = (unsigned char)(tmp>>8);
2577                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2578
2579                         if ( debug_level >= DEBUG_LEVEL_ISR )
2580                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2581                                         __FILE__,__LINE__,info->device_name,
2582                                         status1,dmastatus1,timerstatus1);
2583                 }
2584
2585                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2586                          !status1 && !dmastatus1 && !timerstatus1)
2587                         break;
2588
2589                 for(i=0; i < info->port_count ; i++) {
2590                         if (info->port_array[i] == NULL)
2591                                 continue;
2592                         if (i < 2) {
2593                                 status = status0;
2594                                 dmastatus = dmastatus0;
2595                         } else {
2596                                 status = status1;
2597                                 dmastatus = dmastatus1;
2598                         }
2599
2600                         shift = i & 1 ? 4 :0;
2601
2602                         if (status & BIT0 << shift)
2603                                 isr_rxrdy(info->port_array[i]);
2604                         if (status & BIT1 << shift)
2605                                 isr_txrdy(info->port_array[i]);
2606                         if (status & BIT2 << shift)
2607                                 isr_rxint(info->port_array[i]);
2608                         if (status & BIT3 << shift)
2609                                 isr_txint(info->port_array[i]);
2610
2611                         if (dmastatus & BIT0 << shift)
2612                                 isr_rxdmaerror(info->port_array[i]);
2613                         if (dmastatus & BIT1 << shift)
2614                                 isr_rxdmaok(info->port_array[i]);
2615                         if (dmastatus & BIT2 << shift)
2616                                 isr_txdmaerror(info->port_array[i]);
2617                         if (dmastatus & BIT3 << shift)
2618                                 isr_txdmaok(info->port_array[i]);
2619                 }
2620
2621                 if (timerstatus0 & (BIT5 | BIT4))
2622                         isr_timer(info->port_array[0]);
2623                 if (timerstatus0 & (BIT7 | BIT6))
2624                         isr_timer(info->port_array[1]);
2625                 if (timerstatus1 & (BIT5 | BIT4))
2626                         isr_timer(info->port_array[2]);
2627                 if (timerstatus1 & (BIT7 | BIT6))
2628                         isr_timer(info->port_array[3]);
2629         }
2630
2631         for(i=0; i < info->port_count ; i++) {
2632                 SLMP_INFO * port = info->port_array[i];
2633
2634                 /* Request bottom half processing if there's something
2635                  * for it to do and the bh is not already running.
2636                  *
2637                  * Note: startup adapter diags require interrupts.
2638                  * do not request bottom half processing if the
2639                  * device is not open in a normal mode.
2640                  */
2641                 if ( port && (port->port.count || port->netcount) &&
2642                      port->pending_bh && !port->bh_running &&
2643                      !port->bh_requested ) {
2644                         if ( debug_level >= DEBUG_LEVEL_ISR )
2645                                 printk("%s(%d):%s queueing bh task.\n",
2646                                         __FILE__,__LINE__,port->device_name);
2647                         schedule_work(&port->task);
2648                         port->bh_requested = true;
2649                 }
2650         }
2651
2652         spin_unlock(&info->lock);
2653
2654         if ( debug_level >= DEBUG_LEVEL_ISR )
2655                 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2656                         __FILE__, __LINE__, info->irq_level);
2657         return IRQ_HANDLED;
2658 }
2659
2660 /* Initialize and start device.
2661  */
2662 static int startup(SLMP_INFO * info)
2663 {
2664         if ( debug_level >= DEBUG_LEVEL_INFO )
2665                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2666
2667         if (info->port.flags & ASYNC_INITIALIZED)
2668                 return 0;
2669
2670         if (!info->tx_buf) {
2671                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2672                 if (!info->tx_buf) {
2673                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2674                                 __FILE__,__LINE__,info->device_name);
2675                         return -ENOMEM;
2676                 }
2677         }
2678
2679         info->pending_bh = 0;
2680
2681         memset(&info->icount, 0, sizeof(info->icount));
2682
2683         /* program hardware for current parameters */
2684         reset_port(info);
2685
2686         change_params(info);
2687
2688         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2689
2690         if (info->port.tty)
2691                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2692
2693         info->port.flags |= ASYNC_INITIALIZED;
2694
2695         return 0;
2696 }
2697
2698 /* Called by close() and hangup() to shutdown hardware
2699  */
2700 static void shutdown(SLMP_INFO * info)
2701 {
2702         unsigned long flags;
2703
2704         if (!(info->port.flags & ASYNC_INITIALIZED))
2705                 return;
2706
2707         if (debug_level >= DEBUG_LEVEL_INFO)
2708                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2709                          __FILE__,__LINE__, info->device_name );
2710
2711         /* clear status wait queue because status changes */
2712         /* can't happen after shutting down the hardware */
2713         wake_up_interruptible(&info->status_event_wait_q);
2714         wake_up_interruptible(&info->event_wait_q);
2715
2716         del_timer(&info->tx_timer);
2717         del_timer(&info->status_timer);
2718
2719         kfree(info->tx_buf);
2720         info->tx_buf = NULL;
2721
2722         spin_lock_irqsave(&info->lock,flags);
2723
2724         reset_port(info);
2725
2726         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2727                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2728                 set_signals(info);
2729         }
2730
2731         spin_unlock_irqrestore(&info->lock,flags);
2732
2733         if (info->port.tty)
2734                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2735
2736         info->port.flags &= ~ASYNC_INITIALIZED;
2737 }
2738
2739 static void program_hw(SLMP_INFO *info)
2740 {
2741         unsigned long flags;
2742
2743         spin_lock_irqsave(&info->lock,flags);
2744
2745         rx_stop(info);
2746         tx_stop(info);
2747
2748         info->tx_count = info->tx_put = info->tx_get = 0;
2749
2750         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2751                 hdlc_mode(info);
2752         else
2753                 async_mode(info);
2754
2755         set_signals(info);
2756
2757         info->dcd_chkcount = 0;
2758         info->cts_chkcount = 0;
2759         info->ri_chkcount = 0;
2760         info->dsr_chkcount = 0;
2761
2762         info->ie1_value |= (CDCD|CCTS);
2763         write_reg(info, IE1, info->ie1_value);
2764
2765         get_signals(info);
2766
2767         if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) )
2768                 rx_start(info);
2769
2770         spin_unlock_irqrestore(&info->lock,flags);
2771 }
2772
2773 /* Reconfigure adapter based on new parameters
2774  */
2775 static void change_params(SLMP_INFO *info)
2776 {
2777         unsigned cflag;
2778         int bits_per_char;
2779
2780         if (!info->port.tty || !info->port.tty->termios)
2781                 return;
2782
2783         if (debug_level >= DEBUG_LEVEL_INFO)
2784                 printk("%s(%d):%s change_params()\n",
2785                          __FILE__,__LINE__, info->device_name );
2786
2787         cflag = info->port.tty->termios->c_cflag;
2788
2789         /* if B0 rate (hangup) specified then negate DTR and RTS */
2790         /* otherwise assert DTR and RTS */
2791         if (cflag & CBAUD)
2792                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2793         else
2794                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2795
2796         /* byte size and parity */
2797
2798         switch (cflag & CSIZE) {
2799               case CS5: info->params.data_bits = 5; break;
2800               case CS6: info->params.data_bits = 6; break;
2801               case CS7: info->params.data_bits = 7; break;
2802               case CS8: info->params.data_bits = 8; break;
2803               /* Never happens, but GCC is too dumb to figure it out */
2804               default:  info->params.data_bits = 7; break;
2805               }
2806
2807         if (cflag & CSTOPB)
2808                 info->params.stop_bits = 2;
2809         else
2810                 info->params.stop_bits = 1;
2811
2812         info->params.parity = ASYNC_PARITY_NONE;
2813         if (cflag & PARENB) {
2814                 if (cflag & PARODD)
2815                         info->params.parity = ASYNC_PARITY_ODD;
2816                 else
2817                         info->params.parity = ASYNC_PARITY_EVEN;
2818 #ifdef CMSPAR
2819                 if (cflag & CMSPAR)
2820                         info->params.parity = ASYNC_PARITY_SPACE;
2821 #endif
2822         }
2823
2824         /* calculate number of jiffies to transmit a full
2825          * FIFO (32 bytes) at specified data rate
2826          */
2827         bits_per_char = info->params.data_bits +
2828                         info->params.stop_bits + 1;
2829
2830         /* if port data rate is set to 460800 or less then
2831          * allow tty settings to override, otherwise keep the
2832          * current data rate.
2833          */
2834         if (info->params.data_rate <= 460800) {
2835                 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2836         }
2837
2838         if ( info->params.data_rate ) {
2839                 info->timeout = (32*HZ*bits_per_char) /
2840                                 info->params.data_rate;
2841         }
2842         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2843
2844         if (cflag & CRTSCTS)
2845                 info->port.flags |= ASYNC_CTS_FLOW;
2846         else
2847                 info->port.flags &= ~ASYNC_CTS_FLOW;
2848
2849         if (cflag & CLOCAL)
2850                 info->port.flags &= ~ASYNC_CHECK_CD;
2851         else
2852                 info->port.flags |= ASYNC_CHECK_CD;
2853
2854         /* process tty input control flags */
2855
2856         info->read_status_mask2 = OVRN;
2857         if (I_INPCK(info->port.tty))
2858                 info->read_status_mask2 |= PE | FRME;
2859         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2860                 info->read_status_mask1 |= BRKD;
2861         if (I_IGNPAR(info->port.tty))
2862                 info->ignore_status_mask2 |= PE | FRME;
2863         if (I_IGNBRK(info->port.tty)) {
2864                 info->ignore_status_mask1 |= BRKD;
2865                 /* If ignoring parity and break indicators, ignore
2866                  * overruns too.  (For real raw support).
2867                  */
2868                 if (I_IGNPAR(info->port.tty))
2869                         info->ignore_status_mask2 |= OVRN;
2870         }
2871
2872         program_hw(info);
2873 }
2874
2875 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2876 {
2877         int err;
2878
2879         if (debug_level >= DEBUG_LEVEL_INFO)
2880                 printk("%s(%d):%s get_params()\n",
2881                          __FILE__,__LINE__, info->device_name);
2882
2883         if (!user_icount) {
2884                 memset(&info->icount, 0, sizeof(info->icount));
2885         } else {
2886                 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2887                 if (err)
2888                         return -EFAULT;
2889         }
2890
2891         return 0;
2892 }
2893
2894 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2895 {
2896         int err;
2897         if (debug_level >= DEBUG_LEVEL_INFO)
2898                 printk("%s(%d):%s get_params()\n",
2899                          __FILE__,__LINE__, info->device_name);
2900
2901         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2902         if (err) {
2903                 if ( debug_level >= DEBUG_LEVEL_INFO )
2904                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2905                                 __FILE__,__LINE__,info->device_name);
2906                 return -EFAULT;
2907         }
2908
2909         return 0;
2910 }
2911
2912 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2913 {
2914         unsigned long flags;
2915         MGSL_PARAMS tmp_params;
2916         int err;
2917
2918         if (debug_level >= DEBUG_LEVEL_INFO)
2919                 printk("%s(%d):%s set_params\n",
2920                         __FILE__,__LINE__,info->device_name );
2921         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2922         if (err) {
2923                 if ( debug_level >= DEBUG_LEVEL_INFO )
2924                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2925                                 __FILE__,__LINE__,info->device_name);
2926                 return -EFAULT;
2927         }
2928
2929         spin_lock_irqsave(&info->lock,flags);
2930         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2931         spin_unlock_irqrestore(&info->lock,flags);
2932
2933         change_params(info);
2934
2935         return 0;
2936 }
2937
2938 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2939 {
2940         int err;
2941
2942         if (debug_level >= DEBUG_LEVEL_INFO)
2943                 printk("%s(%d):%s get_txidle()=%d\n",
2944                          __FILE__,__LINE__, info->device_name, info->idle_mode);
2945
2946         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2947         if (err) {
2948                 if ( debug_level >= DEBUG_LEVEL_INFO )
2949                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2950                                 __FILE__,__LINE__,info->device_name);
2951                 return -EFAULT;
2952         }
2953
2954         return 0;
2955 }
2956
2957 static int set_txidle(SLMP_INFO * info, int idle_mode)
2958 {
2959         unsigned long flags;
2960
2961         if (debug_level >= DEBUG_LEVEL_INFO)
2962                 printk("%s(%d):%s set_txidle(%d)\n",
2963                         __FILE__,__LINE__,info->device_name, idle_mode );
2964
2965         spin_lock_irqsave(&info->lock,flags);
2966         info->idle_mode = idle_mode;
2967         tx_set_idle( info );
2968         spin_unlock_irqrestore(&info->lock,flags);
2969         return 0;
2970 }
2971
2972 static int tx_enable(SLMP_INFO * info, int enable)
2973 {
2974         unsigned long flags;
2975
2976         if (debug_level >= DEBUG_LEVEL_INFO)
2977                 printk("%s(%d):%s tx_enable(%d)\n",
2978                         __FILE__,__LINE__,info->device_name, enable);
2979
2980         spin_lock_irqsave(&info->lock,flags);
2981         if ( enable ) {
2982                 if ( !info->tx_enabled ) {
2983                         tx_start(info);
2984                 }
2985         } else {
2986                 if ( info->tx_enabled )
2987                         tx_stop(info);
2988         }
2989         spin_unlock_irqrestore(&info->lock,flags);
2990         return 0;
2991 }
2992
2993 /* abort send HDLC frame
2994  */
2995 static int tx_abort(SLMP_INFO * info)
2996 {
2997         unsigned long flags;
2998
2999         if (debug_level >= DEBUG_LEVEL_INFO)
3000                 printk("%s(%d):%s tx_abort()\n",
3001                         __FILE__,__LINE__,info->device_name);
3002
3003         spin_lock_irqsave(&info->lock,flags);
3004         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3005                 info->ie1_value &= ~UDRN;
3006                 info->ie1_value |= IDLE;
3007                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3008                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3009
3010                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3011                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3012
3013                 write_reg(info, CMD, TXABORT);
3014         }
3015         spin_unlock_irqrestore(&info->lock,flags);
3016         return 0;
3017 }
3018
3019 static int rx_enable(SLMP_INFO * info, int enable)
3020 {
3021         unsigned long flags;
3022
3023         if (debug_level >= DEBUG_LEVEL_INFO)
3024                 printk("%s(%d):%s rx_enable(%d)\n",
3025                         __FILE__,__LINE__,info->device_name,enable);
3026
3027         spin_lock_irqsave(&info->lock,flags);
3028         if ( enable ) {
3029                 if ( !info->rx_enabled )
3030                         rx_start(info);
3031         } else {
3032                 if ( info->rx_enabled )
3033                         rx_stop(info);
3034         }
3035         spin_unlock_irqrestore(&info->lock,flags);
3036         return 0;
3037 }
3038
3039 /* wait for specified event to occur
3040  */
3041 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3042 {
3043         unsigned long flags;
3044         int s;
3045         int rc=0;
3046         struct mgsl_icount cprev, cnow;
3047         int events;
3048         int mask;
3049         struct  _input_signal_events oldsigs, newsigs;
3050         DECLARE_WAITQUEUE(wait, current);
3051
3052         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3053         if (rc) {
3054                 return  -EFAULT;
3055         }
3056
3057         if (debug_level >= DEBUG_LEVEL_INFO)
3058                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3059                         __FILE__,__LINE__,info->device_name,mask);
3060
3061         spin_lock_irqsave(&info->lock,flags);
3062
3063         /* return immediately if state matches requested events */
3064         get_signals(info);
3065         s = info->serial_signals;
3066
3067         events = mask &
3068                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3069                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3070                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3071                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3072         if (events) {
3073                 spin_unlock_irqrestore(&info->lock,flags);
3074                 goto exit;
3075         }
3076
3077         /* save current irq counts */
3078         cprev = info->icount;
3079         oldsigs = info->input_signal_events;
3080
3081         /* enable hunt and idle irqs if needed */
3082         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3083                 unsigned char oldval = info->ie1_value;
3084                 unsigned char newval = oldval +
3085                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3086                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3087                 if ( oldval != newval ) {
3088                         info->ie1_value = newval;
3089                         write_reg(info, IE1, info->ie1_value);
3090                 }
3091         }
3092
3093         set_current_state(TASK_INTERRUPTIBLE);
3094         add_wait_queue(&info->event_wait_q, &wait);
3095
3096         spin_unlock_irqrestore(&info->lock,flags);
3097
3098         for(;;) {
3099                 schedule();
3100                 if (signal_pending(current)) {
3101                         rc = -ERESTARTSYS;
3102                         break;
3103                 }
3104
3105                 /* get current irq counts */
3106                 spin_lock_irqsave(&info->lock,flags);
3107                 cnow = info->icount;
3108                 newsigs = info->input_signal_events;
3109                 set_current_state(TASK_INTERRUPTIBLE);
3110                 spin_unlock_irqrestore(&info->lock,flags);
3111
3112                 /* if no change, wait aborted for some reason */
3113                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3114                     newsigs.dsr_down == oldsigs.dsr_down &&
3115                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3116                     newsigs.dcd_down == oldsigs.dcd_down &&
3117                     newsigs.cts_up   == oldsigs.cts_up   &&
3118                     newsigs.cts_down == oldsigs.cts_down &&
3119                     newsigs.ri_up    == oldsigs.ri_up    &&
3120                     newsigs.ri_down  == oldsigs.ri_down  &&
3121                     cnow.exithunt    == cprev.exithunt   &&
3122                     cnow.rxidle      == cprev.rxidle) {
3123                         rc = -EIO;
3124                         break;
3125                 }
3126
3127                 events = mask &
3128                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3129                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3130                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3131                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3132                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3133                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3134                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3135                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3136                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3137                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3138                 if (events)
3139                         break;
3140
3141                 cprev = cnow;
3142                 oldsigs = newsigs;
3143         }
3144
3145         remove_wait_queue(&info->event_wait_q, &wait);
3146         set_current_state(TASK_RUNNING);
3147
3148
3149         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3150                 spin_lock_irqsave(&info->lock,flags);
3151                 if (!waitqueue_active(&info->event_wait_q)) {
3152                         /* disable enable exit hunt mode/idle rcvd IRQs */
3153                         info->ie1_value &= ~(FLGD|IDLD);
3154                         write_reg(info, IE1, info->ie1_value);
3155                 }
3156                 spin_unlock_irqrestore(&info->lock,flags);
3157         }
3158 exit:
3159         if ( rc == 0 )
3160                 PUT_USER(rc, events, mask_ptr);
3161
3162         return rc;
3163 }
3164
3165 static int modem_input_wait(SLMP_INFO *info,int arg)
3166 {
3167         unsigned long flags;
3168         int rc;
3169         struct mgsl_icount cprev, cnow;
3170         DECLARE_WAITQUEUE(wait, current);
3171
3172         /* save current irq counts */
3173         spin_lock_irqsave(&info->lock,flags);
3174         cprev = info->icount;
3175         add_wait_queue(&info->status_event_wait_q, &wait);
3176         set_current_state(TASK_INTERRUPTIBLE);
3177         spin_unlock_irqrestore(&info->lock,flags);
3178
3179         for(;;) {
3180                 schedule();
3181                 if (signal_pending(current)) {
3182                         rc = -ERESTARTSYS;
3183                         break;
3184                 }
3185
3186                 /* get new irq counts */
3187                 spin_lock_irqsave(&info->lock,flags);
3188                 cnow = info->icount;
3189                 set_current_state(TASK_INTERRUPTIBLE);
3190                 spin_unlock_irqrestore(&info->lock,flags);
3191
3192                 /* if no change, wait aborted for some reason */
3193                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3194                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3195                         rc = -EIO;
3196                         break;
3197                 }
3198
3199                 /* check for change in caller specified modem input */
3200                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3201                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3202                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3203                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3204                         rc = 0;
3205                         break;
3206                 }
3207
3208                 cprev = cnow;
3209         }
3210         remove_wait_queue(&info->status_event_wait_q, &wait);
3211         set_current_state(TASK_RUNNING);
3212         return rc;
3213 }
3214
3215 /* return the state of the serial control and status signals
3216  */
3217 static int tiocmget(struct tty_struct *tty, struct file *file)
3218 {
3219         SLMP_INFO *info = tty->driver_data;
3220         unsigned int result;
3221         unsigned long flags;
3222
3223         spin_lock_irqsave(&info->lock,flags);
3224         get_signals(info);
3225         spin_unlock_irqrestore(&info->lock,flags);
3226
3227         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3228                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3229                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3230                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3231                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3232                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3233
3234         if (debug_level >= DEBUG_LEVEL_INFO)
3235                 printk("%s(%d):%s tiocmget() value=%08X\n",
3236                          __FILE__,__LINE__, info->device_name, result );
3237         return result;
3238 }
3239
3240 /* set modem control signals (DTR/RTS)
3241  */
3242 static int tiocmset(struct tty_struct *tty, struct file *file,
3243                     unsigned int set, unsigned int clear)
3244 {
3245         SLMP_INFO *info = tty->driver_data;
3246         unsigned long flags;
3247
3248         if (debug_level >= DEBUG_LEVEL_INFO)
3249                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3250                         __FILE__,__LINE__,info->device_name, set, clear);
3251
3252         if (set & TIOCM_RTS)
3253                 info->serial_signals |= SerialSignal_RTS;
3254         if (set & TIOCM_DTR)
3255                 info->serial_signals |= SerialSignal_DTR;
3256         if (clear & TIOCM_RTS)
3257                 info->serial_signals &= ~SerialSignal_RTS;
3258         if (clear & TIOCM_DTR)
3259                 info->serial_signals &= ~SerialSignal_DTR;
3260
3261         spin_lock_irqsave(&info->lock,flags);
3262         set_signals(info);
3263         spin_unlock_irqrestore(&info->lock,flags);
3264
3265         return 0;
3266 }
3267
3268 static int carrier_raised(struct tty_port *port)
3269 {
3270         SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3271         unsigned long flags;
3272
3273         spin_lock_irqsave(&info->lock,flags);
3274         get_signals(info);
3275         spin_unlock_irqrestore(&info->lock,flags);
3276
3277         return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3278 }
3279
3280 static void dtr_rts(struct tty_port *port, int on)
3281 {
3282         SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3283         unsigned long flags;
3284
3285         spin_lock_irqsave(&info->lock,flags);
3286         if (on)
3287                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3288         else
3289                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3290         set_signals(info);
3291         spin_unlock_irqrestore(&info->lock,flags);
3292 }
3293
3294 /* Block the current process until the specified port is ready to open.
3295  */
3296 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3297                            SLMP_INFO *info)
3298 {
3299         DECLARE_WAITQUEUE(wait, current);
3300         int             retval;
3301         bool            do_clocal = false;
3302         bool            extra_count = false;
3303         unsigned long   flags;
3304         int             cd;
3305         struct tty_port *port = &info->port;
3306
3307         if (debug_level >= DEBUG_LEVEL_INFO)
3308                 printk("%s(%d):%s block_til_ready()\n",
3309                          __FILE__,__LINE__, tty->driver->name );
3310
3311         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3312                 /* nonblock mode is set or port is not enabled */
3313                 /* just verify that callout device is not active */
3314                 port->flags |= ASYNC_NORMAL_ACTIVE;
3315                 return 0;
3316         }
3317
3318         if (tty->termios->c_cflag & CLOCAL)
3319                 do_clocal = true;
3320
3321         /* Wait for carrier detect and the line to become
3322          * free (i.e., not in use by the callout).  While we are in
3323          * this loop, port->count is dropped by one, so that
3324          * close() knows when to free things.  We restore it upon
3325          * exit, either normal or abnormal.
3326          */
3327
3328         retval = 0;
3329         add_wait_queue(&port->open_wait, &wait);
3330
3331         if (debug_level >= DEBUG_LEVEL_INFO)
3332                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3333                          __FILE__,__LINE__, tty->driver->name, port->count );
3334
3335         spin_lock_irqsave(&info->lock, flags);
3336         if (!tty_hung_up_p(filp)) {
3337                 extra_count = true;
3338                 port->count--;
3339         }
3340         spin_unlock_irqrestore(&info->lock, flags);
3341         port->blocked_open++;
3342
3343         while (1) {
3344                 if (tty->termios->c_cflag & CBAUD)
3345                         tty_port_raise_dtr_rts(port);
3346
3347                 set_current_state(TASK_INTERRUPTIBLE);
3348
3349                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3350                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3351                                         -EAGAIN : -ERESTARTSYS;
3352                         break;
3353                 }
3354
3355                 cd = tty_port_carrier_raised(port);
3356
3357                 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd))
3358                         break;
3359
3360                 if (signal_pending(current)) {
3361                         retval = -ERESTARTSYS;
3362                         break;
3363                 }
3364
3365                 if (debug_level >= DEBUG_LEVEL_INFO)
3366                         printk("%s(%d):%s block_til_ready() count=%d\n",
3367                                  __FILE__,__LINE__, tty->driver->name, port->count );
3368
3369                 schedule();
3370         }
3371
3372         set_current_state(TASK_RUNNING);
3373         remove_wait_queue(&port->open_wait, &wait);
3374
3375         if (extra_count)
3376                 port->count++;
3377         port->blocked_open--;
3378
3379         if (debug_level >= DEBUG_LEVEL_INFO)
3380                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3381                          __FILE__,__LINE__, tty->driver->name, port->count );
3382
3383         if (!retval)
3384                 port->flags |= ASYNC_NORMAL_ACTIVE;
3385
3386         return retval;
3387 }
3388
3389 static int alloc_dma_bufs(SLMP_INFO *info)
3390 {
3391         unsigned short BuffersPerFrame;
3392         unsigned short BufferCount;
3393
3394         // Force allocation to start at 64K boundary for each port.
3395         // This is necessary because *all* buffer descriptors for a port
3396         // *must* be in the same 64K block. All descriptors on a port
3397         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3398         // into the CBP register.
3399         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3400
3401         /* Calculate the number of DMA buffers necessary to hold the */
3402         /* largest allowable frame size. Note: If the max frame size is */
3403         /* not an even multiple of the DMA buffer size then we need to */
3404         /* round the buffer count per frame up one. */
3405
3406         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3407         if ( info->max_frame_size % SCABUFSIZE )
3408                 BuffersPerFrame++;
3409
3410         /* calculate total number of data buffers (SCABUFSIZE) possible
3411          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3412          * for the descriptor list (BUFFERLISTSIZE).
3413          */
3414         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3415
3416         /* limit number of buffers to maximum amount of descriptors */
3417         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3418                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3419
3420         /* use enough buffers to transmit one max size frame */
3421         info->tx_buf_count = BuffersPerFrame + 1;
3422
3423         /* never use more than half the available buffers for transmit */
3424         if (info->tx_buf_count > (BufferCount/2))
3425                 info->tx_buf_count = BufferCount/2;
3426
3427         if (info->tx_buf_count > SCAMAXDESC)
3428                 info->tx_buf_count = SCAMAXDESC;
3429
3430         /* use remaining buffers for receive */
3431         info->rx_buf_count = BufferCount - info->tx_buf_count;
3432
3433         if (info->rx_buf_count > SCAMAXDESC)
3434                 info->rx_buf_count = SCAMAXDESC;
3435
3436         if ( debug_level >= DEBUG_LEVEL_INFO )
3437                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3438                         __FILE__,__LINE__, info->device_name,
3439                         info->tx_buf_count,info->rx_buf_count);
3440
3441         if ( alloc_buf_list( info ) < 0 ||
3442                 alloc_frame_bufs(info,
3443                                         info->rx_buf_list,
3444                                         info->rx_buf_list_ex,
3445                                         info->rx_buf_count) < 0 ||
3446                 alloc_frame_bufs(info,
3447                                         info->tx_buf_list,
3448                                         info->tx_buf_list_ex,
3449                                         info->tx_buf_count) < 0 ||
3450                 alloc_tmp_rx_buf(info) < 0 ) {
3451                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3452                         __FILE__,__LINE__, info->device_name);
3453                 return -ENOMEM;
3454         }
3455
3456         rx_reset_buffers( info );
3457
3458         return 0;
3459 }
3460
3461 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3462  */
3463 static int alloc_buf_list(SLMP_INFO *info)
3464 {
3465         unsigned int i;
3466
3467         /* build list in adapter shared memory */
3468         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3469         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3470         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3471
3472         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3473
3474         /* Save virtual address pointers to the receive and */
3475         /* transmit buffer lists. (Receive 1st). These pointers will */
3476         /* be used by the processor to access the lists. */
3477         info->rx_buf_list = (SCADESC *)info->buffer_list;
3478
3479         info->tx_buf_list = (SCADESC *)info->buffer_list;
3480         info->tx_buf_list += info->rx_buf_count;
3481
3482         /* Build links for circular buffer entry lists (tx and rx)
3483          *
3484          * Note: links are physical addresses read by the SCA device
3485          * to determine the next buffer entry to use.
3486          */
3487
3488         for ( i = 0; i < info->rx_buf_count; i++ ) {
3489                 /* calculate and store physical address of this buffer entry */
3490                 info->rx_buf_list_ex[i].phys_entry =
3491                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3492
3493                 /* calculate and store physical address of */
3494                 /* next entry in cirular list of entries */
3495                 info->rx_buf_list[i].next = info->buffer_list_phys;
3496                 if ( i < info->rx_buf_count - 1 )
3497                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3498
3499                 info->rx_buf_list[i].length = SCABUFSIZE;
3500         }
3501
3502         for ( i = 0; i < info->tx_buf_count; i++ ) {
3503                 /* calculate and store physical address of this buffer entry */
3504                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3505                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3506
3507                 /* calculate and store physical address of */
3508                 /* next entry in cirular list of entries */
3509
3510                 info->tx_buf_list[i].next = info->buffer_list_phys +
3511                         info->rx_buf_count * sizeof(SCADESC);
3512
3513                 if ( i < info->tx_buf_count - 1 )
3514                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3515         }
3516
3517         return 0;
3518 }
3519
3520 /* Allocate the frame DMA buffers used by the specified buffer list.
3521  */
3522 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3523 {
3524         int i;
3525         unsigned long phys_addr;
3526
3527         for ( i = 0; i < count; i++ ) {
3528                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3529                 phys_addr = info->port_array[0]->last_mem_alloc;
3530                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3531
3532                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3533                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3534         }
3535
3536         return 0;
3537 }
3538
3539 static void free_dma_bufs(SLMP_INFO *info)
3540 {
3541         info->buffer_list = NULL;
3542         info->rx_buf_list = NULL;
3543         info->tx_buf_list = NULL;
3544 }
3545
3546 /* allocate buffer large enough to hold max_frame_size.
3547  * This buffer is used to pass an assembled frame to the line discipline.
3548  */
3549 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3550 {
3551         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3552         if (info->tmp_rx_buf == NULL)
3553                 return -ENOMEM;
3554         return 0;
3555 }
3556
3557 static void free_tmp_rx_buf(SLMP_INFO *info)
3558 {
3559         kfree(info->tmp_rx_buf);
3560         info->tmp_rx_buf = NULL;
3561 }
3562
3563 static int claim_resources(SLMP_INFO *info)
3564 {
3565         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3566                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3567                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3568                 info->init_error = DiagStatus_AddressConflict;
3569                 goto errout;
3570         }
3571         else
3572                 info->shared_mem_requested = true;
3573
3574         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3575                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3576                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3577                 info->init_error = DiagStatus_AddressConflict;
3578                 goto errout;
3579         }
3580         else
3581                 info->lcr_mem_requested = true;
3582
3583         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3584                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3585                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3586                 info->init_error = DiagStatus_AddressConflict;
3587                 goto errout;
3588         }
3589         else
3590                 info->sca_base_requested = true;
3591
3592         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3593                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3594                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3595                 info->init_error = DiagStatus_AddressConflict;
3596                 goto errout;
3597         }
3598         else
3599                 info->sca_statctrl_requested = true;
3600
3601         info->memory_base = ioremap_nocache(info->phys_memory_base,
3602                                                                 SCA_MEM_SIZE);
3603         if (!info->memory_base) {
3604                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3605                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3606                 info->init_error = DiagStatus_CantAssignPciResources;
3607                 goto errout;
3608         }
3609
3610         info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3611         if (!info->lcr_base) {
3612                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3613                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3614                 info->init_error = DiagStatus_CantAssignPciResources;
3615                 goto errout;
3616         }
3617         info->lcr_base += info->lcr_offset;
3618
3619         info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3620         if (!info->sca_base) {
3621                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3622                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3623                 info->init_error = DiagStatus_CantAssignPciResources;
3624                 goto errout;
3625         }
3626         info->sca_base += info->sca_offset;
3627
3628         info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3629                                                                 PAGE_SIZE);
3630         if (!info->statctrl_base) {
3631                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3632                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3633                 info->init_error = DiagStatus_CantAssignPciResources;
3634                 goto errout;
3635         }
3636         info->statctrl_base += info->statctrl_offset;
3637
3638         if ( !memory_test(info) ) {
3639                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3640                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3641                 info->init_error = DiagStatus_MemoryError;
3642                 goto errout;
3643         }
3644
3645         return 0;
3646
3647 errout:
3648         release_resources( info );
3649         return -ENODEV;
3650 }
3651
3652 static void release_resources(SLMP_INFO *info)
3653 {
3654         if ( debug_level >= DEBUG_LEVEL_INFO )
3655                 printk( "%s(%d):%s release_resources() entry\n",
3656                         __FILE__,__LINE__,info->device_name );
3657
3658         if ( info->irq_requested ) {
3659                 free_irq(info->irq_level, info);
3660                 info->irq_requested = false;
3661         }
3662
3663         if ( info->shared_mem_requested ) {
3664                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3665                 info->shared_mem_requested = false;
3666         }
3667         if ( info->lcr_mem_requested ) {
3668                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3669                 info->lcr_mem_requested = false;
3670         }
3671         if ( info->sca_base_requested ) {
3672                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3673                 info->sca_base_requested = false;
3674         }
3675         if ( info->sca_statctrl_requested ) {
3676                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3677                 info->sca_statctrl_requested = false;
3678         }
3679
3680         if (info->memory_base){
3681                 iounmap(info->memory_base);
3682                 info->memory_base = NULL;
3683         }
3684
3685         if (info->sca_base) {
3686                 iounmap(info->sca_base - info->sca_offset);
3687                 info->sca_base=NULL;
3688         }
3689
3690         if (info->statctrl_base) {
3691                 iounmap(info->statctrl_base - info->statctrl_offset);
3692                 info->statctrl_base=NULL;
3693         }
3694
3695         if (info->lcr_base){
3696                 iounmap(info->lcr_base - info->lcr_offset);
3697                 info->lcr_base = NULL;
3698         }
3699
3700         if ( debug_level >= DEBUG_LEVEL_INFO )
3701                 printk( "%s(%d):%s release_resources() exit\n",
3702                         __FILE__,__LINE__,info->device_name );
3703 }
3704
3705 /* Add the specified device instance data structure to the
3706  * global linked list of devices and increment the device count.
3707  */
3708 static void add_device(SLMP_INFO *info)
3709 {
3710         info->next_device = NULL;
3711         info->line = synclinkmp_device_count;
3712         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3713
3714         if (info->line < MAX_DEVICES) {
3715                 if (maxframe[info->line])
3716                         info->max_frame_size = maxframe[info->line];
3717         }
3718
3719         synclinkmp_device_count++;
3720
3721         if ( !synclinkmp_device_list )
3722                 synclinkmp_device_list = info;
3723         else {
3724                 SLMP_INFO *current_dev = synclinkmp_device_list;
3725                 while( current_dev->next_device )
3726                         current_dev = current_dev->next_device;
3727                 current_dev->next_device = info;
3728         }
3729
3730         if ( info->max_frame_size < 4096 )
3731                 info->max_frame_size = 4096;
3732         else if ( info->max_frame_size > 65535 )
3733                 info->max_frame_size = 65535;
3734
3735         printk( "SyncLink MultiPort %s: "
3736                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3737                 info->device_name,
3738                 info->phys_sca_base,
3739                 info->phys_memory_base,
3740                 info->phys_statctrl_base,
3741                 info->phys_lcr_base,
3742                 info->irq_level,
3743                 info->max_frame_size );
3744
3745 #if SYNCLINK_GENERIC_HDLC
3746         hdlcdev_init(info);
3747 #endif
3748 }
3749
3750 static const struct tty_port_operations port_ops = {
3751         .carrier_raised = carrier_raised,
3752         .dtr_rts = dtr_rts,
3753 };
3754
3755 /* Allocate and initialize a device instance structure
3756  *
3757  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3758  */
3759 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3760 {
3761         SLMP_INFO *info;
3762
3763         info = kzalloc(sizeof(SLMP_INFO),
3764                  GFP_KERNEL);
3765
3766         if (!info) {
3767                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3768                         __FILE__,__LINE__, adapter_num, port_num);
3769         } else {
3770                 tty_port_init(&info->port);
3771                 info->port.ops = &port_ops;
3772                 info->magic = MGSL_MAGIC;
3773                 INIT_WORK(&info->task, bh_handler);
3774                 info->max_frame_size = 4096;
3775                 info->port.close_delay = 5*HZ/10;
3776                 info->port.closing_wait = 30*HZ;
3777                 init_waitqueue_head(&info->status_event_wait_q);
3778                 init_waitqueue_head(&info->event_wait_q);
3779                 spin_lock_init(&info->netlock);
3780                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3781                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3782                 info->adapter_num = adapter_num;
3783                 info->port_num = port_num;
3784
3785                 /* Copy configuration info to device instance data */
3786                 info->irq_level = pdev->irq;
3787                 info->phys_lcr_base = pci_resource_start(pdev,0);
3788                 info->phys_sca_base = pci_resource_start(pdev,2);
3789                 info->phys_memory_base = pci_resource_start(pdev,3);
3790                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3791
3792                 /* Because veremap only works on page boundaries we must map
3793                  * a larger area than is actually implemented for the LCR
3794                  * memory range. We map a full page starting at the page boundary.
3795                  */
3796                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3797                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3798
3799                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3800                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3801
3802                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3803                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3804
3805                 info->bus_type = MGSL_BUS_TYPE_PCI;
3806                 info->irq_flags = IRQF_SHARED;
3807
3808                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3809                 setup_timer(&info->status_timer, status_timeout,
3810                                 (unsigned long)info);
3811
3812                 /* Store the PCI9050 misc control register value because a flaw
3813                  * in the PCI9050 prevents LCR registers from being read if
3814                  * BIOS assigns an LCR base address with bit 7 set.
3815                  *
3816                  * Only the misc control register is accessed for which only
3817                  * write access is needed, so set an initial value and change
3818                  * bits to the device instance data as we write the value
3819                  * to the actual misc control register.
3820                  */
3821                 info->misc_ctrl_value = 0x087e4546;
3822
3823                 /* initial port state is unknown - if startup errors
3824                  * occur, init_error will be set to indicate the
3825                  * problem. Once the port is fully initialized,
3826                  * this value will be set to 0 to indicate the
3827                  * port is available.
3828                  */
3829                 info->init_error = -1;
3830         }
3831
3832         return info;
3833 }
3834
3835 static void device_init(int adapter_num, struct pci_dev *pdev)
3836 {
3837         SLMP_INFO *port_array[SCA_MAX_PORTS];
3838         int port;
3839
3840         /* allocate device instances for up to SCA_MAX_PORTS devices */
3841         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3842                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3843                 if( port_array[port] == NULL ) {
3844                         for ( --port; port >= 0; --port )
3845                                 kfree(port_array[port]);
3846                         return;
3847                 }
3848         }
3849
3850         /* give copy of port_array to all ports and add to device list  */
3851         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3852                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3853                 add_device( port_array[port] );
3854                 spin_lock_init(&port_array[port]->lock);
3855         }
3856
3857         /* Allocate and claim adapter resources */
3858         if ( !claim_resources(port_array[0]) ) {
3859
3860                 alloc_dma_bufs(port_array[0]);
3861
3862                 /* copy resource information from first port to others */
3863                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3864                         port_array[port]->lock  = port_array[0]->lock;
3865                         port_array[port]->irq_level     = port_array[0]->irq_level;
3866                         port_array[port]->memory_base   = port_array[0]->memory_base;
3867                         port_array[port]->sca_base      = port_array[0]->sca_base;
3868                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3869                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3870                         alloc_dma_bufs(port_array[port]);
3871                 }
3872
3873                 if ( request_irq(port_array[0]->irq_level,
3874                                         synclinkmp_interrupt,
3875                                         port_array[0]->irq_flags,
3876                                         port_array[0]->device_name,
3877                                         port_array[0]) < 0 ) {
3878                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3879                                 __FILE__,__LINE__,
3880                                 port_array[0]->device_name,
3881                                 port_array[0]->irq_level );
3882                 }
3883                 else {
3884                         port_array[0]->irq_requested = true;
3885                         adapter_test(port_array[0]);
3886                 }
3887         }
3888 }
3889
3890 static const struct tty_operations ops = {
3891         .open = open,
3892         .close = close,
3893         .write = write,
3894         .put_char = put_char,
3895         .flush_chars = flush_chars,
3896         .write_room = write_room,
3897         .chars_in_buffer = chars_in_buffer,
3898         .flush_buffer = flush_buffer,
3899         .ioctl = ioctl,
3900         .throttle = throttle,
3901         .unthrottle = unthrottle,
3902         .send_xchar = send_xchar,
3903         .break_ctl = set_break,
3904         .wait_until_sent = wait_until_sent,
3905         .set_termios = set_termios,
3906         .stop = tx_hold,
3907         .start = tx_release,
3908         .hangup = hangup,
3909         .tiocmget = tiocmget,
3910         .tiocmset = tiocmset,
3911         .proc_fops = &synclinkmp_proc_fops,
3912 };
3913
3914
3915 static void synclinkmp_cleanup(void)
3916 {
3917         int rc;
3918         SLMP_INFO *info;
3919         SLMP_INFO *tmp;
3920
3921         printk("Unloading %s %s\n", driver_name, driver_version);
3922
3923         if (serial_driver) {
3924                 if ((rc = tty_unregister_driver(serial_driver)))
3925                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3926                                __FILE__,__LINE__,rc);
3927                 put_tty_driver(serial_driver);
3928         }
3929
3930         /* reset devices */
3931         info = synclinkmp_device_list;
3932         while(info) {
3933                 reset_port(info);
3934                 info = info->next_device;
3935         }
3936
3937         /* release devices */
3938         info = synclinkmp_device_list;
3939         while(info) {
3940 #if SYNCLINK_GENERIC_HDLC
3941                 hdlcdev_exit(info);
3942 #endif
3943                 free_dma_bufs(info);
3944                 free_tmp_rx_buf(info);
3945                 if ( info->port_num == 0 ) {
3946                         if (info->sca_base)
3947                                 write_reg(info, LPR, 1); /* set low power mode */
3948                         release_resources(info);
3949                 }
3950                 tmp = info;
3951                 info = info->next_device;
3952                 kfree(tmp);
3953         }
3954
3955         pci_unregister_driver(&synclinkmp_pci_driver);
3956 }
3957
3958 /* Driver initialization entry point.
3959  */
3960
3961 static int __init synclinkmp_init(void)
3962 {
3963         int rc;
3964
3965         if (break_on_load) {
3966                 synclinkmp_get_text_ptr();
3967                 BREAKPOINT();
3968         }
3969
3970         printk("%s %s\n", driver_name, driver_version);
3971
3972         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3973                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3974                 return rc;
3975         }
3976
3977         serial_driver = alloc_tty_driver(128);
3978         if (!serial_driver) {
3979                 rc = -ENOMEM;
3980                 goto error;
3981         }
3982
3983         /* Initialize the tty_driver structure */
3984
3985         serial_driver->owner = THIS_MODULE;
3986         serial_driver->driver_name = "synclinkmp";
3987         serial_driver->name = "ttySLM";
3988         serial_driver->major = ttymajor;
3989         serial_driver->minor_start = 64;
3990         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3991         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3992         serial_driver->init_termios = tty_std_termios;
3993         serial_driver->init_termios.c_cflag =
3994                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3995         serial_driver->init_termios.c_ispeed = 9600;
3996         serial_driver->init_termios.c_ospeed = 9600;
3997         serial_driver->flags = TTY_DRIVER_REAL_RAW;
3998         tty_set_operations(serial_driver, &ops);
3999         if ((rc = tty_register_driver(serial_driver)) < 0) {
4000                 printk("%s(%d):Couldn't register serial driver\n",
4001                         __FILE__,__LINE__);
4002                 put_tty_driver(serial_driver);
4003                 serial_driver = NULL;
4004                 goto error;
4005         }
4006
4007         printk("%s %s, tty major#%d\n",
4008                 driver_name, driver_version,
4009                 serial_driver->major);
4010
4011         return 0;
4012
4013 error:
4014         synclinkmp_cleanup();
4015         return rc;
4016 }
4017
4018 static void __exit synclinkmp_exit(void)
4019 {
4020         synclinkmp_cleanup();
4021 }
4022
4023 module_init(synclinkmp_init);
4024 module_exit(synclinkmp_exit);
4025
4026 /* Set the port for internal loopback mode.
4027  * The TxCLK and RxCLK signals are generated from the BRG and
4028  * the TxD is looped back to the RxD internally.
4029  */
4030 static void enable_loopback(SLMP_INFO *info, int enable)
4031 {
4032         if (enable) {
4033                 /* MD2 (Mode Register 2)
4034                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4035                  */
4036                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4037
4038                 /* degate external TxC clock source */
4039                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4040                 write_control_reg(info);
4041
4042                 /* RXS/TXS (Rx/Tx clock source)
4043                  * 07      Reserved, must be 0
4044                  * 06..04  Clock Source, 100=BRG
4045                  * 03..00  Clock Divisor, 0000=1
4046                  */
4047                 write_reg(info, RXS, 0x40);
4048                 write_reg(info, TXS, 0x40);
4049
4050         } else {
4051                 /* MD2 (Mode Register 2)
4052                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4053                  */
4054                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4055
4056                 /* RXS/TXS (Rx/Tx clock source)
4057                  * 07      Reserved, must be 0
4058                  * 06..04  Clock Source, 000=RxC/TxC Pin
4059                  * 03..00  Clock Divisor, 0000=1
4060                  */
4061                 write_reg(info, RXS, 0x00);
4062                 write_reg(info, TXS, 0x00);
4063         }
4064
4065         /* set LinkSpeed if available, otherwise default to 2Mbps */
4066         if (info->params.clock_speed)
4067                 set_rate(info, info->params.clock_speed);
4068         else
4069                 set_rate(info, 3686400);
4070 }
4071
4072 /* Set the baud rate register to the desired speed
4073  *
4074  *      data_rate       data rate of clock in bits per second
4075  *                      A data rate of 0 disables the AUX clock.
4076  */
4077 static void set_rate( SLMP_INFO *info, u32 data_rate )
4078 {
4079         u32 TMCValue;
4080         unsigned char BRValue;
4081         u32 Divisor=0;
4082
4083         /* fBRG = fCLK/(TMC * 2^BR)
4084          */
4085         if (data_rate != 0) {
4086                 Divisor = 14745600/data_rate;
4087                 if (!Divisor)
4088                         Divisor = 1;
4089
4090                 TMCValue = Divisor;
4091
4092                 BRValue = 0;
4093                 if (TMCValue != 1 && TMCValue != 2) {
4094                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4095                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4096                          * 50/50 duty cycle.
4097                          */
4098                         BRValue = 1;
4099                         TMCValue >>= 1;
4100                 }
4101
4102                 /* while TMCValue is too big for TMC register, divide
4103                  * by 2 and increment BR exponent.
4104                  */
4105                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4106                         TMCValue >>= 1;
4107
4108                 write_reg(info, TXS,
4109                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4110                 write_reg(info, RXS,
4111                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4112                 write_reg(info, TMC, (unsigned char)TMCValue);
4113         }
4114         else {
4115                 write_reg(info, TXS,0);
4116                 write_reg(info, RXS,0);
4117                 write_reg(info, TMC, 0);
4118         }
4119 }
4120
4121 /* Disable receiver
4122  */
4123 static void rx_stop(SLMP_INFO *info)
4124 {
4125         if (debug_level >= DEBUG_LEVEL_ISR)
4126                 printk("%s(%d):%s rx_stop()\n",
4127                          __FILE__,__LINE__, info->device_name );
4128
4129         write_reg(info, CMD, RXRESET);
4130
4131         info->ie0_value &= ~RXRDYE;
4132         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4133
4134         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4135         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4136         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4137
4138         info->rx_enabled = false;
4139         info->rx_overflow = false;
4140 }
4141
4142 /* enable the receiver
4143  */
4144 static void rx_start(SLMP_INFO *info)
4145 {
4146         int i;
4147
4148         if (debug_level >= DEBUG_LEVEL_ISR)
4149                 printk("%s(%d):%s rx_start()\n",
4150                          __FILE__,__LINE__, info->device_name );
4151
4152         write_reg(info, CMD, RXRESET);
4153
4154         if ( info->params.mode == MGSL_MODE_HDLC ) {
4155                 /* HDLC, disabe IRQ on rxdata */
4156                 info->ie0_value &= ~RXRDYE;
4157                 write_reg(info, IE0, info->ie0_value);
4158
4159                 /* Reset all Rx DMA buffers and program rx dma */
4160                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4161                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4162
4163                 for (i = 0; i < info->rx_buf_count; i++) {
4164                         info->rx_buf_list[i].status = 0xff;
4165
4166                         // throttle to 4 shared memory writes at a time to prevent
4167                         // hogging local bus (keep latency time for DMA requests low).
4168                         if (!(i % 4))
4169                                 read_status_reg(info);
4170                 }
4171                 info->current_rx_buf = 0;
4172
4173                 /* set current/1st descriptor address */
4174                 write_reg16(info, RXDMA + CDA,
4175                         info->rx_buf_list_ex[0].phys_entry);
4176
4177                 /* set new last rx descriptor address */
4178                 write_reg16(info, RXDMA + EDA,
4179                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4180
4181                 /* set buffer length (shared by all rx dma data buffers) */
4182                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4183
4184                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4185                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4186         } else {
4187                 /* async, enable IRQ on rxdata */
4188                 info->ie0_value |= RXRDYE;
4189                 write_reg(info, IE0, info->ie0_value);
4190         }
4191
4192         write_reg(info, CMD, RXENABLE);
4193
4194         info->rx_overflow = false;
4195         info->rx_enabled = true;
4196 }
4197
4198 /* Enable the transmitter and send a transmit frame if
4199  * one is loaded in the DMA buffers.
4200  */
4201 static void tx_start(SLMP_INFO *info)
4202 {
4203         if (debug_level >= DEBUG_LEVEL_ISR)
4204                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4205                          __FILE__,__LINE__, info->device_name,info->tx_count );
4206
4207         if (!info->tx_enabled ) {
4208                 write_reg(info, CMD, TXRESET);
4209                 write_reg(info, CMD, TXENABLE);
4210                 info->tx_enabled = true;
4211         }
4212
4213         if ( info->tx_count ) {
4214
4215                 /* If auto RTS enabled and RTS is inactive, then assert */
4216                 /* RTS and set a flag indicating that the driver should */
4217                 /* negate RTS when the transmission completes. */
4218
4219                 info->drop_rts_on_tx_done = false;
4220
4221                 if (info->params.mode != MGSL_MODE_ASYNC) {
4222
4223                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4224                                 get_signals( info );
4225                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4226                                         info->serial_signals |= SerialSignal_RTS;
4227                                         set_signals( info );
4228                                         info->drop_rts_on_tx_done = true;
4229                                 }
4230                         }
4231
4232                         write_reg16(info, TRC0,
4233                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4234
4235                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4236                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4237
4238                         /* set TX CDA (current descriptor address) */
4239                         write_reg16(info, TXDMA + CDA,
4240                                 info->tx_buf_list_ex[0].phys_entry);
4241
4242                         /* set TX EDA (last descriptor address) */
4243                         write_reg16(info, TXDMA + EDA,
4244                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4245
4246                         /* enable underrun IRQ */
4247                         info->ie1_value &= ~IDLE;
4248                         info->ie1_value |= UDRN;
4249                         write_reg(info, IE1, info->ie1_value);
4250                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4251
4252                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4253                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4254
4255                         mod_timer(&info->tx_timer, jiffies +
4256                                         msecs_to_jiffies(5000));
4257                 }
4258                 else {
4259                         tx_load_fifo(info);
4260                         /* async, enable IRQ on txdata */
4261                         info->ie0_value |= TXRDYE;
4262                         write_reg(info, IE0, info->ie0_value);
4263                 }
4264
4265                 info->tx_active = true;
4266         }
4267 }
4268
4269 /* stop the transmitter and DMA
4270  */
4271 static void tx_stop( SLMP_INFO *info )
4272 {
4273         if (debug_level >= DEBUG_LEVEL_ISR)
4274                 printk("%s(%d):%s tx_stop()\n",
4275                          __FILE__,__LINE__, info->device_name );
4276
4277         del_timer(&info->tx_timer);
4278
4279         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4280         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4281
4282         write_reg(info, CMD, TXRESET);
4283
4284         info->ie1_value &= ~(UDRN + IDLE);
4285         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4286         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4287
4288         info->ie0_value &= ~TXRDYE;
4289         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4290
4291         info->tx_enabled = false;
4292         info->tx_active = false;
4293 }
4294
4295 /* Fill the transmit FIFO until the FIFO is full or
4296  * there is no more data to load.
4297  */
4298 static void tx_load_fifo(SLMP_INFO *info)
4299 {
4300         u8 TwoBytes[2];
4301
4302         /* do nothing is now tx data available and no XON/XOFF pending */
4303
4304         if ( !info->tx_count && !info->x_char )
4305                 return;
4306
4307         /* load the Transmit FIFO until FIFOs full or all data sent */
4308
4309         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4310
4311                 /* there is more space in the transmit FIFO and */
4312                 /* there is more data in transmit buffer */
4313
4314                 if ( (info->tx_count > 1) && !info->x_char ) {
4315                         /* write 16-bits */
4316                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4317                         if (info->tx_get >= info->max_frame_size)
4318                                 info->tx_get -= info->max_frame_size;
4319                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4320                         if (info->tx_get >= info->max_frame_size)
4321                                 info->tx_get -= info->max_frame_size;
4322
4323                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4324
4325                         info->tx_count -= 2;
4326                         info->icount.tx += 2;
4327                 } else {
4328                         /* only 1 byte left to transmit or 1 FIFO slot left */
4329
4330                         if (info->x_char) {
4331                                 /* transmit pending high priority char */
4332                                 write_reg(info, TRB, info->x_char);
4333                                 info->x_char = 0;
4334                         } else {
4335                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4336                                 if (info->tx_get >= info->max_frame_size)
4337                                         info->tx_get -= info->max_frame_size;
4338                                 info->tx_count--;
4339                         }
4340                         info->icount.tx++;
4341                 }
4342         }
4343 }
4344
4345 /* Reset a port to a known state
4346  */
4347 static void reset_port(SLMP_INFO *info)
4348 {
4349         if (info->sca_base) {
4350
4351                 tx_stop(info);
4352                 rx_stop(info);
4353
4354                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4355                 set_signals(info);
4356
4357                 /* disable all port interrupts */
4358                 info->ie0_value = 0;
4359                 info->ie1_value = 0;
4360                 info->ie2_value = 0;
4361                 write_reg(info, IE0, info->ie0_value);
4362                 write_reg(info, IE1, info->ie1_value);
4363                 write_reg(info, IE2, info->ie2_value);
4364
4365                 write_reg(info, CMD, CHRESET);
4366         }
4367 }
4368
4369 /* Reset all the ports to a known state.
4370  */
4371 static void reset_adapter(SLMP_INFO *info)
4372 {
4373         int i;
4374
4375         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4376                 if (info->port_array[i])
4377                         reset_port(info->port_array[i]);
4378         }
4379 }
4380
4381 /* Program port for asynchronous communications.
4382  */
4383 static void async_mode(SLMP_INFO *info)
4384 {
4385
4386         unsigned char RegValue;
4387
4388         tx_stop(info);
4389         rx_stop(info);
4390
4391         /* MD0, Mode Register 0
4392          *
4393          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4394          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4395          * 03      Reserved, must be 0
4396          * 02      CRCCC, CRC Calculation, 0=disabled
4397          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4398          *
4399          * 0000 0000
4400          */
4401         RegValue = 0x00;
4402         if (info->params.stop_bits != 1)
4403                 RegValue |= BIT1;
4404         write_reg(info, MD0, RegValue);
4405
4406         /* MD1, Mode Register 1
4407          *
4408          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4409          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4410          * 03..02  RXCHR<1..0>, rx char size
4411          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4412          *
4413          * 0100 0000
4414          */
4415         RegValue = 0x40;
4416         switch (info->params.data_bits) {
4417         case 7: RegValue |= BIT4 + BIT2; break;
4418         case 6: RegValue |= BIT5 + BIT3; break;
4419         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4420         }
4421         if (info->params.parity != ASYNC_PARITY_NONE) {
4422                 RegValue |= BIT1;
4423                 if (info->params.parity == ASYNC_PARITY_ODD)
4424                         RegValue |= BIT0;
4425         }
4426         write_reg(info, MD1, RegValue);
4427
4428         /* MD2, Mode Register 2
4429          *
4430          * 07..02  Reserved, must be 0
4431          * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4432          *
4433          * 0000 0000
4434          */
4435         RegValue = 0x00;
4436         if (info->params.loopback)
4437                 RegValue |= (BIT1 + BIT0);
4438         write_reg(info, MD2, RegValue);
4439
4440         /* RXS, Receive clock source
4441          *
4442          * 07      Reserved, must be 0
4443          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4444          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4445          */
4446         RegValue=BIT6;
4447         write_reg(info, RXS, RegValue);
4448
4449         /* TXS, Transmit clock source
4450          *
4451          * 07      Reserved, must be 0
4452          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4453          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4454          */
4455         RegValue=BIT6;
4456         write_reg(info, TXS, RegValue);
4457
4458         /* Control Register
4459          *
4460          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4461          */
4462         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4463         write_control_reg(info);
4464
4465         tx_set_idle(info);
4466
4467         /* RRC Receive Ready Control 0
4468          *
4469          * 07..05  Reserved, must be 0
4470          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4471          */
4472         write_reg(info, RRC, 0x00);
4473
4474         /* TRC0 Transmit Ready Control 0
4475          *
4476          * 07..05  Reserved, must be 0
4477          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4478          */
4479         write_reg(info, TRC0, 0x10);
4480
4481         /* TRC1 Transmit Ready Control 1
4482          *
4483          * 07..05  Reserved, must be 0
4484          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4485          */
4486         write_reg(info, TRC1, 0x1e);
4487
4488         /* CTL, MSCI control register
4489          *
4490          * 07..06  Reserved, set to 0
4491          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4492          * 04      IDLC, idle control, 0=mark 1=idle register
4493          * 03      BRK, break, 0=off 1 =on (async)
4494          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4495          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4496          * 00      RTS, RTS output control, 0=active 1=inactive
4497          *
4498          * 0001 0001
4499          */
4500         RegValue = 0x10;
4501         if (!(info->serial_signals & SerialSignal_RTS))
4502                 RegValue |= 0x01;
4503         write_reg(info, CTL, RegValue);
4504
4505         /* enable status interrupts */
4506         info->ie0_value |= TXINTE + RXINTE;
4507         write_reg(info, IE0, info->ie0_value);
4508
4509         /* enable break detect interrupt */
4510         info->ie1_value = BRKD;
4511         write_reg(info, IE1, info->ie1_value);
4512
4513         /* enable rx overrun interrupt */
4514         info->ie2_value = OVRN;
4515         write_reg(info, IE2, info->ie2_value);
4516
4517         set_rate( info, info->params.data_rate * 16 );
4518 }
4519
4520 /* Program the SCA for HDLC communications.
4521  */
4522 static void hdlc_mode(SLMP_INFO *info)
4523 {
4524         unsigned char RegValue;
4525         u32 DpllDivisor;
4526
4527         // Can't use DPLL because SCA outputs recovered clock on RxC when
4528         // DPLL mode selected. This causes output contention with RxC receiver.
4529         // Use of DPLL would require external hardware to disable RxC receiver
4530         // when DPLL mode selected.
4531         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4532
4533         /* disable DMA interrupts */
4534         write_reg(info, TXDMA + DIR, 0);
4535         write_reg(info, RXDMA + DIR, 0);
4536
4537         /* MD0, Mode Register 0
4538          *
4539          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4540          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4541          * 03      Reserved, must be 0
4542          * 02      CRCCC, CRC Calculation, 1=enabled
4543          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4544          * 00      CRC0, CRC initial value, 1 = all 1s
4545          *
4546          * 1000 0001
4547          */
4548         RegValue = 0x81;
4549         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4550                 RegValue |= BIT4;
4551         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4552                 RegValue |= BIT4;
4553         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4554                 RegValue |= BIT2 + BIT1;
4555         write_reg(info, MD0, RegValue);
4556
4557         /* MD1, Mode Register 1
4558          *
4559          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4560          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4561          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4562          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4563          *
4564          * 0000 0000
4565          */
4566         RegValue = 0x00;
4567         write_reg(info, MD1, RegValue);
4568
4569         /* MD2, Mode Register 2
4570          *
4571          * 07      NRZFM, 0=NRZ, 1=FM
4572          * 06..05  CODE<1..0> Encoding, 00=NRZ
4573          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4574          * 02      Reserved, must be 0
4575          * 01..00  CNCT<1..0> Channel connection, 0=normal
4576          *
4577          * 0000 0000
4578          */
4579         RegValue = 0x00;
4580         switch(info->params.encoding) {
4581         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4582         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4583         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4584         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4585 #if 0
4586         case HDLC_ENCODING_NRZB:                                        /* not supported */
4587         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4588         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4589 #endif
4590         }
4591         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4592                 DpllDivisor = 16;
4593                 RegValue |= BIT3;
4594         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4595                 DpllDivisor = 8;
4596         } else {
4597                 DpllDivisor = 32;
4598                 RegValue |= BIT4;
4599         }
4600         write_reg(info, MD2, RegValue);
4601
4602
4603         /* RXS, Receive clock source
4604          *
4605          * 07      Reserved, must be 0
4606          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4607          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4608          */
4609         RegValue=0;
4610         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4611                 RegValue |= BIT6;
4612         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4613                 RegValue |= BIT6 + BIT5;
4614         write_reg(info, RXS, RegValue);
4615
4616         /* TXS, Transmit clock source
4617          *
4618          * 07      Reserved, must be 0
4619          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4620          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4621          */
4622         RegValue=0;
4623         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4624                 RegValue |= BIT6;
4625         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4626                 RegValue |= BIT6 + BIT5;
4627         write_reg(info, TXS, RegValue);
4628
4629         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4630                 set_rate(info, info->params.clock_speed * DpllDivisor);
4631         else
4632                 set_rate(info, info->params.clock_speed);
4633
4634         /* GPDATA (General Purpose I/O Data Register)
4635          *
4636          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4637          */
4638         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4639                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4640         else
4641                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4642         write_control_reg(info);
4643
4644         /* RRC Receive Ready Control 0
4645          *
4646          * 07..05  Reserved, must be 0
4647          * 04..00  RRC<4..0> Rx FIFO trigger active
4648          */
4649         write_reg(info, RRC, rx_active_fifo_level);
4650
4651         /* TRC0 Transmit Ready Control 0
4652          *
4653          * 07..05  Reserved, must be 0
4654          * 04..00  TRC<4..0> Tx FIFO trigger active
4655          */
4656         write_reg(info, TRC0, tx_active_fifo_level);
4657
4658         /* TRC1 Transmit Ready Control 1
4659          *
4660          * 07..05  Reserved, must be 0
4661          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4662          */
4663         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4664
4665         /* DMR, DMA Mode Register
4666          *
4667          * 07..05  Reserved, must be 0
4668          * 04      TMOD, Transfer Mode: 1=chained-block
4669          * 03      Reserved, must be 0
4670          * 02      NF, Number of Frames: 1=multi-frame
4671          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4672          * 00      Reserved, must be 0
4673          *
4674          * 0001 0100
4675          */
4676         write_reg(info, TXDMA + DMR, 0x14);
4677         write_reg(info, RXDMA + DMR, 0x14);
4678
4679         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4680         write_reg(info, RXDMA + CPB,
4681                 (unsigned char)(info->buffer_list_phys >> 16));
4682
4683         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4684         write_reg(info, TXDMA + CPB,
4685                 (unsigned char)(info->buffer_list_phys >> 16));
4686
4687         /* enable status interrupts. other code enables/disables
4688          * the individual sources for these two interrupt classes.
4689          */
4690         info->ie0_value |= TXINTE + RXINTE;
4691         write_reg(info, IE0, info->ie0_value);
4692
4693         /* CTL, MSCI control register
4694          *
4695          * 07..06  Reserved, set to 0
4696          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4697          * 04      IDLC, idle control, 0=mark 1=idle register
4698          * 03      BRK, break, 0=off 1 =on (async)
4699          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4700          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4701          * 00      RTS, RTS output control, 0=active 1=inactive
4702          *
4703          * 0001 0001
4704          */
4705         RegValue = 0x10;
4706         if (!(info->serial_signals & SerialSignal_RTS))
4707                 RegValue |= 0x01;
4708         write_reg(info, CTL, RegValue);
4709
4710         /* preamble not supported ! */
4711
4712         tx_set_idle(info);
4713         tx_stop(info);
4714         rx_stop(info);
4715
4716         set_rate(info, info->params.clock_speed);
4717
4718         if (info->params.loopback)
4719                 enable_loopback(info,1);
4720 }
4721
4722 /* Set the transmit HDLC idle mode
4723  */
4724 static void tx_set_idle(SLMP_INFO *info)
4725 {
4726         unsigned char RegValue = 0xff;
4727
4728         /* Map API idle mode to SCA register bits */
4729         switch(info->idle_mode) {
4730         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4731         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4732         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4733         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4734         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4735         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4736         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4737         }
4738
4739         write_reg(info, IDL, RegValue);
4740 }
4741
4742 /* Query the adapter for the state of the V24 status (input) signals.
4743  */
4744 static void get_signals(SLMP_INFO *info)
4745 {
4746         u16 status = read_reg(info, SR3);
4747         u16 gpstatus = read_status_reg(info);
4748         u16 testbit;
4749
4750         /* clear all serial signals except DTR and RTS */
4751         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4752
4753         /* set serial signal bits to reflect MISR */
4754
4755         if (!(status & BIT3))
4756                 info->serial_signals |= SerialSignal_CTS;
4757
4758         if ( !(status & BIT2))
4759                 info->serial_signals |= SerialSignal_DCD;
4760
4761         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4762         if (!(gpstatus & testbit))
4763                 info->serial_signals |= SerialSignal_RI;
4764
4765         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4766         if (!(gpstatus & testbit))
4767                 info->serial_signals |= SerialSignal_DSR;
4768 }
4769
4770 /* Set the state of DTR and RTS based on contents of
4771  * serial_signals member of device context.
4772  */
4773 static void set_signals(SLMP_INFO *info)
4774 {
4775         unsigned char RegValue;
4776         u16 EnableBit;
4777
4778         RegValue = read_reg(info, CTL);
4779         if (info->serial_signals & SerialSignal_RTS)
4780                 RegValue &= ~BIT0;
4781         else
4782                 RegValue |= BIT0;
4783         write_reg(info, CTL, RegValue);
4784
4785         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4786         EnableBit = BIT1 << (info->port_num*2);
4787         if (info->serial_signals & SerialSignal_DTR)
4788                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4789         else
4790                 info->port_array[0]->ctrlreg_value |= EnableBit;
4791         write_control_reg(info);
4792 }
4793
4794 /*******************/
4795 /* DMA Buffer Code */
4796 /*******************/
4797
4798 /* Set the count for all receive buffers to SCABUFSIZE
4799  * and set the current buffer to the first buffer. This effectively
4800  * makes all buffers free and discards any data in buffers.
4801  */
4802 static void rx_reset_buffers(SLMP_INFO *info)
4803 {
4804         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4805 }
4806
4807 /* Free the buffers used by a received frame
4808  *
4809  * info   pointer to device instance data
4810  * first  index of 1st receive buffer of frame
4811  * last   index of last receive buffer of frame
4812  */
4813 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4814 {
4815         bool done = false;
4816
4817         while(!done) {
4818                 /* reset current buffer for reuse */
4819                 info->rx_buf_list[first].status = 0xff;
4820
4821                 if (first == last) {
4822                         done = true;
4823                         /* set new last rx descriptor address */
4824                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4825                 }
4826
4827                 first++;
4828                 if (first == info->rx_buf_count)
4829                         first = 0;
4830         }
4831
4832         /* set current buffer to next buffer after last buffer of frame */
4833         info->current_rx_buf = first;
4834 }
4835
4836 /* Return a received frame from the receive DMA buffers.
4837  * Only frames received without errors are returned.
4838  *
4839  * Return Value:        true if frame returned, otherwise false
4840  */
4841 static bool rx_get_frame(SLMP_INFO *info)
4842 {
4843         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4844         unsigned short status;
4845         unsigned int framesize = 0;
4846         bool ReturnCode = false;
4847         unsigned long flags;
4848         struct tty_struct *tty = info->port.tty;
4849         unsigned char addr_field = 0xff;
4850         SCADESC *desc;
4851         SCADESC_EX *desc_ex;
4852
4853 CheckAgain:
4854         /* assume no frame returned, set zero length */
4855         framesize = 0;
4856         addr_field = 0xff;
4857
4858         /*
4859          * current_rx_buf points to the 1st buffer of the next available
4860          * receive frame. To find the last buffer of the frame look for
4861          * a non-zero status field in the buffer entries. (The status
4862          * field is set by the 16C32 after completing a receive frame.
4863          */
4864         StartIndex = EndIndex = info->current_rx_buf;
4865
4866         for ( ;; ) {
4867                 desc = &info->rx_buf_list[EndIndex];
4868                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4869
4870                 if (desc->status == 0xff)
4871                         goto Cleanup;   /* current desc still in use, no frames available */
4872
4873                 if (framesize == 0 && info->params.addr_filter != 0xff)
4874                         addr_field = desc_ex->virt_addr[0];
4875
4876                 framesize += desc->length;
4877
4878                 /* Status != 0 means last buffer of frame */
4879                 if (desc->status)
4880                         break;
4881
4882                 EndIndex++;
4883                 if (EndIndex == info->rx_buf_count)
4884                         EndIndex = 0;
4885
4886                 if (EndIndex == info->current_rx_buf) {
4887                         /* all buffers have been 'used' but none mark      */
4888                         /* the end of a frame. Reset buffers and receiver. */
4889                         if ( info->rx_enabled ){
4890                                 spin_lock_irqsave(&info->lock,flags);
4891                                 rx_start(info);
4892                                 spin_unlock_irqrestore(&info->lock,flags);
4893                         }
4894                         goto Cleanup;
4895                 }
4896
4897         }
4898
4899         /* check status of receive frame */
4900
4901         /* frame status is byte stored after frame data
4902          *
4903          * 7 EOM (end of msg), 1 = last buffer of frame
4904          * 6 Short Frame, 1 = short frame
4905          * 5 Abort, 1 = frame aborted
4906          * 4 Residue, 1 = last byte is partial
4907          * 3 Overrun, 1 = overrun occurred during frame reception
4908          * 2 CRC,     1 = CRC error detected
4909          *
4910          */
4911         status = desc->status;
4912
4913         /* ignore CRC bit if not using CRC (bit is undefined) */
4914         /* Note:CRC is not save to data buffer */
4915         if (info->params.crc_type == HDLC_CRC_NONE)
4916                 status &= ~BIT2;
4917
4918         if (framesize == 0 ||
4919                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4920                 /* discard 0 byte frames, this seems to occur sometime
4921                  * when remote is idling flags.
4922                  */
4923                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4924                 goto CheckAgain;
4925         }
4926
4927         if (framesize < 2)
4928                 status |= BIT6;
4929
4930         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4931                 /* received frame has errors,
4932                  * update counts and mark frame size as 0
4933                  */
4934                 if (status & BIT6)
4935                         info->icount.rxshort++;
4936                 else if (status & BIT5)
4937                         info->icount.rxabort++;
4938                 else if (status & BIT3)
4939                         info->icount.rxover++;
4940                 else
4941                         info->icount.rxcrc++;
4942
4943                 framesize = 0;
4944 #if SYNCLINK_GENERIC_HDLC
4945                 {
4946                         info->netdev->stats.rx_errors++;
4947                         info->netdev->stats.rx_frame_errors++;
4948                 }
4949 #endif
4950         }
4951
4952         if ( debug_level >= DEBUG_LEVEL_BH )
4953                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4954                         __FILE__,__LINE__,info->device_name,status,framesize);
4955
4956         if ( debug_level >= DEBUG_LEVEL_DATA )
4957                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4958                         min_t(int, framesize,SCABUFSIZE),0);
4959
4960         if (framesize) {
4961                 if (framesize > info->max_frame_size)
4962                         info->icount.rxlong++;
4963                 else {
4964                         /* copy dma buffer(s) to contiguous intermediate buffer */
4965                         int copy_count = framesize;
4966                         int index = StartIndex;
4967                         unsigned char *ptmp = info->tmp_rx_buf;
4968                         info->tmp_rx_buf_count = framesize;
4969
4970                         info->icount.rxok++;
4971
4972                         while(copy_count) {
4973                                 int partial_count = min(copy_count,SCABUFSIZE);
4974                                 memcpy( ptmp,
4975                                         info->rx_buf_list_ex[index].virt_addr,
4976                                         partial_count );
4977                                 ptmp += partial_count;
4978                                 copy_count -= partial_count;
4979
4980                                 if ( ++index == info->rx_buf_count )
4981                                         index = 0;
4982                         }
4983
4984 #if SYNCLINK_GENERIC_HDLC
4985                         if (info->netcount)
4986                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4987                         else
4988 #endif
4989                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
4990                                                   info->flag_buf, framesize);
4991                 }
4992         }
4993         /* Free the buffers used by this frame. */
4994         rx_free_frame_buffers( info, StartIndex, EndIndex );
4995
4996         ReturnCode = true;
4997
4998 Cleanup:
4999         if ( info->rx_enabled && info->rx_overflow ) {
5000                 /* Receiver is enabled, but needs to restarted due to
5001                  * rx buffer overflow. If buffers are empty, restart receiver.
5002                  */
5003                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5004                         spin_lock_irqsave(&info->lock,flags);
5005                         rx_start(info);
5006                         spin_unlock_irqrestore(&info->lock,flags);
5007                 }
5008         }
5009
5010         return ReturnCode;
5011 }
5012
5013 /* load the transmit DMA buffer with data
5014  */
5015 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5016 {
5017         unsigned short copy_count;
5018         unsigned int i = 0;
5019         SCADESC *desc;
5020         SCADESC_EX *desc_ex;
5021
5022         if ( debug_level >= DEBUG_LEVEL_DATA )
5023                 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5024
5025         /* Copy source buffer to one or more DMA buffers, starting with
5026          * the first transmit dma buffer.
5027          */
5028         for(i=0;;)
5029         {
5030                 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5031
5032                 desc = &info->tx_buf_list[i];
5033                 desc_ex = &info->tx_buf_list_ex[i];
5034
5035                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5036
5037                 desc->length = copy_count;
5038                 desc->status = 0;
5039
5040                 buf += copy_count;
5041                 count -= copy_count;
5042
5043                 if (!count)
5044                         break;
5045
5046                 i++;
5047                 if (i >= info->tx_buf_count)
5048                         i = 0;
5049         }
5050
5051         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5052         info->last_tx_buf = ++i;
5053 }
5054
5055 static bool register_test(SLMP_INFO *info)
5056 {
5057         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5058         static unsigned int count = ARRAY_SIZE(testval);
5059         unsigned int i;
5060         bool rc = true;
5061         unsigned long flags;
5062
5063         spin_lock_irqsave(&info->lock,flags);
5064         reset_port(info);
5065
5066         /* assume failure */
5067         info->init_error = DiagStatus_AddressFailure;
5068
5069         /* Write bit patterns to various registers but do it out of */
5070         /* sync, then read back and verify values. */
5071
5072         for (i = 0 ; i < count ; i++) {
5073                 write_reg(info, TMC, testval[i]);
5074                 write_reg(info, IDL, testval[(i+1)%count]);
5075                 write_reg(info, SA0, testval[(i+2)%count]);
5076                 write_reg(info, SA1, testval[(i+3)%count]);
5077
5078                 if ( (read_reg(info, TMC) != testval[i]) ||
5079                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5080                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5081                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5082                 {
5083                         rc = false;
5084                         break;
5085                 }
5086         }
5087
5088         reset_port(info);
5089         spin_unlock_irqrestore(&info->lock,flags);
5090
5091         return rc;
5092 }
5093
5094 static bool irq_test(SLMP_INFO *info)
5095 {
5096         unsigned long timeout;
5097         unsigned long flags;
5098
5099         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5100
5101         spin_lock_irqsave(&info->lock,flags);
5102         reset_port(info);
5103
5104         /* assume failure */
5105         info->init_error = DiagStatus_IrqFailure;
5106         info->irq_occurred = false;
5107
5108         /* setup timer0 on SCA0 to interrupt */
5109
5110         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5111         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5112
5113         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5114         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5115
5116
5117         /* TMCS, Timer Control/Status Register
5118          *
5119          * 07      CMF, Compare match flag (read only) 1=match
5120          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5121          * 05      Reserved, must be 0
5122          * 04      TME, Timer Enable
5123          * 03..00  Reserved, must be 0
5124          *
5125          * 0101 0000
5126          */
5127         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5128
5129         spin_unlock_irqrestore(&info->lock,flags);
5130
5131         timeout=100;
5132         while( timeout-- && !info->irq_occurred ) {
5133                 msleep_interruptible(10);
5134         }
5135
5136         spin_lock_irqsave(&info->lock,flags);
5137         reset_port(info);
5138         spin_unlock_irqrestore(&info->lock,flags);
5139
5140         return info->irq_occurred;
5141 }
5142
5143 /* initialize individual SCA device (2 ports)
5144  */
5145 static bool sca_init(SLMP_INFO *info)
5146 {
5147         /* set wait controller to single mem partition (low), no wait states */
5148         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5149         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5150         write_reg(info, WCRL, 0);       /* wait controller low range */
5151         write_reg(info, WCRM, 0);       /* wait controller mid range */
5152         write_reg(info, WCRH, 0);       /* wait controller high range */
5153
5154         /* DPCR, DMA Priority Control
5155          *
5156          * 07..05  Not used, must be 0
5157          * 04      BRC, bus release condition: 0=all transfers complete
5158          * 03      CCC, channel change condition: 0=every cycle
5159          * 02..00  PR<2..0>, priority 100=round robin
5160          *
5161          * 00000100 = 0x04
5162          */
5163         write_reg(info, DPCR, dma_priority);
5164
5165         /* DMA Master Enable, BIT7: 1=enable all channels */
5166         write_reg(info, DMER, 0x80);
5167
5168         /* enable all interrupt classes */
5169         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5170         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5171         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5172
5173         /* ITCR, interrupt control register
5174          * 07      IPC, interrupt priority, 0=MSCI->DMA
5175          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5176          * 04      VOS, Vector Output, 0=unmodified vector
5177          * 03..00  Reserved, must be 0
5178          */
5179         write_reg(info, ITCR, 0);
5180
5181         return true;
5182 }
5183
5184 /* initialize adapter hardware
5185  */
5186 static bool init_adapter(SLMP_INFO *info)
5187 {
5188         int i;
5189
5190         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5191         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5192         u32 readval;
5193
5194         info->misc_ctrl_value |= BIT30;
5195         *MiscCtrl = info->misc_ctrl_value;
5196
5197         /*
5198          * Force at least 170ns delay before clearing
5199          * reset bit. Each read from LCR takes at least
5200          * 30ns so 10 times for 300ns to be safe.
5201          */
5202         for(i=0;i<10;i++)
5203                 readval = *MiscCtrl;
5204
5205         info->misc_ctrl_value &= ~BIT30;
5206         *MiscCtrl = info->misc_ctrl_value;
5207
5208         /* init control reg (all DTRs off, all clksel=input) */
5209         info->ctrlreg_value = 0xaa;
5210         write_control_reg(info);
5211
5212         {
5213                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5214                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5215
5216                 switch(read_ahead_count)
5217                 {
5218                 case 16:
5219                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5220                         break;
5221                 case 8:
5222                         lcr1_brdr_value |= BIT5 + BIT4;
5223                         break;
5224                 case 4:
5225                         lcr1_brdr_value |= BIT5 + BIT3;
5226                         break;
5227                 case 0:
5228                         lcr1_brdr_value |= BIT5;
5229                         break;
5230                 }
5231
5232                 *LCR1BRDR = lcr1_brdr_value;
5233                 *MiscCtrl = misc_ctrl_value;
5234         }
5235
5236         sca_init(info->port_array[0]);
5237         sca_init(info->port_array[2]);
5238
5239         return true;
5240 }
5241
5242 /* Loopback an HDLC frame to test the hardware
5243  * interrupt and DMA functions.
5244  */
5245 static bool loopback_test(SLMP_INFO *info)
5246 {
5247 #define TESTFRAMESIZE 20
5248
5249         unsigned long timeout;
5250         u16 count = TESTFRAMESIZE;
5251         unsigned char buf[TESTFRAMESIZE];
5252         bool rc = false;
5253         unsigned long flags;
5254
5255         struct tty_struct *oldtty = info->port.tty;
5256         u32 speed = info->params.clock_speed;
5257
5258         info->params.clock_speed = 3686400;
5259         info->port.tty = NULL;
5260
5261         /* assume failure */
5262         info->init_error = DiagStatus_DmaFailure;
5263
5264         /* build and send transmit frame */
5265         for (count = 0; count < TESTFRAMESIZE;++count)
5266                 buf[count] = (unsigned char)count;
5267
5268         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5269
5270         /* program hardware for HDLC and enabled receiver */
5271         spin_lock_irqsave(&info->lock,flags);
5272         hdlc_mode(info);
5273         enable_loopback(info,1);
5274         rx_start(info);
5275         info->tx_count = count;
5276         tx_load_dma_buffer(info,buf,count);
5277         tx_start(info);
5278         spin_unlock_irqrestore(&info->lock,flags);
5279
5280         /* wait for receive complete */
5281         /* Set a timeout for waiting for interrupt. */
5282         for ( timeout = 100; timeout; --timeout ) {
5283                 msleep_interruptible(10);
5284
5285                 if (rx_get_frame(info)) {
5286                         rc = true;
5287                         break;
5288                 }
5289         }
5290
5291         /* verify received frame length and contents */
5292         if (rc &&
5293             ( info->tmp_rx_buf_count != count ||
5294               memcmp(buf, info->tmp_rx_buf,count))) {
5295                 rc = false;
5296         }
5297
5298         spin_lock_irqsave(&info->lock,flags);
5299         reset_adapter(info);
5300         spin_unlock_irqrestore(&info->lock,flags);
5301
5302         info->params.clock_speed = speed;
5303         info->port.tty = oldtty;
5304
5305         return rc;
5306 }
5307
5308 /* Perform diagnostics on hardware
5309  */
5310 static int adapter_test( SLMP_INFO *info )
5311 {
5312         unsigned long flags;
5313         if ( debug_level >= DEBUG_LEVEL_INFO )
5314                 printk( "%s(%d):Testing device %s\n",
5315                         __FILE__,__LINE__,info->device_name );
5316
5317         spin_lock_irqsave(&info->lock,flags);
5318         init_adapter(info);
5319         spin_unlock_irqrestore(&info->lock,flags);
5320
5321         info->port_array[0]->port_count = 0;
5322
5323         if ( register_test(info->port_array[0]) &&
5324                 register_test(info->port_array[1])) {
5325
5326                 info->port_array[0]->port_count = 2;
5327
5328                 if ( register_test(info->port_array[2]) &&
5329                         register_test(info->port_array[3]) )
5330                         info->port_array[0]->port_count += 2;
5331         }
5332         else {
5333                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5334                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5335                 return -ENODEV;
5336         }
5337
5338         if ( !irq_test(info->port_array[0]) ||
5339                 !irq_test(info->port_array[1]) ||
5340                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5341                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5342                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5343                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5344                 return -ENODEV;
5345         }
5346
5347         if (!loopback_test(info->port_array[0]) ||
5348                 !loopback_test(info->port_array[1]) ||
5349                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5350                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5351                 printk( "%s(%d):DMA test failure for device %s\n",
5352                         __FILE__,__LINE__,info->device_name);
5353                 return -ENODEV;
5354         }
5355
5356         if ( debug_level >= DEBUG_LEVEL_INFO )
5357                 printk( "%s(%d):device %s passed diagnostics\n",
5358                         __FILE__,__LINE__,info->device_name );
5359
5360         info->port_array[0]->init_error = 0;
5361         info->port_array[1]->init_error = 0;
5362         if ( info->port_count > 2 ) {
5363                 info->port_array[2]->init_error = 0;
5364                 info->port_array[3]->init_error = 0;
5365         }
5366
5367         return 0;
5368 }
5369
5370 /* Test the shared memory on a PCI adapter.
5371  */
5372 static bool memory_test(SLMP_INFO *info)
5373 {
5374         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5375                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5376         unsigned long count = ARRAY_SIZE(testval);
5377         unsigned long i;
5378         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5379         unsigned long * addr = (unsigned long *)info->memory_base;
5380
5381         /* Test data lines with test pattern at one location. */
5382
5383         for ( i = 0 ; i < count ; i++ ) {
5384                 *addr = testval[i];
5385                 if ( *addr != testval[i] )
5386                         return false;
5387         }
5388
5389         /* Test address lines with incrementing pattern over */
5390         /* entire address range. */
5391
5392         for ( i = 0 ; i < limit ; i++ ) {
5393                 *addr = i * 4;
5394                 addr++;
5395         }
5396
5397         addr = (unsigned long *)info->memory_base;
5398
5399         for ( i = 0 ; i < limit ; i++ ) {
5400                 if ( *addr != i * 4 )
5401                         return false;
5402                 addr++;
5403         }
5404
5405         memset( info->memory_base, 0, SCA_MEM_SIZE );
5406         return true;
5407 }
5408
5409 /* Load data into PCI adapter shared memory.
5410  *
5411  * The PCI9050 releases control of the local bus
5412  * after completing the current read or write operation.
5413  *
5414  * While the PCI9050 write FIFO not empty, the
5415  * PCI9050 treats all of the writes as a single transaction
5416  * and does not release the bus. This causes DMA latency problems
5417  * at high speeds when copying large data blocks to the shared memory.
5418  *
5419  * This function breaks a write into multiple transations by
5420  * interleaving a read which flushes the write FIFO and 'completes'
5421  * the write transation. This allows any pending DMA request to gain control
5422  * of the local bus in a timely fasion.
5423  */
5424 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5425 {
5426         /* A load interval of 16 allows for 4 32-bit writes at */
5427         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5428
5429         unsigned short interval = count / sca_pci_load_interval;
5430         unsigned short i;
5431
5432         for ( i = 0 ; i < interval ; i++ )
5433         {
5434                 memcpy(dest, src, sca_pci_load_interval);
5435                 read_status_reg(info);
5436                 dest += sca_pci_load_interval;
5437                 src += sca_pci_load_interval;
5438         }
5439
5440         memcpy(dest, src, count % sca_pci_load_interval);
5441 }
5442
5443 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5444 {
5445         int i;
5446         int linecount;
5447         if (xmit)
5448                 printk("%s tx data:\n",info->device_name);
5449         else
5450                 printk("%s rx data:\n",info->device_name);
5451
5452         while(count) {
5453                 if (count > 16)
5454                         linecount = 16;
5455                 else
5456                         linecount = count;
5457
5458                 for(i=0;i<linecount;i++)
5459                         printk("%02X ",(unsigned char)data[i]);
5460                 for(;i<17;i++)
5461                         printk("   ");
5462                 for(i=0;i<linecount;i++) {
5463                         if (data[i]>=040 && data[i]<=0176)
5464                                 printk("%c",data[i]);
5465                         else
5466                                 printk(".");
5467                 }
5468                 printk("\n");
5469
5470                 data  += linecount;
5471                 count -= linecount;
5472         }
5473 }       /* end of trace_block() */
5474
5475 /* called when HDLC frame times out
5476  * update stats and do tx completion processing
5477  */
5478 static void tx_timeout(unsigned long context)
5479 {
5480         SLMP_INFO *info = (SLMP_INFO*)context;
5481         unsigned long flags;
5482
5483         if ( debug_level >= DEBUG_LEVEL_INFO )
5484                 printk( "%s(%d):%s tx_timeout()\n",
5485                         __FILE__,__LINE__,info->device_name);
5486         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5487                 info->icount.txtimeout++;
5488         }
5489         spin_lock_irqsave(&info->lock,flags);
5490         info->tx_active = false;
5491         info->tx_count = info->tx_put = info->tx_get = 0;
5492
5493         spin_unlock_irqrestore(&info->lock,flags);
5494
5495 #if SYNCLINK_GENERIC_HDLC
5496         if (info->netcount)
5497                 hdlcdev_tx_done(info);
5498         else
5499 #endif
5500                 bh_transmit(info);
5501 }
5502
5503 /* called to periodically check the DSR/RI modem signal input status
5504  */
5505 static void status_timeout(unsigned long context)
5506 {
5507         u16 status = 0;
5508         SLMP_INFO *info = (SLMP_INFO*)context;
5509         unsigned long flags;
5510         unsigned char delta;
5511
5512
5513         spin_lock_irqsave(&info->lock,flags);
5514         get_signals(info);
5515         spin_unlock_irqrestore(&info->lock,flags);
5516
5517         /* check for DSR/RI state change */
5518
5519         delta = info->old_signals ^ info->serial_signals;
5520         info->old_signals = info->serial_signals;
5521
5522         if (delta & SerialSignal_DSR)
5523                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5524
5525         if (delta & SerialSignal_RI)
5526                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5527
5528         if (delta & SerialSignal_DCD)
5529                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5530
5531         if (delta & SerialSignal_CTS)
5532                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5533
5534         if (status)
5535                 isr_io_pin(info,status);
5536
5537         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5538 }
5539
5540
5541 /* Register Access Routines -
5542  * All registers are memory mapped
5543  */
5544 #define CALC_REGADDR() \
5545         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5546         if (info->port_num > 1) \
5547                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5548         if ( info->port_num & 1) { \
5549                 if (Addr > 0x7f) \
5550                         RegAddr += 0x40;        /* DMA access */ \
5551                 else if (Addr > 0x1f && Addr < 0x60) \
5552                         RegAddr += 0x20;        /* MSCI access */ \
5553         }
5554
5555
5556 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5557 {
5558         CALC_REGADDR();
5559         return *RegAddr;
5560 }
5561 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5562 {
5563         CALC_REGADDR();
5564         *RegAddr = Value;
5565 }
5566
5567 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5568 {
5569         CALC_REGADDR();
5570         return *((u16 *)RegAddr);
5571 }
5572
5573 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5574 {
5575         CALC_REGADDR();
5576         *((u16 *)RegAddr) = Value;
5577 }
5578
5579 static unsigned char read_status_reg(SLMP_INFO * info)
5580 {
5581         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5582         return *RegAddr;
5583 }
5584
5585 static void write_control_reg(SLMP_INFO * info)
5586 {
5587         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5588         *RegAddr = info->port_array[0]->ctrlreg_value;
5589 }
5590
5591
5592 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5593                                           const struct pci_device_id *ent)
5594 {
5595         if (pci_enable_device(dev)) {
5596                 printk("error enabling pci device %p\n", dev);
5597                 return -EIO;
5598         }
5599         device_init( ++synclinkmp_adapter_count, dev );
5600         return 0;
5601 }
5602
5603 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5604 {
5605 }