drivers/char/synclink_gt.c

   1 /*
   2  * Device driver for Microgate SyncLink GT serial adapters.
   3  *
   4  * written by Paul Fulghum for Microgate Corporation
   5  * paulkf@microgate.com
   6  *
   7  * Microgate and SyncLink are trademarks of Microgate Corporation
   8  *
   9  * This code is released under the GNU General Public License (GPL)
  10  *
  11  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  13  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  14  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  15  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  16  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  17  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  18  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  19  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  21  * OF THE POSSIBILITY OF SUCH DAMAGE.
  22  */
  23
  24 /*
  25  * DEBUG OUTPUT DEFINITIONS
  26  *
  27  * uncomment lines below to enable specific types of debug output
  28  *
  29  * DBGINFO   information - most verbose output
  30  * DBGERR    serious errors
  31  * DBGBH     bottom half service routine debugging
  32  * DBGISR    interrupt service routine debugging
  33  * DBGDATA   output receive and transmit data
  34  * DBGTBUF   output transmit DMA buffers and registers
  35  * DBGRBUF   output receive DMA buffers and registers
  36  */
  37
  38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  43 //#define DBGTBUF(info) dump_tbufs(info)
  44 //#define DBGRBUF(info) dump_rbufs(info)
  45
  46
  47 #include <linux/module.h>
  48 #include <linux/errno.h>
  49 #include <linux/signal.h>
  50 #include <linux/sched.h>
  51 #include <linux/timer.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/pci.h>
  54 #include <linux/tty.h>
  55 #include <linux/tty_flip.h>
  56 #include <linux/serial.h>
  57 #include <linux/major.h>
  58 #include <linux/string.h>
  59 #include <linux/fcntl.h>
  60 #include <linux/ptrace.h>
  61 #include <linux/ioport.h>
  62 #include <linux/mm.h>
  63 #include <linux/seq_file.h>
  64 #include <linux/slab.h>
  65 #include <linux/smp_lock.h>
  66 #include <linux/netdevice.h>
  67 #include <linux/vmalloc.h>
  68 #include <linux/init.h>
  69 #include <linux/delay.h>
  70 #include <linux/ioctl.h>
  71 #include <linux/termios.h>
  72 #include <linux/bitops.h>
  73 #include <linux/workqueue.h>
  74 #include <linux/hdlc.h>
  75 #include <linux/synclink.h>
  76
  77 #include <asm/system.h>
  78 #include <asm/io.h>
  79 #include <asm/irq.h>
  80 #include <asm/dma.h>
  81 #include <asm/types.h>
  82 #include <asm/uaccess.h>
  83
  84 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  85 #define SYNCLINK_GENERIC_HDLC 1
  86 #else
  87 #define SYNCLINK_GENERIC_HDLC 0
  88 #endif
  89
  90 /*
  91  * module identification
  92  */
  93 static char *driver_name     = "SyncLink GT";
  94 static char *tty_driver_name = "synclink_gt";
  95 static char *tty_dev_prefix  = "ttySLG";
  96 MODULE_LICENSE("GPL");
  97 #define MGSL_MAGIC 0x5401
  98 #define MAX_DEVICES 32
  99
 100 static struct pci_device_id pci_table[] = {
 101         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 102         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {0,}, /* terminate list */
 106 };
 107 MODULE_DEVICE_TABLE(pci, pci_table);
 108
 109 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 110 static void remove_one(struct pci_dev *dev);
 111 static struct pci_driver pci_driver = {
 112         .name           = "synclink_gt",
 113         .id_table       = pci_table,
 114         .probe          = init_one,
 115         .remove         = __devexit_p(remove_one),
 116 };
 117
 118 static bool pci_registered;
 119
 120 /*
 121  * module configuration and status
 122  */
 123 static struct slgt_info *slgt_device_list;
 124 static int slgt_device_count;
 125
 126 static int ttymajor;
 127 static int debug_level;
 128 static int maxframe[MAX_DEVICES];
 129
 130 module_param(ttymajor, int, 0);
 131 module_param(debug_level, int, 0);
 132 module_param_array(maxframe, int, NULL, 0);
 133
 134 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 135 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 136 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 137
 138 /*
 139  * tty support and callbacks
 140  */
 141 static struct tty_driver *serial_driver;
 142
 143 static int  open(struct tty_struct *tty, struct file * filp);
 144 static void close(struct tty_struct *tty, struct file * filp);
 145 static void hangup(struct tty_struct *tty);
 146 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 147
 148 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 149 static int put_char(struct tty_struct *tty, unsigned char ch);
 150 static void send_xchar(struct tty_struct *tty, char ch);
 151 static void wait_until_sent(struct tty_struct *tty, int timeout);
 152 static int  write_room(struct tty_struct *tty);
 153 static void flush_chars(struct tty_struct *tty);
 154 static void flush_buffer(struct tty_struct *tty);
 155 static void tx_hold(struct tty_struct *tty);
 156 static void tx_release(struct tty_struct *tty);
 157
 158 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 159 static int  chars_in_buffer(struct tty_struct *tty);
 160 static void throttle(struct tty_struct * tty);
 161 static void unthrottle(struct tty_struct * tty);
 162 static int set_break(struct tty_struct *tty, int break_state);
 163
 164 /*
 165  * generic HDLC support and callbacks
 166  */
 167 #if SYNCLINK_GENERIC_HDLC
 168 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 169 static void hdlcdev_tx_done(struct slgt_info *info);
 170 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 171 static int  hdlcdev_init(struct slgt_info *info);
 172 static void hdlcdev_exit(struct slgt_info *info);
 173 #endif
 174
 175
 176 /*
 177  * device specific structures, macros and functions
 178  */
 179
 180 #define SLGT_MAX_PORTS 4
 181 #define SLGT_REG_SIZE  256
 182
 183 /*
 184  * conditional wait facility
 185  */
 186 struct cond_wait {
 187         struct cond_wait *next;
 188         wait_queue_head_t q;
 189         wait_queue_t wait;
 190         unsigned int data;
 191 };
 192 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 193 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 194 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 195 static void flush_cond_wait(struct cond_wait **head);
 196
 197 /*
 198  * DMA buffer descriptor and access macros
 199  */
 200 struct slgt_desc
 201 {
 202         __le16 count;
 203         __le16 status;
 204         __le32 pbuf;  /* physical address of data buffer */
 205         __le32 next;  /* physical address of next descriptor */
 206
 207         /* driver book keeping */
 208         char *buf;          /* virtual  address of data buffer */
 209         unsigned int pdesc; /* physical address of this descriptor */
 210         dma_addr_t buf_dma_addr;
 211         unsigned short buf_count;
 212 };
 213
 214 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 215 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 216 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 217 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 218 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
 219 #define desc_count(a)      (le16_to_cpu((a).count))
 220 #define desc_status(a)     (le16_to_cpu((a).status))
 221 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 222 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 223 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 224 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 225 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 226
 227 struct _input_signal_events {
 228         int ri_up;
 229         int ri_down;
 230         int dsr_up;
 231         int dsr_down;
 232         int dcd_up;
 233         int dcd_down;
 234         int cts_up;
 235         int cts_down;
 236 };
 237
 238 /*
 239  * device instance data structure
 240  */
 241 struct slgt_info {
 242         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 243         struct tty_port port;
 244
 245         struct slgt_info *next_device;  /* device list link */
 246
 247         int magic;
 248
 249         char device_name[25];
 250         struct pci_dev *pdev;
 251
 252         int port_count;  /* count of ports on adapter */
 253         int adapter_num; /* adapter instance number */
 254         int port_num;    /* port instance number */
 255
 256         /* array of pointers to port contexts on this adapter */
 257         struct slgt_info *port_array[SLGT_MAX_PORTS];
 258
 259         int                     line;           /* tty line instance number */
 260
 261         struct mgsl_icount      icount;
 262
 263         int                     timeout;
 264         int                     x_char;         /* xon/xoff character */
 265         unsigned int            read_status_mask;
 266         unsigned int            ignore_status_mask;
 267
 268         wait_queue_head_t       status_event_wait_q;
 269         wait_queue_head_t       event_wait_q;
 270         struct timer_list       tx_timer;
 271         struct timer_list       rx_timer;
 272
 273         unsigned int            gpio_present;
 274         struct cond_wait        *gpio_wait_q;
 275
 276         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 277
 278         struct work_struct task;
 279         u32 pending_bh;
 280         bool bh_requested;
 281         bool bh_running;
 282
 283         int isr_overflow;
 284         bool irq_requested;     /* true if IRQ requested */
 285         bool irq_occurred;      /* for diagnostics use */
 286
 287         /* device configuration */
 288
 289         unsigned int bus_type;
 290         unsigned int irq_level;
 291         unsigned long irq_flags;
 292
 293         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 294         u32 phys_reg_addr;
 295         bool reg_addr_requested;
 296
 297         MGSL_PARAMS params;       /* communications parameters */
 298         u32 idle_mode;
 299         u32 max_frame_size;       /* as set by device config */
 300
 301         unsigned int rbuf_fill_level;
 302         unsigned int rx_pio;
 303         unsigned int if_mode;
 304         unsigned int base_clock;
 305
 306         /* device status */
 307
 308         bool rx_enabled;
 309         bool rx_restart;
 310
 311         bool tx_enabled;
 312         bool tx_active;
 313
 314         unsigned char signals;    /* serial signal states */
 315         int init_error;  /* initialization error */
 316
 317         unsigned char *tx_buf;
 318         int tx_count;
 319
 320         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 321         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 322         bool drop_rts_on_tx_done;
 323         struct  _input_signal_events    input_signal_events;
 324
 325         int dcd_chkcount;       /* check counts to prevent */
 326         int cts_chkcount;       /* too many IRQs if a signal */
 327         int dsr_chkcount;       /* is floating */
 328         int ri_chkcount;
 329
 330         char *bufs;             /* virtual address of DMA buffer lists */
 331         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 332
 333         unsigned int rbuf_count;
 334         struct slgt_desc *rbufs;
 335         unsigned int rbuf_current;
 336         unsigned int rbuf_index;
 337         unsigned int rbuf_fill_index;
 338         unsigned short rbuf_fill_count;
 339
 340         unsigned int tbuf_count;
 341         struct slgt_desc *tbufs;
 342         unsigned int tbuf_current;
 343         unsigned int tbuf_start;
 344
 345         unsigned char *tmp_rbuf;
 346         unsigned int tmp_rbuf_count;
 347
 348         /* SPPP/Cisco HDLC device parts */
 349
 350         int netcount;
 351         spinlock_t netlock;
 352 #if SYNCLINK_GENERIC_HDLC
 353         struct net_device *netdev;
 354 #endif
 355
 356 };
 357
 358 static MGSL_PARAMS default_params = {
 359         .mode            = MGSL_MODE_HDLC,
 360         .loopback        = 0,
 361         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 362         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 363         .clock_speed     = 0,
 364         .addr_filter     = 0xff,
 365         .crc_type        = HDLC_CRC_16_CCITT,
 366         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 367         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 368         .data_rate       = 9600,
 369         .data_bits       = 8,
 370         .stop_bits       = 1,
 371         .parity          = ASYNC_PARITY_NONE
 372 };
 373
 374
 375 #define BH_RECEIVE  1
 376 #define BH_TRANSMIT 2
 377 #define BH_STATUS   4
 378 #define IO_PIN_SHUTDOWN_LIMIT 100
 379
 380 #define DMABUFSIZE 256
 381 #define DESC_LIST_SIZE 4096
 382
 383 #define MASK_PARITY  BIT1
 384 #define MASK_FRAMING BIT0
 385 #define MASK_BREAK   BIT14
 386 #define MASK_OVERRUN BIT4
 387
 388 #define GSR   0x00 /* global status */
 389 #define JCR   0x04 /* JTAG control */
 390 #define IODR  0x08 /* GPIO direction */
 391 #define IOER  0x0c /* GPIO interrupt enable */
 392 #define IOVR  0x10 /* GPIO value */
 393 #define IOSR  0x14 /* GPIO interrupt status */
 394 #define TDR   0x80 /* tx data */
 395 #define RDR   0x80 /* rx data */
 396 #define TCR   0x82 /* tx control */
 397 #define TIR   0x84 /* tx idle */
 398 #define TPR   0x85 /* tx preamble */
 399 #define RCR   0x86 /* rx control */
 400 #define VCR   0x88 /* V.24 control */
 401 #define CCR   0x89 /* clock control */
 402 #define BDR   0x8a /* baud divisor */
 403 #define SCR   0x8c /* serial control */
 404 #define SSR   0x8e /* serial status */
 405 #define RDCSR 0x90 /* rx DMA control/status */
 406 #define TDCSR 0x94 /* tx DMA control/status */
 407 #define RDDAR 0x98 /* rx DMA descriptor address */
 408 #define TDDAR 0x9c /* tx DMA descriptor address */
 409
 410 #define RXIDLE      BIT14
 411 #define RXBREAK     BIT14
 412 #define IRQ_TXDATA  BIT13
 413 #define IRQ_TXIDLE  BIT12
 414 #define IRQ_TXUNDER BIT11 /* HDLC */
 415 #define IRQ_RXDATA  BIT10
 416 #define IRQ_RXIDLE  BIT9  /* HDLC */
 417 #define IRQ_RXBREAK BIT9  /* async */
 418 #define IRQ_RXOVER  BIT8
 419 #define IRQ_DSR     BIT7
 420 #define IRQ_CTS     BIT6
 421 #define IRQ_DCD     BIT5
 422 #define IRQ_RI      BIT4
 423 #define IRQ_ALL     0x3ff0
 424 #define IRQ_MASTER  BIT0
 425
 426 #define slgt_irq_on(info, mask) \
 427         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 428 #define slgt_irq_off(info, mask) \
 429         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 430
 431 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 432 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 433 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 434 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 435 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 436 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 437
 438 static void  msc_set_vcr(struct slgt_info *info);
 439
 440 static int  startup(struct slgt_info *info);
 441 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 442 static void shutdown(struct slgt_info *info);
 443 static void program_hw(struct slgt_info *info);
 444 static void change_params(struct slgt_info *info);
 445
 446 static int  register_test(struct slgt_info *info);
 447 static int  irq_test(struct slgt_info *info);
 448 static int  loopback_test(struct slgt_info *info);
 449 static int  adapter_test(struct slgt_info *info);
 450
 451 static void reset_adapter(struct slgt_info *info);
 452 static void reset_port(struct slgt_info *info);
 453 static void async_mode(struct slgt_info *info);
 454 static void sync_mode(struct slgt_info *info);
 455
 456 static void rx_stop(struct slgt_info *info);
 457 static void rx_start(struct slgt_info *info);
 458 static void reset_rbufs(struct slgt_info *info);
 459 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 460 static void rdma_reset(struct slgt_info *info);
 461 static bool rx_get_frame(struct slgt_info *info);
 462 static bool rx_get_buf(struct slgt_info *info);
 463
 464 static void tx_start(struct slgt_info *info);
 465 static void tx_stop(struct slgt_info *info);
 466 static void tx_set_idle(struct slgt_info *info);
 467 static unsigned int free_tbuf_count(struct slgt_info *info);
 468 static unsigned int tbuf_bytes(struct slgt_info *info);
 469 static void reset_tbufs(struct slgt_info *info);
 470 static void tdma_reset(struct slgt_info *info);
 471 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 472
 473 static void get_signals(struct slgt_info *info);
 474 static void set_signals(struct slgt_info *info);
 475 static void enable_loopback(struct slgt_info *info);
 476 static void set_rate(struct slgt_info *info, u32 data_rate);
 477
 478 static int  bh_action(struct slgt_info *info);
 479 static void bh_handler(struct work_struct *work);
 480 static void bh_transmit(struct slgt_info *info);
 481 static void isr_serial(struct slgt_info *info);
 482 static void isr_rdma(struct slgt_info *info);
 483 static void isr_txeom(struct slgt_info *info, unsigned short status);
 484 static void isr_tdma(struct slgt_info *info);
 485
 486 static int  alloc_dma_bufs(struct slgt_info *info);
 487 static void free_dma_bufs(struct slgt_info *info);
 488 static int  alloc_desc(struct slgt_info *info);
 489 static void free_desc(struct slgt_info *info);
 490 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 491 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 492
 493 static int  alloc_tmp_rbuf(struct slgt_info *info);
 494 static void free_tmp_rbuf(struct slgt_info *info);
 495
 496 static void tx_timeout(unsigned long context);
 497 static void rx_timeout(unsigned long context);
 498
 499 /*
 500  * ioctl handlers
 501  */
 502 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 503 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 504 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 505 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 506 static int  set_txidle(struct slgt_info *info, int idle_mode);
 507 static int  tx_enable(struct slgt_info *info, int enable);
 508 static int  tx_abort(struct slgt_info *info);
 509 static int  rx_enable(struct slgt_info *info, int enable);
 510 static int  modem_input_wait(struct slgt_info *info,int arg);
 511 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 512 static int  tiocmget(struct tty_struct *tty, struct file *file);
 513 static int  tiocmset(struct tty_struct *tty, struct file *file,
 514                      unsigned int set, unsigned int clear);
 515 static int set_break(struct tty_struct *tty, int break_state);
 516 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 517 static int  set_interface(struct slgt_info *info, int if_mode);
 518 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 519 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 520 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 521
 522 /*
 523  * driver functions
 524  */
 525 static void add_device(struct slgt_info *info);
 526 static void device_init(int adapter_num, struct pci_dev *pdev);
 527 static int  claim_resources(struct slgt_info *info);
 528 static void release_resources(struct slgt_info *info);
 529
 530 /*
 531  * DEBUG OUTPUT CODE
 532  */
 533 #ifndef DBGINFO
 534 #define DBGINFO(fmt)
 535 #endif
 536 #ifndef DBGERR
 537 #define DBGERR(fmt)
 538 #endif
 539 #ifndef DBGBH
 540 #define DBGBH(fmt)
 541 #endif
 542 #ifndef DBGISR
 543 #define DBGISR(fmt)
 544 #endif
 545
 546 #ifdef DBGDATA
 547 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 548 {
 549         int i;
 550         int linecount;
 551         printk("%s %s data:\n",info->device_name, label);
 552         while(count) {
 553                 linecount = (count > 16) ? 16 : count;
 554                 for(i=0; i < linecount; i++)
 555                         printk("%02X ",(unsigned char)data[i]);
 556                 for(;i<17;i++)
 557                         printk("   ");
 558                 for(i=0;i<linecount;i++) {
 559                         if (data[i]>=040 && data[i]<=0176)
 560                                 printk("%c",data[i]);
 561                         else
 562                                 printk(".");
 563                 }
 564                 printk("\n");
 565                 data  += linecount;
 566                 count -= linecount;
 567         }
 568 }
 569 #else
 570 #define DBGDATA(info, buf, size, label)
 571 #endif
 572
 573 #ifdef DBGTBUF
 574 static void dump_tbufs(struct slgt_info *info)
 575 {
 576         int i;
 577         printk("tbuf_current=%d\n", info->tbuf_current);
 578         for (i=0 ; i < info->tbuf_count ; i++) {
 579                 printk("%d: count=%04X status=%04X\n",
 580                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 581         }
 582 }
 583 #else
 584 #define DBGTBUF(info)
 585 #endif
 586
 587 #ifdef DBGRBUF
 588 static void dump_rbufs(struct slgt_info *info)
 589 {
 590         int i;
 591         printk("rbuf_current=%d\n", info->rbuf_current);
 592         for (i=0 ; i < info->rbuf_count ; i++) {
 593                 printk("%d: count=%04X status=%04X\n",
 594                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 595         }
 596 }
 597 #else
 598 #define DBGRBUF(info)
 599 #endif
 600
 601 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 602 {
 603 #ifdef SANITY_CHECK
 604         if (!info) {
 605                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 606                 return 1;
 607         }
 608         if (info->magic != MGSL_MAGIC) {
 609                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 610                 return 1;
 611         }
 612 #else
 613         if (!info)
 614                 return 1;
 615 #endif
 616         return 0;
 617 }
 618
 619 /**
 620  * line discipline callback wrappers
 621  *
 622  * The wrappers maintain line discipline references
 623  * while calling into the line discipline.
 624  *
 625  * ldisc_receive_buf  - pass receive data to line discipline
 626  */
 627 static void ldisc_receive_buf(struct tty_struct *tty,
 628                               const __u8 *data, char *flags, int count)
 629 {
 630         struct tty_ldisc *ld;
 631         if (!tty)
 632                 return;
 633         ld = tty_ldisc_ref(tty);
 634         if (ld) {
 635                 if (ld->ops->receive_buf)
 636                         ld->ops->receive_buf(tty, data, flags, count);
 637                 tty_ldisc_deref(ld);
 638         }
 639 }
 640
 641 /* tty callbacks */
 642
 643 static int open(struct tty_struct *tty, struct file *filp)
 644 {
 645         struct slgt_info *info;
 646         int retval, line;
 647         unsigned long flags;
 648
 649         line = tty->index;
 650         if ((line < 0) || (line >= slgt_device_count)) {
 651                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 652                 return -ENODEV;
 653         }
 654
 655         info = slgt_device_list;
 656         while(info && info->line != line)
 657                 info = info->next_device;
 658         if (sanity_check(info, tty->name, "open"))
 659                 return -ENODEV;
 660         if (info->init_error) {
 661                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 662                 return -ENODEV;
 663         }
 664
 665         tty->driver_data = info;
 666         info->port.tty = tty;
 667
 668         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 669
 670         /* If port is closing, signal caller to try again */
 671         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 672                 if (info->port.flags & ASYNC_CLOSING)
 673                         interruptible_sleep_on(&info->port.close_wait);
 674                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 675                         -EAGAIN : -ERESTARTSYS);
 676                 goto cleanup;
 677         }
 678
 679         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 680
 681         spin_lock_irqsave(&info->netlock, flags);
 682         if (info->netcount) {
 683                 retval = -EBUSY;
 684                 spin_unlock_irqrestore(&info->netlock, flags);
 685                 goto cleanup;
 686         }
 687         info->port.count++;
 688         spin_unlock_irqrestore(&info->netlock, flags);
 689
 690         if (info->port.count == 1) {
 691                 /* 1st open on this device, init hardware */
 692                 retval = startup(info);
 693                 if (retval < 0)
 694                         goto cleanup;
 695         }
 696
 697         retval = block_til_ready(tty, filp, info);
 698         if (retval) {
 699                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 700                 goto cleanup;
 701         }
 702
 703         retval = 0;
 704
 705 cleanup:
 706         if (retval) {
 707                 if (tty->count == 1)
 708                         info->port.tty = NULL; /* tty layer will release tty struct */
 709                 if(info->port.count)
 710                         info->port.count--;
 711         }
 712
 713         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 714         return retval;
 715 }
 716
 717 static void close(struct tty_struct *tty, struct file *filp)
 718 {
 719         struct slgt_info *info = tty->driver_data;
 720
 721         if (sanity_check(info, tty->name, "close"))
 722                 return;
 723         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 724
 725         if (tty_port_close_start(&info->port, tty, filp) == 0)
 726                 goto cleanup;
 727
 728         if (info->port.flags & ASYNC_INITIALIZED)
 729                 wait_until_sent(tty, info->timeout);
 730         flush_buffer(tty);
 731         tty_ldisc_flush(tty);
 732
 733         shutdown(info);
 734
 735         tty_port_close_end(&info->port, tty);
 736         info->port.tty = NULL;
 737 cleanup:
 738         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 739 }
 740
 741 static void hangup(struct tty_struct *tty)
 742 {
 743         struct slgt_info *info = tty->driver_data;
 744
 745         if (sanity_check(info, tty->name, "hangup"))
 746                 return;
 747         DBGINFO(("%s hangup\n", info->device_name));
 748
 749         flush_buffer(tty);
 750         shutdown(info);
 751
 752         info->port.count = 0;
 753         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 754         info->port.tty = NULL;
 755
 756         wake_up_interruptible(&info->port.open_wait);
 757 }
 758
 759 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 760 {
 761         struct slgt_info *info = tty->driver_data;
 762         unsigned long flags;
 763
 764         DBGINFO(("%s set_termios\n", tty->driver->name));
 765
 766         change_params(info);
 767
 768         /* Handle transition to B0 status */
 769         if (old_termios->c_cflag & CBAUD &&
 770             !(tty->termios->c_cflag & CBAUD)) {
 771                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 772                 spin_lock_irqsave(&info->lock,flags);
 773                 set_signals(info);
 774                 spin_unlock_irqrestore(&info->lock,flags);
 775         }
 776
 777         /* Handle transition away from B0 status */
 778         if (!(old_termios->c_cflag & CBAUD) &&
 779             tty->termios->c_cflag & CBAUD) {
 780                 info->signals |= SerialSignal_DTR;
 781                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 782                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 783                         info->signals |= SerialSignal_RTS;
 784                 }
 785                 spin_lock_irqsave(&info->lock,flags);
 786                 set_signals(info);
 787                 spin_unlock_irqrestore(&info->lock,flags);
 788         }
 789
 790         /* Handle turning off CRTSCTS */
 791         if (old_termios->c_cflag & CRTSCTS &&
 792             !(tty->termios->c_cflag & CRTSCTS)) {
 793                 tty->hw_stopped = 0;
 794                 tx_release(tty);
 795         }
 796 }
 797
 798 static void update_tx_timer(struct slgt_info *info)
 799 {
 800         /*
 801          * use worst case speed of 1200bps to calculate transmit timeout
 802          * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
 803          */
 804         if (info->params.mode == MGSL_MODE_HDLC) {
 805                 int timeout  = (tbuf_bytes(info) * 7) + 1000;
 806                 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
 807         }
 808 }
 809
 810 static int write(struct tty_struct *tty,
 811                  const unsigned char *buf, int count)
 812 {
 813         int ret = 0;
 814         struct slgt_info *info = tty->driver_data;
 815         unsigned long flags;
 816         unsigned int bufs_needed;
 817
 818         if (sanity_check(info, tty->name, "write"))
 819                 goto cleanup;
 820         DBGINFO(("%s write count=%d\n", info->device_name, count));
 821
 822         if (!info->tx_buf)
 823                 goto cleanup;
 824
 825         if (count > info->max_frame_size) {
 826                 ret = -EIO;
 827                 goto cleanup;
 828         }
 829
 830         if (!count)
 831                 goto cleanup;
 832
 833         if (!info->tx_active && info->tx_count) {
 834                 /* send accumulated data from send_char() */
 835                 tx_load(info, info->tx_buf, info->tx_count);
 836                 goto start;
 837         }
 838         bufs_needed = (count/DMABUFSIZE);
 839         if (count % DMABUFSIZE)
 840                 ++bufs_needed;
 841         if (bufs_needed > free_tbuf_count(info))
 842                 goto cleanup;
 843
 844         ret = info->tx_count = count;
 845         tx_load(info, buf, count);
 846         goto start;
 847
 848 start:
 849         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 850                 spin_lock_irqsave(&info->lock,flags);
 851                 if (!info->tx_active)
 852                         tx_start(info);
 853                 else if (!(rd_reg32(info, TDCSR) & BIT0)) {
 854                         /* transmit still active but transmit DMA stopped */
 855                         unsigned int i = info->tbuf_current;
 856                         if (!i)
 857                                 i = info->tbuf_count;
 858                         i--;
 859                         /* if DMA buf unsent must try later after tx idle */
 860                         if (desc_count(info->tbufs[i]))
 861                                 ret = 0;
 862                 }
 863                 if (ret > 0)
 864                         update_tx_timer(info);
 865                 spin_unlock_irqrestore(&info->lock,flags);
 866         }
 867
 868 cleanup:
 869         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 870         return ret;
 871 }
 872
 873 static int put_char(struct tty_struct *tty, unsigned char ch)
 874 {
 875         struct slgt_info *info = tty->driver_data;
 876         unsigned long flags;
 877         int ret = 0;
 878
 879         if (sanity_check(info, tty->name, "put_char"))
 880                 return 0;
 881         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 882         if (!info->tx_buf)
 883                 return 0;
 884         spin_lock_irqsave(&info->lock,flags);
 885         if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
 886                 info->tx_buf[info->tx_count++] = ch;
 887                 ret = 1;
 888         }
 889         spin_unlock_irqrestore(&info->lock,flags);
 890         return ret;
 891 }
 892
 893 static void send_xchar(struct tty_struct *tty, char ch)
 894 {
 895         struct slgt_info *info = tty->driver_data;
 896         unsigned long flags;
 897
 898         if (sanity_check(info, tty->name, "send_xchar"))
 899                 return;
 900         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 901         info->x_char = ch;
 902         if (ch) {
 903                 spin_lock_irqsave(&info->lock,flags);
 904                 if (!info->tx_enabled)
 905                         tx_start(info);
 906                 spin_unlock_irqrestore(&info->lock,flags);
 907         }
 908 }
 909
 910 static void wait_until_sent(struct tty_struct *tty, int timeout)
 911 {
 912         struct slgt_info *info = tty->driver_data;
 913         unsigned long orig_jiffies, char_time;
 914
 915         if (!info )
 916                 return;
 917         if (sanity_check(info, tty->name, "wait_until_sent"))
 918                 return;
 919         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 920         if (!(info->port.flags & ASYNC_INITIALIZED))
 921                 goto exit;
 922
 923         orig_jiffies = jiffies;
 924
 925         /* Set check interval to 1/5 of estimated time to
 926          * send a character, and make it at least 1. The check
 927          * interval should also be less than the timeout.
 928          * Note: use tight timings here to satisfy the NIST-PCTS.
 929          */
 930
 931         lock_kernel();
 932
 933         if (info->params.data_rate) {
 934                 char_time = info->timeout/(32 * 5);
 935                 if (!char_time)
 936                         char_time++;
 937         } else
 938                 char_time = 1;
 939
 940         if (timeout)
 941                 char_time = min_t(unsigned long, char_time, timeout);
 942
 943         while (info->tx_active) {
 944                 msleep_interruptible(jiffies_to_msecs(char_time));
 945                 if (signal_pending(current))
 946                         break;
 947                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 948                         break;
 949         }
 950         unlock_kernel();
 951
 952 exit:
 953         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 954 }
 955
 956 static int write_room(struct tty_struct *tty)
 957 {
 958         struct slgt_info *info = tty->driver_data;
 959         int ret;
 960
 961         if (sanity_check(info, tty->name, "write_room"))
 962                 return 0;
 963         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 964         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 965         return ret;
 966 }
 967
 968 static void flush_chars(struct tty_struct *tty)
 969 {
 970         struct slgt_info *info = tty->driver_data;
 971         unsigned long flags;
 972
 973         if (sanity_check(info, tty->name, "flush_chars"))
 974                 return;
 975         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 976
 977         if (info->tx_count <= 0 || tty->stopped ||
 978             tty->hw_stopped || !info->tx_buf)
 979                 return;
 980
 981         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 982
 983         spin_lock_irqsave(&info->lock,flags);
 984         if (!info->tx_active && info->tx_count) {
 985                 tx_load(info, info->tx_buf,info->tx_count);
 986                 tx_start(info);
 987         }
 988         spin_unlock_irqrestore(&info->lock,flags);
 989 }
 990
 991 static void flush_buffer(struct tty_struct *tty)
 992 {
 993         struct slgt_info *info = tty->driver_data;
 994         unsigned long flags;
 995
 996         if (sanity_check(info, tty->name, "flush_buffer"))
 997                 return;
 998         DBGINFO(("%s flush_buffer\n", info->device_name));
 999
1000         spin_lock_irqsave(&info->lock,flags);
1001         if (!info->tx_active)
1002                 info->tx_count = 0;
1003         spin_unlock_irqrestore(&info->lock,flags);
1004
1005         tty_wakeup(tty);
1006 }
1007
1008 /*
1009  * throttle (stop) transmitter
1010  */
1011 static void tx_hold(struct tty_struct *tty)
1012 {
1013         struct slgt_info *info = tty->driver_data;
1014         unsigned long flags;
1015
1016         if (sanity_check(info, tty->name, "tx_hold"))
1017                 return;
1018         DBGINFO(("%s tx_hold\n", info->device_name));
1019         spin_lock_irqsave(&info->lock,flags);
1020         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1021                 tx_stop(info);
1022         spin_unlock_irqrestore(&info->lock,flags);
1023 }
1024
1025 /*
1026  * release (start) transmitter
1027  */
1028 static void tx_release(struct tty_struct *tty)
1029 {
1030         struct slgt_info *info = tty->driver_data;
1031         unsigned long flags;
1032
1033         if (sanity_check(info, tty->name, "tx_release"))
1034                 return;
1035         DBGINFO(("%s tx_release\n", info->device_name));
1036         spin_lock_irqsave(&info->lock,flags);
1037         if (!info->tx_active && info->tx_count) {
1038                 tx_load(info, info->tx_buf, info->tx_count);
1039                 tx_start(info);
1040         }
1041         spin_unlock_irqrestore(&info->lock,flags);
1042 }
1043
1044 /*
1045  * Service an IOCTL request
1046  *
1047  * Arguments
1048  *
1049  *      tty     pointer to tty instance data
1050  *      file    pointer to associated file object for device
1051  *      cmd     IOCTL command code
1052  *      arg     command argument/context
1053  *
1054  * Return 0 if success, otherwise error code
1055  */
1056 static int ioctl(struct tty_struct *tty, struct file *file,
1057                  unsigned int cmd, unsigned long arg)
1058 {
1059         struct slgt_info *info = tty->driver_data;
1060         struct mgsl_icount cnow;        /* kernel counter temps */
1061         struct serial_icounter_struct __user *p_cuser;  /* user space */
1062         unsigned long flags;
1063         void __user *argp = (void __user *)arg;
1064         int ret;
1065
1066         if (sanity_check(info, tty->name, "ioctl"))
1067                 return -ENODEV;
1068         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1069
1070         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1071             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1072                 if (tty->flags & (1 << TTY_IO_ERROR))
1073                     return -EIO;
1074         }
1075
1076         lock_kernel();
1077
1078         switch (cmd) {
1079         case MGSL_IOCGPARAMS:
1080                 ret = get_params(info, argp);
1081                 break;
1082         case MGSL_IOCSPARAMS:
1083                 ret = set_params(info, argp);
1084                 break;
1085         case MGSL_IOCGTXIDLE:
1086                 ret = get_txidle(info, argp);
1087                 break;
1088         case MGSL_IOCSTXIDLE:
1089                 ret = set_txidle(info, (int)arg);
1090                 break;
1091         case MGSL_IOCTXENABLE:
1092                 ret = tx_enable(info, (int)arg);
1093                 break;
1094         case MGSL_IOCRXENABLE:
1095                 ret = rx_enable(info, (int)arg);
1096                 break;
1097         case MGSL_IOCTXABORT:
1098                 ret = tx_abort(info);
1099                 break;
1100         case MGSL_IOCGSTATS:
1101                 ret = get_stats(info, argp);
1102                 break;
1103         case MGSL_IOCWAITEVENT:
1104                 ret = wait_mgsl_event(info, argp);
1105                 break;
1106         case TIOCMIWAIT:
1107                 ret = modem_input_wait(info,(int)arg);
1108                 break;
1109         case MGSL_IOCGIF:
1110                 ret = get_interface(info, argp);
1111                 break;
1112         case MGSL_IOCSIF:
1113                 ret = set_interface(info,(int)arg);
1114                 break;
1115         case MGSL_IOCSGPIO:
1116                 ret = set_gpio(info, argp);
1117                 break;
1118         case MGSL_IOCGGPIO:
1119                 ret = get_gpio(info, argp);
1120                 break;
1121         case MGSL_IOCWAITGPIO:
1122                 ret = wait_gpio(info, argp);
1123                 break;
1124         case TIOCGICOUNT:
1125                 spin_lock_irqsave(&info->lock,flags);
1126                 cnow = info->icount;
1127                 spin_unlock_irqrestore(&info->lock,flags);
1128                 p_cuser = argp;
1129                 if (put_user(cnow.cts, &p_cuser->cts) ||
1130                     put_user(cnow.dsr, &p_cuser->dsr) ||
1131                     put_user(cnow.rng, &p_cuser->rng) ||
1132                     put_user(cnow.dcd, &p_cuser->dcd) ||
1133                     put_user(cnow.rx, &p_cuser->rx) ||
1134                     put_user(cnow.tx, &p_cuser->tx) ||
1135                     put_user(cnow.frame, &p_cuser->frame) ||
1136                     put_user(cnow.overrun, &p_cuser->overrun) ||
1137                     put_user(cnow.parity, &p_cuser->parity) ||
1138                     put_user(cnow.brk, &p_cuser->brk) ||
1139                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1140                         ret = -EFAULT;
1141                 ret = 0;
1142                 break;
1143         default:
1144                 ret = -ENOIOCTLCMD;
1145         }
1146         unlock_kernel();
1147         return ret;
1148 }
1149
1150 /*
1151  * support for 32 bit ioctl calls on 64 bit systems
1152  */
1153 #ifdef CONFIG_COMPAT
1154 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1155 {
1156         struct MGSL_PARAMS32 tmp_params;
1157
1158         DBGINFO(("%s get_params32\n", info->device_name));
1159         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1160         tmp_params.loopback        = info->params.loopback;
1161         tmp_params.flags           = info->params.flags;
1162         tmp_params.encoding        = info->params.encoding;
1163         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1164         tmp_params.addr_filter     = info->params.addr_filter;
1165         tmp_params.crc_type        = info->params.crc_type;
1166         tmp_params.preamble_length = info->params.preamble_length;
1167         tmp_params.preamble        = info->params.preamble;
1168         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1169         tmp_params.data_bits       = info->params.data_bits;
1170         tmp_params.stop_bits       = info->params.stop_bits;
1171         tmp_params.parity          = info->params.parity;
1172         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1173                 return -EFAULT;
1174         return 0;
1175 }
1176
1177 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1178 {
1179         struct MGSL_PARAMS32 tmp_params;
1180
1181         DBGINFO(("%s set_params32\n", info->device_name));
1182         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1183                 return -EFAULT;
1184
1185         spin_lock(&info->lock);
1186         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1187                 info->base_clock = tmp_params.clock_speed;
1188         } else {
1189                 info->params.mode            = tmp_params.mode;
1190                 info->params.loopback        = tmp_params.loopback;
1191                 info->params.flags           = tmp_params.flags;
1192                 info->params.encoding        = tmp_params.encoding;
1193                 info->params.clock_speed     = tmp_params.clock_speed;
1194                 info->params.addr_filter     = tmp_params.addr_filter;
1195                 info->params.crc_type        = tmp_params.crc_type;
1196                 info->params.preamble_length = tmp_params.preamble_length;
1197                 info->params.preamble        = tmp_params.preamble;
1198                 info->params.data_rate       = tmp_params.data_rate;
1199                 info->params.data_bits       = tmp_params.data_bits;
1200                 info->params.stop_bits       = tmp_params.stop_bits;
1201                 info->params.parity          = tmp_params.parity;
1202         }
1203         spin_unlock(&info->lock);
1204
1205         program_hw(info);
1206
1207         return 0;
1208 }
1209
1210 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1211                          unsigned int cmd, unsigned long arg)
1212 {
1213         struct slgt_info *info = tty->driver_data;
1214         int rc = -ENOIOCTLCMD;
1215
1216         if (sanity_check(info, tty->name, "compat_ioctl"))
1217                 return -ENODEV;
1218         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1219
1220         switch (cmd) {
1221
1222         case MGSL_IOCSPARAMS32:
1223                 rc = set_params32(info, compat_ptr(arg));
1224                 break;
1225
1226         case MGSL_IOCGPARAMS32:
1227                 rc = get_params32(info, compat_ptr(arg));
1228                 break;
1229
1230         case MGSL_IOCGPARAMS:
1231         case MGSL_IOCSPARAMS:
1232         case MGSL_IOCGTXIDLE:
1233         case MGSL_IOCGSTATS:
1234         case MGSL_IOCWAITEVENT:
1235         case MGSL_IOCGIF:
1236         case MGSL_IOCSGPIO:
1237         case MGSL_IOCGGPIO:
1238         case MGSL_IOCWAITGPIO:
1239         case TIOCGICOUNT:
1240                 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1241                 break;
1242
1243         case MGSL_IOCSTXIDLE:
1244         case MGSL_IOCTXENABLE:
1245         case MGSL_IOCRXENABLE:
1246         case MGSL_IOCTXABORT:
1247         case TIOCMIWAIT:
1248         case MGSL_IOCSIF:
1249                 rc = ioctl(tty, file, cmd, arg);
1250                 break;
1251         }
1252
1253         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1254         return rc;
1255 }
1256 #else
1257 #define slgt_compat_ioctl NULL
1258 #endif /* ifdef CONFIG_COMPAT */
1259
1260 /*
1261  * proc fs support
1262  */
1263 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1264 {
1265         char stat_buf[30];
1266         unsigned long flags;
1267
1268         seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1269                       info->device_name, info->phys_reg_addr,
1270                       info->irq_level, info->max_frame_size);
1271
1272         /* output current serial signal states */
1273         spin_lock_irqsave(&info->lock,flags);
1274         get_signals(info);
1275         spin_unlock_irqrestore(&info->lock,flags);
1276
1277         stat_buf[0] = 0;
1278         stat_buf[1] = 0;
1279         if (info->signals & SerialSignal_RTS)
1280                 strcat(stat_buf, "|RTS");
1281         if (info->signals & SerialSignal_CTS)
1282                 strcat(stat_buf, "|CTS");
1283         if (info->signals & SerialSignal_DTR)
1284                 strcat(stat_buf, "|DTR");
1285         if (info->signals & SerialSignal_DSR)
1286                 strcat(stat_buf, "|DSR");
1287         if (info->signals & SerialSignal_DCD)
1288                 strcat(stat_buf, "|CD");
1289         if (info->signals & SerialSignal_RI)
1290                 strcat(stat_buf, "|RI");
1291
1292         if (info->params.mode != MGSL_MODE_ASYNC) {
1293                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1294                                info->icount.txok, info->icount.rxok);
1295                 if (info->icount.txunder)
1296                         seq_printf(m, " txunder:%d", info->icount.txunder);
1297                 if (info->icount.txabort)
1298                         seq_printf(m, " txabort:%d", info->icount.txabort);
1299                 if (info->icount.rxshort)
1300                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1301                 if (info->icount.rxlong)
1302                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1303                 if (info->icount.rxover)
1304                         seq_printf(m, " rxover:%d", info->icount.rxover);
1305                 if (info->icount.rxcrc)
1306                         seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1307         } else {
1308                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1309                                info->icount.tx, info->icount.rx);
1310                 if (info->icount.frame)
1311                         seq_printf(m, " fe:%d", info->icount.frame);
1312                 if (info->icount.parity)
1313                         seq_printf(m, " pe:%d", info->icount.parity);
1314                 if (info->icount.brk)
1315                         seq_printf(m, " brk:%d", info->icount.brk);
1316                 if (info->icount.overrun)
1317                         seq_printf(m, " oe:%d", info->icount.overrun);
1318         }
1319
1320         /* Append serial signal status to end */
1321         seq_printf(m, " %s\n", stat_buf+1);
1322
1323         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1324                        info->tx_active,info->bh_requested,info->bh_running,
1325                        info->pending_bh);
1326 }
1327
1328 /* Called to print information about devices
1329  */
1330 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1331 {
1332         struct slgt_info *info;
1333
1334         seq_puts(m, "synclink_gt driver\n");
1335
1336         info = slgt_device_list;
1337         while( info ) {
1338                 line_info(m, info);
1339                 info = info->next_device;
1340         }
1341         return 0;
1342 }
1343
1344 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1345 {
1346         return single_open(file, synclink_gt_proc_show, NULL);
1347 }
1348
1349 static const struct file_operations synclink_gt_proc_fops = {
1350         .owner          = THIS_MODULE,
1351         .open           = synclink_gt_proc_open,
1352         .read           = seq_read,
1353         .llseek         = seq_lseek,
1354         .release        = single_release,
1355 };
1356
1357 /*
1358  * return count of bytes in transmit buffer
1359  */
1360 static int chars_in_buffer(struct tty_struct *tty)
1361 {
1362         struct slgt_info *info = tty->driver_data;
1363         int count;
1364         if (sanity_check(info, tty->name, "chars_in_buffer"))
1365                 return 0;
1366         count = tbuf_bytes(info);
1367         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1368         return count;
1369 }
1370
1371 /*
1372  * signal remote device to throttle send data (our receive data)
1373  */
1374 static void throttle(struct tty_struct * tty)
1375 {
1376         struct slgt_info *info = tty->driver_data;
1377         unsigned long flags;
1378
1379         if (sanity_check(info, tty->name, "throttle"))
1380                 return;
1381         DBGINFO(("%s throttle\n", info->device_name));
1382         if (I_IXOFF(tty))
1383                 send_xchar(tty, STOP_CHAR(tty));
1384         if (tty->termios->c_cflag & CRTSCTS) {
1385                 spin_lock_irqsave(&info->lock,flags);
1386                 info->signals &= ~SerialSignal_RTS;
1387                 set_signals(info);
1388                 spin_unlock_irqrestore(&info->lock,flags);
1389         }
1390 }
1391
1392 /*
1393  * signal remote device to stop throttling send data (our receive data)
1394  */
1395 static void unthrottle(struct tty_struct * tty)
1396 {
1397         struct slgt_info *info = tty->driver_data;
1398         unsigned long flags;
1399
1400         if (sanity_check(info, tty->name, "unthrottle"))
1401                 return;
1402         DBGINFO(("%s unthrottle\n", info->device_name));
1403         if (I_IXOFF(tty)) {
1404                 if (info->x_char)
1405                         info->x_char = 0;
1406                 else
1407                         send_xchar(tty, START_CHAR(tty));
1408         }
1409         if (tty->termios->c_cflag & CRTSCTS) {
1410                 spin_lock_irqsave(&info->lock,flags);
1411                 info->signals |= SerialSignal_RTS;
1412                 set_signals(info);
1413                 spin_unlock_irqrestore(&info->lock,flags);
1414         }
1415 }
1416
1417 /*
1418  * set or clear transmit break condition
1419  * break_state  -1=set break condition, 0=clear
1420  */
1421 static int set_break(struct tty_struct *tty, int break_state)
1422 {
1423         struct slgt_info *info = tty->driver_data;
1424         unsigned short value;
1425         unsigned long flags;
1426
1427         if (sanity_check(info, tty->name, "set_break"))
1428                 return -EINVAL;
1429         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1430
1431         spin_lock_irqsave(&info->lock,flags);
1432         value = rd_reg16(info, TCR);
1433         if (break_state == -1)
1434                 value |= BIT6;
1435         else
1436                 value &= ~BIT6;
1437         wr_reg16(info, TCR, value);
1438         spin_unlock_irqrestore(&info->lock,flags);
1439         return 0;
1440 }
1441
1442 #if SYNCLINK_GENERIC_HDLC
1443
1444 /**
1445  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1446  * set encoding and frame check sequence (FCS) options
1447  *
1448  * dev       pointer to network device structure
1449  * encoding  serial encoding setting
1450  * parity    FCS setting
1451  *
1452  * returns 0 if success, otherwise error code
1453  */
1454 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1455                           unsigned short parity)
1456 {
1457         struct slgt_info *info = dev_to_port(dev);
1458         unsigned char  new_encoding;
1459         unsigned short new_crctype;
1460
1461         /* return error if TTY interface open */
1462         if (info->port.count)
1463                 return -EBUSY;
1464
1465         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1466
1467         switch (encoding)
1468         {
1469         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1470         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1471         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1472         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1473         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1474         default: return -EINVAL;
1475         }
1476
1477         switch (parity)
1478         {
1479         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1480         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1481         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1482         default: return -EINVAL;
1483         }
1484
1485         info->params.encoding = new_encoding;
1486         info->params.crc_type = new_crctype;
1487
1488         /* if network interface up, reprogram hardware */
1489         if (info->netcount)
1490                 program_hw(info);
1491
1492         return 0;
1493 }
1494
1495 /**
1496  * called by generic HDLC layer to send frame
1497  *
1498  * skb  socket buffer containing HDLC frame
1499  * dev  pointer to network device structure
1500  */
1501 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1502                                       struct net_device *dev)
1503 {
1504         struct slgt_info *info = dev_to_port(dev);
1505         unsigned long flags;
1506
1507         DBGINFO(("%s hdlc_xmit\n", dev->name));
1508
1509         /* stop sending until this frame completes */
1510         netif_stop_queue(dev);
1511
1512         /* copy data to device buffers */
1513         info->tx_count = skb->len;
1514         tx_load(info, skb->data, skb->len);
1515
1516         /* update network statistics */
1517         dev->stats.tx_packets++;
1518         dev->stats.tx_bytes += skb->len;
1519
1520         /* done with socket buffer, so free it */
1521         dev_kfree_skb(skb);
1522
1523         /* save start time for transmit timeout detection */
1524         dev->trans_start = jiffies;
1525
1526         spin_lock_irqsave(&info->lock,flags);
1527         tx_start(info);
1528         update_tx_timer(info);
1529         spin_unlock_irqrestore(&info->lock,flags);
1530
1531         return NETDEV_TX_OK;
1532 }
1533
1534 /**
1535  * called by network layer when interface enabled
1536  * claim resources and initialize hardware
1537  *
1538  * dev  pointer to network device structure
1539  *
1540  * returns 0 if success, otherwise error code
1541  */
1542 static int hdlcdev_open(struct net_device *dev)
1543 {
1544         struct slgt_info *info = dev_to_port(dev);
1545         int rc;
1546         unsigned long flags;
1547
1548         if (!try_module_get(THIS_MODULE))
1549                 return -EBUSY;
1550
1551         DBGINFO(("%s hdlcdev_open\n", dev->name));
1552
1553         /* generic HDLC layer open processing */
1554         if ((rc = hdlc_open(dev)))
1555                 return rc;
1556
1557         /* arbitrate between network and tty opens */
1558         spin_lock_irqsave(&info->netlock, flags);
1559         if (info->port.count != 0 || info->netcount != 0) {
1560                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1561                 spin_unlock_irqrestore(&info->netlock, flags);
1562                 return -EBUSY;
1563         }
1564         info->netcount=1;
1565         spin_unlock_irqrestore(&info->netlock, flags);
1566
1567         /* claim resources and init adapter */
1568         if ((rc = startup(info)) != 0) {
1569                 spin_lock_irqsave(&info->netlock, flags);
1570                 info->netcount=0;
1571                 spin_unlock_irqrestore(&info->netlock, flags);
1572                 return rc;
1573         }
1574
1575         /* assert DTR and RTS, apply hardware settings */
1576         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1577         program_hw(info);
1578
1579         /* enable network layer transmit */
1580         dev->trans_start = jiffies;
1581         netif_start_queue(dev);
1582
1583         /* inform generic HDLC layer of current DCD status */
1584         spin_lock_irqsave(&info->lock, flags);
1585         get_signals(info);
1586         spin_unlock_irqrestore(&info->lock, flags);
1587         if (info->signals & SerialSignal_DCD)
1588                 netif_carrier_on(dev);
1589         else
1590                 netif_carrier_off(dev);
1591         return 0;
1592 }
1593
1594 /**
1595  * called by network layer when interface is disabled
1596  * shutdown hardware and release resources
1597  *
1598  * dev  pointer to network device structure
1599  *
1600  * returns 0 if success, otherwise error code
1601  */
1602 static int hdlcdev_close(struct net_device *dev)
1603 {
1604         struct slgt_info *info = dev_to_port(dev);
1605         unsigned long flags;
1606
1607         DBGINFO(("%s hdlcdev_close\n", dev->name));
1608
1609         netif_stop_queue(dev);
1610
1611         /* shutdown adapter and release resources */
1612         shutdown(info);
1613
1614         hdlc_close(dev);
1615
1616         spin_lock_irqsave(&info->netlock, flags);
1617         info->netcount=0;
1618         spin_unlock_irqrestore(&info->netlock, flags);
1619
1620         module_put(THIS_MODULE);
1621         return 0;
1622 }
1623
1624 /**
1625  * called by network layer to process IOCTL call to network device
1626  *
1627  * dev  pointer to network device structure
1628  * ifr  pointer to network interface request structure
1629  * cmd  IOCTL command code
1630  *
1631  * returns 0 if success, otherwise error code
1632  */
1633 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1634 {
1635         const size_t size = sizeof(sync_serial_settings);
1636         sync_serial_settings new_line;
1637         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1638         struct slgt_info *info = dev_to_port(dev);
1639         unsigned int flags;
1640
1641         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1642
1643         /* return error if TTY interface open */
1644         if (info->port.count)
1645                 return -EBUSY;
1646
1647         if (cmd != SIOCWANDEV)
1648                 return hdlc_ioctl(dev, ifr, cmd);
1649
1650         switch(ifr->ifr_settings.type) {
1651         case IF_GET_IFACE: /* return current sync_serial_settings */
1652
1653                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1654                 if (ifr->ifr_settings.size < size) {
1655                         ifr->ifr_settings.size = size; /* data size wanted */
1656                         return -ENOBUFS;
1657                 }
1658
1659                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1660                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1661                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1662                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1663
1664                 switch (flags){
1665                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1666                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1667                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1668                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1669                 default: new_line.clock_type = CLOCK_DEFAULT;
1670                 }
1671
1672                 new_line.clock_rate = info->params.clock_speed;
1673                 new_line.loopback   = info->params.loopback ? 1:0;
1674
1675                 if (copy_to_user(line, &new_line, size))
1676                         return -EFAULT;
1677                 return 0;
1678
1679         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1680
1681                 if(!capable(CAP_NET_ADMIN))
1682                         return -EPERM;
1683                 if (copy_from_user(&new_line, line, size))
1684                         return -EFAULT;
1685
1686                 switch (new_line.clock_type)
1687                 {
1688                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1689                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1690                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1691                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1692                 case CLOCK_DEFAULT:  flags = info->params.flags &
1693                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1694                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1695                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1696                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1697                 default: return -EINVAL;
1698                 }
1699
1700                 if (new_line.loopback != 0 && new_line.loopback != 1)
1701                         return -EINVAL;
1702
1703                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1704                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1705                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1706                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1707                 info->params.flags |= flags;
1708
1709                 info->params.loopback = new_line.loopback;
1710
1711                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1712                         info->params.clock_speed = new_line.clock_rate;
1713                 else
1714                         info->params.clock_speed = 0;
1715
1716                 /* if network interface up, reprogram hardware */
1717                 if (info->netcount)
1718                         program_hw(info);
1719                 return 0;
1720
1721         default:
1722                 return hdlc_ioctl(dev, ifr, cmd);
1723         }
1724 }
1725
1726 /**
1727  * called by network layer when transmit timeout is detected
1728  *
1729  * dev  pointer to network device structure
1730  */
1731 static void hdlcdev_tx_timeout(struct net_device *dev)
1732 {
1733         struct slgt_info *info = dev_to_port(dev);
1734         unsigned long flags;
1735
1736         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1737
1738         dev->stats.tx_errors++;
1739         dev->stats.tx_aborted_errors++;
1740
1741         spin_lock_irqsave(&info->lock,flags);
1742         tx_stop(info);
1743         spin_unlock_irqrestore(&info->lock,flags);
1744
1745         netif_wake_queue(dev);
1746 }
1747
1748 /**
1749  * called by device driver when transmit completes
1750  * reenable network layer transmit if stopped
1751  *
1752  * info  pointer to device instance information
1753  */
1754 static void hdlcdev_tx_done(struct slgt_info *info)
1755 {
1756         if (netif_queue_stopped(info->netdev))
1757                 netif_wake_queue(info->netdev);
1758 }
1759
1760 /**
1761  * called by device driver when frame received
1762  * pass frame to network layer
1763  *
1764  * info  pointer to device instance information
1765  * buf   pointer to buffer contianing frame data
1766  * size  count of data bytes in buf
1767  */
1768 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1769 {
1770         struct sk_buff *skb = dev_alloc_skb(size);
1771         struct net_device *dev = info->netdev;
1772
1773         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1774
1775         if (skb == NULL) {
1776                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1777                 dev->stats.rx_dropped++;
1778                 return;
1779         }
1780
1781         memcpy(skb_put(skb, size), buf, size);
1782
1783         skb->protocol = hdlc_type_trans(skb, dev);
1784
1785         dev->stats.rx_packets++;
1786         dev->stats.rx_bytes += size;
1787
1788         netif_rx(skb);
1789 }
1790
1791 static const struct net_device_ops hdlcdev_ops = {
1792         .ndo_open       = hdlcdev_open,
1793         .ndo_stop       = hdlcdev_close,
1794         .ndo_change_mtu = hdlc_change_mtu,
1795         .ndo_start_xmit = hdlc_start_xmit,
1796         .ndo_do_ioctl   = hdlcdev_ioctl,
1797         .ndo_tx_timeout = hdlcdev_tx_timeout,
1798 };
1799
1800 /**
1801  * called by device driver when adding device instance
1802  * do generic HDLC initialization
1803  *
1804  * info  pointer to device instance information
1805  *
1806  * returns 0 if success, otherwise error code
1807  */
1808 static int hdlcdev_init(struct slgt_info *info)
1809 {
1810         int rc;
1811         struct net_device *dev;
1812         hdlc_device *hdlc;
1813
1814         /* allocate and initialize network and HDLC layer objects */
1815
1816         if (!(dev = alloc_hdlcdev(info))) {
1817                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1818                 return -ENOMEM;
1819         }
1820
1821         /* for network layer reporting purposes only */
1822         dev->mem_start = info->phys_reg_addr;
1823         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1824         dev->irq       = info->irq_level;
1825
1826         /* network layer callbacks and settings */
1827         dev->netdev_ops     = &hdlcdev_ops;
1828         dev->watchdog_timeo = 10 * HZ;
1829         dev->tx_queue_len   = 50;
1830
1831         /* generic HDLC layer callbacks and settings */
1832         hdlc         = dev_to_hdlc(dev);
1833         hdlc->attach = hdlcdev_attach;
1834         hdlc->xmit   = hdlcdev_xmit;
1835
1836         /* register objects with HDLC layer */
1837         if ((rc = register_hdlc_device(dev))) {
1838                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1839                 free_netdev(dev);
1840                 return rc;
1841         }
1842
1843         info->netdev = dev;
1844         return 0;
1845 }
1846
1847 /**
1848  * called by device driver when removing device instance
1849  * do generic HDLC cleanup
1850  *
1851  * info  pointer to device instance information
1852  */
1853 static void hdlcdev_exit(struct slgt_info *info)
1854 {
1855         unregister_hdlc_device(info->netdev);
1856         free_netdev(info->netdev);
1857         info->netdev = NULL;
1858 }
1859
1860 #endif /* ifdef CONFIG_HDLC */
1861
1862 /*
1863  * get async data from rx DMA buffers
1864  */
1865 static void rx_async(struct slgt_info *info)
1866 {
1867         struct tty_struct *tty = info->port.tty;
1868         struct mgsl_icount *icount = &info->icount;
1869         unsigned int start, end;
1870         unsigned char *p;
1871         unsigned char status;
1872         struct slgt_desc *bufs = info->rbufs;
1873         int i, count;
1874         int chars = 0;
1875         int stat;
1876         unsigned char ch;
1877
1878         start = end = info->rbuf_current;
1879
1880         while(desc_complete(bufs[end])) {
1881                 count = desc_count(bufs[end]) - info->rbuf_index;
1882                 p     = bufs[end].buf + info->rbuf_index;
1883
1884                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1885                 DBGDATA(info, p, count, "rx");
1886
1887                 for(i=0 ; i < count; i+=2, p+=2) {
1888                         ch = *p;
1889                         icount->rx++;
1890
1891                         stat = 0;
1892
1893                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1894                                 if (status & BIT1)
1895                                         icount->parity++;
1896                                 else if (status & BIT0)
1897                                         icount->frame++;
1898                                 /* discard char if tty control flags say so */
1899                                 if (status & info->ignore_status_mask)
1900                                         continue;
1901                                 if (status & BIT1)
1902                                         stat = TTY_PARITY;
1903                                 else if (status & BIT0)
1904                                         stat = TTY_FRAME;
1905                         }
1906                         if (tty) {
1907                                 tty_insert_flip_char(tty, ch, stat);
1908                                 chars++;
1909                         }
1910                 }
1911
1912                 if (i < count) {
1913                         /* receive buffer not completed */
1914                         info->rbuf_index += i;
1915                         mod_timer(&info->rx_timer, jiffies + 1);
1916                         break;
1917                 }
1918
1919                 info->rbuf_index = 0;
1920                 free_rbufs(info, end, end);
1921
1922                 if (++end == info->rbuf_count)
1923                         end = 0;
1924
1925                 /* if entire list searched then no frame available */
1926                 if (end == start)
1927                         break;
1928         }
1929
1930         if (tty && chars)
1931                 tty_flip_buffer_push(tty);
1932 }
1933
1934 /*
1935  * return next bottom half action to perform
1936  */
1937 static int bh_action(struct slgt_info *info)
1938 {
1939         unsigned long flags;
1940         int rc;
1941
1942         spin_lock_irqsave(&info->lock,flags);
1943
1944         if (info->pending_bh & BH_RECEIVE) {
1945                 info->pending_bh &= ~BH_RECEIVE;
1946                 rc = BH_RECEIVE;
1947         } else if (info->pending_bh & BH_TRANSMIT) {
1948                 info->pending_bh &= ~BH_TRANSMIT;
1949                 rc = BH_TRANSMIT;
1950         } else if (info->pending_bh & BH_STATUS) {
1951                 info->pending_bh &= ~BH_STATUS;
1952                 rc = BH_STATUS;
1953         } else {
1954                 /* Mark BH routine as complete */
1955                 info->bh_running = false;
1956                 info->bh_requested = false;
1957                 rc = 0;
1958         }
1959
1960         spin_unlock_irqrestore(&info->lock,flags);
1961
1962         return rc;
1963 }
1964
1965 /*
1966  * perform bottom half processing
1967  */
1968 static void bh_handler(struct work_struct *work)
1969 {
1970         struct slgt_info *info = container_of(work, struct slgt_info, task);
1971         int action;
1972
1973         if (!info)
1974                 return;
1975         info->bh_running = true;
1976
1977         while((action = bh_action(info))) {
1978                 switch (action) {
1979                 case BH_RECEIVE:
1980                         DBGBH(("%s bh receive\n", info->device_name));
1981                         switch(info->params.mode) {
1982                         case MGSL_MODE_ASYNC:
1983                                 rx_async(info);
1984                                 break;
1985                         case MGSL_MODE_HDLC:
1986                                 while(rx_get_frame(info));
1987                                 break;
1988                         case MGSL_MODE_RAW:
1989                         case MGSL_MODE_MONOSYNC:
1990                         case MGSL_MODE_BISYNC:
1991                                 while(rx_get_buf(info));
1992                                 break;
1993                         }
1994                         /* restart receiver if rx DMA buffers exhausted */
1995                         if (info->rx_restart)
1996                                 rx_start(info);
1997                         break;
1998                 case BH_TRANSMIT:
1999                         bh_transmit(info);
2000                         break;
2001                 case BH_STATUS:
2002                         DBGBH(("%s bh status\n", info->device_name));
2003                         info->ri_chkcount = 0;
2004                         info->dsr_chkcount = 0;
2005                         info->dcd_chkcount = 0;
2006                         info->cts_chkcount = 0;
2007                         break;
2008                 default:
2009                         DBGBH(("%s unknown action\n", info->device_name));
2010                         break;
2011                 }
2012         }
2013         DBGBH(("%s bh_handler exit\n", info->device_name));
2014 }
2015
2016 static void bh_transmit(struct slgt_info *info)
2017 {
2018         struct tty_struct *tty = info->port.tty;
2019
2020         DBGBH(("%s bh_transmit\n", info->device_name));
2021         if (tty)
2022                 tty_wakeup(tty);
2023 }
2024
2025 static void dsr_change(struct slgt_info *info, unsigned short status)
2026 {
2027         if (status & BIT3) {
2028                 info->signals |= SerialSignal_DSR;
2029                 info->input_signal_events.dsr_up++;
2030         } else {
2031                 info->signals &= ~SerialSignal_DSR;
2032                 info->input_signal_events.dsr_down++;
2033         }
2034         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2035         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2036                 slgt_irq_off(info, IRQ_DSR);
2037                 return;
2038         }
2039         info->icount.dsr++;
2040         wake_up_interruptible(&info->status_event_wait_q);
2041         wake_up_interruptible(&info->event_wait_q);
2042         info->pending_bh |= BH_STATUS;
2043 }
2044
2045 static void cts_change(struct slgt_info *info, unsigned short status)
2046 {
2047         if (status & BIT2) {
2048                 info->signals |= SerialSignal_CTS;
2049                 info->input_signal_events.cts_up++;
2050         } else {
2051                 info->signals &= ~SerialSignal_CTS;
2052                 info->input_signal_events.cts_down++;
2053         }
2054         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2055         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2056                 slgt_irq_off(info, IRQ_CTS);
2057                 return;
2058         }
2059         info->icount.cts++;
2060         wake_up_interruptible(&info->status_event_wait_q);
2061         wake_up_interruptible(&info->event_wait_q);
2062         info->pending_bh |= BH_STATUS;
2063
2064         if (info->port.flags & ASYNC_CTS_FLOW) {
2065                 if (info->port.tty) {
2066                         if (info->port.tty->hw_stopped) {
2067                                 if (info->signals & SerialSignal_CTS) {
2068                                         info->port.tty->hw_stopped = 0;
2069                                         info->pending_bh |= BH_TRANSMIT;
2070                                         return;
2071                                 }
2072                         } else {
2073                                 if (!(info->signals & SerialSignal_CTS))
2074                                         info->port.tty->hw_stopped = 1;
2075                         }
2076                 }
2077         }
2078 }
2079
2080 static void dcd_change(struct slgt_info *info, unsigned short status)
2081 {
2082         if (status & BIT1) {
2083                 info->signals |= SerialSignal_DCD;
2084                 info->input_signal_events.dcd_up++;
2085         } else {
2086                 info->signals &= ~SerialSignal_DCD;
2087                 info->input_signal_events.dcd_down++;
2088         }
2089         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2090         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2091                 slgt_irq_off(info, IRQ_DCD);
2092                 return;
2093         }
2094         info->icount.dcd++;
2095 #if SYNCLINK_GENERIC_HDLC
2096         if (info->netcount) {
2097                 if (info->signals & SerialSignal_DCD)
2098                         netif_carrier_on(info->netdev);
2099                 else
2100                         netif_carrier_off(info->netdev);
2101         }
2102 #endif
2103         wake_up_interruptible(&info->status_event_wait_q);
2104         wake_up_interruptible(&info->event_wait_q);
2105         info->pending_bh |= BH_STATUS;
2106
2107         if (info->port.flags & ASYNC_CHECK_CD) {
2108                 if (info->signals & SerialSignal_DCD)
2109                         wake_up_interruptible(&info->port.open_wait);
2110                 else {
2111                         if (info->port.tty)
2112                                 tty_hangup(info->port.tty);
2113                 }
2114         }
2115 }
2116
2117 static void ri_change(struct slgt_info *info, unsigned short status)
2118 {
2119         if (status & BIT0) {
2120                 info->signals |= SerialSignal_RI;
2121                 info->input_signal_events.ri_up++;
2122         } else {
2123                 info->signals &= ~SerialSignal_RI;
2124                 info->input_signal_events.ri_down++;
2125         }
2126         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2127         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2128                 slgt_irq_off(info, IRQ_RI);
2129                 return;
2130         }
2131         info->icount.rng++;
2132         wake_up_interruptible(&info->status_event_wait_q);
2133         wake_up_interruptible(&info->event_wait_q);
2134         info->pending_bh |= BH_STATUS;
2135 }
2136
2137 static void isr_rxdata(struct slgt_info *info)
2138 {
2139         unsigned int count = info->rbuf_fill_count;
2140         unsigned int i = info->rbuf_fill_index;
2141         unsigned short reg;
2142
2143         while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2144                 reg = rd_reg16(info, RDR);
2145                 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2146                 if (desc_complete(info->rbufs[i])) {
2147                         /* all buffers full */
2148                         rx_stop(info);
2149                         info->rx_restart = 1;
2150                         continue;
2151                 }
2152                 info->rbufs[i].buf[count++] = (unsigned char)reg;
2153                 /* async mode saves status byte to buffer for each data byte */
2154                 if (info->params.mode == MGSL_MODE_ASYNC)
2155                         info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2156                 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2157                         /* buffer full or end of frame */
2158                         set_desc_count(info->rbufs[i], count);
2159                         set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2160                         info->rbuf_fill_count = count = 0;
2161                         if (++i == info->rbuf_count)
2162                                 i = 0;
2163                         info->pending_bh |= BH_RECEIVE;
2164                 }
2165         }
2166
2167         info->rbuf_fill_index = i;
2168         info->rbuf_fill_count = count;
2169 }
2170
2171 static void isr_serial(struct slgt_info *info)
2172 {
2173         unsigned short status = rd_reg16(info, SSR);
2174
2175         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2176
2177         wr_reg16(info, SSR, status); /* clear pending */
2178
2179         info->irq_occurred = true;
2180
2181         if (info->params.mode == MGSL_MODE_ASYNC) {
2182                 if (status & IRQ_TXIDLE) {
2183                         if (info->tx_count)
2184                                 isr_txeom(info, status);
2185                 }
2186                 if (info->rx_pio && (status & IRQ_RXDATA))
2187                         isr_rxdata(info);
2188                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2189                         info->icount.brk++;
2190                         /* process break detection if tty control allows */
2191                         if (info->port.tty) {
2192                                 if (!(status & info->ignore_status_mask)) {
2193                                         if (info->read_status_mask & MASK_BREAK) {
2194                                                 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2195                                                 if (info->port.flags & ASYNC_SAK)
2196                                                         do_SAK(info->port.tty);
2197                                         }
2198                                 }
2199                         }
2200                 }
2201         } else {
2202                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2203                         isr_txeom(info, status);
2204                 if (info->rx_pio && (status & IRQ_RXDATA))
2205                         isr_rxdata(info);
2206                 if (status & IRQ_RXIDLE) {
2207                         if (status & RXIDLE)
2208                                 info->icount.rxidle++;
2209                         else
2210                                 info->icount.exithunt++;
2211                         wake_up_interruptible(&info->event_wait_q);
2212                 }
2213
2214                 if (status & IRQ_RXOVER)
2215                         rx_start(info);
2216         }
2217
2218         if (status & IRQ_DSR)
2219                 dsr_change(info, status);
2220         if (status & IRQ_CTS)
2221                 cts_change(info, status);
2222         if (status & IRQ_DCD)
2223                 dcd_change(info, status);
2224         if (status & IRQ_RI)
2225                 ri_change(info, status);
2226 }
2227
2228 static void isr_rdma(struct slgt_info *info)
2229 {
2230         unsigned int status = rd_reg32(info, RDCSR);
2231
2232         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2233
2234         /* RDCSR (rx DMA control/status)
2235          *
2236          * 31..07  reserved
2237          * 06      save status byte to DMA buffer
2238          * 05      error
2239          * 04      eol (end of list)
2240          * 03      eob (end of buffer)
2241          * 02      IRQ enable
2242          * 01      reset
2243          * 00      enable
2244          */
2245         wr_reg32(info, RDCSR, status);  /* clear pending */
2246
2247         if (status & (BIT5 + BIT4)) {
2248                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2249                 info->rx_restart = true;
2250         }
2251         info->pending_bh |= BH_RECEIVE;
2252 }
2253
2254 static void isr_tdma(struct slgt_info *info)
2255 {
2256         unsigned int status = rd_reg32(info, TDCSR);
2257
2258         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2259
2260         /* TDCSR (tx DMA control/status)
2261          *
2262          * 31..06  reserved
2263          * 05      error
2264          * 04      eol (end of list)
2265          * 03      eob (end of buffer)
2266          * 02      IRQ enable
2267          * 01      reset
2268          * 00      enable
2269          */
2270         wr_reg32(info, TDCSR, status);  /* clear pending */
2271
2272         if (status & (BIT5 + BIT4 + BIT3)) {
2273                 // another transmit buffer has completed
2274                 // run bottom half to get more send data from user
2275                 info->pending_bh |= BH_TRANSMIT;
2276         }
2277 }
2278
2279 static void isr_txeom(struct slgt_info *info, unsigned short status)
2280 {
2281         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2282
2283         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2284         tdma_reset(info);
2285         reset_tbufs(info);
2286         if (status & IRQ_TXUNDER) {
2287                 unsigned short val = rd_reg16(info, TCR);
2288                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2289                 wr_reg16(info, TCR, val); /* clear reset bit */
2290         }
2291
2292         if (info->tx_active) {
2293                 if (info->params.mode != MGSL_MODE_ASYNC) {
2294                         if (status & IRQ_TXUNDER)
2295                                 info->icount.txunder++;
2296                         else if (status & IRQ_TXIDLE)
2297                                 info->icount.txok++;
2298                 }
2299
2300                 info->tx_active = false;
2301                 info->tx_count = 0;
2302
2303                 del_timer(&info->tx_timer);
2304
2305                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2306                         info->signals &= ~SerialSignal_RTS;
2307                         info->drop_rts_on_tx_done = false;
2308                         set_signals(info);
2309                 }
2310
2311 #if SYNCLINK_GENERIC_HDLC
2312                 if (info->netcount)
2313                         hdlcdev_tx_done(info);
2314                 else
2315 #endif
2316                 {
2317                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2318                                 tx_stop(info);
2319                                 return;
2320                         }
2321                         info->pending_bh |= BH_TRANSMIT;
2322                 }
2323         }
2324 }
2325
2326 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2327 {
2328         struct cond_wait *w, *prev;
2329
2330         /* wake processes waiting for specific transitions */
2331         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2332                 if (w->data & changed) {
2333                         w->data = state;
2334                         wake_up_interruptible(&w->q);
2335                         if (prev != NULL)
2336                                 prev->next = w->next;
2337                         else
2338                                 info->gpio_wait_q = w->next;
2339                 } else
2340                         prev = w;
2341         }
2342 }
2343
2344 /* interrupt service routine
2345  *
2346  *      irq     interrupt number
2347  *      dev_id  device ID supplied during interrupt registration
2348  */
2349 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2350 {
2351         struct slgt_info *info = dev_id;
2352         unsigned int gsr;
2353         unsigned int i;
2354
2355         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2356
2357         spin_lock(&info->lock);
2358
2359         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2360                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2361                 info->irq_occurred = true;
2362                 for(i=0; i < info->port_count ; i++) {
2363                         if (info->port_array[i] == NULL)
2364                                 continue;
2365                         if (gsr & (BIT8 << i))
2366                                 isr_serial(info->port_array[i]);
2367                         if (gsr & (BIT16 << (i*2)))
2368                                 isr_rdma(info->port_array[i]);
2369                         if (gsr & (BIT17 << (i*2)))
2370                                 isr_tdma(info->port_array[i]);
2371                 }
2372         }
2373
2374         if (info->gpio_present) {
2375                 unsigned int state;
2376                 unsigned int changed;
2377                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2378                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2379                         /* read latched state of GPIO signals */
2380                         state = rd_reg32(info, IOVR);
2381                         /* clear pending GPIO interrupt bits */
2382                         wr_reg32(info, IOSR, changed);
2383                         for (i=0 ; i < info->port_count ; i++) {
2384                                 if (info->port_array[i] != NULL)
2385                                         isr_gpio(info->port_array[i], changed, state);
2386                         }
2387                 }
2388         }
2389
2390         for(i=0; i < info->port_count ; i++) {
2391                 struct slgt_info *port = info->port_array[i];
2392
2393                 if (port && (port->port.count || port->netcount) &&
2394                     port->pending_bh && !port->bh_running &&
2395                     !port->bh_requested) {
2396                         DBGISR(("%s bh queued\n", port->device_name));
2397                         schedule_work(&port->task);
2398                         port->bh_requested = true;
2399                 }
2400         }
2401
2402         spin_unlock(&info->lock);
2403
2404         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2405         return IRQ_HANDLED;
2406 }
2407
2408 static int startup(struct slgt_info *info)
2409 {
2410         DBGINFO(("%s startup\n", info->device_name));
2411
2412         if (info->port.flags & ASYNC_INITIALIZED)
2413                 return 0;
2414
2415         if (!info->tx_buf) {
2416                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2417                 if (!info->tx_buf) {
2418                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2419                         return -ENOMEM;
2420                 }
2421         }
2422
2423         info->pending_bh = 0;
2424
2425         memset(&info->icount, 0, sizeof(info->icount));
2426
2427         /* program hardware for current parameters */
2428         change_params(info);
2429
2430         if (info->port.tty)
2431                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2432
2433         info->port.flags |= ASYNC_INITIALIZED;
2434
2435         return 0;
2436 }
2437
2438 /*
2439  *  called by close() and hangup() to shutdown hardware
2440  */
2441 static void shutdown(struct slgt_info *info)
2442 {
2443         unsigned long flags;
2444
2445         if (!(info->port.flags & ASYNC_INITIALIZED))
2446                 return;
2447
2448         DBGINFO(("%s shutdown\n", info->device_name));
2449
2450         /* clear status wait queue because status changes */
2451         /* can't happen after shutting down the hardware */
2452         wake_up_interruptible(&info->status_event_wait_q);
2453         wake_up_interruptible(&info->event_wait_q);
2454
2455         del_timer_sync(&info->tx_timer);
2456         del_timer_sync(&info->rx_timer);
2457
2458         kfree(info->tx_buf);
2459         info->tx_buf = NULL;
2460
2461         spin_lock_irqsave(&info->lock,flags);
2462
2463         tx_stop(info);
2464         rx_stop(info);
2465
2466         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2467
2468         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2469                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2470                 set_signals(info);
2471         }
2472
2473         flush_cond_wait(&info->gpio_wait_q);
2474
2475         spin_unlock_irqrestore(&info->lock,flags);
2476
2477         if (info->port.tty)
2478                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2479
2480         info->port.flags &= ~ASYNC_INITIALIZED;
2481 }
2482
2483 static void program_hw(struct slgt_info *info)
2484 {
2485         unsigned long flags;
2486
2487         spin_lock_irqsave(&info->lock,flags);
2488
2489         rx_stop(info);
2490         tx_stop(info);
2491
2492         if (info->params.mode != MGSL_MODE_ASYNC ||
2493             info->netcount)
2494                 sync_mode(info);
2495         else
2496                 async_mode(info);
2497
2498         set_signals(info);
2499
2500         info->dcd_chkcount = 0;
2501         info->cts_chkcount = 0;
2502         info->ri_chkcount = 0;
2503         info->dsr_chkcount = 0;
2504
2505         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2506         get_signals(info);
2507
2508         if (info->netcount ||
2509             (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2510                 rx_start(info);
2511
2512         spin_unlock_irqrestore(&info->lock,flags);
2513 }
2514
2515 /*
2516  * reconfigure adapter based on new parameters
2517  */
2518 static void change_params(struct slgt_info *info)
2519 {
2520         unsigned cflag;
2521         int bits_per_char;
2522
2523         if (!info->port.tty || !info->port.tty->termios)
2524                 return;
2525         DBGINFO(("%s change_params\n", info->device_name));
2526
2527         cflag = info->port.tty->termios->c_cflag;
2528
2529         /* if B0 rate (hangup) specified then negate DTR and RTS */
2530         /* otherwise assert DTR and RTS */
2531         if (cflag & CBAUD)
2532                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2533         else
2534                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2535
2536         /* byte size and parity */
2537
2538         switch (cflag & CSIZE) {
2539         case CS5: info->params.data_bits = 5; break;
2540         case CS6: info->params.data_bits = 6; break;
2541         case CS7: info->params.data_bits = 7; break;
2542         case CS8: info->params.data_bits = 8; break;
2543         default:  info->params.data_bits = 7; break;
2544         }
2545
2546         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2547
2548         if (cflag & PARENB)
2549                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2550         else
2551                 info->params.parity = ASYNC_PARITY_NONE;
2552
2553         /* calculate number of jiffies to transmit a full
2554          * FIFO (32 bytes) at specified data rate
2555          */
2556         bits_per_char = info->params.data_bits +
2557                         info->params.stop_bits + 1;
2558
2559         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2560
2561         if (info->params.data_rate) {
2562                 info->timeout = (32*HZ*bits_per_char) /
2563                                 info->params.data_rate;
2564         }
2565         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2566
2567         if (cflag & CRTSCTS)
2568                 info->port.flags |= ASYNC_CTS_FLOW;
2569         else
2570                 info->port.flags &= ~ASYNC_CTS_FLOW;
2571
2572         if (cflag & CLOCAL)
2573                 info->port.flags &= ~ASYNC_CHECK_CD;
2574         else
2575                 info->port.flags |= ASYNC_CHECK_CD;
2576
2577         /* process tty input control flags */
2578
2579         info->read_status_mask = IRQ_RXOVER;
2580         if (I_INPCK(info->port.tty))
2581                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2582         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2583                 info->read_status_mask |= MASK_BREAK;
2584         if (I_IGNPAR(info->port.tty))
2585                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2586         if (I_IGNBRK(info->port.tty)) {
2587                 info->ignore_status_mask |= MASK_BREAK;
2588                 /* If ignoring parity and break indicators, ignore
2589                  * overruns too.  (For real raw support).
2590                  */
2591                 if (I_IGNPAR(info->port.tty))
2592                         info->ignore_status_mask |= MASK_OVERRUN;
2593         }
2594
2595         program_hw(info);
2596 }
2597
2598 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2599 {
2600         DBGINFO(("%s get_stats\n",  info->device_name));
2601         if (!user_icount) {
2602                 memset(&info->icount, 0, sizeof(info->icount));
2603         } else {
2604                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2605                         return -EFAULT;
2606         }
2607         return 0;
2608 }
2609
2610 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2611 {
2612         DBGINFO(("%s get_params\n", info->device_name));
2613         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2614                 return -EFAULT;
2615         return 0;
2616 }
2617
2618 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2619 {
2620         unsigned long flags;
2621         MGSL_PARAMS tmp_params;
2622
2623         DBGINFO(("%s set_params\n", info->device_name));
2624         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2625                 return -EFAULT;
2626
2627         spin_lock_irqsave(&info->lock, flags);
2628         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2629                 info->base_clock = tmp_params.clock_speed;
2630         else
2631                 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2632         spin_unlock_irqrestore(&info->lock, flags);
2633
2634         program_hw(info);
2635
2636         return 0;
2637 }
2638
2639 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2640 {
2641         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2642         if (put_user(info->idle_mode, idle_mode))
2643                 return -EFAULT;
2644         return 0;
2645 }
2646
2647 static int set_txidle(struct slgt_info *info, int idle_mode)
2648 {
2649         unsigned long flags;
2650         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2651         spin_lock_irqsave(&info->lock,flags);
2652         info->idle_mode = idle_mode;
2653         if (info->params.mode != MGSL_MODE_ASYNC)
2654                 tx_set_idle(info);
2655         spin_unlock_irqrestore(&info->lock,flags);
2656         return 0;
2657 }
2658
2659 static int tx_enable(struct slgt_info *info, int enable)
2660 {
2661         unsigned long flags;
2662         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2663         spin_lock_irqsave(&info->lock,flags);
2664         if (enable) {
2665                 if (!info->tx_enabled)
2666                         tx_start(info);
2667         } else {
2668                 if (info->tx_enabled)
2669                         tx_stop(info);
2670         }
2671         spin_unlock_irqrestore(&info->lock,flags);
2672         return 0;
2673 }
2674
2675 /*
2676  * abort transmit HDLC frame
2677  */
2678 static int tx_abort(struct slgt_info *info)
2679 {
2680         unsigned long flags;
2681         DBGINFO(("%s tx_abort\n", info->device_name));
2682         spin_lock_irqsave(&info->lock,flags);
2683         tdma_reset(info);
2684         spin_unlock_irqrestore(&info->lock,flags);
2685         return 0;
2686 }
2687
2688 static int rx_enable(struct slgt_info *info, int enable)
2689 {
2690         unsigned long flags;
2691         unsigned int rbuf_fill_level;
2692         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2693         spin_lock_irqsave(&info->lock,flags);
2694         /*
2695          * enable[31..16] = receive DMA buffer fill level
2696          * 0 = noop (leave fill level unchanged)
2697          * fill level must be multiple of 4 and <= buffer size
2698          */
2699         rbuf_fill_level = ((unsigned int)enable) >> 16;
2700         if (rbuf_fill_level) {
2701                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2702                         spin_unlock_irqrestore(&info->lock, flags);
2703                         return -EINVAL;
2704                 }
2705                 info->rbuf_fill_level = rbuf_fill_level;
2706                 if (rbuf_fill_level < 128)
2707                         info->rx_pio = 1; /* PIO mode */
2708                 else
2709                         info->rx_pio = 0; /* DMA mode */
2710                 rx_stop(info); /* restart receiver to use new fill level */
2711         }
2712
2713         /*
2714          * enable[1..0] = receiver enable command
2715          * 0 = disable
2716          * 1 = enable
2717          * 2 = enable or force hunt mode if already enabled
2718          */
2719         enable &= 3;
2720         if (enable) {
2721                 if (!info->rx_enabled)
2722                         rx_start(info);
2723                 else if (enable == 2) {
2724                         /* force hunt mode (write 1 to RCR[3]) */
2725                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2726                 }
2727         } else {
2728                 if (info->rx_enabled)
2729                         rx_stop(info);
2730         }
2731         spin_unlock_irqrestore(&info->lock,flags);
2732         return 0;
2733 }
2734
2735 /*
2736  *  wait for specified event to occur
2737  */
2738 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2739 {
2740         unsigned long flags;
2741         int s;
2742         int rc=0;
2743         struct mgsl_icount cprev, cnow;
2744         int events;
2745         int mask;
2746         struct  _input_signal_events oldsigs, newsigs;
2747         DECLARE_WAITQUEUE(wait, current);
2748
2749         if (get_user(mask, mask_ptr))
2750                 return -EFAULT;
2751
2752         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2753
2754         spin_lock_irqsave(&info->lock,flags);
2755
2756         /* return immediately if state matches requested events */
2757         get_signals(info);
2758         s = info->signals;
2759
2760         events = mask &
2761                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2762                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2763                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2764                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2765         if (events) {
2766                 spin_unlock_irqrestore(&info->lock,flags);
2767                 goto exit;
2768         }
2769
2770         /* save current irq counts */
2771         cprev = info->icount;
2772         oldsigs = info->input_signal_events;
2773
2774         /* enable hunt and idle irqs if needed */
2775         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2776                 unsigned short val = rd_reg16(info, SCR);
2777                 if (!(val & IRQ_RXIDLE))
2778                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2779         }
2780
2781         set_current_state(TASK_INTERRUPTIBLE);
2782         add_wait_queue(&info->event_wait_q, &wait);
2783
2784         spin_unlock_irqrestore(&info->lock,flags);
2785
2786         for(;;) {
2787                 schedule();
2788                 if (signal_pending(current)) {
2789                         rc = -ERESTARTSYS;
2790                         break;
2791                 }
2792
2793                 /* get current irq counts */
2794                 spin_lock_irqsave(&info->lock,flags);
2795                 cnow = info->icount;
2796                 newsigs = info->input_signal_events;
2797                 set_current_state(TASK_INTERRUPTIBLE);
2798                 spin_unlock_irqrestore(&info->lock,flags);
2799
2800                 /* if no change, wait aborted for some reason */
2801                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2802                     newsigs.dsr_down == oldsigs.dsr_down &&
2803                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2804                     newsigs.dcd_down == oldsigs.dcd_down &&
2805                     newsigs.cts_up   == oldsigs.cts_up   &&
2806                     newsigs.cts_down == oldsigs.cts_down &&
2807                     newsigs.ri_up    == oldsigs.ri_up    &&
2808                     newsigs.ri_down  == oldsigs.ri_down  &&
2809                     cnow.exithunt    == cprev.exithunt   &&
2810                     cnow.rxidle      == cprev.rxidle) {
2811                         rc = -EIO;
2812                         break;
2813                 }
2814
2815                 events = mask &
2816                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2817                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2818                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2819                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2820                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2821                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2822                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2823                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2824                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2825                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2826                 if (events)
2827                         break;
2828
2829                 cprev = cnow;
2830                 oldsigs = newsigs;
2831         }
2832
2833         remove_wait_queue(&info->event_wait_q, &wait);
2834         set_current_state(TASK_RUNNING);
2835
2836
2837         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2838                 spin_lock_irqsave(&info->lock,flags);
2839                 if (!waitqueue_active(&info->event_wait_q)) {
2840                         /* disable enable exit hunt mode/idle rcvd IRQs */
2841                         wr_reg16(info, SCR,
2842                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2843                 }
2844                 spin_unlock_irqrestore(&info->lock,flags);
2845         }
2846 exit:
2847         if (rc == 0)
2848                 rc = put_user(events, mask_ptr);
2849         return rc;
2850 }
2851
2852 static int get_interface(struct slgt_info *info, int __user *if_mode)
2853 {
2854         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2855         if (put_user(info->if_mode, if_mode))
2856                 return -EFAULT;
2857         return 0;
2858 }
2859
2860 static int set_interface(struct slgt_info *info, int if_mode)
2861 {
2862         unsigned long flags;
2863         unsigned short val;
2864
2865         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2866         spin_lock_irqsave(&info->lock,flags);
2867         info->if_mode = if_mode;
2868
2869         msc_set_vcr(info);
2870
2871         /* TCR (tx control) 07  1=RTS driver control */
2872         val = rd_reg16(info, TCR);
2873         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2874                 val |= BIT7;
2875         else
2876                 val &= ~BIT7;
2877         wr_reg16(info, TCR, val);
2878
2879         spin_unlock_irqrestore(&info->lock,flags);
2880         return 0;
2881 }
2882
2883 /*
2884  * set general purpose IO pin state and direction
2885  *
2886  * user_gpio fields:
2887  * state   each bit indicates a pin state
2888  * smask   set bit indicates pin state to set
2889  * dir     each bit indicates a pin direction (0=input, 1=output)
2890  * dmask   set bit indicates pin direction to set
2891  */
2892 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2893 {
2894         unsigned long flags;
2895         struct gpio_desc gpio;
2896         __u32 data;
2897
2898         if (!info->gpio_present)
2899                 return -EINVAL;
2900         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2901                 return -EFAULT;
2902         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2903                  info->device_name, gpio.state, gpio.smask,
2904                  gpio.dir, gpio.dmask));
2905
2906         spin_lock_irqsave(&info->lock,flags);
2907         if (gpio.dmask) {
2908                 data = rd_reg32(info, IODR);
2909                 data |= gpio.dmask & gpio.dir;
2910                 data &= ~(gpio.dmask & ~gpio.dir);
2911                 wr_reg32(info, IODR, data);
2912         }
2913         if (gpio.smask) {
2914                 data = rd_reg32(info, IOVR);
2915                 data |= gpio.smask & gpio.state;
2916                 data &= ~(gpio.smask & ~gpio.state);
2917                 wr_reg32(info, IOVR, data);
2918         }
2919         spin_unlock_irqrestore(&info->lock,flags);
2920
2921         return 0;
2922 }
2923
2924 /*
2925  * get general purpose IO pin state and direction
2926  */
2927 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2928 {
2929         struct gpio_desc gpio;
2930         if (!info->gpio_present)
2931                 return -EINVAL;
2932         gpio.state = rd_reg32(info, IOVR);
2933         gpio.smask = 0xffffffff;
2934         gpio.dir   = rd_reg32(info, IODR);
2935         gpio.dmask = 0xffffffff;
2936         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2937                 return -EFAULT;
2938         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2939                  info->device_name, gpio.state, gpio.dir));
2940         return 0;
2941 }
2942
2943 /*
2944  * conditional wait facility
2945  */
2946 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2947 {
2948         init_waitqueue_head(&w->q);
2949         init_waitqueue_entry(&w->wait, current);
2950         w->data = data;
2951 }
2952
2953 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2954 {
2955         set_current_state(TASK_INTERRUPTIBLE);
2956         add_wait_queue(&w->q, &w->wait);
2957         w->next = *head;
2958         *head = w;
2959 }
2960
2961 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2962 {
2963         struct cond_wait *w, *prev;
2964         remove_wait_queue(&cw->q, &cw->wait);
2965         set_current_state(TASK_RUNNING);
2966         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2967                 if (w == cw) {
2968                         if (prev != NULL)
2969                                 prev->next = w->next;
2970                         else
2971                                 *head = w->next;
2972                         break;
2973                 }
2974         }
2975 }
2976
2977 static void flush_cond_wait(struct cond_wait **head)
2978 {
2979         while (*head != NULL) {
2980                 wake_up_interruptible(&(*head)->q);
2981                 *head = (*head)->next;
2982         }
2983 }
2984
2985 /*
2986  * wait for general purpose I/O pin(s) to enter specified state
2987  *
2988  * user_gpio fields:
2989  * state - bit indicates target pin state
2990  * smask - set bit indicates watched pin
2991  *
2992  * The wait ends when at least one watched pin enters the specified
2993  * state. When 0 (no error) is returned, user_gpio->state is set to the
2994  * state of all GPIO pins when the wait ends.
2995  *
2996  * Note: Each pin may be a dedicated input, dedicated output, or
2997  * configurable input/output. The number and configuration of pins
2998  * varies with the specific adapter model. Only input pins (dedicated
2999  * or configured) can be monitored with this function.
3000  */
3001 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3002 {
3003         unsigned long flags;
3004         int rc = 0;
3005         struct gpio_desc gpio;
3006         struct cond_wait wait;
3007         u32 state;
3008
3009         if (!info->gpio_present)
3010                 return -EINVAL;
3011         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3012                 return -EFAULT;
3013         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3014                  info->device_name, gpio.state, gpio.smask));
3015         /* ignore output pins identified by set IODR bit */
3016         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3017                 return -EINVAL;
3018         init_cond_wait(&wait, gpio.smask);
3019
3020         spin_lock_irqsave(&info->lock, flags);
3021         /* enable interrupts for watched pins */
3022         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3023         /* get current pin states */
3024         state = rd_reg32(info, IOVR);
3025
3026         if (gpio.smask & ~(state ^ gpio.state)) {
3027                 /* already in target state */
3028                 gpio.state = state;
3029         } else {
3030                 /* wait for target state */
3031                 add_cond_wait(&info->gpio_wait_q, &wait);
3032                 spin_unlock_irqrestore(&info->lock, flags);
3033                 schedule();
3034                 if (signal_pending(current))
3035                         rc = -ERESTARTSYS;
3036                 else
3037                         gpio.state = wait.data;
3038                 spin_lock_irqsave(&info->lock, flags);
3039                 remove_cond_wait(&info->gpio_wait_q, &wait);
3040         }
3041
3042         /* disable all GPIO interrupts if no waiting processes */
3043         if (info->gpio_wait_q == NULL)
3044                 wr_reg32(info, IOER, 0);
3045         spin_unlock_irqrestore(&info->lock,flags);
3046
3047         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3048                 rc = -EFAULT;
3049         return rc;
3050 }
3051
3052 static int modem_input_wait(struct slgt_info *info,int arg)
3053 {
3054         unsigned long flags;
3055         int rc;
3056         struct mgsl_icount cprev, cnow;
3057         DECLARE_WAITQUEUE(wait, current);
3058
3059         /* save current irq counts */
3060         spin_lock_irqsave(&info->lock,flags);
3061         cprev = info->icount;
3062         add_wait_queue(&info->status_event_wait_q, &wait);
3063         set_current_state(TASK_INTERRUPTIBLE);
3064         spin_unlock_irqrestore(&info->lock,flags);
3065
3066         for(;;) {
3067                 schedule();
3068                 if (signal_pending(current)) {
3069                         rc = -ERESTARTSYS;
3070                         break;
3071                 }
3072
3073                 /* get new irq counts */
3074                 spin_lock_irqsave(&info->lock,flags);
3075                 cnow = info->icount;
3076                 set_current_state(TASK_INTERRUPTIBLE);
3077                 spin_unlock_irqrestore(&info->lock,flags);
3078
3079                 /* if no change, wait aborted for some reason */
3080                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3081                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3082                         rc = -EIO;
3083                         break;
3084                 }
3085
3086                 /* check for change in caller specified modem input */
3087                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3088                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3089                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3090                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3091                         rc = 0;
3092                         break;
3093                 }
3094
3095                 cprev = cnow;
3096         }
3097         remove_wait_queue(&info->status_event_wait_q, &wait);
3098         set_current_state(TASK_RUNNING);
3099         return rc;
3100 }
3101
3102 /*
3103  *  return state of serial control and status signals
3104  */
3105 static int tiocmget(struct tty_struct *tty, struct file *file)
3106 {
3107         struct slgt_info *info = tty->driver_data;
3108         unsigned int result;
3109         unsigned long flags;
3110
3111         spin_lock_irqsave(&info->lock,flags);
3112         get_signals(info);
3113         spin_unlock_irqrestore(&info->lock,flags);
3114
3115         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3116                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3117                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3118                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3119                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3120                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3121
3122         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3123         return result;
3124 }
3125
3126 /*
3127  * set modem control signals (DTR/RTS)
3128  *
3129  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3130  *              TIOCMSET = set/clear signal values
3131  *      value   bit mask for command
3132  */
3133 static int tiocmset(struct tty_struct *tty, struct file *file,
3134                     unsigned int set, unsigned int clear)
3135 {
3136         struct slgt_info *info = tty->driver_data;
3137         unsigned long flags;
3138
3139         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3140
3141         if (set & TIOCM_RTS)
3142                 info->signals |= SerialSignal_RTS;
3143         if (set & TIOCM_DTR)
3144                 info->signals |= SerialSignal_DTR;
3145         if (clear & TIOCM_RTS)
3146                 info->signals &= ~SerialSignal_RTS;
3147         if (clear & TIOCM_DTR)
3148                 info->signals &= ~SerialSignal_DTR;
3149
3150         spin_lock_irqsave(&info->lock,flags);
3151         set_signals(info);
3152         spin_unlock_irqrestore(&info->lock,flags);
3153         return 0;
3154 }
3155
3156 static int carrier_raised(struct tty_port *port)
3157 {
3158         unsigned long flags;
3159         struct slgt_info *info = container_of(port, struct slgt_info, port);
3160
3161         spin_lock_irqsave(&info->lock,flags);
3162         get_signals(info);
3163         spin_unlock_irqrestore(&info->lock,flags);
3164         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3165 }
3166
3167 static void dtr_rts(struct tty_port *port, int on)
3168 {
3169         unsigned long flags;
3170         struct slgt_info *info = container_of(port, struct slgt_info, port);
3171
3172         spin_lock_irqsave(&info->lock,flags);
3173         if (on)
3174                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3175         else
3176                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3177         set_signals(info);
3178         spin_unlock_irqrestore(&info->lock,flags);
3179 }
3180
3181
3182 /*
3183  *  block current process until the device is ready to open
3184  */
3185 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3186                            struct slgt_info *info)
3187 {
3188         DECLARE_WAITQUEUE(wait, current);
3189         int             retval;
3190         bool            do_clocal = false;
3191         bool            extra_count = false;
3192         unsigned long   flags;
3193         int             cd;
3194         struct tty_port *port = &info->port;
3195
3196         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3197
3198         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3199                 /* nonblock mode is set or port is not enabled */
3200                 port->flags |= ASYNC_NORMAL_ACTIVE;
3201                 return 0;
3202         }
3203
3204         if (tty->termios->c_cflag & CLOCAL)
3205                 do_clocal = true;
3206
3207         /* Wait for carrier detect and the line to become
3208          * free (i.e., not in use by the callout).  While we are in
3209          * this loop, port->count is dropped by one, so that
3210          * close() knows when to free things.  We restore it upon
3211          * exit, either normal or abnormal.
3212          */
3213
3214         retval = 0;
3215         add_wait_queue(&port->open_wait, &wait);
3216
3217         spin_lock_irqsave(&info->lock, flags);
3218         if (!tty_hung_up_p(filp)) {
3219                 extra_count = true;
3220                 port->count--;
3221         }
3222         spin_unlock_irqrestore(&info->lock, flags);
3223         port->blocked_open++;
3224
3225         while (1) {
3226                 if ((tty->termios->c_cflag & CBAUD))
3227                         tty_port_raise_dtr_rts(port);
3228
3229                 set_current_state(TASK_INTERRUPTIBLE);
3230
3231                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3232                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3233                                         -EAGAIN : -ERESTARTSYS;
3234                         break;
3235                 }
3236
3237                 cd = tty_port_carrier_raised(port);
3238
3239                 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3240                         break;
3241
3242                 if (signal_pending(current)) {
3243                         retval = -ERESTARTSYS;
3244                         break;
3245                 }
3246
3247                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3248                 schedule();
3249         }
3250
3251         set_current_state(TASK_RUNNING);
3252         remove_wait_queue(&port->open_wait, &wait);
3253
3254         if (extra_count)
3255                 port->count++;
3256         port->blocked_open--;
3257
3258         if (!retval)
3259                 port->flags |= ASYNC_NORMAL_ACTIVE;
3260
3261         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3262         return retval;
3263 }
3264
3265 static int alloc_tmp_rbuf(struct slgt_info *info)
3266 {
3267         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3268         if (info->tmp_rbuf == NULL)
3269                 return -ENOMEM;
3270         return 0;
3271 }
3272
3273 static void free_tmp_rbuf(struct slgt_info *info)
3274 {
3275         kfree(info->tmp_rbuf);
3276         info->tmp_rbuf = NULL;
3277 }
3278
3279 /*
3280  * allocate DMA descriptor lists.
3281  */
3282 static int alloc_desc(struct slgt_info *info)
3283 {
3284         unsigned int i;
3285         unsigned int pbufs;
3286
3287         /* allocate memory to hold descriptor lists */
3288         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3289         if (info->bufs == NULL)
3290                 return -ENOMEM;
3291
3292         memset(info->bufs, 0, DESC_LIST_SIZE);
3293
3294         info->rbufs = (struct slgt_desc*)info->bufs;
3295         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3296
3297         pbufs = (unsigned int)info->bufs_dma_addr;
3298
3299         /*
3300          * Build circular lists of descriptors
3301          */
3302
3303         for (i=0; i < info->rbuf_count; i++) {
3304                 /* physical address of this descriptor */
3305                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3306
3307                 /* physical address of next descriptor */
3308                 if (i == info->rbuf_count - 1)
3309                         info->rbufs[i].next = cpu_to_le32(pbufs);
3310                 else
3311                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3312                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3313         }
3314
3315         for (i=0; i < info->tbuf_count; i++) {
3316                 /* physical address of this descriptor */
3317                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3318
3319                 /* physical address of next descriptor */
3320                 if (i == info->tbuf_count - 1)
3321                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3322                 else
3323                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3324         }
3325
3326         return 0;
3327 }
3328
3329 static void free_desc(struct slgt_info *info)
3330 {
3331         if (info->bufs != NULL) {
3332                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3333                 info->bufs  = NULL;
3334                 info->rbufs = NULL;
3335                 info->tbufs = NULL;
3336         }
3337 }
3338
3339 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3340 {
3341         int i;
3342         for (i=0; i < count; i++) {
3343                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3344                         return -ENOMEM;
3345                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3346         }
3347         return 0;
3348 }
3349
3350 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3351 {
3352         int i;
3353         for (i=0; i < count; i++) {
3354                 if (bufs[i].buf == NULL)
3355                         continue;
3356                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3357                 bufs[i].buf = NULL;
3358         }
3359 }
3360
3361 static int alloc_dma_bufs(struct slgt_info *info)
3362 {
3363         info->rbuf_count = 32;
3364         info->tbuf_count = 32;
3365
3366         if (alloc_desc(info) < 0 ||
3367             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3368             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3369             alloc_tmp_rbuf(info) < 0) {
3370                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3371                 return -ENOMEM;
3372         }
3373         reset_rbufs(info);
3374         return 0;
3375 }
3376
3377 static void free_dma_bufs(struct slgt_info *info)
3378 {
3379         if (info->bufs) {
3380                 free_bufs(info, info->rbufs, info->rbuf_count);
3381                 free_bufs(info, info->tbufs, info->tbuf_count);
3382                 free_desc(info);
3383         }
3384         free_tmp_rbuf(info);
3385 }
3386
3387 static int claim_resources(struct slgt_info *info)
3388 {
3389         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3390                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3391                         info->device_name, info->phys_reg_addr));
3392                 info->init_error = DiagStatus_AddressConflict;
3393                 goto errout;
3394         }
3395         else
3396                 info->reg_addr_requested = true;
3397
3398         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3399         if (!info->reg_addr) {
3400                 DBGERR(("%s cant map device registers, addr=%08X\n",
3401                         info->device_name, info->phys_reg_addr));
3402                 info->init_error = DiagStatus_CantAssignPciResources;
3403                 goto errout;
3404         }
3405         return 0;
3406
3407 errout:
3408         release_resources(info);
3409         return -ENODEV;
3410 }
3411
3412 static void release_resources(struct slgt_info *info)
3413 {
3414         if (info->irq_requested) {
3415                 free_irq(info->irq_level, info);
3416                 info->irq_requested = false;
3417         }
3418
3419         if (info->reg_addr_requested) {
3420                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3421                 info->reg_addr_requested = false;
3422         }
3423
3424         if (info->reg_addr) {
3425                 iounmap(info->reg_addr);
3426                 info->reg_addr = NULL;
3427         }
3428 }
3429
3430 /* Add the specified device instance data structure to the
3431  * global linked list of devices and increment the device count.
3432  */
3433 static void add_device(struct slgt_info *info)
3434 {
3435         char *devstr;
3436
3437         info->next_device = NULL;
3438         info->line = slgt_device_count;
3439         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3440
3441         if (info->line < MAX_DEVICES) {
3442                 if (maxframe[info->line])
3443                         info->max_frame_size = maxframe[info->line];
3444         }
3445
3446         slgt_device_count++;
3447
3448         if (!slgt_device_list)
3449                 slgt_device_list = info;
3450         else {
3451                 struct slgt_info *current_dev = slgt_device_list;
3452                 while(current_dev->next_device)
3453                         current_dev = current_dev->next_device;
3454                 current_dev->next_device = info;
3455         }
3456
3457         if (info->max_frame_size < 4096)
3458                 info->max_frame_size = 4096;
3459         else if (info->max_frame_size > 65535)
3460                 info->max_frame_size = 65535;
3461
3462         switch(info->pdev->device) {
3463         case SYNCLINK_GT_DEVICE_ID:
3464                 devstr = "GT";
3465                 break;
3466         case SYNCLINK_GT2_DEVICE_ID:
3467                 devstr = "GT2";
3468                 break;
3469         case SYNCLINK_GT4_DEVICE_ID:
3470                 devstr = "GT4";
3471                 break;
3472         case SYNCLINK_AC_DEVICE_ID:
3473                 devstr = "AC";
3474                 info->params.mode = MGSL_MODE_ASYNC;
3475                 break;
3476         default:
3477                 devstr = "(unknown model)";
3478         }
3479         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3480                 devstr, info->device_name, info->phys_reg_addr,
3481                 info->irq_level, info->max_frame_size);
3482
3483 #if SYNCLINK_GENERIC_HDLC
3484         hdlcdev_init(info);
3485 #endif
3486 }
3487
3488 static const struct tty_port_operations slgt_port_ops = {
3489         .carrier_raised = carrier_raised,
3490         .dtr_rts = dtr_rts,
3491 };
3492
3493 /*
3494  *  allocate device instance structure, return NULL on failure
3495  */
3496 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3497 {
3498         struct slgt_info *info;
3499
3500         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3501
3502         if (!info) {
3503                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3504                         driver_name, adapter_num, port_num));
3505         } else {
3506                 tty_port_init(&info->port);
3507                 info->port.ops = &slgt_port_ops;
3508                 info->magic = MGSL_MAGIC;
3509                 INIT_WORK(&info->task, bh_handler);
3510                 info->max_frame_size = 4096;
3511                 info->base_clock = 14745600;
3512                 info->rbuf_fill_level = DMABUFSIZE;
3513                 info->port.close_delay = 5*HZ/10;
3514                 info->port.closing_wait = 30*HZ;
3515                 init_waitqueue_head(&info->status_event_wait_q);
3516                 init_waitqueue_head(&info->event_wait_q);
3517                 spin_lock_init(&info->netlock);
3518                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3519                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3520                 info->adapter_num = adapter_num;
3521                 info->port_num = port_num;
3522
3523                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3524                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3525
3526                 /* Copy configuration info to device instance data */
3527                 info->pdev = pdev;
3528                 info->irq_level = pdev->irq;
3529                 info->phys_reg_addr = pci_resource_start(pdev,0);
3530
3531                 info->bus_type = MGSL_BUS_TYPE_PCI;
3532                 info->irq_flags = IRQF_SHARED;
3533
3534                 info->init_error = -1; /* assume error, set to 0 on successful init */
3535         }
3536
3537         return info;
3538 }
3539
3540 static void device_init(int adapter_num, struct pci_dev *pdev)
3541 {
3542         struct slgt_info *port_array[SLGT_MAX_PORTS];
3543         int i;
3544         int port_count = 1;
3545
3546         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3547                 port_count = 2;
3548         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3549                 port_count = 4;
3550
3551         /* allocate device instances for all ports */
3552         for (i=0; i < port_count; ++i) {
3553                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3554                 if (port_array[i] == NULL) {
3555                         for (--i; i >= 0; --i)
3556                                 kfree(port_array[i]);
3557                         return;
3558                 }
3559         }
3560
3561         /* give copy of port_array to all ports and add to device list  */
3562         for (i=0; i < port_count; ++i) {
3563                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3564                 add_device(port_array[i]);
3565                 port_array[i]->port_count = port_count;
3566                 spin_lock_init(&port_array[i]->lock);
3567         }
3568
3569         /* Allocate and claim adapter resources */
3570         if (!claim_resources(port_array[0])) {
3571
3572                 alloc_dma_bufs(port_array[0]);
3573
3574                 /* copy resource information from first port to others */
3575                 for (i = 1; i < port_count; ++i) {
3576                         port_array[i]->lock      = port_array[0]->lock;
3577                         port_array[i]->irq_level = port_array[0]->irq_level;
3578                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3579                         alloc_dma_bufs(port_array[i]);
3580                 }
3581
3582                 if (request_irq(port_array[0]->irq_level,
3583                                         slgt_interrupt,
3584                                         port_array[0]->irq_flags,
3585                                         port_array[0]->device_name,
3586                                         port_array[0]) < 0) {
3587                         DBGERR(("%s request_irq failed IRQ=%d\n",
3588                                 port_array[0]->device_name,
3589                                 port_array[0]->irq_level));
3590                 } else {
3591                         port_array[0]->irq_requested = true;
3592                         adapter_test(port_array[0]);
3593                         for (i=1 ; i < port_count ; i++) {
3594                                 port_array[i]->init_error = port_array[0]->init_error;
3595                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3596                         }
3597                 }
3598         }
3599
3600         for (i=0; i < port_count; ++i)
3601                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3602 }
3603
3604 static int __devinit init_one(struct pci_dev *dev,
3605                               const struct pci_device_id *ent)
3606 {
3607         if (pci_enable_device(dev)) {
3608                 printk("error enabling pci device %p\n", dev);
3609                 return -EIO;
3610         }
3611         pci_set_master(dev);
3612         device_init(slgt_device_count, dev);
3613         return 0;
3614 }
3615
3616 static void __devexit remove_one(struct pci_dev *dev)
3617 {
3618 }
3619
3620 static const struct tty_operations ops = {
3621         .open = open,
3622         .close = close,
3623         .write = write,
3624         .put_char = put_char,
3625         .flush_chars = flush_chars,
3626         .write_room = write_room,
3627         .chars_in_buffer = chars_in_buffer,
3628         .flush_buffer = flush_buffer,
3629         .ioctl = ioctl,
3630         .compat_ioctl = slgt_compat_ioctl,
3631         .throttle = throttle,
3632         .unthrottle = unthrottle,
3633         .send_xchar = send_xchar,
3634         .break_ctl = set_break,
3635         .wait_until_sent = wait_until_sent,
3636         .set_termios = set_termios,
3637         .stop = tx_hold,
3638         .start = tx_release,
3639         .hangup = hangup,
3640         .tiocmget = tiocmget,
3641         .tiocmset = tiocmset,
3642         .proc_fops = &synclink_gt_proc_fops,
3643 };
3644
3645 static void slgt_cleanup(void)
3646 {
3647         int rc;
3648         struct slgt_info *info;
3649         struct slgt_info *tmp;
3650
3651         printk(KERN_INFO "unload %s\n", driver_name);
3652
3653         if (serial_driver) {
3654                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3655                         tty_unregister_device(serial_driver, info->line);
3656                 if ((rc = tty_unregister_driver(serial_driver)))
3657                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3658                 put_tty_driver(serial_driver);
3659         }
3660
3661         /* reset devices */
3662         info = slgt_device_list;
3663         while(info) {
3664                 reset_port(info);
3665                 info = info->next_device;
3666         }
3667
3668         /* release devices */
3669         info = slgt_device_list;
3670         while(info) {
3671 #if SYNCLINK_GENERIC_HDLC
3672                 hdlcdev_exit(info);
3673 #endif
3674                 free_dma_bufs(info);
3675                 free_tmp_rbuf(info);
3676                 if (info->port_num == 0)
3677                         release_resources(info);
3678                 tmp = info;
3679                 info = info->next_device;
3680                 kfree(tmp);
3681         }
3682
3683         if (pci_registered)
3684                 pci_unregister_driver(&pci_driver);
3685 }
3686
3687 /*
3688  *  Driver initialization entry point.
3689  */
3690 static int __init slgt_init(void)
3691 {
3692         int rc;
3693
3694         printk(KERN_INFO "%s\n", driver_name);
3695
3696         serial_driver = alloc_tty_driver(MAX_DEVICES);
3697         if (!serial_driver) {
3698                 printk("%s can't allocate tty driver\n", driver_name);
3699                 return -ENOMEM;
3700         }
3701
3702         /* Initialize the tty_driver structure */
3703
3704         serial_driver->owner = THIS_MODULE;
3705         serial_driver->driver_name = tty_driver_name;
3706         serial_driver->name = tty_dev_prefix;
3707         serial_driver->major = ttymajor;
3708         serial_driver->minor_start = 64;
3709         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3710         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3711         serial_driver->init_termios = tty_std_termios;
3712         serial_driver->init_termios.c_cflag =
3713                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3714         serial_driver->init_termios.c_ispeed = 9600;
3715         serial_driver->init_termios.c_ospeed = 9600;
3716         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3717         tty_set_operations(serial_driver, &ops);
3718         if ((rc = tty_register_driver(serial_driver)) < 0) {
3719                 DBGERR(("%s can't register serial driver\n", driver_name));
3720                 put_tty_driver(serial_driver);
3721                 serial_driver = NULL;
3722                 goto error;
3723         }
3724
3725         printk(KERN_INFO "%s, tty major#%d\n",
3726                driver_name, serial_driver->major);
3727
3728         slgt_device_count = 0;
3729         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3730                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3731                 goto error;
3732         }
3733         pci_registered = true;
3734
3735         if (!slgt_device_list)
3736                 printk("%s no devices found\n",driver_name);
3737
3738         return 0;
3739
3740 error:
3741         slgt_cleanup();
3742         return rc;
3743 }
3744
3745 static void __exit slgt_exit(void)
3746 {
3747         slgt_cleanup();
3748 }
3749
3750 module_init(slgt_init);
3751 module_exit(slgt_exit);
3752
3753 /*
3754  * register access routines
3755  */
3756
3757 #define CALC_REGADDR() \
3758         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3759         if (addr >= 0x80) \
3760                 reg_addr += (info->port_num) * 32;
3761
3762 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3763 {
3764         CALC_REGADDR();
3765         return readb((void __iomem *)reg_addr);
3766 }
3767
3768 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3769 {
3770         CALC_REGADDR();
3771         writeb(value, (void __iomem *)reg_addr);
3772 }
3773
3774 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3775 {
3776         CALC_REGADDR();
3777         return readw((void __iomem *)reg_addr);
3778 }
3779
3780 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3781 {
3782         CALC_REGADDR();
3783         writew(value, (void __iomem *)reg_addr);
3784 }
3785
3786 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3787 {
3788         CALC_REGADDR();
3789         return readl((void __iomem *)reg_addr);
3790 }
3791
3792 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3793 {
3794         CALC_REGADDR();
3795         writel(value, (void __iomem *)reg_addr);
3796 }
3797
3798 static void rdma_reset(struct slgt_info *info)
3799 {
3800         unsigned int i;
3801
3802         /* set reset bit */
3803         wr_reg32(info, RDCSR, BIT1);
3804
3805         /* wait for enable bit cleared */
3806         for(i=0 ; i < 1000 ; i++)
3807                 if (!(rd_reg32(info, RDCSR) & BIT0))
3808                         break;
3809 }
3810
3811 static void tdma_reset(struct slgt_info *info)
3812 {
3813         unsigned int i;
3814
3815         /* set reset bit */
3816         wr_reg32(info, TDCSR, BIT1);
3817
3818         /* wait for enable bit cleared */
3819         for(i=0 ; i < 1000 ; i++)
3820                 if (!(rd_reg32(info, TDCSR) & BIT0))
3821                         break;
3822 }
3823
3824 /*
3825  * enable internal loopback
3826  * TxCLK and RxCLK are generated from BRG
3827  * and TxD is looped back to RxD internally.
3828  */
3829 static void enable_loopback(struct slgt_info *info)
3830 {
3831         /* SCR (serial control) BIT2=looopback enable */
3832         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3833
3834         if (info->params.mode != MGSL_MODE_ASYNC) {
3835                 /* CCR (clock control)
3836                  * 07..05  tx clock source (010 = BRG)
3837                  * 04..02  rx clock source (010 = BRG)
3838                  * 01      auxclk enable   (0 = disable)
3839                  * 00      BRG enable      (1 = enable)
3840                  *
3841                  * 0100 1001
3842                  */
3843                 wr_reg8(info, CCR, 0x49);
3844
3845                 /* set speed if available, otherwise use default */
3846                 if (info->params.clock_speed)
3847                         set_rate(info, info->params.clock_speed);
3848                 else
3849                         set_rate(info, 3686400);
3850         }
3851 }
3852
3853 /*
3854  *  set baud rate generator to specified rate
3855  */
3856 static void set_rate(struct slgt_info *info, u32 rate)
3857 {
3858         unsigned int div;
3859         unsigned int osc = info->base_clock;
3860
3861         /* div = osc/rate - 1
3862          *
3863          * Round div up if osc/rate is not integer to
3864          * force to next slowest rate.
3865          */
3866
3867         if (rate) {
3868                 div = osc/rate;
3869                 if (!(osc % rate) && div)
3870                         div--;
3871                 wr_reg16(info, BDR, (unsigned short)div);
3872         }
3873 }
3874
3875 static void rx_stop(struct slgt_info *info)
3876 {
3877         unsigned short val;
3878
3879         /* disable and reset receiver */
3880         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3881         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3882         wr_reg16(info, RCR, val);                  /* clear reset bit */
3883
3884         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3885
3886         /* clear pending rx interrupts */
3887         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3888
3889         rdma_reset(info);
3890
3891         info->rx_enabled = false;
3892         info->rx_restart = false;
3893 }
3894
3895 static void rx_start(struct slgt_info *info)
3896 {
3897         unsigned short val;
3898
3899         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3900
3901         /* clear pending rx overrun IRQ */
3902         wr_reg16(info, SSR, IRQ_RXOVER);
3903
3904         /* reset and disable receiver */
3905         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3906         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3907         wr_reg16(info, RCR, val);                  /* clear reset bit */
3908
3909         rdma_reset(info);
3910         reset_rbufs(info);
3911
3912         if (info->rx_pio) {
3913                 /* rx request when rx FIFO not empty */
3914                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3915                 slgt_irq_on(info, IRQ_RXDATA);
3916                 if (info->params.mode == MGSL_MODE_ASYNC) {
3917                         /* enable saving of rx status */
3918                         wr_reg32(info, RDCSR, BIT6);
3919                 }
3920         } else {
3921                 /* rx request when rx FIFO half full */
3922                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3923                 /* set 1st descriptor address */
3924                 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3925
3926                 if (info->params.mode != MGSL_MODE_ASYNC) {
3927                         /* enable rx DMA and DMA interrupt */
3928                         wr_reg32(info, RDCSR, (BIT2 + BIT0));
3929                 } else {
3930                         /* enable saving of rx status, rx DMA and DMA interrupt */
3931                         wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3932                 }
3933         }
3934
3935         slgt_irq_on(info, IRQ_RXOVER);
3936
3937         /* enable receiver */
3938         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3939
3940         info->rx_restart = false;
3941         info->rx_enabled = true;
3942 }
3943
3944 static void tx_start(struct slgt_info *info)
3945 {
3946         if (!info->tx_enabled) {
3947                 wr_reg16(info, TCR,
3948                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3949                 info->tx_enabled = true;
3950         }
3951
3952         if (info->tx_count) {
3953                 info->drop_rts_on_tx_done = false;
3954
3955                 if (info->params.mode != MGSL_MODE_ASYNC) {
3956                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3957                                 get_signals(info);
3958                                 if (!(info->signals & SerialSignal_RTS)) {
3959                                         info->signals |= SerialSignal_RTS;
3960                                         set_signals(info);
3961                                         info->drop_rts_on_tx_done = true;
3962                                 }
3963                         }
3964
3965                         slgt_irq_off(info, IRQ_TXDATA);
3966                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3967                         /* clear tx idle and underrun status bits */
3968                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3969                 } else {
3970                         slgt_irq_off(info, IRQ_TXDATA);
3971                         slgt_irq_on(info, IRQ_TXIDLE);
3972                         /* clear tx idle status bit */
3973                         wr_reg16(info, SSR, IRQ_TXIDLE);
3974                 }
3975                 /* set 1st descriptor address and start DMA */
3976                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3977                 wr_reg32(info, TDCSR, BIT2 + BIT0);
3978                 info->tx_active = true;
3979         }
3980 }
3981
3982 static void tx_stop(struct slgt_info *info)
3983 {
3984         unsigned short val;
3985
3986         del_timer(&info->tx_timer);
3987
3988         tdma_reset(info);
3989
3990         /* reset and disable transmitter */
3991         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3992         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3993
3994         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3995
3996         /* clear tx idle and underrun status bit */
3997         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3998
3999         reset_tbufs(info);
4000
4001         info->tx_enabled = false;
4002         info->tx_active = false;
4003 }
4004
4005 static void reset_port(struct slgt_info *info)
4006 {
4007         if (!info->reg_addr)
4008                 return;
4009
4010         tx_stop(info);
4011         rx_stop(info);
4012
4013         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4014         set_signals(info);
4015
4016         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4017 }
4018
4019 static void reset_adapter(struct slgt_info *info)
4020 {
4021         int i;
4022         for (i=0; i < info->port_count; ++i) {
4023                 if (info->port_array[i])
4024                         reset_port(info->port_array[i]);
4025         }
4026 }
4027
4028 static void async_mode(struct slgt_info *info)
4029 {
4030         unsigned short val;
4031
4032         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4033         tx_stop(info);
4034         rx_stop(info);
4035
4036         /* TCR (tx control)
4037          *
4038          * 15..13  mode, 010=async
4039          * 12..10  encoding, 000=NRZ
4040          * 09      parity enable
4041          * 08      1=odd parity, 0=even parity
4042          * 07      1=RTS driver control
4043          * 06      1=break enable
4044          * 05..04  character length
4045          *         00=5 bits
4046          *         01=6 bits
4047          *         10=7 bits
4048          *         11=8 bits
4049          * 03      0=1 stop bit, 1=2 stop bits
4050          * 02      reset
4051          * 01      enable
4052          * 00      auto-CTS enable
4053          */
4054         val = 0x4000;
4055
4056         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4057                 val |= BIT7;
4058
4059         if (info->params.parity != ASYNC_PARITY_NONE) {
4060                 val |= BIT9;
4061                 if (info->params.parity == ASYNC_PARITY_ODD)
4062                         val |= BIT8;
4063         }
4064
4065         switch (info->params.data_bits)
4066         {
4067         case 6: val |= BIT4; break;
4068         case 7: val |= BIT5; break;
4069         case 8: val |= BIT5 + BIT4; break;
4070         }
4071
4072         if (info->params.stop_bits != 1)
4073                 val |= BIT3;
4074
4075         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4076                 val |= BIT0;
4077
4078         wr_reg16(info, TCR, val);
4079
4080         /* RCR (rx control)
4081          *
4082          * 15..13  mode, 010=async
4083          * 12..10  encoding, 000=NRZ
4084          * 09      parity enable
4085          * 08      1=odd parity, 0=even parity
4086          * 07..06  reserved, must be 0
4087          * 05..04  character length
4088          *         00=5 bits
4089          *         01=6 bits
4090          *         10=7 bits
4091          *         11=8 bits
4092          * 03      reserved, must be zero
4093          * 02      reset
4094          * 01      enable
4095          * 00      auto-DCD enable
4096          */
4097         val = 0x4000;
4098
4099         if (info->params.parity != ASYNC_PARITY_NONE) {
4100                 val |= BIT9;
4101                 if (info->params.parity == ASYNC_PARITY_ODD)
4102                         val |= BIT8;
4103         }
4104
4105         switch (info->params.data_bits)
4106         {
4107         case 6: val |= BIT4; break;
4108         case 7: val |= BIT5; break;
4109         case 8: val |= BIT5 + BIT4; break;
4110         }
4111
4112         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4113                 val |= BIT0;
4114
4115         wr_reg16(info, RCR, val);
4116
4117         /* CCR (clock control)
4118          *
4119          * 07..05  011 = tx clock source is BRG/16
4120          * 04..02  010 = rx clock source is BRG
4121          * 01      0 = auxclk disabled
4122          * 00      1 = BRG enabled
4123          *
4124          * 0110 1001
4125          */
4126         wr_reg8(info, CCR, 0x69);
4127
4128         msc_set_vcr(info);
4129
4130         /* SCR (serial control)
4131          *
4132          * 15  1=tx req on FIFO half empty
4133          * 14  1=rx req on FIFO half full
4134          * 13  tx data  IRQ enable
4135          * 12  tx idle  IRQ enable
4136          * 11  rx break on IRQ enable
4137          * 10  rx data  IRQ enable
4138          * 09  rx break off IRQ enable
4139          * 08  overrun  IRQ enable
4140          * 07  DSR      IRQ enable
4141          * 06  CTS      IRQ enable
4142          * 05  DCD      IRQ enable
4143          * 04  RI       IRQ enable
4144          * 03  0=16x sampling, 1=8x sampling
4145          * 02  1=txd->rxd internal loopback enable
4146          * 01  reserved, must be zero
4147          * 00  1=master IRQ enable
4148          */
4149         val = BIT15 + BIT14 + BIT0;
4150         /* JCR[8] : 1 = x8 async mode feature available */
4151         if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4152             ((info->base_clock < (info->params.data_rate * 16)) ||
4153              (info->base_clock % (info->params.data_rate * 16)))) {
4154                 /* use 8x sampling */
4155                 val |= BIT3;
4156                 set_rate(info, info->params.data_rate * 8);
4157         } else {
4158                 /* use 16x sampling */
4159                 set_rate(info, info->params.data_rate * 16);
4160         }
4161         wr_reg16(info, SCR, val);
4162
4163         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4164
4165         if (info->params.loopback)
4166                 enable_loopback(info);
4167 }
4168
4169 static void sync_mode(struct slgt_info *info)
4170 {
4171         unsigned short val;
4172
4173         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4174         tx_stop(info);
4175         rx_stop(info);
4176
4177         /* TCR (tx control)
4178          *
4179          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4180          * 12..10  encoding
4181          * 09      CRC enable
4182          * 08      CRC32
4183          * 07      1=RTS driver control
4184          * 06      preamble enable
4185          * 05..04  preamble length
4186          * 03      share open/close flag
4187          * 02      reset
4188          * 01      enable
4189          * 00      auto-CTS enable
4190          */
4191         val = BIT2;
4192
4193         switch(info->params.mode) {
4194         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4195         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4196         case MGSL_MODE_RAW:      val |= BIT13; break;
4197         }
4198         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4199                 val |= BIT7;
4200
4201         switch(info->params.encoding)
4202         {
4203         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4204         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4205         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4206         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4207         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4208         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4209         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4210         }
4211
4212         switch (info->params.crc_type & HDLC_CRC_MASK)
4213         {
4214         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4215         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4216         }
4217
4218         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4219                 val |= BIT6;
4220
4221         switch (info->params.preamble_length)
4222         {
4223         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4224         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4225         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4226         }
4227
4228         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4229                 val |= BIT0;
4230
4231         wr_reg16(info, TCR, val);
4232
4233         /* TPR (transmit preamble) */
4234
4235         switch (info->params.preamble)
4236         {
4237         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4238         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4239         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4240         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4241         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4242         default:                          val = 0x7e; break;
4243         }
4244         wr_reg8(info, TPR, (unsigned char)val);
4245
4246         /* RCR (rx control)
4247          *
4248          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4249          * 12..10  encoding
4250          * 09      CRC enable
4251          * 08      CRC32
4252          * 07..03  reserved, must be 0
4253          * 02      reset
4254          * 01      enable
4255          * 00      auto-DCD enable
4256          */
4257         val = 0;
4258
4259         switch(info->params.mode) {
4260         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4261         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4262         case MGSL_MODE_RAW:      val |= BIT13; break;
4263         }
4264
4265         switch(info->params.encoding)
4266         {
4267         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4268         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4269         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4270         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4271         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4272         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4273         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4274         }
4275
4276         switch (info->params.crc_type & HDLC_CRC_MASK)
4277         {
4278         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4279         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4280         }
4281
4282         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4283                 val |= BIT0;
4284
4285         wr_reg16(info, RCR, val);
4286
4287         /* CCR (clock control)
4288          *
4289          * 07..05  tx clock source
4290          * 04..02  rx clock source
4291          * 01      auxclk enable
4292          * 00      BRG enable
4293          */
4294         val = 0;
4295
4296         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4297         {
4298                 // when RxC source is DPLL, BRG generates 16X DPLL
4299                 // reference clock, so take TxC from BRG/16 to get
4300                 // transmit clock at actual data rate
4301                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4302                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4303                 else
4304                         val |= BIT6;    /* 010, txclk = BRG */
4305         }
4306         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4307                 val |= BIT7;    /* 100, txclk = DPLL Input */
4308         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4309                 val |= BIT5;    /* 001, txclk = RXC Input */
4310
4311         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4312                 val |= BIT3;    /* 010, rxclk = BRG */
4313         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4314                 val |= BIT4;    /* 100, rxclk = DPLL */
4315         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4316                 val |= BIT2;    /* 001, rxclk = TXC Input */
4317
4318         if (info->params.clock_speed)
4319                 val |= BIT1 + BIT0;
4320
4321         wr_reg8(info, CCR, (unsigned char)val);
4322
4323         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4324         {
4325                 // program DPLL mode
4326                 switch(info->params.encoding)
4327                 {
4328                 case HDLC_ENCODING_BIPHASE_MARK:
4329                 case HDLC_ENCODING_BIPHASE_SPACE:
4330                         val = BIT7; break;
4331                 case HDLC_ENCODING_BIPHASE_LEVEL:
4332                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4333                         val = BIT7 + BIT6; break;
4334                 default: val = BIT6;    // NRZ encodings
4335                 }
4336                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4337
4338                 // DPLL requires a 16X reference clock from BRG
4339                 set_rate(info, info->params.clock_speed * 16);
4340         }
4341         else
4342                 set_rate(info, info->params.clock_speed);
4343
4344         tx_set_idle(info);
4345
4346         msc_set_vcr(info);
4347
4348         /* SCR (serial control)
4349          *
4350          * 15  1=tx req on FIFO half empty
4351          * 14  1=rx req on FIFO half full
4352          * 13  tx data  IRQ enable
4353          * 12  tx idle  IRQ enable
4354          * 11  underrun IRQ enable
4355          * 10  rx data  IRQ enable
4356          * 09  rx idle  IRQ enable
4357          * 08  overrun  IRQ enable
4358          * 07  DSR      IRQ enable
4359          * 06  CTS      IRQ enable
4360          * 05  DCD      IRQ enable
4361          * 04  RI       IRQ enable
4362          * 03  reserved, must be zero
4363          * 02  1=txd->rxd internal loopback enable
4364          * 01  reserved, must be zero
4365          * 00  1=master IRQ enable
4366          */
4367         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4368
4369         if (info->params.loopback)
4370                 enable_loopback(info);
4371 }
4372
4373 /*
4374  *  set transmit idle mode
4375  */
4376 static void tx_set_idle(struct slgt_info *info)
4377 {
4378         unsigned char val;
4379         unsigned short tcr;
4380
4381         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4382          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4383          */
4384         tcr = rd_reg16(info, TCR);
4385         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4386                 /* disable preamble, set idle size to 16 bits */
4387                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4388                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4389                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4390         } else if (!(tcr & BIT6)) {
4391                 /* preamble is disabled, set idle size to 8 bits */
4392                 tcr &= ~(BIT5 + BIT4);
4393         }
4394         wr_reg16(info, TCR, tcr);
4395
4396         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4397                 /* LSB of custom tx idle specified in tx idle register */
4398                 val = (unsigned char)(info->idle_mode & 0xff);
4399         } else {
4400                 /* standard 8 bit idle patterns */
4401                 switch(info->idle_mode)
4402                 {
4403                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4404                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4405                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4406                 case HDLC_TXIDLE_ZEROS:
4407                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4408                 default:                         val = 0xff;
4409                 }
4410         }
4411
4412         wr_reg8(info, TIR, val);
4413 }
4414
4415 /*
4416  * get state of V24 status (input) signals
4417  */
4418 static void get_signals(struct slgt_info *info)
4419 {
4420         unsigned short status = rd_reg16(info, SSR);
4421
4422         /* clear all serial signals except DTR and RTS */
4423         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4424
4425         if (status & BIT3)
4426                 info->signals |= SerialSignal_DSR;
4427         if (status & BIT2)
4428                 info->signals |= SerialSignal_CTS;
4429         if (status & BIT1)
4430                 info->signals |= SerialSignal_DCD;
4431         if (status & BIT0)
4432                 info->signals |= SerialSignal_RI;
4433 }
4434
4435 /*
4436  * set V.24 Control Register based on current configuration
4437  */
4438 static void msc_set_vcr(struct slgt_info *info)
4439 {
4440         unsigned char val = 0;
4441
4442         /* VCR (V.24 control)
4443          *
4444          * 07..04  serial IF select
4445          * 03      DTR
4446          * 02      RTS
4447          * 01      LL
4448          * 00      RL
4449          */
4450
4451         switch(info->if_mode & MGSL_INTERFACE_MASK)
4452         {
4453         case MGSL_INTERFACE_RS232:
4454                 val |= BIT5; /* 0010 */
4455                 break;
4456         case MGSL_INTERFACE_V35:
4457                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4458                 break;
4459         case MGSL_INTERFACE_RS422:
4460                 val |= BIT6; /* 0100 */
4461                 break;
4462         }
4463
4464         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4465                 val |= BIT4;
4466         if (info->signals & SerialSignal_DTR)
4467                 val |= BIT3;
4468         if (info->signals & SerialSignal_RTS)
4469                 val |= BIT2;
4470         if (info->if_mode & MGSL_INTERFACE_LL)
4471                 val |= BIT1;
4472         if (info->if_mode & MGSL_INTERFACE_RL)
4473                 val |= BIT0;
4474         wr_reg8(info, VCR, val);
4475 }
4476
4477 /*
4478  * set state of V24 control (output) signals
4479  */
4480 static void set_signals(struct slgt_info *info)
4481 {
4482         unsigned char val = rd_reg8(info, VCR);
4483         if (info->signals & SerialSignal_DTR)
4484                 val |= BIT3;
4485         else
4486                 val &= ~BIT3;
4487         if (info->signals & SerialSignal_RTS)
4488                 val |= BIT2;
4489         else
4490                 val &= ~BIT2;
4491         wr_reg8(info, VCR, val);
4492 }
4493
4494 /*
4495  * free range of receive DMA buffers (i to last)
4496  */
4497 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4498 {
4499         int done = 0;
4500
4501         while(!done) {
4502                 /* reset current buffer for reuse */
4503                 info->rbufs[i].status = 0;
4504                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4505                 if (i == last)
4506                         done = 1;
4507                 if (++i == info->rbuf_count)
4508                         i = 0;
4509         }
4510         info->rbuf_current = i;
4511 }
4512
4513 /*
4514  * mark all receive DMA buffers as free
4515  */
4516 static void reset_rbufs(struct slgt_info *info)
4517 {
4518         free_rbufs(info, 0, info->rbuf_count - 1);
4519         info->rbuf_fill_index = 0;
4520         info->rbuf_fill_count = 0;
4521 }
4522
4523 /*
4524  * pass receive HDLC frame to upper layer
4525  *
4526  * return true if frame available, otherwise false
4527  */
4528 static bool rx_get_frame(struct slgt_info *info)
4529 {
4530         unsigned int start, end;
4531         unsigned short status;
4532         unsigned int framesize = 0;
4533         unsigned long flags;
4534         struct tty_struct *tty = info->port.tty;
4535         unsigned char addr_field = 0xff;
4536         unsigned int crc_size = 0;
4537
4538         switch (info->params.crc_type & HDLC_CRC_MASK) {
4539         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4540         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4541         }
4542
4543 check_again:
4544
4545         framesize = 0;
4546         addr_field = 0xff;
4547         start = end = info->rbuf_current;
4548
4549         for (;;) {
4550                 if (!desc_complete(info->rbufs[end]))
4551                         goto cleanup;
4552
4553                 if (framesize == 0 && info->params.addr_filter != 0xff)
4554                         addr_field = info->rbufs[end].buf[0];
4555
4556                 framesize += desc_count(info->rbufs[end]);
4557
4558                 if (desc_eof(info->rbufs[end]))
4559                         break;
4560
4561                 if (++end == info->rbuf_count)
4562                         end = 0;
4563
4564                 if (end == info->rbuf_current) {
4565                         if (info->rx_enabled){
4566                                 spin_lock_irqsave(&info->lock,flags);
4567                                 rx_start(info);
4568                                 spin_unlock_irqrestore(&info->lock,flags);
4569                         }
4570                         goto cleanup;
4571                 }
4572         }
4573
4574         /* status
4575          *
4576          * 15      buffer complete
4577          * 14..06  reserved
4578          * 05..04  residue
4579          * 02      eof (end of frame)
4580          * 01      CRC error
4581          * 00      abort
4582          */
4583         status = desc_status(info->rbufs[end]);
4584
4585         /* ignore CRC bit if not using CRC (bit is undefined) */
4586         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4587                 status &= ~BIT1;
4588
4589         if (framesize == 0 ||
4590                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4591                 free_rbufs(info, start, end);
4592                 goto check_again;
4593         }
4594
4595         if (framesize < (2 + crc_size) || status & BIT0) {
4596                 info->icount.rxshort++;
4597                 framesize = 0;
4598         } else if (status & BIT1) {
4599                 info->icount.rxcrc++;
4600                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4601                         framesize = 0;
4602         }
4603
4604 #if SYNCLINK_GENERIC_HDLC
4605         if (framesize == 0) {
4606                 info->netdev->stats.rx_errors++;
4607                 info->netdev->stats.rx_frame_errors++;
4608         }
4609 #endif
4610
4611         DBGBH(("%s rx frame status=%04X size=%d\n",
4612                 info->device_name, status, framesize));
4613         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4614
4615         if (framesize) {
4616                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4617                         framesize -= crc_size;
4618                         crc_size = 0;
4619                 }
4620
4621                 if (framesize > info->max_frame_size + crc_size)
4622                         info->icount.rxlong++;
4623                 else {
4624                         /* copy dma buffer(s) to contiguous temp buffer */
4625                         int copy_count = framesize;
4626                         int i = start;
4627                         unsigned char *p = info->tmp_rbuf;
4628                         info->tmp_rbuf_count = framesize;
4629
4630                         info->icount.rxok++;
4631
4632                         while(copy_count) {
4633                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4634                                 memcpy(p, info->rbufs[i].buf, partial_count);
4635                                 p += partial_count;
4636                                 copy_count -= partial_count;
4637                                 if (++i == info->rbuf_count)
4638                                         i = 0;
4639                         }
4640
4641                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4642                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4643                                 framesize++;
4644                         }
4645
4646 #if SYNCLINK_GENERIC_HDLC
4647                         if (info->netcount)
4648                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4649                         else
4650 #endif
4651                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4652                 }
4653         }
4654         free_rbufs(info, start, end);
4655         return true;
4656
4657 cleanup:
4658         return false;
4659 }
4660
4661 /*
4662  * pass receive buffer (RAW synchronous mode) to tty layer
4663  * return true if buffer available, otherwise false
4664  */
4665 static bool rx_get_buf(struct slgt_info *info)
4666 {
4667         unsigned int i = info->rbuf_current;
4668         unsigned int count;
4669
4670         if (!desc_complete(info->rbufs[i]))
4671                 return false;
4672         count = desc_count(info->rbufs[i]);
4673         switch(info->params.mode) {
4674         case MGSL_MODE_MONOSYNC:
4675         case MGSL_MODE_BISYNC:
4676                 /* ignore residue in byte synchronous modes */
4677                 if (desc_residue(info->rbufs[i]))
4678                         count--;
4679                 break;
4680         }
4681         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4682         DBGINFO(("rx_get_buf size=%d\n", count));
4683         if (count)
4684                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4685                                   info->flag_buf, count);
4686         free_rbufs(info, i, i);
4687         return true;
4688 }
4689
4690 static void reset_tbufs(struct slgt_info *info)
4691 {
4692         unsigned int i;
4693         info->tbuf_current = 0;
4694         for (i=0 ; i < info->tbuf_count ; i++) {
4695                 info->tbufs[i].status = 0;
4696                 info->tbufs[i].count  = 0;
4697         }
4698 }
4699
4700 /*
4701  * return number of free transmit DMA buffers
4702  */
4703 static unsigned int free_tbuf_count(struct slgt_info *info)
4704 {
4705         unsigned int count = 0;
4706         unsigned int i = info->tbuf_current;
4707
4708         do
4709         {
4710                 if (desc_count(info->tbufs[i]))
4711                         break; /* buffer in use */
4712                 ++count;
4713                 if (++i == info->tbuf_count)
4714                         i=0;
4715         } while (i != info->tbuf_current);
4716
4717         /* if tx DMA active, last zero count buffer is in use */
4718         if (count && (rd_reg32(info, TDCSR) & BIT0))
4719                 --count;
4720
4721         return count;
4722 }
4723
4724 /*
4725  * return number of bytes in unsent transmit DMA buffers
4726  * and the serial controller tx FIFO
4727  */
4728 static unsigned int tbuf_bytes(struct slgt_info *info)
4729 {
4730         unsigned int total_count = 0;
4731         unsigned int i = info->tbuf_current;
4732         unsigned int reg_value;
4733         unsigned int count;
4734         unsigned int active_buf_count = 0;
4735
4736         /*
4737          * Add descriptor counts for all tx DMA buffers.
4738          * If count is zero (cleared by DMA controller after read),
4739          * the buffer is complete or is actively being read from.
4740          *
4741          * Record buf_count of last buffer with zero count starting
4742          * from current ring position. buf_count is mirror
4743          * copy of count and is not cleared by serial controller.
4744          * If DMA controller is active, that buffer is actively
4745          * being read so add to total.
4746          */
4747         do {
4748                 count = desc_count(info->tbufs[i]);
4749                 if (count)
4750                         total_count += count;
4751                 else if (!total_count)
4752                         active_buf_count = info->tbufs[i].buf_count;
4753                 if (++i == info->tbuf_count)
4754                         i = 0;
4755         } while (i != info->tbuf_current);
4756
4757         /* read tx DMA status register */
4758         reg_value = rd_reg32(info, TDCSR);
4759
4760         /* if tx DMA active, last zero count buffer is in use */
4761         if (reg_value & BIT0)
4762                 total_count += active_buf_count;
4763
4764         /* add tx FIFO count = reg_value[15..8] */
4765         total_count += (reg_value >> 8) & 0xff;
4766
4767         /* if transmitter active add one byte for shift register */
4768         if (info->tx_active)
4769                 total_count++;
4770
4771         return total_count;
4772 }
4773
4774 /*
4775  * load transmit DMA buffer(s) with data
4776  */
4777 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4778 {
4779         unsigned short count;
4780         unsigned int i;
4781         struct slgt_desc *d;
4782
4783         if (size == 0)
4784                 return;
4785
4786         DBGDATA(info, buf, size, "tx");
4787
4788         info->tbuf_start = i = info->tbuf_current;
4789
4790         while (size) {
4791                 d = &info->tbufs[i];
4792                 if (++i == info->tbuf_count)
4793                         i = 0;
4794
4795                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4796                 memcpy(d->buf, buf, count);
4797
4798                 size -= count;
4799                 buf  += count;
4800
4801                 /*
4802                  * set EOF bit for last buffer of HDLC frame or
4803                  * for every buffer in raw mode
4804                  */
4805                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4806                     info->params.mode == MGSL_MODE_RAW)
4807                         set_desc_eof(*d, 1);
4808                 else
4809                         set_desc_eof(*d, 0);
4810
4811                 set_desc_count(*d, count);
4812                 d->buf_count = count;
4813         }
4814
4815         info->tbuf_current = i;
4816 }
4817
4818 static int register_test(struct slgt_info *info)
4819 {
4820         static unsigned short patterns[] =
4821                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4822         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4823         unsigned int i;
4824         int rc = 0;
4825
4826         for (i=0 ; i < count ; i++) {
4827                 wr_reg16(info, TIR, patterns[i]);
4828                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4829                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4830                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4831                         rc = -ENODEV;
4832                         break;
4833                 }
4834         }
4835         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4836         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4837         return rc;
4838 }
4839
4840 static int irq_test(struct slgt_info *info)
4841 {
4842         unsigned long timeout;
4843         unsigned long flags;
4844         struct tty_struct *oldtty = info->port.tty;
4845         u32 speed = info->params.data_rate;
4846
4847         info->params.data_rate = 921600;
4848         info->port.tty = NULL;
4849
4850         spin_lock_irqsave(&info->lock, flags);
4851         async_mode(info);
4852         slgt_irq_on(info, IRQ_TXIDLE);
4853
4854         /* enable transmitter */
4855         wr_reg16(info, TCR,
4856                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4857
4858         /* write one byte and wait for tx idle */
4859         wr_reg16(info, TDR, 0);
4860
4861         /* assume failure */
4862         info->init_error = DiagStatus_IrqFailure;
4863         info->irq_occurred = false;
4864
4865         spin_unlock_irqrestore(&info->lock, flags);
4866
4867         timeout=100;
4868         while(timeout-- && !info->irq_occurred)
4869                 msleep_interruptible(10);
4870
4871         spin_lock_irqsave(&info->lock,flags);
4872         reset_port(info);
4873         spin_unlock_irqrestore(&info->lock,flags);
4874
4875         info->params.data_rate = speed;
4876         info->port.tty = oldtty;
4877
4878         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4879         return info->irq_occurred ? 0 : -ENODEV;
4880 }
4881
4882 static int loopback_test_rx(struct slgt_info *info)
4883 {
4884         unsigned char *src, *dest;
4885         int count;
4886
4887         if (desc_complete(info->rbufs[0])) {
4888                 count = desc_count(info->rbufs[0]);
4889                 src   = info->rbufs[0].buf;
4890                 dest  = info->tmp_rbuf;
4891
4892                 for( ; count ; count-=2, src+=2) {
4893                         /* src=data byte (src+1)=status byte */
4894                         if (!(*(src+1) & (BIT9 + BIT8))) {
4895                                 *dest = *src;
4896                                 dest++;
4897                                 info->tmp_rbuf_count++;
4898                         }
4899                 }
4900                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4901                 return 1;
4902         }
4903         return 0;
4904 }
4905
4906 static int loopback_test(struct slgt_info *info)
4907 {
4908 #define TESTFRAMESIZE 20
4909
4910         unsigned long timeout;
4911         u16 count = TESTFRAMESIZE;
4912         unsigned char buf[TESTFRAMESIZE];
4913         int rc = -ENODEV;
4914         unsigned long flags;
4915
4916         struct tty_struct *oldtty = info->port.tty;
4917         MGSL_PARAMS params;
4918
4919         memcpy(&params, &info->params, sizeof(params));
4920
4921         info->params.mode = MGSL_MODE_ASYNC;
4922         info->params.data_rate = 921600;
4923         info->params.loopback = 1;
4924         info->port.tty = NULL;
4925
4926         /* build and send transmit frame */
4927         for (count = 0; count < TESTFRAMESIZE; ++count)
4928                 buf[count] = (unsigned char)count;
4929
4930         info->tmp_rbuf_count = 0;
4931         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4932
4933         /* program hardware for HDLC and enabled receiver */
4934         spin_lock_irqsave(&info->lock,flags);
4935         async_mode(info);
4936         rx_start(info);
4937         info->tx_count = count;
4938         tx_load(info, buf, count);
4939         tx_start(info);
4940         spin_unlock_irqrestore(&info->lock, flags);
4941
4942         /* wait for receive complete */
4943         for (timeout = 100; timeout; --timeout) {
4944                 msleep_interruptible(10);
4945                 if (loopback_test_rx(info)) {
4946                         rc = 0;
4947                         break;
4948                 }
4949         }
4950
4951         /* verify received frame length and contents */
4952         if (!rc && (info->tmp_rbuf_count != count ||
4953                   memcmp(buf, info->tmp_rbuf, count))) {
4954                 rc = -ENODEV;
4955         }
4956
4957         spin_lock_irqsave(&info->lock,flags);
4958         reset_adapter(info);
4959         spin_unlock_irqrestore(&info->lock,flags);
4960
4961         memcpy(&info->params, &params, sizeof(info->params));
4962         info->port.tty = oldtty;
4963
4964         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4965         return rc;
4966 }
4967
4968 static int adapter_test(struct slgt_info *info)
4969 {
4970         DBGINFO(("testing %s\n", info->device_name));
4971         if (register_test(info) < 0) {
4972                 printk("register test failure %s addr=%08X\n",
4973                         info->device_name, info->phys_reg_addr);
4974         } else if (irq_test(info) < 0) {
4975                 printk("IRQ test failure %s IRQ=%d\n",
4976                         info->device_name, info->irq_level);
4977         } else if (loopback_test(info) < 0) {
4978                 printk("loopback test failure %s\n", info->device_name);
4979         }
4980         return info->init_error;
4981 }
4982
4983 /*
4984  * transmit timeout handler
4985  */
4986 static void tx_timeout(unsigned long context)
4987 {
4988         struct slgt_info *info = (struct slgt_info*)context;
4989         unsigned long flags;
4990
4991         DBGINFO(("%s tx_timeout\n", info->device_name));
4992         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4993                 info->icount.txtimeout++;
4994         }
4995         spin_lock_irqsave(&info->lock,flags);
4996         tx_stop(info);
4997         spin_unlock_irqrestore(&info->lock,flags);
4998
4999 #if SYNCLINK_GENERIC_HDLC
5000         if (info->netcount)
5001                 hdlcdev_tx_done(info);
5002         else
5003 #endif
5004                 bh_transmit(info);
5005 }
5006
5007 /*
5008  * receive buffer polling timer
5009  */
5010 static void rx_timeout(unsigned long context)
5011 {
5012         struct slgt_info *info = (struct slgt_info*)context;
5013         unsigned long flags;
5014
5015         DBGINFO(("%s rx_timeout\n", info->device_name));
5016         spin_lock_irqsave(&info->lock, flags);
5017         info->pending_bh |= BH_RECEIVE;
5018         spin_unlock_irqrestore(&info->lock, flags);
5019         bh_handler(&info->task);
5020 }
5021