hwrng: omap - Fix RNG wait loop timeout
[sfrench/cifs-2.6.git] / drivers / char / hw_random / omap-rng.c
1 /*
2  * omap-rng.c - RNG driver for TI OMAP CPU family
3  *
4  * Author: Deepak Saxena <dsaxena@plexity.net>
5  *
6  * Copyright 2005 (c) MontaVista Software, Inc.
7  *
8  * Mostly based on original driver:
9  *
10  * Copyright (C) 2005 Nokia Corporation
11  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
12  *
13  * This file is licensed under  the terms of the GNU General Public
14  * License version 2. This program is licensed "as is" without any
15  * warranty of any kind, whether express or implied.
16  */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/random.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/hw_random.h>
24 #include <linux/delay.h>
25 #include <linux/slab.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/of.h>
28 #include <linux/of_device.h>
29 #include <linux/of_address.h>
30 #include <linux/interrupt.h>
31 #include <linux/clk.h>
32
33 #include <asm/io.h>
34
35 #define RNG_REG_STATUS_RDY                      (1 << 0)
36
37 #define RNG_REG_INTACK_RDY_MASK                 (1 << 0)
38 #define RNG_REG_INTACK_SHUTDOWN_OFLO_MASK       (1 << 1)
39 #define RNG_SHUTDOWN_OFLO_MASK                  (1 << 1)
40
41 #define RNG_CONTROL_STARTUP_CYCLES_SHIFT        16
42 #define RNG_CONTROL_STARTUP_CYCLES_MASK         (0xffff << 16)
43 #define RNG_CONTROL_ENABLE_TRNG_SHIFT           10
44 #define RNG_CONTROL_ENABLE_TRNG_MASK            (1 << 10)
45
46 #define RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT       16
47 #define RNG_CONFIG_MAX_REFIL_CYCLES_MASK        (0xffff << 16)
48 #define RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT       0
49 #define RNG_CONFIG_MIN_REFIL_CYCLES_MASK        (0xff << 0)
50
51 #define RNG_CONTROL_STARTUP_CYCLES              0xff
52 #define RNG_CONFIG_MIN_REFIL_CYCLES             0x21
53 #define RNG_CONFIG_MAX_REFIL_CYCLES             0x22
54
55 #define RNG_ALARMCNT_ALARM_TH_SHIFT             0x0
56 #define RNG_ALARMCNT_ALARM_TH_MASK              (0xff << 0)
57 #define RNG_ALARMCNT_SHUTDOWN_TH_SHIFT          16
58 #define RNG_ALARMCNT_SHUTDOWN_TH_MASK           (0x1f << 16)
59 #define RNG_ALARM_THRESHOLD                     0xff
60 #define RNG_SHUTDOWN_THRESHOLD                  0x4
61
62 #define RNG_REG_FROENABLE_MASK                  0xffffff
63 #define RNG_REG_FRODETUNE_MASK                  0xffffff
64
65 #define OMAP2_RNG_OUTPUT_SIZE                   0x4
66 #define OMAP4_RNG_OUTPUT_SIZE                   0x8
67 #define EIP76_RNG_OUTPUT_SIZE                   0x10
68
69 /*
70  * EIP76 RNG takes approx. 700us to produce 16 bytes of output data
71  * as per testing results. And to account for the lack of udelay()'s
72  * reliability, we keep the timeout as 1000us.
73  */
74 #define RNG_DATA_FILL_TIMEOUT                   100
75
76 enum {
77         RNG_OUTPUT_0_REG = 0,
78         RNG_OUTPUT_1_REG,
79         RNG_OUTPUT_2_REG,
80         RNG_OUTPUT_3_REG,
81         RNG_STATUS_REG,
82         RNG_INTMASK_REG,
83         RNG_INTACK_REG,
84         RNG_CONTROL_REG,
85         RNG_CONFIG_REG,
86         RNG_ALARMCNT_REG,
87         RNG_FROENABLE_REG,
88         RNG_FRODETUNE_REG,
89         RNG_ALARMMASK_REG,
90         RNG_ALARMSTOP_REG,
91         RNG_REV_REG,
92         RNG_SYSCONFIG_REG,
93 };
94
95 static const u16 reg_map_omap2[] = {
96         [RNG_OUTPUT_0_REG]      = 0x0,
97         [RNG_STATUS_REG]        = 0x4,
98         [RNG_CONFIG_REG]        = 0x28,
99         [RNG_REV_REG]           = 0x3c,
100         [RNG_SYSCONFIG_REG]     = 0x40,
101 };
102
103 static const u16 reg_map_omap4[] = {
104         [RNG_OUTPUT_0_REG]      = 0x0,
105         [RNG_OUTPUT_1_REG]      = 0x4,
106         [RNG_STATUS_REG]        = 0x8,
107         [RNG_INTMASK_REG]       = 0xc,
108         [RNG_INTACK_REG]        = 0x10,
109         [RNG_CONTROL_REG]       = 0x14,
110         [RNG_CONFIG_REG]        = 0x18,
111         [RNG_ALARMCNT_REG]      = 0x1c,
112         [RNG_FROENABLE_REG]     = 0x20,
113         [RNG_FRODETUNE_REG]     = 0x24,
114         [RNG_ALARMMASK_REG]     = 0x28,
115         [RNG_ALARMSTOP_REG]     = 0x2c,
116         [RNG_REV_REG]           = 0x1FE0,
117         [RNG_SYSCONFIG_REG]     = 0x1FE4,
118 };
119
120 static const u16 reg_map_eip76[] = {
121         [RNG_OUTPUT_0_REG]      = 0x0,
122         [RNG_OUTPUT_1_REG]      = 0x4,
123         [RNG_OUTPUT_2_REG]      = 0x8,
124         [RNG_OUTPUT_3_REG]      = 0xc,
125         [RNG_STATUS_REG]        = 0x10,
126         [RNG_INTACK_REG]        = 0x10,
127         [RNG_CONTROL_REG]       = 0x14,
128         [RNG_CONFIG_REG]        = 0x18,
129         [RNG_ALARMCNT_REG]      = 0x1c,
130         [RNG_FROENABLE_REG]     = 0x20,
131         [RNG_FRODETUNE_REG]     = 0x24,
132         [RNG_ALARMMASK_REG]     = 0x28,
133         [RNG_ALARMSTOP_REG]     = 0x2c,
134         [RNG_REV_REG]           = 0x7c,
135 };
136
137 struct omap_rng_dev;
138 /**
139  * struct omap_rng_pdata - RNG IP block-specific data
140  * @regs: Pointer to the register offsets structure.
141  * @data_size: No. of bytes in RNG output.
142  * @data_present: Callback to determine if data is available.
143  * @init: Callback for IP specific initialization sequence.
144  * @cleanup: Callback for IP specific cleanup sequence.
145  */
146 struct omap_rng_pdata {
147         u16     *regs;
148         u32     data_size;
149         u32     (*data_present)(struct omap_rng_dev *priv);
150         int     (*init)(struct omap_rng_dev *priv);
151         void    (*cleanup)(struct omap_rng_dev *priv);
152 };
153
154 struct omap_rng_dev {
155         void __iomem                    *base;
156         struct device                   *dev;
157         const struct omap_rng_pdata     *pdata;
158         struct hwrng rng;
159         struct clk                      *clk;
160         struct clk                      *clk_reg;
161 };
162
163 static inline u32 omap_rng_read(struct omap_rng_dev *priv, u16 reg)
164 {
165         return __raw_readl(priv->base + priv->pdata->regs[reg]);
166 }
167
168 static inline void omap_rng_write(struct omap_rng_dev *priv, u16 reg,
169                                       u32 val)
170 {
171         __raw_writel(val, priv->base + priv->pdata->regs[reg]);
172 }
173
174
175 static int omap_rng_do_read(struct hwrng *rng, void *data, size_t max,
176                             bool wait)
177 {
178         struct omap_rng_dev *priv;
179         int i, present;
180
181         priv = (struct omap_rng_dev *)rng->priv;
182
183         if (max < priv->pdata->data_size)
184                 return 0;
185
186         for (i = 0; i < RNG_DATA_FILL_TIMEOUT; i++) {
187                 present = priv->pdata->data_present(priv);
188                 if (present || !wait)
189                         break;
190
191                 udelay(10);
192         }
193         if (!present)
194                 return 0;
195
196         memcpy_fromio(data, priv->base + priv->pdata->regs[RNG_OUTPUT_0_REG],
197                       priv->pdata->data_size);
198
199         if (priv->pdata->regs[RNG_INTACK_REG])
200                 omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_RDY_MASK);
201
202         return priv->pdata->data_size;
203 }
204
205 static int omap_rng_init(struct hwrng *rng)
206 {
207         struct omap_rng_dev *priv;
208
209         priv = (struct omap_rng_dev *)rng->priv;
210         return priv->pdata->init(priv);
211 }
212
213 static void omap_rng_cleanup(struct hwrng *rng)
214 {
215         struct omap_rng_dev *priv;
216
217         priv = (struct omap_rng_dev *)rng->priv;
218         priv->pdata->cleanup(priv);
219 }
220
221
222 static inline u32 omap2_rng_data_present(struct omap_rng_dev *priv)
223 {
224         return omap_rng_read(priv, RNG_STATUS_REG) ? 0 : 1;
225 }
226
227 static int omap2_rng_init(struct omap_rng_dev *priv)
228 {
229         omap_rng_write(priv, RNG_SYSCONFIG_REG, 0x1);
230         return 0;
231 }
232
233 static void omap2_rng_cleanup(struct omap_rng_dev *priv)
234 {
235         omap_rng_write(priv, RNG_SYSCONFIG_REG, 0x0);
236 }
237
238 static struct omap_rng_pdata omap2_rng_pdata = {
239         .regs           = (u16 *)reg_map_omap2,
240         .data_size      = OMAP2_RNG_OUTPUT_SIZE,
241         .data_present   = omap2_rng_data_present,
242         .init           = omap2_rng_init,
243         .cleanup        = omap2_rng_cleanup,
244 };
245
246 #if defined(CONFIG_OF)
247 static inline u32 omap4_rng_data_present(struct omap_rng_dev *priv)
248 {
249         return omap_rng_read(priv, RNG_STATUS_REG) & RNG_REG_STATUS_RDY;
250 }
251
252 static int eip76_rng_init(struct omap_rng_dev *priv)
253 {
254         u32 val;
255
256         /* Return if RNG is already running. */
257         if (omap_rng_read(priv, RNG_CONTROL_REG) & RNG_CONTROL_ENABLE_TRNG_MASK)
258                 return 0;
259
260         /*  Number of 512 bit blocks of raw Noise Source output data that must
261          *  be processed by either the Conditioning Function or the
262          *  SP 800-90 DRBG ‘BC_DF’ functionality to yield a ‘full entropy’
263          *  output value.
264          */
265         val = 0x5 << RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT;
266
267         /* Number of FRO samples that are XOR-ed together into one bit to be
268          * shifted into the main shift register
269          */
270         val |= RNG_CONFIG_MAX_REFIL_CYCLES << RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT;
271         omap_rng_write(priv, RNG_CONFIG_REG, val);
272
273         /* Enable all available FROs */
274         omap_rng_write(priv, RNG_FRODETUNE_REG, 0x0);
275         omap_rng_write(priv, RNG_FROENABLE_REG, RNG_REG_FROENABLE_MASK);
276
277         /* Enable TRNG */
278         val = RNG_CONTROL_ENABLE_TRNG_MASK;
279         omap_rng_write(priv, RNG_CONTROL_REG, val);
280
281         return 0;
282 }
283
284 static int omap4_rng_init(struct omap_rng_dev *priv)
285 {
286         u32 val;
287
288         /* Return if RNG is already running. */
289         if (omap_rng_read(priv, RNG_CONTROL_REG) & RNG_CONTROL_ENABLE_TRNG_MASK)
290                 return 0;
291
292         val = RNG_CONFIG_MIN_REFIL_CYCLES << RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT;
293         val |= RNG_CONFIG_MAX_REFIL_CYCLES << RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT;
294         omap_rng_write(priv, RNG_CONFIG_REG, val);
295
296         omap_rng_write(priv, RNG_FRODETUNE_REG, 0x0);
297         omap_rng_write(priv, RNG_FROENABLE_REG, RNG_REG_FROENABLE_MASK);
298         val = RNG_ALARM_THRESHOLD << RNG_ALARMCNT_ALARM_TH_SHIFT;
299         val |= RNG_SHUTDOWN_THRESHOLD << RNG_ALARMCNT_SHUTDOWN_TH_SHIFT;
300         omap_rng_write(priv, RNG_ALARMCNT_REG, val);
301
302         val = RNG_CONTROL_STARTUP_CYCLES << RNG_CONTROL_STARTUP_CYCLES_SHIFT;
303         val |= RNG_CONTROL_ENABLE_TRNG_MASK;
304         omap_rng_write(priv, RNG_CONTROL_REG, val);
305
306         return 0;
307 }
308
309 static void omap4_rng_cleanup(struct omap_rng_dev *priv)
310 {
311         int val;
312
313         val = omap_rng_read(priv, RNG_CONTROL_REG);
314         val &= ~RNG_CONTROL_ENABLE_TRNG_MASK;
315         omap_rng_write(priv, RNG_CONTROL_REG, val);
316 }
317
318 static irqreturn_t omap4_rng_irq(int irq, void *dev_id)
319 {
320         struct omap_rng_dev *priv = dev_id;
321         u32 fro_detune, fro_enable;
322
323         /*
324          * Interrupt raised by a fro shutdown threshold, do the following:
325          * 1. Clear the alarm events.
326          * 2. De tune the FROs which are shutdown.
327          * 3. Re enable the shutdown FROs.
328          */
329         omap_rng_write(priv, RNG_ALARMMASK_REG, 0x0);
330         omap_rng_write(priv, RNG_ALARMSTOP_REG, 0x0);
331
332         fro_enable = omap_rng_read(priv, RNG_FROENABLE_REG);
333         fro_detune = ~fro_enable & RNG_REG_FRODETUNE_MASK;
334         fro_detune = fro_detune | omap_rng_read(priv, RNG_FRODETUNE_REG);
335         fro_enable = RNG_REG_FROENABLE_MASK;
336
337         omap_rng_write(priv, RNG_FRODETUNE_REG, fro_detune);
338         omap_rng_write(priv, RNG_FROENABLE_REG, fro_enable);
339
340         omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_SHUTDOWN_OFLO_MASK);
341
342         return IRQ_HANDLED;
343 }
344
345 static struct omap_rng_pdata omap4_rng_pdata = {
346         .regs           = (u16 *)reg_map_omap4,
347         .data_size      = OMAP4_RNG_OUTPUT_SIZE,
348         .data_present   = omap4_rng_data_present,
349         .init           = omap4_rng_init,
350         .cleanup        = omap4_rng_cleanup,
351 };
352
353 static struct omap_rng_pdata eip76_rng_pdata = {
354         .regs           = (u16 *)reg_map_eip76,
355         .data_size      = EIP76_RNG_OUTPUT_SIZE,
356         .data_present   = omap4_rng_data_present,
357         .init           = eip76_rng_init,
358         .cleanup        = omap4_rng_cleanup,
359 };
360
361 static const struct of_device_id omap_rng_of_match[] = {
362                 {
363                         .compatible     = "ti,omap2-rng",
364                         .data           = &omap2_rng_pdata,
365                 },
366                 {
367                         .compatible     = "ti,omap4-rng",
368                         .data           = &omap4_rng_pdata,
369                 },
370                 {
371                         .compatible     = "inside-secure,safexcel-eip76",
372                         .data           = &eip76_rng_pdata,
373                 },
374                 {},
375 };
376 MODULE_DEVICE_TABLE(of, omap_rng_of_match);
377
378 static int of_get_omap_rng_device_details(struct omap_rng_dev *priv,
379                                           struct platform_device *pdev)
380 {
381         const struct of_device_id *match;
382         struct device *dev = &pdev->dev;
383         int irq, err;
384
385         match = of_match_device(of_match_ptr(omap_rng_of_match), dev);
386         if (!match) {
387                 dev_err(dev, "no compatible OF match\n");
388                 return -EINVAL;
389         }
390         priv->pdata = match->data;
391
392         if (of_device_is_compatible(dev->of_node, "ti,omap4-rng") ||
393             of_device_is_compatible(dev->of_node, "inside-secure,safexcel-eip76")) {
394                 irq = platform_get_irq(pdev, 0);
395                 if (irq < 0) {
396                         dev_err(dev, "%s: error getting IRQ resource - %d\n",
397                                 __func__, irq);
398                         return irq;
399                 }
400
401                 err = devm_request_irq(dev, irq, omap4_rng_irq,
402                                        IRQF_TRIGGER_NONE, dev_name(dev), priv);
403                 if (err) {
404                         dev_err(dev, "unable to request irq %d, err = %d\n",
405                                 irq, err);
406                         return err;
407                 }
408
409                 /*
410                  * On OMAP4, enabling the shutdown_oflo interrupt is
411                  * done in the interrupt mask register. There is no
412                  * such register on EIP76, and it's enabled by the
413                  * same bit in the control register
414                  */
415                 if (priv->pdata->regs[RNG_INTMASK_REG])
416                         omap_rng_write(priv, RNG_INTMASK_REG,
417                                        RNG_SHUTDOWN_OFLO_MASK);
418                 else
419                         omap_rng_write(priv, RNG_CONTROL_REG,
420                                        RNG_SHUTDOWN_OFLO_MASK);
421         }
422         return 0;
423 }
424 #else
425 static int of_get_omap_rng_device_details(struct omap_rng_dev *omap_rng,
426                                           struct platform_device *pdev)
427 {
428         return -EINVAL;
429 }
430 #endif
431
432 static int get_omap_rng_device_details(struct omap_rng_dev *omap_rng)
433 {
434         /* Only OMAP2/3 can be non-DT */
435         omap_rng->pdata = &omap2_rng_pdata;
436         return 0;
437 }
438
439 static int omap_rng_probe(struct platform_device *pdev)
440 {
441         struct omap_rng_dev *priv;
442         struct resource *res;
443         struct device *dev = &pdev->dev;
444         int ret;
445
446         priv = devm_kzalloc(dev, sizeof(struct omap_rng_dev), GFP_KERNEL);
447         if (!priv)
448                 return -ENOMEM;
449
450         priv->rng.read = omap_rng_do_read;
451         priv->rng.init = omap_rng_init;
452         priv->rng.cleanup = omap_rng_cleanup;
453         priv->rng.quality = 900;
454
455         priv->rng.priv = (unsigned long)priv;
456         platform_set_drvdata(pdev, priv);
457         priv->dev = dev;
458
459         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
460         priv->base = devm_ioremap_resource(dev, res);
461         if (IS_ERR(priv->base)) {
462                 ret = PTR_ERR(priv->base);
463                 goto err_ioremap;
464         }
465
466         priv->rng.name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
467         if (!priv->rng.name) {
468                 ret = -ENOMEM;
469                 goto err_ioremap;
470         }
471
472         pm_runtime_enable(&pdev->dev);
473         ret = pm_runtime_get_sync(&pdev->dev);
474         if (ret < 0) {
475                 dev_err(&pdev->dev, "Failed to runtime_get device: %d\n", ret);
476                 pm_runtime_put_noidle(&pdev->dev);
477                 goto err_ioremap;
478         }
479
480         priv->clk = devm_clk_get(&pdev->dev, NULL);
481         if (IS_ERR(priv->clk) && PTR_ERR(priv->clk) == -EPROBE_DEFER)
482                 return -EPROBE_DEFER;
483         if (!IS_ERR(priv->clk)) {
484                 ret = clk_prepare_enable(priv->clk);
485                 if (ret) {
486                         dev_err(&pdev->dev,
487                                 "Unable to enable the clk: %d\n", ret);
488                         goto err_register;
489                 }
490         }
491
492         priv->clk_reg = devm_clk_get(&pdev->dev, "reg");
493         if (IS_ERR(priv->clk_reg) && PTR_ERR(priv->clk_reg) == -EPROBE_DEFER)
494                 return -EPROBE_DEFER;
495         if (!IS_ERR(priv->clk_reg)) {
496                 ret = clk_prepare_enable(priv->clk_reg);
497                 if (ret) {
498                         dev_err(&pdev->dev,
499                                 "Unable to enable the register clk: %d\n",
500                                 ret);
501                         goto err_register;
502                 }
503         }
504
505         ret = (dev->of_node) ? of_get_omap_rng_device_details(priv, pdev) :
506                                 get_omap_rng_device_details(priv);
507         if (ret)
508                 goto err_register;
509
510         ret = devm_hwrng_register(&pdev->dev, &priv->rng);
511         if (ret)
512                 goto err_register;
513
514         dev_info(&pdev->dev, "Random Number Generator ver. %02x\n",
515                  omap_rng_read(priv, RNG_REV_REG));
516
517         return 0;
518
519 err_register:
520         priv->base = NULL;
521         pm_runtime_put_sync(&pdev->dev);
522         pm_runtime_disable(&pdev->dev);
523
524         clk_disable_unprepare(priv->clk_reg);
525         clk_disable_unprepare(priv->clk);
526 err_ioremap:
527         dev_err(dev, "initialization failed.\n");
528         return ret;
529 }
530
531 static int omap_rng_remove(struct platform_device *pdev)
532 {
533         struct omap_rng_dev *priv = platform_get_drvdata(pdev);
534
535
536         priv->pdata->cleanup(priv);
537
538         pm_runtime_put_sync(&pdev->dev);
539         pm_runtime_disable(&pdev->dev);
540
541         clk_disable_unprepare(priv->clk);
542         clk_disable_unprepare(priv->clk_reg);
543
544         return 0;
545 }
546
547 static int __maybe_unused omap_rng_suspend(struct device *dev)
548 {
549         struct omap_rng_dev *priv = dev_get_drvdata(dev);
550
551         priv->pdata->cleanup(priv);
552         pm_runtime_put_sync(dev);
553
554         return 0;
555 }
556
557 static int __maybe_unused omap_rng_resume(struct device *dev)
558 {
559         struct omap_rng_dev *priv = dev_get_drvdata(dev);
560         int ret;
561
562         ret = pm_runtime_get_sync(dev);
563         if (ret < 0) {
564                 dev_err(dev, "Failed to runtime_get device: %d\n", ret);
565                 pm_runtime_put_noidle(dev);
566                 return ret;
567         }
568
569         priv->pdata->init(priv);
570
571         return 0;
572 }
573
574 static SIMPLE_DEV_PM_OPS(omap_rng_pm, omap_rng_suspend, omap_rng_resume);
575
576 static struct platform_driver omap_rng_driver = {
577         .driver = {
578                 .name           = "omap_rng",
579                 .pm             = &omap_rng_pm,
580                 .of_match_table = of_match_ptr(omap_rng_of_match),
581         },
582         .probe          = omap_rng_probe,
583         .remove         = omap_rng_remove,
584 };
585
586 module_platform_driver(omap_rng_driver);
587 MODULE_ALIAS("platform:omap_rng");
588 MODULE_AUTHOR("Deepak Saxena (and others)");
589 MODULE_LICENSE("GPL");