drivers/char/drm/via_dma.c

   1 /* via_dma.c -- DMA support for the VIA Unichrome/Pro
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
   7  * All Rights Reserved.
   8  *
   9  * Copyright 2004 The Unichrome project.
  10  * All Rights Reserved.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a
  13  * copy of this software and associated documentation files (the "Software"),
  14  * to deal in the Software without restriction, including without limitation
  15  * the rights to use, copy, modify, merge, publish, distribute, sub license,
  16  * and/or sell copies of the Software, and to permit persons to whom the
  17  * Software is furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice (including the
  20  * next paragraph) shall be included in all copies or substantial portions
  21  * of the Software.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  24  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  25  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  26  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  27  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  28  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  29  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  30  *
  31  * Authors:
  32  *    Tungsten Graphics,
  33  *    Erdi Chen,
  34  *    Thomas Hellstrom.
  35  */
  36
  37 #include "drmP.h"
  38 #include "drm.h"
  39 #include "via_drm.h"
  40 #include "via_drv.h"
  41 #include "via_3d_reg.h"
  42
  43 #define CMDBUF_ALIGNMENT_SIZE   (0x100)
  44 #define CMDBUF_ALIGNMENT_MASK   (0x0ff)
  45
  46 /* defines for VIA 3D registers */
  47 #define VIA_REG_STATUS          0x400
  48 #define VIA_REG_TRANSET         0x43C
  49 #define VIA_REG_TRANSPACE       0x440
  50
  51 /* VIA_REG_STATUS(0x400): Engine Status */
  52 #define VIA_CMD_RGTR_BUSY       0x00000080      /* Command Regulator is busy */
  53 #define VIA_2D_ENG_BUSY         0x00000001      /* 2D Engine is busy */
  54 #define VIA_3D_ENG_BUSY         0x00000002      /* 3D Engine is busy */
  55 #define VIA_VR_QUEUE_BUSY       0x00020000      /* Virtual Queue is busy */
  56
  57 #define SetReg2DAGP(nReg, nData) {                              \
  58         *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1;  \
  59         *((uint32_t *)(vb) + 1) = (nData);                      \
  60         vb = ((uint32_t *)vb) + 2;                              \
  61         dev_priv->dma_low +=8;                                  \
  62 }
  63
  64 #define via_flush_write_combine() DRM_MEMORYBARRIER()
  65
  66 #define VIA_OUT_RING_QW(w1,w2)                  \
  67         *vb++ = (w1);                           \
  68         *vb++ = (w2);                           \
  69         dev_priv->dma_low += 8;
  70
  71 static void via_cmdbuf_start(drm_via_private_t * dev_priv);
  72 static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
  73 static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
  74 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv);
  75 static int via_wait_idle(drm_via_private_t * dev_priv);
  76 static void via_pad_cache(drm_via_private_t * dev_priv, int qwords);
  77
  78 /*
  79  * Free space in command buffer.
  80  */
  81
  82 static uint32_t via_cmdbuf_space(drm_via_private_t * dev_priv)
  83 {
  84         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
  85         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
  86
  87         return ((hw_addr <= dev_priv->dma_low) ?
  88                 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
  89                 (hw_addr - dev_priv->dma_low));
  90 }
  91
  92 /*
  93  * How much does the command regulator lag behind?
  94  */
  95
  96 static uint32_t via_cmdbuf_lag(drm_via_private_t * dev_priv)
  97 {
  98         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
  99         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
 100
 101         return ((hw_addr <= dev_priv->dma_low) ?
 102                 (dev_priv->dma_low - hw_addr) :
 103                 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));
 104 }
 105
 106 /*
 107  * Check that the given size fits in the buffer, otherwise wait.
 108  */
 109
 110 static inline int
 111 via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
 112 {
 113         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 114         uint32_t cur_addr, hw_addr, next_addr;
 115         volatile uint32_t *hw_addr_ptr;
 116         uint32_t count;
 117         hw_addr_ptr = dev_priv->hw_addr_ptr;
 118         cur_addr = dev_priv->dma_low;
 119         next_addr = cur_addr + size + 512 * 1024;
 120         count = 1000000;
 121         do {
 122                 hw_addr = *hw_addr_ptr - agp_base;
 123                 if (count-- == 0) {
 124                         DRM_ERROR
 125                             ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",
 126                              hw_addr, cur_addr, next_addr);
 127                         return -1;
 128                 }
 129         } while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
 130         return 0;
 131 }
 132
 133 /*
 134  * Checks whether buffer head has reach the end. Rewind the ring buffer
 135  * when necessary.
 136  *
 137  * Returns virtual pointer to ring buffer.
 138  */
 139
 140 static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
 141                                       unsigned int size)
 142 {
 143         if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) >
 144             dev_priv->dma_high) {
 145                 via_cmdbuf_rewind(dev_priv);
 146         }
 147         if (via_cmdbuf_wait(dev_priv, size) != 0) {
 148                 return NULL;
 149         }
 150
 151         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
 152 }
 153
 154 int via_dma_cleanup(struct drm_device * dev)
 155 {
 156         if (dev->dev_private) {
 157                 drm_via_private_t *dev_priv =
 158                     (drm_via_private_t *) dev->dev_private;
 159
 160                 if (dev_priv->ring.virtual_start) {
 161                         via_cmdbuf_reset(dev_priv);
 162
 163                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
 164                         dev_priv->ring.virtual_start = NULL;
 165                 }
 166
 167         }
 168
 169         return 0;
 170 }
 171
 172 static int via_initialize(struct drm_device * dev,
 173                           drm_via_private_t * dev_priv,
 174                           drm_via_dma_init_t * init)
 175 {
 176         if (!dev_priv || !dev_priv->mmio) {
 177                 DRM_ERROR("via_dma_init called before via_map_init\n");
 178                 return DRM_ERR(EFAULT);
 179         }
 180
 181         if (dev_priv->ring.virtual_start != NULL) {
 182                 DRM_ERROR("%s called again without calling cleanup\n",
 183                           __FUNCTION__);
 184                 return DRM_ERR(EFAULT);
 185         }
 186
 187         if (!dev->agp || !dev->agp->base) {
 188                 DRM_ERROR("%s called with no agp memory available\n",
 189                           __FUNCTION__);
 190                 return DRM_ERR(EFAULT);
 191         }
 192
 193         if (dev_priv->chipset == VIA_DX9_0) {
 194                 DRM_ERROR("AGP DMA is not supported on this chip\n");
 195                 return DRM_ERR(EINVAL);
 196         }
 197
 198         dev_priv->ring.map.offset = dev->agp->base + init->offset;
 199         dev_priv->ring.map.size = init->size;
 200         dev_priv->ring.map.type = 0;
 201         dev_priv->ring.map.flags = 0;
 202         dev_priv->ring.map.mtrr = 0;
 203
 204         drm_core_ioremap(&dev_priv->ring.map, dev);
 205
 206         if (dev_priv->ring.map.handle == NULL) {
 207                 via_dma_cleanup(dev);
 208                 DRM_ERROR("can not ioremap virtual address for"
 209                           " ring buffer\n");
 210                 return DRM_ERR(ENOMEM);
 211         }
 212
 213         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 214
 215         dev_priv->dma_ptr = dev_priv->ring.virtual_start;
 216         dev_priv->dma_low = 0;
 217         dev_priv->dma_high = init->size;
 218         dev_priv->dma_wrap = init->size;
 219         dev_priv->dma_offset = init->offset;
 220         dev_priv->last_pause_ptr = NULL;
 221         dev_priv->hw_addr_ptr =
 222                 (volatile uint32_t *)((char *)dev_priv->mmio->handle +
 223                 init->reg_pause_addr);
 224
 225         via_cmdbuf_start(dev_priv);
 226
 227         return 0;
 228 }
 229
 230 static int via_dma_init(DRM_IOCTL_ARGS)
 231 {
 232         DRM_DEVICE;
 233         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
 234         drm_via_dma_init_t init;
 235         int retcode = 0;
 236
 237         DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t __user *) data,
 238                                  sizeof(init));
 239
 240         switch (init.func) {
 241         case VIA_INIT_DMA:
 242                 if (!DRM_SUSER(DRM_CURPROC))
 243                         retcode = DRM_ERR(EPERM);
 244                 else
 245                         retcode = via_initialize(dev, dev_priv, &init);
 246                 break;
 247         case VIA_CLEANUP_DMA:
 248                 if (!DRM_SUSER(DRM_CURPROC))
 249                         retcode = DRM_ERR(EPERM);
 250                 else
 251                         retcode = via_dma_cleanup(dev);
 252                 break;
 253         case VIA_DMA_INITIALIZED:
 254                 retcode = (dev_priv->ring.virtual_start != NULL) ?
 255                         0 : DRM_ERR(EFAULT);
 256                 break;
 257         default:
 258                 retcode = DRM_ERR(EINVAL);
 259                 break;
 260         }
 261
 262         return retcode;
 263 }
 264
 265 static int via_dispatch_cmdbuffer(struct drm_device * dev, drm_via_cmdbuffer_t * cmd)
 266 {
 267         drm_via_private_t *dev_priv;
 268         uint32_t *vb;
 269         int ret;
 270
 271         dev_priv = (drm_via_private_t *) dev->dev_private;
 272
 273         if (dev_priv->ring.virtual_start == NULL) {
 274                 DRM_ERROR("%s called without initializing AGP ring buffer.\n",
 275                           __FUNCTION__);
 276                 return DRM_ERR(EFAULT);
 277         }
 278
 279         if (cmd->size > VIA_PCI_BUF_SIZE) {
 280                 return DRM_ERR(ENOMEM);
 281         }
 282
 283         if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
 284                 return DRM_ERR(EFAULT);
 285
 286         /*
 287          * Running this function on AGP memory is dead slow. Therefore
 288          * we run it on a temporary cacheable system memory buffer and
 289          * copy it to AGP memory when ready.
 290          */
 291
 292         if ((ret =
 293              via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
 294                                        cmd->size, dev, 1))) {
 295                 return ret;
 296         }
 297
 298         vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);
 299         if (vb == NULL) {
 300                 return DRM_ERR(EAGAIN);
 301         }
 302
 303         memcpy(vb, dev_priv->pci_buf, cmd->size);
 304
 305         dev_priv->dma_low += cmd->size;
 306
 307         /*
 308          * Small submissions somehow stalls the CPU. (AGP cache effects?)
 309          * pad to greater size.
 310          */
 311
 312         if (cmd->size < 0x100)
 313                 via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3);
 314         via_cmdbuf_pause(dev_priv);
 315
 316         return 0;
 317 }
 318
 319 int via_driver_dma_quiescent(struct drm_device * dev)
 320 {
 321         drm_via_private_t *dev_priv = dev->dev_private;
 322
 323         if (!via_wait_idle(dev_priv)) {
 324                 return DRM_ERR(EBUSY);
 325         }
 326         return 0;
 327 }
 328
 329 static int via_flush_ioctl(DRM_IOCTL_ARGS)
 330 {
 331         DRM_DEVICE;
 332
 333         LOCK_TEST_WITH_RETURN(dev, filp);
 334
 335         return via_driver_dma_quiescent(dev);
 336 }
 337
 338 static int via_cmdbuffer(DRM_IOCTL_ARGS)
 339 {
 340         DRM_DEVICE;
 341         drm_via_cmdbuffer_t cmdbuf;
 342         int ret;
 343
 344         LOCK_TEST_WITH_RETURN(dev, filp);
 345
 346         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
 347                                  sizeof(cmdbuf));
 348
 349         DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf.buf, cmdbuf.size);
 350
 351         ret = via_dispatch_cmdbuffer(dev, &cmdbuf);
 352         if (ret) {
 353                 return ret;
 354         }
 355
 356         return 0;
 357 }
 358
 359 static int via_dispatch_pci_cmdbuffer(struct drm_device * dev,
 360                                       drm_via_cmdbuffer_t * cmd)
 361 {
 362         drm_via_private_t *dev_priv = dev->dev_private;
 363         int ret;
 364
 365         if (cmd->size > VIA_PCI_BUF_SIZE) {
 366                 return DRM_ERR(ENOMEM);
 367         }
 368         if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
 369                 return DRM_ERR(EFAULT);
 370
 371         if ((ret =
 372              via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
 373                                        cmd->size, dev, 0))) {
 374                 return ret;
 375         }
 376
 377         ret =
 378             via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf,
 379                                      cmd->size);
 380         return ret;
 381 }
 382
 383 static int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
 384 {
 385         DRM_DEVICE;
 386         drm_via_cmdbuffer_t cmdbuf;
 387         int ret;
 388
 389         LOCK_TEST_WITH_RETURN(dev, filp);
 390
 391         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
 392                                  sizeof(cmdbuf));
 393
 394         DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf.buf,
 395                   cmdbuf.size);
 396
 397         ret = via_dispatch_pci_cmdbuffer(dev, &cmdbuf);
 398         if (ret) {
 399                 return ret;
 400         }
 401
 402         return 0;
 403 }
 404
 405 static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
 406                                          uint32_t * vb, int qw_count)
 407 {
 408         for (; qw_count > 0; --qw_count) {
 409                 VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY);
 410         }
 411         return vb;
 412 }
 413
 414 /*
 415  * This function is used internally by ring buffer mangement code.
 416  *
 417  * Returns virtual pointer to ring buffer.
 418  */
 419 static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)
 420 {
 421         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
 422 }
 423
 424 /*
 425  * Hooks a segment of data into the tail of the ring-buffer by
 426  * modifying the pause address stored in the buffer itself. If
 427  * the regulator has already paused, restart it.
 428  */
 429 static int via_hook_segment(drm_via_private_t * dev_priv,
 430                             uint32_t pause_addr_hi, uint32_t pause_addr_lo,
 431                             int no_pci_fire)
 432 {
 433         int paused, count;
 434         volatile uint32_t *paused_at = dev_priv->last_pause_ptr;
 435         uint32_t reader,ptr;
 436
 437         paused = 0;
 438         via_flush_write_combine();
 439         (void) *(volatile uint32_t *)(via_get_dma(dev_priv) -1);
 440         *paused_at = pause_addr_lo;
 441         via_flush_write_combine();
 442         (void) *paused_at;
 443         reader = *(dev_priv->hw_addr_ptr);
 444         ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +
 445                 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
 446         dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
 447
 448         if ((ptr - reader) <= dev_priv->dma_diff ) {
 449                 count = 10000000;
 450                 while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--);
 451         }
 452
 453         if (paused && !no_pci_fire) {
 454                 reader = *(dev_priv->hw_addr_ptr);
 455                 if ((ptr - reader) == dev_priv->dma_diff) {
 456
 457                         /*
 458                          * There is a concern that these writes may stall the PCI bus
 459                          * if the GPU is not idle. However, idling the GPU first
 460                          * doesn't make a difference.
 461                          */
 462
 463                         VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
 464                         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
 465                         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
 466                         VIA_READ(VIA_REG_TRANSPACE);
 467                 }
 468         }
 469         return paused;
 470 }
 471
 472 static int via_wait_idle(drm_via_private_t * dev_priv)
 473 {
 474         int count = 10000000;
 475
 476         while (!(VIA_READ(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && count--);
 477
 478         while (count-- && (VIA_READ(VIA_REG_STATUS) &
 479                            (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
 480                             VIA_3D_ENG_BUSY))) ;
 481         return count;
 482 }
 483
 484 static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type,
 485                                uint32_t addr, uint32_t * cmd_addr_hi,
 486                                uint32_t * cmd_addr_lo, int skip_wait)
 487 {
 488         uint32_t agp_base;
 489         uint32_t cmd_addr, addr_lo, addr_hi;
 490         uint32_t *vb;
 491         uint32_t qw_pad_count;
 492
 493         if (!skip_wait)
 494                 via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);
 495
 496         vb = via_get_dma(dev_priv);
 497         VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
 498                         (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
 499         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 500         qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
 501             ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
 502
 503         cmd_addr = (addr) ? addr :
 504             agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
 505         addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |
 506                    (cmd_addr & HC_HAGPBpL_MASK));
 507         addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24));
 508
 509         vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
 510         VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo);
 511         return vb;
 512 }
 513
 514 static void via_cmdbuf_start(drm_via_private_t * dev_priv)
 515 {
 516         uint32_t pause_addr_lo, pause_addr_hi;
 517         uint32_t start_addr, start_addr_lo;
 518         uint32_t end_addr, end_addr_lo;
 519         uint32_t command;
 520         uint32_t agp_base;
 521         uint32_t ptr;
 522         uint32_t reader;
 523         int count;
 524
 525         dev_priv->dma_low = 0;
 526
 527         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 528         start_addr = agp_base;
 529         end_addr = agp_base + dev_priv->dma_high;
 530
 531         start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));
 532         end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
 533         command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
 534                    ((end_addr & 0xff000000) >> 16));
 535
 536         dev_priv->last_pause_ptr =
 537             via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
 538                           &pause_addr_hi, &pause_addr_lo, 1) - 1;
 539
 540         via_flush_write_combine();
 541         (void) *(volatile uint32_t *)dev_priv->last_pause_ptr;
 542
 543         VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
 544         VIA_WRITE(VIA_REG_TRANSPACE, command);
 545         VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);
 546         VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);
 547
 548         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
 549         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
 550         DRM_WRITEMEMORYBARRIER();
 551         VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
 552         VIA_READ(VIA_REG_TRANSPACE);
 553
 554         dev_priv->dma_diff = 0;
 555
 556         count = 10000000;
 557         while (!(VIA_READ(0x41c) & 0x80000000) && count--);
 558
 559         reader = *(dev_priv->hw_addr_ptr);
 560         ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +
 561             dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
 562
 563         /*
 564          * This is the difference between where we tell the
 565          * command reader to pause and where it actually pauses.
 566          * This differs between hw implementation so we need to
 567          * detect it.
 568          */
 569
 570         dev_priv->dma_diff = ptr - reader;
 571 }
 572
 573 static void via_pad_cache(drm_via_private_t * dev_priv, int qwords)
 574 {
 575         uint32_t *vb;
 576
 577         via_cmdbuf_wait(dev_priv, qwords + 2);
 578         vb = via_get_dma(dev_priv);
 579         VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16);
 580         via_align_buffer(dev_priv, vb, qwords);
 581 }
 582
 583 static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
 584 {
 585         uint32_t *vb = via_get_dma(dev_priv);
 586         SetReg2DAGP(0x0C, (0 | (0 << 16)));
 587         SetReg2DAGP(0x10, 0 | (0 << 16));
 588         SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
 589 }
 590
 591 static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
 592 {
 593         uint32_t agp_base;
 594         uint32_t pause_addr_lo, pause_addr_hi;
 595         uint32_t jump_addr_lo, jump_addr_hi;
 596         volatile uint32_t *last_pause_ptr;
 597
 598         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 599         via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
 600                       &jump_addr_lo, 0);
 601
 602         dev_priv->dma_wrap = dev_priv->dma_low;
 603
 604         /*
 605          * Wrap command buffer to the beginning.
 606          */
 607
 608         dev_priv->dma_low = 0;
 609         if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) {
 610                 DRM_ERROR("via_cmdbuf_jump failed\n");
 611         }
 612
 613         via_dummy_bitblt(dev_priv);
 614         via_dummy_bitblt(dev_priv);
 615
 616         last_pause_ptr =
 617             via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 618                           &pause_addr_lo, 0) - 1;
 619         via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 620                       &pause_addr_lo, 0);
 621
 622         *last_pause_ptr = pause_addr_lo;
 623
 624         via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0);
 625 }
 626
 627
 628 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
 629 {
 630         via_cmdbuf_jump(dev_priv);
 631 }
 632
 633 static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
 634 {
 635         uint32_t pause_addr_lo, pause_addr_hi;
 636
 637         via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);
 638         via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
 639 }
 640
 641 static void via_cmdbuf_pause(drm_via_private_t * dev_priv)
 642 {
 643         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);
 644 }
 645
 646 static void via_cmdbuf_reset(drm_via_private_t * dev_priv)
 647 {
 648         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);
 649         via_wait_idle(dev_priv);
 650 }
 651
 652 /*
 653  * User interface to the space and lag functions.
 654  */
 655
 656 static int via_cmdbuf_size(DRM_IOCTL_ARGS)
 657 {
 658         DRM_DEVICE;
 659         drm_via_cmdbuf_size_t d_siz;
 660         int ret = 0;
 661         uint32_t tmp_size, count;
 662         drm_via_private_t *dev_priv;
 663
 664         DRM_DEBUG("via cmdbuf_size\n");
 665         LOCK_TEST_WITH_RETURN(dev, filp);
 666
 667         dev_priv = (drm_via_private_t *) dev->dev_private;
 668
 669         if (dev_priv->ring.virtual_start == NULL) {
 670                 DRM_ERROR("%s called without initializing AGP ring buffer.\n",
 671                           __FUNCTION__);
 672                 return DRM_ERR(EFAULT);
 673         }
 674
 675         DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t __user *) data,
 676                                  sizeof(d_siz));
 677
 678         count = 1000000;
 679         tmp_size = d_siz.size;
 680         switch (d_siz.func) {
 681         case VIA_CMDBUF_SPACE:
 682                 while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz.size)
 683                        && count--) {
 684                         if (!d_siz.wait) {
 685                                 break;
 686                         }
 687                 }
 688                 if (!count) {
 689                         DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n");
 690                         ret = DRM_ERR(EAGAIN);
 691                 }
 692                 break;
 693         case VIA_CMDBUF_LAG:
 694                 while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz.size)
 695                        && count--) {
 696                         if (!d_siz.wait) {
 697                                 break;
 698                         }
 699                 }
 700                 if (!count) {
 701                         DRM_ERROR("VIA_CMDBUF_LAG timed out.\n");
 702                         ret = DRM_ERR(EAGAIN);
 703                 }
 704                 break;
 705         default:
 706                 ret = DRM_ERR(EFAULT);
 707         }
 708         d_siz.size = tmp_size;
 709
 710         DRM_COPY_TO_USER_IOCTL((drm_via_cmdbuf_size_t __user *) data, d_siz,
 711                                sizeof(d_siz));
 712         return ret;
 713 }
 714
 715 drm_ioctl_desc_t via_ioctls[] = {
 716         [DRM_IOCTL_NR(DRM_VIA_ALLOCMEM)] = {via_mem_alloc, DRM_AUTH},
 717         [DRM_IOCTL_NR(DRM_VIA_FREEMEM)] = {via_mem_free, DRM_AUTH},
 718         [DRM_IOCTL_NR(DRM_VIA_AGP_INIT)] = {via_agp_init, DRM_AUTH|DRM_MASTER},
 719         [DRM_IOCTL_NR(DRM_VIA_FB_INIT)] = {via_fb_init, DRM_AUTH|DRM_MASTER},
 720         [DRM_IOCTL_NR(DRM_VIA_MAP_INIT)] = {via_map_init, DRM_AUTH|DRM_MASTER},
 721         [DRM_IOCTL_NR(DRM_VIA_DEC_FUTEX)] = {via_decoder_futex, DRM_AUTH},
 722         [DRM_IOCTL_NR(DRM_VIA_DMA_INIT)] = {via_dma_init, DRM_AUTH},
 723         [DRM_IOCTL_NR(DRM_VIA_CMDBUFFER)] = {via_cmdbuffer, DRM_AUTH},
 724         [DRM_IOCTL_NR(DRM_VIA_FLUSH)] = {via_flush_ioctl, DRM_AUTH},
 725         [DRM_IOCTL_NR(DRM_VIA_PCICMD)] = {via_pci_cmdbuffer, DRM_AUTH},
 726         [DRM_IOCTL_NR(DRM_VIA_CMDBUF_SIZE)] = {via_cmdbuf_size, DRM_AUTH},
 727         [DRM_IOCTL_NR(DRM_VIA_WAIT_IRQ)] = {via_wait_irq, DRM_AUTH},
 728         [DRM_IOCTL_NR(DRM_VIA_DMA_BLIT)] = {via_dma_blit, DRM_AUTH},
 729         [DRM_IOCTL_NR(DRM_VIA_BLIT_SYNC)] = {via_dma_blit_sync, DRM_AUTH}
 730 };
 731
 732 int via_max_ioctl = DRM_ARRAY_SIZE(via_ioctls);