drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/slab.h>
   8 #include <linux/init.h>
   9 #include <linux/kernel.h>
  10 #include <linux/pagemap.h>
  11 #include <linux/agp_backend.h>
  12 #include <asm/smp.h>
  13 #include "agp.h"
  14
  15 int intel_agp_enabled;
  16 EXPORT_SYMBOL(intel_agp_enabled);
  17
  18 /*
  19  * If we have Intel graphics, we're not going to have anything other than
  20  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  21  * on the Intel IOMMU support (CONFIG_DMAR).
  22  * Only newer chipsets need to bother with this, of course.
  23  */
  24 #ifdef CONFIG_DMAR
  25 #define USE_PCI_DMA_API 1
  26 #endif
  27
  28 #define PCI_DEVICE_ID_INTEL_E7221_HB    0x2588
  29 #define PCI_DEVICE_ID_INTEL_E7221_IG    0x258a
  30 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  31 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  32 #define PCI_DEVICE_ID_INTEL_82G35_HB     0x2980
  33 #define PCI_DEVICE_ID_INTEL_82G35_IG     0x2982
  34 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  35 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  36 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  37 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  38 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
  39 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
  40 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
  41 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
  42 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
  43 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
  44 #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB        0xA010
  45 #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG        0xA011
  46 #define PCI_DEVICE_ID_INTEL_PINEVIEW_HB         0xA000
  47 #define PCI_DEVICE_ID_INTEL_PINEVIEW_IG         0xA001
  48 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
  49 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
  50 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
  51 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
  52 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
  53 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
  54 #define PCI_DEVICE_ID_INTEL_B43_HB          0x2E40
  55 #define PCI_DEVICE_ID_INTEL_B43_IG          0x2E42
  56 #define PCI_DEVICE_ID_INTEL_GM45_HB         0x2A40
  57 #define PCI_DEVICE_ID_INTEL_GM45_IG         0x2A42
  58 #define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB        0x2E00
  59 #define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG        0x2E02
  60 #define PCI_DEVICE_ID_INTEL_Q45_HB          0x2E10
  61 #define PCI_DEVICE_ID_INTEL_Q45_IG          0x2E12
  62 #define PCI_DEVICE_ID_INTEL_G45_HB          0x2E20
  63 #define PCI_DEVICE_ID_INTEL_G45_IG          0x2E22
  64 #define PCI_DEVICE_ID_INTEL_G41_HB          0x2E30
  65 #define PCI_DEVICE_ID_INTEL_G41_IG          0x2E32
  66 #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB           0x0040
  67 #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG           0x0042
  68 #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB           0x0044
  69 #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB          0x0062
  70 #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB    0x006a
  71 #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG           0x0046
  72 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB  0x0100
  73 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG  0x0102
  74 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB  0x0104
  75 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG  0x0106
  76
  77 /* cover 915 and 945 variants */
  78 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
  79                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
  80                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
  81                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
  82                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
  83                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
  84
  85 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  86                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
  87                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  88                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
  89                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
  90                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
  91
  92 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
  93                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
  94                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
  95                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
  96                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
  97
  98 #define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
  99                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
 100
 101 #define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \
 102                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
 103
 104 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
 105                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
 106                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
 107                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
 108                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
 109                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
 110                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \
 111                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \
 112                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
 113                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \
 114                 IS_SNB)
 115
 116 extern int agp_memory_reserved;
 117
 118
 119 /* Intel 815 register */
 120 #define INTEL_815_APCONT        0x51
 121 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
 122
 123 /* Intel i820 registers */
 124 #define INTEL_I820_RDCR         0x51
 125 #define INTEL_I820_ERRSTS       0xc8
 126
 127 /* Intel i840 registers */
 128 #define INTEL_I840_MCHCFG       0x50
 129 #define INTEL_I840_ERRSTS       0xc8
 130
 131 /* Intel i850 registers */
 132 #define INTEL_I850_MCHCFG       0x50
 133 #define INTEL_I850_ERRSTS       0xc8
 134
 135 /* intel 915G registers */
 136 #define I915_GMADDR     0x18
 137 #define I915_MMADDR     0x10
 138 #define I915_PTEADDR    0x1C
 139 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
 140 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
 141 #define G33_GMCH_GMS_STOLEN_128M        (0x8 << 4)
 142 #define G33_GMCH_GMS_STOLEN_256M        (0x9 << 4)
 143 #define INTEL_GMCH_GMS_STOLEN_96M       (0xa << 4)
 144 #define INTEL_GMCH_GMS_STOLEN_160M      (0xb << 4)
 145 #define INTEL_GMCH_GMS_STOLEN_224M      (0xc << 4)
 146 #define INTEL_GMCH_GMS_STOLEN_352M      (0xd << 4)
 147
 148 #define I915_IFPADDR    0x60
 149
 150 /* Intel 965G registers */
 151 #define I965_MSAC 0x62
 152 #define I965_IFPADDR    0x70
 153
 154 /* Intel 7505 registers */
 155 #define INTEL_I7505_APSIZE      0x74
 156 #define INTEL_I7505_NCAPID      0x60
 157 #define INTEL_I7505_NISTAT      0x6c
 158 #define INTEL_I7505_ATTBASE     0x78
 159 #define INTEL_I7505_ERRSTS      0x42
 160 #define INTEL_I7505_AGPCTRL     0x70
 161 #define INTEL_I7505_MCHCFG      0x50
 162
 163 #define SNB_GMCH_CTRL   0x50
 164 #define SNB_GMCH_GMS_STOLEN_MASK        0xF8
 165 #define SNB_GMCH_GMS_STOLEN_32M         (1 << 3)
 166 #define SNB_GMCH_GMS_STOLEN_64M         (2 << 3)
 167 #define SNB_GMCH_GMS_STOLEN_96M         (3 << 3)
 168 #define SNB_GMCH_GMS_STOLEN_128M        (4 << 3)
 169 #define SNB_GMCH_GMS_STOLEN_160M        (5 << 3)
 170 #define SNB_GMCH_GMS_STOLEN_192M        (6 << 3)
 171 #define SNB_GMCH_GMS_STOLEN_224M        (7 << 3)
 172 #define SNB_GMCH_GMS_STOLEN_256M        (8 << 3)
 173 #define SNB_GMCH_GMS_STOLEN_288M        (9 << 3)
 174 #define SNB_GMCH_GMS_STOLEN_320M        (0xa << 3)
 175 #define SNB_GMCH_GMS_STOLEN_352M        (0xb << 3)
 176 #define SNB_GMCH_GMS_STOLEN_384M        (0xc << 3)
 177 #define SNB_GMCH_GMS_STOLEN_416M        (0xd << 3)
 178 #define SNB_GMCH_GMS_STOLEN_448M        (0xe << 3)
 179 #define SNB_GMCH_GMS_STOLEN_480M        (0xf << 3)
 180 #define SNB_GMCH_GMS_STOLEN_512M        (0x10 << 3)
 181 #define SNB_GTT_SIZE_0M                 (0 << 8)
 182 #define SNB_GTT_SIZE_1M                 (1 << 8)
 183 #define SNB_GTT_SIZE_2M                 (2 << 8)
 184 #define SNB_GTT_SIZE_MASK               (3 << 8)
 185
 186 static const struct aper_size_info_fixed intel_i810_sizes[] =
 187 {
 188         {64, 16384, 4},
 189         /* The 32M mode still requires a 64k gatt */
 190         {32, 8192, 4}
 191 };
 192
 193 #define AGP_DCACHE_MEMORY       1
 194 #define AGP_PHYS_MEMORY         2
 195 #define INTEL_AGP_CACHED_MEMORY 3
 196
 197 static struct gatt_mask intel_i810_masks[] =
 198 {
 199         {.mask = I810_PTE_VALID, .type = 0},
 200         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
 201         {.mask = I810_PTE_VALID, .type = 0},
 202         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
 203          .type = INTEL_AGP_CACHED_MEMORY}
 204 };
 205
 206 static struct _intel_private {
 207         struct pci_dev *pcidev; /* device one */
 208         u8 __iomem *registers;
 209         u32 __iomem *gtt;               /* I915G */
 210         int num_dcache_entries;
 211         /* gtt_entries is the number of gtt entries that are already mapped
 212          * to stolen memory.  Stolen memory is larger than the memory mapped
 213          * through gtt_entries, as it includes some reserved space for the BIOS
 214          * popup and for the GTT.
 215          */
 216         int gtt_entries;                        /* i830+ */
 217         int gtt_total_size;
 218         union {
 219                 void __iomem *i9xx_flush_page;
 220                 void *i8xx_flush_page;
 221         };
 222         struct page *i8xx_page;
 223         struct resource ifp_resource;
 224         int resource_valid;
 225 } intel_private;
 226
 227 #ifdef USE_PCI_DMA_API
 228 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
 229 {
 230         *ret = pci_map_page(intel_private.pcidev, page, 0,
 231                             PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 232         if (pci_dma_mapping_error(intel_private.pcidev, *ret))
 233                 return -EINVAL;
 234         return 0;
 235 }
 236
 237 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
 238 {
 239         pci_unmap_page(intel_private.pcidev, dma,
 240                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 241 }
 242
 243 static void intel_agp_free_sglist(struct agp_memory *mem)
 244 {
 245         struct sg_table st;
 246
 247         st.sgl = mem->sg_list;
 248         st.orig_nents = st.nents = mem->page_count;
 249
 250         sg_free_table(&st);
 251
 252         mem->sg_list = NULL;
 253         mem->num_sg = 0;
 254 }
 255
 256 static int intel_agp_map_memory(struct agp_memory *mem)
 257 {
 258         struct sg_table st;
 259         struct scatterlist *sg;
 260         int i;
 261
 262         DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
 263
 264         if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
 265                 return -ENOMEM;
 266
 267         mem->sg_list = sg = st.sgl;
 268
 269         for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
 270                 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
 271
 272         mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
 273                                  mem->page_count, PCI_DMA_BIDIRECTIONAL);
 274         if (unlikely(!mem->num_sg)) {
 275                 intel_agp_free_sglist(mem);
 276                 return -ENOMEM;
 277         }
 278         return 0;
 279 }
 280
 281 static void intel_agp_unmap_memory(struct agp_memory *mem)
 282 {
 283         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 284
 285         pci_unmap_sg(intel_private.pcidev, mem->sg_list,
 286                      mem->page_count, PCI_DMA_BIDIRECTIONAL);
 287         intel_agp_free_sglist(mem);
 288 }
 289
 290 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 291                                         off_t pg_start, int mask_type)
 292 {
 293         struct scatterlist *sg;
 294         int i, j;
 295
 296         j = pg_start;
 297
 298         WARN_ON(!mem->num_sg);
 299
 300         if (mem->num_sg == mem->page_count) {
 301                 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
 302                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 303                                         sg_dma_address(sg), mask_type),
 304                                         intel_private.gtt+j);
 305                         j++;
 306                 }
 307         } else {
 308                 /* sg may merge pages, but we have to separate
 309                  * per-page addr for GTT */
 310                 unsigned int len, m;
 311
 312                 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
 313                         len = sg_dma_len(sg) / PAGE_SIZE;
 314                         for (m = 0; m < len; m++) {
 315                                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 316                                                                        sg_dma_address(sg) + m * PAGE_SIZE,
 317                                                                        mask_type),
 318                                        intel_private.gtt+j);
 319                                 j++;
 320                         }
 321                 }
 322         }
 323         readl(intel_private.gtt+j-1);
 324 }
 325
 326 #else
 327
 328 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 329                                         off_t pg_start, int mask_type)
 330 {
 331         int i, j;
 332         u32 cache_bits = 0;
 333
 334         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||
 335             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
 336         {
 337                 cache_bits = I830_PTE_SYSTEM_CACHED;
 338         }
 339
 340         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 341                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 342                                 page_to_phys(mem->pages[i]), mask_type),
 343                        intel_private.gtt+j);
 344         }
 345
 346         readl(intel_private.gtt+j-1);
 347 }
 348
 349 #endif
 350
 351 static int intel_i810_fetch_size(void)
 352 {
 353         u32 smram_miscc;
 354         struct aper_size_info_fixed *values;
 355
 356         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
 357         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 358
 359         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 360                 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
 361                 return 0;
 362         }
 363         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 364                 agp_bridge->previous_size =
 365                         agp_bridge->current_size = (void *) (values + 1);
 366                 agp_bridge->aperture_size_idx = 1;
 367                 return values[1].size;
 368         } else {
 369                 agp_bridge->previous_size =
 370                         agp_bridge->current_size = (void *) (values);
 371                 agp_bridge->aperture_size_idx = 0;
 372                 return values[0].size;
 373         }
 374
 375         return 0;
 376 }
 377
 378 static int intel_i810_configure(void)
 379 {
 380         struct aper_size_info_fixed *current_size;
 381         u32 temp;
 382         int i;
 383
 384         current_size = A_SIZE_FIX(agp_bridge->current_size);
 385
 386         if (!intel_private.registers) {
 387                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 388                 temp &= 0xfff80000;
 389
 390                 intel_private.registers = ioremap(temp, 128 * 4096);
 391                 if (!intel_private.registers) {
 392                         dev_err(&intel_private.pcidev->dev,
 393                                 "can't remap memory\n");
 394                         return -ENOMEM;
 395                 }
 396         }
 397
 398         if ((readl(intel_private.registers+I810_DRAM_CTL)
 399                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 400                 /* This will need to be dynamically assigned */
 401                 dev_info(&intel_private.pcidev->dev,
 402                          "detected 4MB dedicated video ram\n");
 403                 intel_private.num_dcache_entries = 1024;
 404         }
 405         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 406         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 407         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 408         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 409
 410         if (agp_bridge->driver->needs_scratch_page) {
 411                 for (i = 0; i < current_size->num_entries; i++) {
 412                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 413                 }
 414                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
 415         }
 416         global_cache_flush();
 417         return 0;
 418 }
 419
 420 static void intel_i810_cleanup(void)
 421 {
 422         writel(0, intel_private.registers+I810_PGETBL_CTL);
 423         readl(intel_private.registers); /* PCI Posting. */
 424         iounmap(intel_private.registers);
 425 }
 426
 427 static void intel_i810_tlbflush(struct agp_memory *mem)
 428 {
 429         return;
 430 }
 431
 432 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 433 {
 434         return;
 435 }
 436
 437 /* Exists to support ARGB cursors */
 438 static struct page *i8xx_alloc_pages(void)
 439 {
 440         struct page *page;
 441
 442         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 443         if (page == NULL)
 444                 return NULL;
 445
 446         if (set_pages_uc(page, 4) < 0) {
 447                 set_pages_wb(page, 4);
 448                 __free_pages(page, 2);
 449                 return NULL;
 450         }
 451         get_page(page);
 452         atomic_inc(&agp_bridge->current_memory_agp);
 453         return page;
 454 }
 455
 456 static void i8xx_destroy_pages(struct page *page)
 457 {
 458         if (page == NULL)
 459                 return;
 460
 461         set_pages_wb(page, 4);
 462         put_page(page);
 463         __free_pages(page, 2);
 464         atomic_dec(&agp_bridge->current_memory_agp);
 465 }
 466
 467 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 468                                         int type)
 469 {
 470         if (type < AGP_USER_TYPES)
 471                 return type;
 472         else if (type == AGP_USER_CACHED_MEMORY)
 473                 return INTEL_AGP_CACHED_MEMORY;
 474         else
 475                 return 0;
 476 }
 477
 478 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 479                                 int type)
 480 {
 481         int i, j, num_entries;
 482         void *temp;
 483         int ret = -EINVAL;
 484         int mask_type;
 485
 486         if (mem->page_count == 0)
 487                 goto out;
 488
 489         temp = agp_bridge->current_size;
 490         num_entries = A_SIZE_FIX(temp)->num_entries;
 491
 492         if ((pg_start + mem->page_count) > num_entries)
 493                 goto out_err;
 494
 495
 496         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 497                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 498                         ret = -EBUSY;
 499                         goto out_err;
 500                 }
 501         }
 502
 503         if (type != mem->type)
 504                 goto out_err;
 505
 506         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 507
 508         switch (mask_type) {
 509         case AGP_DCACHE_MEMORY:
 510                 if (!mem->is_flushed)
 511                         global_cache_flush();
 512                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 513                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 514                                intel_private.registers+I810_PTE_BASE+(i*4));
 515                 }
 516                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 517                 break;
 518         case AGP_PHYS_MEMORY:
 519         case AGP_NORMAL_MEMORY:
 520                 if (!mem->is_flushed)
 521                         global_cache_flush();
 522                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 523                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 524                                         page_to_phys(mem->pages[i]), mask_type),
 525                                intel_private.registers+I810_PTE_BASE+(j*4));
 526                 }
 527                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 528                 break;
 529         default:
 530                 goto out_err;
 531         }
 532
 533         agp_bridge->driver->tlb_flush(mem);
 534 out:
 535         ret = 0;
 536 out_err:
 537         mem->is_flushed = true;
 538         return ret;
 539 }
 540
 541 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 542                                 int type)
 543 {
 544         int i;
 545
 546         if (mem->page_count == 0)
 547                 return 0;
 548
 549         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 550                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 551         }
 552         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 553
 554         agp_bridge->driver->tlb_flush(mem);
 555         return 0;
 556 }
 557
 558 /*
 559  * The i810/i830 requires a physical address to program its mouse
 560  * pointer into hardware.
 561  * However the Xserver still writes to it through the agp aperture.
 562  */
 563 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 564 {
 565         struct agp_memory *new;
 566         struct page *page;
 567
 568         switch (pg_count) {
 569         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 570                 break;
 571         case 4:
 572                 /* kludge to get 4 physical pages for ARGB cursor */
 573                 page = i8xx_alloc_pages();
 574                 break;
 575         default:
 576                 return NULL;
 577         }
 578
 579         if (page == NULL)
 580                 return NULL;
 581
 582         new = agp_create_memory(pg_count);
 583         if (new == NULL)
 584                 return NULL;
 585
 586         new->pages[0] = page;
 587         if (pg_count == 4) {
 588                 /* kludge to get 4 physical pages for ARGB cursor */
 589                 new->pages[1] = new->pages[0] + 1;
 590                 new->pages[2] = new->pages[1] + 1;
 591                 new->pages[3] = new->pages[2] + 1;
 592         }
 593         new->page_count = pg_count;
 594         new->num_scratch_pages = pg_count;
 595         new->type = AGP_PHYS_MEMORY;
 596         new->physical = page_to_phys(new->pages[0]);
 597         return new;
 598 }
 599
 600 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 601 {
 602         struct agp_memory *new;
 603
 604         if (type == AGP_DCACHE_MEMORY) {
 605                 if (pg_count != intel_private.num_dcache_entries)
 606                         return NULL;
 607
 608                 new = agp_create_memory(1);
 609                 if (new == NULL)
 610                         return NULL;
 611
 612                 new->type = AGP_DCACHE_MEMORY;
 613                 new->page_count = pg_count;
 614                 new->num_scratch_pages = 0;
 615                 agp_free_page_array(new);
 616                 return new;
 617         }
 618         if (type == AGP_PHYS_MEMORY)
 619                 return alloc_agpphysmem_i8xx(pg_count, type);
 620         return NULL;
 621 }
 622
 623 static void intel_i810_free_by_type(struct agp_memory *curr)
 624 {
 625         agp_free_key(curr->key);
 626         if (curr->type == AGP_PHYS_MEMORY) {
 627                 if (curr->page_count == 4)
 628                         i8xx_destroy_pages(curr->pages[0]);
 629                 else {
 630                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 631                                                              AGP_PAGE_DESTROY_UNMAP);
 632                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 633                                                              AGP_PAGE_DESTROY_FREE);
 634                 }
 635                 agp_free_page_array(curr);
 636         }
 637         kfree(curr);
 638 }
 639
 640 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 641                                             dma_addr_t addr, int type)
 642 {
 643         /* Type checking must be done elsewhere */
 644         return addr | bridge->driver->masks[type].mask;
 645 }
 646
 647 static struct aper_size_info_fixed intel_i830_sizes[] =
 648 {
 649         {128, 32768, 5},
 650         /* The 64M mode still requires a 128k gatt */
 651         {64, 16384, 5},
 652         {256, 65536, 6},
 653         {512, 131072, 7},
 654 };
 655
 656 static void intel_i830_init_gtt_entries(void)
 657 {
 658         u16 gmch_ctrl;
 659         int gtt_entries = 0;
 660         u8 rdct;
 661         int local = 0;
 662         static const int ddt[4] = { 0, 16, 32, 64 };
 663         int size; /* reserved space (in kb) at the top of stolen memory */
 664
 665         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 666
 667         if (IS_I965) {
 668                 u32 pgetbl_ctl;
 669                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 670
 671                 /* The 965 has a field telling us the size of the GTT,
 672                  * which may be larger than what is necessary to map the
 673                  * aperture.
 674                  */
 675                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 676                 case I965_PGETBL_SIZE_128KB:
 677                         size = 128;
 678                         break;
 679                 case I965_PGETBL_SIZE_256KB:
 680                         size = 256;
 681                         break;
 682                 case I965_PGETBL_SIZE_512KB:
 683                         size = 512;
 684                         break;
 685                 case I965_PGETBL_SIZE_1MB:
 686                         size = 1024;
 687                         break;
 688                 case I965_PGETBL_SIZE_2MB:
 689                         size = 2048;
 690                         break;
 691                 case I965_PGETBL_SIZE_1_5MB:
 692                         size = 1024 + 512;
 693                         break;
 694                 default:
 695                         dev_info(&intel_private.pcidev->dev,
 696                                  "unknown page table size, assuming 512KB\n");
 697                         size = 512;
 698                 }
 699                 size += 4; /* add in BIOS popup space */
 700         } else if (IS_G33 && !IS_PINEVIEW) {
 701         /* G33's GTT size defined in gmch_ctrl */
 702                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
 703                 case G33_PGETBL_SIZE_1M:
 704                         size = 1024;
 705                         break;
 706                 case G33_PGETBL_SIZE_2M:
 707                         size = 2048;
 708                         break;
 709                 default:
 710                         dev_info(&agp_bridge->dev->dev,
 711                                  "unknown page table size 0x%x, assuming 512KB\n",
 712                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
 713                         size = 512;
 714                 }
 715                 size += 4;
 716         } else if (IS_G4X || IS_PINEVIEW) {
 717                 /* On 4 series hardware, GTT stolen is separate from graphics
 718                  * stolen, ignore it in stolen gtt entries counting.  However,
 719                  * 4KB of the stolen memory doesn't get mapped to the GTT.
 720                  */
 721                 size = 4;
 722         } else {
 723                 /* On previous hardware, the GTT size was just what was
 724                  * required to map the aperture.
 725                  */
 726                 size = agp_bridge->driver->fetch_size() + 4;
 727         }
 728
 729         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 730             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 731                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 732                 case I830_GMCH_GMS_STOLEN_512:
 733                         gtt_entries = KB(512) - KB(size);
 734                         break;
 735                 case I830_GMCH_GMS_STOLEN_1024:
 736                         gtt_entries = MB(1) - KB(size);
 737                         break;
 738                 case I830_GMCH_GMS_STOLEN_8192:
 739                         gtt_entries = MB(8) - KB(size);
 740                         break;
 741                 case I830_GMCH_GMS_LOCAL:
 742                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 743                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 744                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 745                         local = 1;
 746                         break;
 747                 default:
 748                         gtt_entries = 0;
 749                         break;
 750                 }
 751         } else if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||
 752                    agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) {
 753                 /*
 754                  * SandyBridge has new memory control reg at 0x50.w
 755                  */
 756                 u16 snb_gmch_ctl;
 757                 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 758                 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
 759                 case SNB_GMCH_GMS_STOLEN_32M:
 760                         gtt_entries = MB(32) - KB(size);
 761                         break;
 762                 case SNB_GMCH_GMS_STOLEN_64M:
 763                         gtt_entries = MB(64) - KB(size);
 764                         break;
 765                 case SNB_GMCH_GMS_STOLEN_96M:
 766                         gtt_entries = MB(96) - KB(size);
 767                         break;
 768                 case SNB_GMCH_GMS_STOLEN_128M:
 769                         gtt_entries = MB(128) - KB(size);
 770                         break;
 771                 case SNB_GMCH_GMS_STOLEN_160M:
 772                         gtt_entries = MB(160) - KB(size);
 773                         break;
 774                 case SNB_GMCH_GMS_STOLEN_192M:
 775                         gtt_entries = MB(192) - KB(size);
 776                         break;
 777                 case SNB_GMCH_GMS_STOLEN_224M:
 778                         gtt_entries = MB(224) - KB(size);
 779                         break;
 780                 case SNB_GMCH_GMS_STOLEN_256M:
 781                         gtt_entries = MB(256) - KB(size);
 782                         break;
 783                 case SNB_GMCH_GMS_STOLEN_288M:
 784                         gtt_entries = MB(288) - KB(size);
 785                         break;
 786                 case SNB_GMCH_GMS_STOLEN_320M:
 787                         gtt_entries = MB(320) - KB(size);
 788                         break;
 789                 case SNB_GMCH_GMS_STOLEN_352M:
 790                         gtt_entries = MB(352) - KB(size);
 791                         break;
 792                 case SNB_GMCH_GMS_STOLEN_384M:
 793                         gtt_entries = MB(384) - KB(size);
 794                         break;
 795                 case SNB_GMCH_GMS_STOLEN_416M:
 796                         gtt_entries = MB(416) - KB(size);
 797                         break;
 798                 case SNB_GMCH_GMS_STOLEN_448M:
 799                         gtt_entries = MB(448) - KB(size);
 800                         break;
 801                 case SNB_GMCH_GMS_STOLEN_480M:
 802                         gtt_entries = MB(480) - KB(size);
 803                         break;
 804                 case SNB_GMCH_GMS_STOLEN_512M:
 805                         gtt_entries = MB(512) - KB(size);
 806                         break;
 807                 }
 808         } else {
 809                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 810                 case I855_GMCH_GMS_STOLEN_1M:
 811                         gtt_entries = MB(1) - KB(size);
 812                         break;
 813                 case I855_GMCH_GMS_STOLEN_4M:
 814                         gtt_entries = MB(4) - KB(size);
 815                         break;
 816                 case I855_GMCH_GMS_STOLEN_8M:
 817                         gtt_entries = MB(8) - KB(size);
 818                         break;
 819                 case I855_GMCH_GMS_STOLEN_16M:
 820                         gtt_entries = MB(16) - KB(size);
 821                         break;
 822                 case I855_GMCH_GMS_STOLEN_32M:
 823                         gtt_entries = MB(32) - KB(size);
 824                         break;
 825                 case I915_GMCH_GMS_STOLEN_48M:
 826                         /* Check it's really I915G */
 827                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 828                                 gtt_entries = MB(48) - KB(size);
 829                         else
 830                                 gtt_entries = 0;
 831                         break;
 832                 case I915_GMCH_GMS_STOLEN_64M:
 833                         /* Check it's really I915G */
 834                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 835                                 gtt_entries = MB(64) - KB(size);
 836                         else
 837                                 gtt_entries = 0;
 838                         break;
 839                 case G33_GMCH_GMS_STOLEN_128M:
 840                         if (IS_G33 || IS_I965 || IS_G4X)
 841                                 gtt_entries = MB(128) - KB(size);
 842                         else
 843                                 gtt_entries = 0;
 844                         break;
 845                 case G33_GMCH_GMS_STOLEN_256M:
 846                         if (IS_G33 || IS_I965 || IS_G4X)
 847                                 gtt_entries = MB(256) - KB(size);
 848                         else
 849                                 gtt_entries = 0;
 850                         break;
 851                 case INTEL_GMCH_GMS_STOLEN_96M:
 852                         if (IS_I965 || IS_G4X)
 853                                 gtt_entries = MB(96) - KB(size);
 854                         else
 855                                 gtt_entries = 0;
 856                         break;
 857                 case INTEL_GMCH_GMS_STOLEN_160M:
 858                         if (IS_I965 || IS_G4X)
 859                                 gtt_entries = MB(160) - KB(size);
 860                         else
 861                                 gtt_entries = 0;
 862                         break;
 863                 case INTEL_GMCH_GMS_STOLEN_224M:
 864                         if (IS_I965 || IS_G4X)
 865                                 gtt_entries = MB(224) - KB(size);
 866                         else
 867                                 gtt_entries = 0;
 868                         break;
 869                 case INTEL_GMCH_GMS_STOLEN_352M:
 870                         if (IS_I965 || IS_G4X)
 871                                 gtt_entries = MB(352) - KB(size);
 872                         else
 873                                 gtt_entries = 0;
 874                         break;
 875                 default:
 876                         gtt_entries = 0;
 877                         break;
 878                 }
 879         }
 880         if (gtt_entries > 0) {
 881                 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
 882                        gtt_entries / KB(1), local ? "local" : "stolen");
 883                 gtt_entries /= KB(4);
 884         } else {
 885                 dev_info(&agp_bridge->dev->dev,
 886                        "no pre-allocated video memory detected\n");
 887                 gtt_entries = 0;
 888         }
 889
 890         intel_private.gtt_entries = gtt_entries;
 891 }
 892
 893 static void intel_i830_fini_flush(void)
 894 {
 895         kunmap(intel_private.i8xx_page);
 896         intel_private.i8xx_flush_page = NULL;
 897         unmap_page_from_agp(intel_private.i8xx_page);
 898
 899         __free_page(intel_private.i8xx_page);
 900         intel_private.i8xx_page = NULL;
 901 }
 902
 903 static void intel_i830_setup_flush(void)
 904 {
 905         /* return if we've already set the flush mechanism up */
 906         if (intel_private.i8xx_page)
 907                 return;
 908
 909         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
 910         if (!intel_private.i8xx_page)
 911                 return;
 912
 913         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 914         if (!intel_private.i8xx_flush_page)
 915                 intel_i830_fini_flush();
 916 }
 917
 918 /* The chipset_flush interface needs to get data that has already been
 919  * flushed out of the CPU all the way out to main memory, because the GPU
 920  * doesn't snoop those buffers.
 921  *
 922  * The 8xx series doesn't have the same lovely interface for flushing the
 923  * chipset write buffers that the later chips do. According to the 865
 924  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
 925  * that buffer out, we just fill 1KB and clflush it out, on the assumption
 926  * that it'll push whatever was in there out.  It appears to work.
 927  */
 928 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 929 {
 930         unsigned int *pg = intel_private.i8xx_flush_page;
 931
 932         memset(pg, 0, 1024);
 933
 934         if (cpu_has_clflush)
 935                 clflush_cache_range(pg, 1024);
 936         else if (wbinvd_on_all_cpus() != 0)
 937                 printk(KERN_ERR "Timed out waiting for cache flush.\n");
 938 }
 939
 940 /* The intel i830 automatically initializes the agp aperture during POST.
 941  * Use the memory already set aside for in the GTT.
 942  */
 943 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 944 {
 945         int page_order;
 946         struct aper_size_info_fixed *size;
 947         int num_entries;
 948         u32 temp;
 949
 950         size = agp_bridge->current_size;
 951         page_order = size->page_order;
 952         num_entries = size->num_entries;
 953         agp_bridge->gatt_table_real = NULL;
 954
 955         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 956         temp &= 0xfff80000;
 957
 958         intel_private.registers = ioremap(temp, 128 * 4096);
 959         if (!intel_private.registers)
 960                 return -ENOMEM;
 961
 962         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 963         global_cache_flush();   /* FIXME: ?? */
 964
 965         /* we have to call this as early as possible after the MMIO base address is known */
 966         intel_i830_init_gtt_entries();
 967
 968         agp_bridge->gatt_table = NULL;
 969
 970         agp_bridge->gatt_bus_addr = temp;
 971
 972         return 0;
 973 }
 974
 975 /* Return the gatt table to a sane state. Use the top of stolen
 976  * memory for the GTT.
 977  */
 978 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 979 {
 980         return 0;
 981 }
 982
 983 static int intel_i830_fetch_size(void)
 984 {
 985         u16 gmch_ctrl;
 986         struct aper_size_info_fixed *values;
 987
 988         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 989
 990         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 991             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 992                 /* 855GM/852GM/865G has 128MB aperture size */
 993                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 994                 agp_bridge->aperture_size_idx = 0;
 995                 return values[0].size;
 996         }
 997
 998         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 999
1000         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
1001                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
1002                 agp_bridge->aperture_size_idx = 0;
1003                 return values[0].size;
1004         } else {
1005                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
1006                 agp_bridge->aperture_size_idx = 1;
1007                 return values[1].size;
1008         }
1009
1010         return 0;
1011 }
1012
1013 static int intel_i830_configure(void)
1014 {
1015         struct aper_size_info_fixed *current_size;
1016         u32 temp;
1017         u16 gmch_ctrl;
1018         int i;
1019
1020         current_size = A_SIZE_FIX(agp_bridge->current_size);
1021
1022         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
1023         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1024
1025         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1026         gmch_ctrl |= I830_GMCH_ENABLED;
1027         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1028
1029         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1030         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1031
1032         if (agp_bridge->driver->needs_scratch_page) {
1033                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
1034                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1035                 }
1036                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
1037         }
1038
1039         global_cache_flush();
1040
1041         intel_i830_setup_flush();
1042         return 0;
1043 }
1044
1045 static void intel_i830_cleanup(void)
1046 {
1047         iounmap(intel_private.registers);
1048 }
1049
1050 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
1051                                      int type)
1052 {
1053         int i, j, num_entries;
1054         void *temp;
1055         int ret = -EINVAL;
1056         int mask_type;
1057
1058         if (mem->page_count == 0)
1059                 goto out;
1060
1061         temp = agp_bridge->current_size;
1062         num_entries = A_SIZE_FIX(temp)->num_entries;
1063
1064         if (pg_start < intel_private.gtt_entries) {
1065                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1066                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1067                            pg_start, intel_private.gtt_entries);
1068
1069                 dev_info(&intel_private.pcidev->dev,
1070                          "trying to insert into local/stolen memory\n");
1071                 goto out_err;
1072         }
1073
1074         if ((pg_start + mem->page_count) > num_entries)
1075                 goto out_err;
1076
1077         /* The i830 can't check the GTT for entries since its read only,
1078          * depend on the caller to make the correct offset decisions.
1079          */
1080
1081         if (type != mem->type)
1082                 goto out_err;
1083
1084         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1085
1086         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1087             mask_type != INTEL_AGP_CACHED_MEMORY)
1088                 goto out_err;
1089
1090         if (!mem->is_flushed)
1091                 global_cache_flush();
1092
1093         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1094                 writel(agp_bridge->driver->mask_memory(agp_bridge,
1095                                 page_to_phys(mem->pages[i]), mask_type),
1096                        intel_private.registers+I810_PTE_BASE+(j*4));
1097         }
1098         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
1099         agp_bridge->driver->tlb_flush(mem);
1100
1101 out:
1102         ret = 0;
1103 out_err:
1104         mem->is_flushed = true;
1105         return ret;
1106 }
1107
1108 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
1109                                      int type)
1110 {
1111         int i;
1112
1113         if (mem->page_count == 0)
1114                 return 0;
1115
1116         if (pg_start < intel_private.gtt_entries) {
1117                 dev_info(&intel_private.pcidev->dev,
1118                          "trying to disable local/stolen memory\n");
1119                 return -EINVAL;
1120         }
1121
1122         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1123                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1124         }
1125         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1126
1127         agp_bridge->driver->tlb_flush(mem);
1128         return 0;
1129 }
1130
1131 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
1132 {
1133         if (type == AGP_PHYS_MEMORY)
1134                 return alloc_agpphysmem_i8xx(pg_count, type);
1135         /* always return NULL for other allocation types for now */
1136         return NULL;
1137 }
1138
1139 static int intel_alloc_chipset_flush_resource(void)
1140 {
1141         int ret;
1142         ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1143                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1144                                      pcibios_align_resource, agp_bridge->dev);
1145
1146         return ret;
1147 }
1148
1149 static void intel_i915_setup_chipset_flush(void)
1150 {
1151         int ret;
1152         u32 temp;
1153
1154         pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
1155         if (!(temp & 0x1)) {
1156                 intel_alloc_chipset_flush_resource();
1157                 intel_private.resource_valid = 1;
1158                 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1159         } else {
1160                 temp &= ~1;
1161
1162                 intel_private.resource_valid = 1;
1163                 intel_private.ifp_resource.start = temp;
1164                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1165                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1166                 /* some BIOSes reserve this area in a pnp some don't */
1167                 if (ret)
1168                         intel_private.resource_valid = 0;
1169         }
1170 }
1171
1172 static void intel_i965_g33_setup_chipset_flush(void)
1173 {
1174         u32 temp_hi, temp_lo;
1175         int ret;
1176
1177         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
1178         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
1179
1180         if (!(temp_lo & 0x1)) {
1181
1182                 intel_alloc_chipset_flush_resource();
1183
1184                 intel_private.resource_valid = 1;
1185                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
1186                         upper_32_bits(intel_private.ifp_resource.start));
1187                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1188         } else {
1189                 u64 l64;
1190
1191                 temp_lo &= ~0x1;
1192                 l64 = ((u64)temp_hi << 32) | temp_lo;
1193
1194                 intel_private.resource_valid = 1;
1195                 intel_private.ifp_resource.start = l64;
1196                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1197                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1198                 /* some BIOSes reserve this area in a pnp some don't */
1199                 if (ret)
1200                         intel_private.resource_valid = 0;
1201         }
1202 }
1203
1204 static void intel_i9xx_setup_flush(void)
1205 {
1206         /* return if already configured */
1207         if (intel_private.ifp_resource.start)
1208                 return;
1209
1210         if (IS_SNB)
1211                 return;
1212
1213         /* setup a resource for this object */
1214         intel_private.ifp_resource.name = "Intel Flush Page";
1215         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1216
1217         /* Setup chipset flush for 915 */
1218         if (IS_I965 || IS_G33 || IS_G4X) {
1219                 intel_i965_g33_setup_chipset_flush();
1220         } else {
1221                 intel_i915_setup_chipset_flush();
1222         }
1223
1224         if (intel_private.ifp_resource.start) {
1225                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1226                 if (!intel_private.i9xx_flush_page)
1227                         dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
1228         }
1229 }
1230
1231 static int intel_i915_configure(void)
1232 {
1233         struct aper_size_info_fixed *current_size;
1234         u32 temp;
1235         u16 gmch_ctrl;
1236         int i;
1237
1238         current_size = A_SIZE_FIX(agp_bridge->current_size);
1239
1240         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1241
1242         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1243
1244         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1245         gmch_ctrl |= I830_GMCH_ENABLED;
1246         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1247
1248         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1249         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1250
1251         if (agp_bridge->driver->needs_scratch_page) {
1252                 for (i = intel_private.gtt_entries; i < intel_private.gtt_total_size; i++) {
1253                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
1254                 }
1255                 readl(intel_private.gtt+i-1);   /* PCI Posting. */
1256         }
1257
1258         global_cache_flush();
1259
1260         intel_i9xx_setup_flush();
1261
1262         return 0;
1263 }
1264
1265 static void intel_i915_cleanup(void)
1266 {
1267         if (intel_private.i9xx_flush_page)
1268                 iounmap(intel_private.i9xx_flush_page);
1269         if (intel_private.resource_valid)
1270                 release_resource(&intel_private.ifp_resource);
1271         intel_private.ifp_resource.start = 0;
1272         intel_private.resource_valid = 0;
1273         iounmap(intel_private.gtt);
1274         iounmap(intel_private.registers);
1275 }
1276
1277 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1278 {
1279         if (intel_private.i9xx_flush_page)
1280                 writel(1, intel_private.i9xx_flush_page);
1281 }
1282
1283 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1284                                      int type)
1285 {
1286         int num_entries;
1287         void *temp;
1288         int ret = -EINVAL;
1289         int mask_type;
1290
1291         if (mem->page_count == 0)
1292                 goto out;
1293
1294         temp = agp_bridge->current_size;
1295         num_entries = A_SIZE_FIX(temp)->num_entries;
1296
1297         if (pg_start < intel_private.gtt_entries) {
1298                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1299                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1300                            pg_start, intel_private.gtt_entries);
1301
1302                 dev_info(&intel_private.pcidev->dev,
1303                          "trying to insert into local/stolen memory\n");
1304                 goto out_err;
1305         }
1306
1307         if ((pg_start + mem->page_count) > num_entries)
1308                 goto out_err;
1309
1310         /* The i915 can't check the GTT for entries since it's read only;
1311          * depend on the caller to make the correct offset decisions.
1312          */
1313
1314         if (type != mem->type)
1315                 goto out_err;
1316
1317         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1318
1319         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1320             mask_type != INTEL_AGP_CACHED_MEMORY)
1321                 goto out_err;
1322
1323         if (!mem->is_flushed)
1324                 global_cache_flush();
1325
1326         intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1327         agp_bridge->driver->tlb_flush(mem);
1328
1329  out:
1330         ret = 0;
1331  out_err:
1332         mem->is_flushed = true;
1333         return ret;
1334 }
1335
1336 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1337                                      int type)
1338 {
1339         int i;
1340
1341         if (mem->page_count == 0)
1342                 return 0;
1343
1344         if (pg_start < intel_private.gtt_entries) {
1345                 dev_info(&intel_private.pcidev->dev,
1346                          "trying to disable local/stolen memory\n");
1347                 return -EINVAL;
1348         }
1349
1350         for (i = pg_start; i < (mem->page_count + pg_start); i++)
1351                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1352
1353         readl(intel_private.gtt+i-1);
1354
1355         agp_bridge->driver->tlb_flush(mem);
1356         return 0;
1357 }
1358
1359 /* Return the aperture size by just checking the resource length.  The effect
1360  * described in the spec of the MSAC registers is just changing of the
1361  * resource size.
1362  */
1363 static int intel_i9xx_fetch_size(void)
1364 {
1365         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1366         int aper_size; /* size in megabytes */
1367         int i;
1368
1369         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1370
1371         for (i = 0; i < num_sizes; i++) {
1372                 if (aper_size == intel_i830_sizes[i].size) {
1373                         agp_bridge->current_size = intel_i830_sizes + i;
1374                         agp_bridge->previous_size = agp_bridge->current_size;
1375                         return aper_size;
1376                 }
1377         }
1378
1379         return 0;
1380 }
1381
1382 /* The intel i915 automatically initializes the agp aperture during POST.
1383  * Use the memory already set aside for in the GTT.
1384  */
1385 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1386 {
1387         int page_order;
1388         struct aper_size_info_fixed *size;
1389         int num_entries;
1390         u32 temp, temp2;
1391         int gtt_map_size = 256 * 1024;
1392
1393         size = agp_bridge->current_size;
1394         page_order = size->page_order;
1395         num_entries = size->num_entries;
1396         agp_bridge->gatt_table_real = NULL;
1397
1398         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1399         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1400
1401         if (IS_G33)
1402             gtt_map_size = 1024 * 1024; /* 1M on G33 */
1403         intel_private.gtt = ioremap(temp2, gtt_map_size);
1404         if (!intel_private.gtt)
1405                 return -ENOMEM;
1406
1407         intel_private.gtt_total_size = gtt_map_size / 4;
1408
1409         temp &= 0xfff80000;
1410
1411         intel_private.registers = ioremap(temp, 128 * 4096);
1412         if (!intel_private.registers) {
1413                 iounmap(intel_private.gtt);
1414                 return -ENOMEM;
1415         }
1416
1417         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1418         global_cache_flush();   /* FIXME: ? */
1419
1420         /* we have to call this as early as possible after the MMIO base address is known */
1421         intel_i830_init_gtt_entries();
1422
1423         agp_bridge->gatt_table = NULL;
1424
1425         agp_bridge->gatt_bus_addr = temp;
1426
1427         return 0;
1428 }
1429
1430 /*
1431  * The i965 supports 36-bit physical addresses, but to keep
1432  * the format of the GTT the same, the bits that don't fit
1433  * in a 32-bit word are shifted down to bits 4..7.
1434  *
1435  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1436  * is always zero on 32-bit architectures, so no need to make
1437  * this conditional.
1438  */
1439 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1440                                             dma_addr_t addr, int type)
1441 {
1442         /* Shift high bits down */
1443         addr |= (addr >> 28) & 0xf0;
1444
1445         /* Type checking must be done elsewhere */
1446         return addr | bridge->driver->masks[type].mask;
1447 }
1448
1449 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1450 {
1451         u16 snb_gmch_ctl;
1452
1453         switch (agp_bridge->dev->device) {
1454         case PCI_DEVICE_ID_INTEL_GM45_HB:
1455         case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
1456         case PCI_DEVICE_ID_INTEL_Q45_HB:
1457         case PCI_DEVICE_ID_INTEL_G45_HB:
1458         case PCI_DEVICE_ID_INTEL_G41_HB:
1459         case PCI_DEVICE_ID_INTEL_B43_HB:
1460         case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB:
1461         case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
1462         case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
1463         case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
1464                 *gtt_offset = *gtt_size = MB(2);
1465                 break;
1466         case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:
1467         case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:
1468                 *gtt_offset = MB(2);
1469
1470                 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1471                 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
1472                 default:
1473                 case SNB_GTT_SIZE_0M:
1474                         printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
1475                         *gtt_size = MB(0);
1476                         break;
1477                 case SNB_GTT_SIZE_1M:
1478                         *gtt_size = MB(1);
1479                         break;
1480                 case SNB_GTT_SIZE_2M:
1481                         *gtt_size = MB(2);
1482                         break;
1483                 }
1484                 break;
1485         default:
1486                 *gtt_offset = *gtt_size = KB(512);
1487         }
1488 }
1489
1490 /* The intel i965 automatically initializes the agp aperture during POST.
1491  * Use the memory already set aside for in the GTT.
1492  */
1493 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1494 {
1495         int page_order;
1496         struct aper_size_info_fixed *size;
1497         int num_entries;
1498         u32 temp;
1499         int gtt_offset, gtt_size;
1500
1501         size = agp_bridge->current_size;
1502         page_order = size->page_order;
1503         num_entries = size->num_entries;
1504         agp_bridge->gatt_table_real = NULL;
1505
1506         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1507
1508         temp &= 0xfff00000;
1509
1510         intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1511
1512         intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1513
1514         if (!intel_private.gtt)
1515                 return -ENOMEM;
1516
1517         intel_private.gtt_total_size = gtt_size / 4;
1518
1519         intel_private.registers = ioremap(temp, 128 * 4096);
1520         if (!intel_private.registers) {
1521                 iounmap(intel_private.gtt);
1522                 return -ENOMEM;
1523         }
1524
1525         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1526         global_cache_flush();   /* FIXME: ? */
1527
1528         /* we have to call this as early as possible after the MMIO base address is known */
1529         intel_i830_init_gtt_entries();
1530
1531         agp_bridge->gatt_table = NULL;
1532
1533         agp_bridge->gatt_bus_addr = temp;
1534
1535         return 0;
1536 }
1537
1538
1539 static int intel_fetch_size(void)
1540 {
1541         int i;
1542         u16 temp;
1543         struct aper_size_info_16 *values;
1544
1545         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1546         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1547
1548         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1549                 if (temp == values[i].size_value) {
1550                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1551                         agp_bridge->aperture_size_idx = i;
1552                         return values[i].size;
1553                 }
1554         }
1555
1556         return 0;
1557 }
1558
1559 static int __intel_8xx_fetch_size(u8 temp)
1560 {
1561         int i;
1562         struct aper_size_info_8 *values;
1563
1564         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1565
1566         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1567                 if (temp == values[i].size_value) {
1568                         agp_bridge->previous_size =
1569                                 agp_bridge->current_size = (void *) (values + i);
1570                         agp_bridge->aperture_size_idx = i;
1571                         return values[i].size;
1572                 }
1573         }
1574         return 0;
1575 }
1576
1577 static int intel_8xx_fetch_size(void)
1578 {
1579         u8 temp;
1580
1581         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1582         return __intel_8xx_fetch_size(temp);
1583 }
1584
1585 static int intel_815_fetch_size(void)
1586 {
1587         u8 temp;
1588
1589         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1590          * one non-reserved bit, so mask the others out ... */
1591         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1592         temp &= (1 << 3);
1593
1594         return __intel_8xx_fetch_size(temp);
1595 }
1596
1597 static void intel_tlbflush(struct agp_memory *mem)
1598 {
1599         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1600         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1601 }
1602
1603
1604 static void intel_8xx_tlbflush(struct agp_memory *mem)
1605 {
1606         u32 temp;
1607         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1608         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1609         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1610         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1611 }
1612
1613
1614 static void intel_cleanup(void)
1615 {
1616         u16 temp;
1617         struct aper_size_info_16 *previous_size;
1618
1619         previous_size = A_SIZE_16(agp_bridge->previous_size);
1620         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1621         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1622         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1623 }
1624
1625
1626 static void intel_8xx_cleanup(void)
1627 {
1628         u16 temp;
1629         struct aper_size_info_8 *previous_size;
1630
1631         previous_size = A_SIZE_8(agp_bridge->previous_size);
1632         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1633         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1634         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1635 }
1636
1637
1638 static int intel_configure(void)
1639 {
1640         u32 temp;
1641         u16 temp2;
1642         struct aper_size_info_16 *current_size;
1643
1644         current_size = A_SIZE_16(agp_bridge->current_size);
1645
1646         /* aperture size */
1647         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1648
1649         /* address to map to */
1650         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1651         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1652
1653         /* attbase - aperture base */
1654         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1655
1656         /* agpctrl */
1657         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1658
1659         /* paccfg/nbxcfg */
1660         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1661         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1662                         (temp2 & ~(1 << 10)) | (1 << 9));
1663         /* clear any possible error conditions */
1664         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1665         return 0;
1666 }
1667
1668 static int intel_815_configure(void)
1669 {
1670         u32 temp, addr;
1671         u8 temp2;
1672         struct aper_size_info_8 *current_size;
1673
1674         /* attbase - aperture base */
1675         /* the Intel 815 chipset spec. says that bits 29-31 in the
1676         * ATTBASE register are reserved -> try not to write them */
1677         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1678                 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
1679                 return -EINVAL;
1680         }
1681
1682         current_size = A_SIZE_8(agp_bridge->current_size);
1683
1684         /* aperture size */
1685         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1686                         current_size->size_value);
1687
1688         /* address to map to */
1689         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1690         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1691
1692         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1693         addr &= INTEL_815_ATTBASE_MASK;
1694         addr |= agp_bridge->gatt_bus_addr;
1695         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1696
1697         /* agpctrl */
1698         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1699
1700         /* apcont */
1701         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1702         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1703
1704         /* clear any possible error conditions */
1705         /* Oddness : this chipset seems to have no ERRSTS register ! */
1706         return 0;
1707 }
1708
1709 static void intel_820_tlbflush(struct agp_memory *mem)
1710 {
1711         return;
1712 }
1713
1714 static void intel_820_cleanup(void)
1715 {
1716         u8 temp;
1717         struct aper_size_info_8 *previous_size;
1718
1719         previous_size = A_SIZE_8(agp_bridge->previous_size);
1720         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1721         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1722                         temp & ~(1 << 1));
1723         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1724                         previous_size->size_value);
1725 }
1726
1727
1728 static int intel_820_configure(void)
1729 {
1730         u32 temp;
1731         u8 temp2;
1732         struct aper_size_info_8 *current_size;
1733
1734         current_size = A_SIZE_8(agp_bridge->current_size);
1735
1736         /* aperture size */
1737         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1738
1739         /* address to map to */
1740         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1741         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1742
1743         /* attbase - aperture base */
1744         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1745
1746         /* agpctrl */
1747         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1748
1749         /* global enable aperture access */
1750         /* This flag is not accessed through MCHCFG register as in */
1751         /* i850 chipset. */
1752         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1753         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1754         /* clear any possible AGP-related error conditions */
1755         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1756         return 0;
1757 }
1758
1759 static int intel_840_configure(void)
1760 {
1761         u32 temp;
1762         u16 temp2;
1763         struct aper_size_info_8 *current_size;
1764
1765         current_size = A_SIZE_8(agp_bridge->current_size);
1766
1767         /* aperture size */
1768         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1769
1770         /* address to map to */
1771         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1772         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1773
1774         /* attbase - aperture base */
1775         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1776
1777         /* agpctrl */
1778         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1779
1780         /* mcgcfg */
1781         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1782         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1783         /* clear any possible error conditions */
1784         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1785         return 0;
1786 }
1787
1788 static int intel_845_configure(void)
1789 {
1790         u32 temp;
1791         u8 temp2;
1792         struct aper_size_info_8 *current_size;
1793
1794         current_size = A_SIZE_8(agp_bridge->current_size);
1795
1796         /* aperture size */
1797         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1798
1799         if (agp_bridge->apbase_config != 0) {
1800                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1801                                        agp_bridge->apbase_config);
1802         } else {
1803                 /* address to map to */
1804                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1805                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1806                 agp_bridge->apbase_config = temp;
1807         }
1808
1809         /* attbase - aperture base */
1810         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1811
1812         /* agpctrl */
1813         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1814
1815         /* agpm */
1816         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1817         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1818         /* clear any possible error conditions */
1819         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1820         return 0;
1821 }
1822
1823 static int intel_850_configure(void)
1824 {
1825         u32 temp;
1826         u16 temp2;
1827         struct aper_size_info_8 *current_size;
1828
1829         current_size = A_SIZE_8(agp_bridge->current_size);
1830
1831         /* aperture size */
1832         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1833
1834         /* address to map to */
1835         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1836         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1837
1838         /* attbase - aperture base */
1839         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1840
1841         /* agpctrl */
1842         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1843
1844         /* mcgcfg */
1845         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1846         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1847         /* clear any possible AGP-related error conditions */
1848         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1849         return 0;
1850 }
1851
1852 static int intel_860_configure(void)
1853 {
1854         u32 temp;
1855         u16 temp2;
1856         struct aper_size_info_8 *current_size;
1857
1858         current_size = A_SIZE_8(agp_bridge->current_size);
1859
1860         /* aperture size */
1861         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1862
1863         /* address to map to */
1864         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1865         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1866
1867         /* attbase - aperture base */
1868         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1869
1870         /* agpctrl */
1871         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1872
1873         /* mcgcfg */
1874         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1875         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1876         /* clear any possible AGP-related error conditions */
1877         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1878         return 0;
1879 }
1880
1881 static int intel_830mp_configure(void)
1882 {
1883         u32 temp;
1884         u16 temp2;
1885         struct aper_size_info_8 *current_size;
1886
1887         current_size = A_SIZE_8(agp_bridge->current_size);
1888
1889         /* aperture size */
1890         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1891
1892         /* address to map to */
1893         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1894         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1895
1896         /* attbase - aperture base */
1897         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1898
1899         /* agpctrl */
1900         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1901
1902         /* gmch */
1903         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1904         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1905         /* clear any possible AGP-related error conditions */
1906         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1907         return 0;
1908 }
1909
1910 static int intel_7505_configure(void)
1911 {
1912         u32 temp;
1913         u16 temp2;
1914         struct aper_size_info_8 *current_size;
1915
1916         current_size = A_SIZE_8(agp_bridge->current_size);
1917
1918         /* aperture size */
1919         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1920
1921         /* address to map to */
1922         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1923         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1924
1925         /* attbase - aperture base */
1926         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1927
1928         /* agpctrl */
1929         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1930
1931         /* mchcfg */
1932         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1933         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1934
1935         return 0;
1936 }
1937
1938 /* Setup function */
1939 static const struct gatt_mask intel_generic_masks[] =
1940 {
1941         {.mask = 0x00000017, .type = 0}
1942 };
1943
1944 static const struct aper_size_info_8 intel_815_sizes[2] =
1945 {
1946         {64, 16384, 4, 0},
1947         {32, 8192, 3, 8},
1948 };
1949
1950 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1951 {
1952         {256, 65536, 6, 0},
1953         {128, 32768, 5, 32},
1954         {64, 16384, 4, 48},
1955         {32, 8192, 3, 56},
1956         {16, 4096, 2, 60},
1957         {8, 2048, 1, 62},
1958         {4, 1024, 0, 63}
1959 };
1960
1961 static const struct aper_size_info_16 intel_generic_sizes[7] =
1962 {
1963         {256, 65536, 6, 0},
1964         {128, 32768, 5, 32},
1965         {64, 16384, 4, 48},
1966         {32, 8192, 3, 56},
1967         {16, 4096, 2, 60},
1968         {8, 2048, 1, 62},
1969         {4, 1024, 0, 63}
1970 };
1971
1972 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1973 {
1974         {256, 65536, 6, 0},
1975         {128, 32768, 5, 32},
1976         {64, 16384, 4, 48},
1977         {32, 8192, 3, 56}
1978 };
1979
1980 static const struct agp_bridge_driver intel_generic_driver = {
1981         .owner                  = THIS_MODULE,
1982         .aperture_sizes         = intel_generic_sizes,
1983         .size_type              = U16_APER_SIZE,
1984         .num_aperture_sizes     = 7,
1985         .configure              = intel_configure,
1986         .fetch_size             = intel_fetch_size,
1987         .cleanup                = intel_cleanup,
1988         .tlb_flush              = intel_tlbflush,
1989         .mask_memory            = agp_generic_mask_memory,
1990         .masks                  = intel_generic_masks,
1991         .agp_enable             = agp_generic_enable,
1992         .cache_flush            = global_cache_flush,
1993         .create_gatt_table      = agp_generic_create_gatt_table,
1994         .free_gatt_table        = agp_generic_free_gatt_table,
1995         .insert_memory          = agp_generic_insert_memory,
1996         .remove_memory          = agp_generic_remove_memory,
1997         .alloc_by_type          = agp_generic_alloc_by_type,
1998         .free_by_type           = agp_generic_free_by_type,
1999         .agp_alloc_page         = agp_generic_alloc_page,
2000         .agp_alloc_pages        = agp_generic_alloc_pages,
2001         .agp_destroy_page       = agp_generic_destroy_page,
2002         .agp_destroy_pages      = agp_generic_destroy_pages,
2003         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2004 };
2005
2006 static const struct agp_bridge_driver intel_810_driver = {
2007         .owner                  = THIS_MODULE,
2008         .aperture_sizes         = intel_i810_sizes,
2009         .size_type              = FIXED_APER_SIZE,
2010         .num_aperture_sizes     = 2,
2011         .needs_scratch_page     = true,
2012         .configure              = intel_i810_configure,
2013         .fetch_size             = intel_i810_fetch_size,
2014         .cleanup                = intel_i810_cleanup,
2015         .tlb_flush              = intel_i810_tlbflush,
2016         .mask_memory            = intel_i810_mask_memory,
2017         .masks                  = intel_i810_masks,
2018         .agp_enable             = intel_i810_agp_enable,
2019         .cache_flush            = global_cache_flush,
2020         .create_gatt_table      = agp_generic_create_gatt_table,
2021         .free_gatt_table        = agp_generic_free_gatt_table,
2022         .insert_memory          = intel_i810_insert_entries,
2023         .remove_memory          = intel_i810_remove_entries,
2024         .alloc_by_type          = intel_i810_alloc_by_type,
2025         .free_by_type           = intel_i810_free_by_type,
2026         .agp_alloc_page         = agp_generic_alloc_page,
2027         .agp_alloc_pages        = agp_generic_alloc_pages,
2028         .agp_destroy_page       = agp_generic_destroy_page,
2029         .agp_destroy_pages      = agp_generic_destroy_pages,
2030         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2031 };
2032
2033 static const struct agp_bridge_driver intel_815_driver = {
2034         .owner                  = THIS_MODULE,
2035         .aperture_sizes         = intel_815_sizes,
2036         .size_type              = U8_APER_SIZE,
2037         .num_aperture_sizes     = 2,
2038         .configure              = intel_815_configure,
2039         .fetch_size             = intel_815_fetch_size,
2040         .cleanup                = intel_8xx_cleanup,
2041         .tlb_flush              = intel_8xx_tlbflush,
2042         .mask_memory            = agp_generic_mask_memory,
2043         .masks                  = intel_generic_masks,
2044         .agp_enable             = agp_generic_enable,
2045         .cache_flush            = global_cache_flush,
2046         .create_gatt_table      = agp_generic_create_gatt_table,
2047         .free_gatt_table        = agp_generic_free_gatt_table,
2048         .insert_memory          = agp_generic_insert_memory,
2049         .remove_memory          = agp_generic_remove_memory,
2050         .alloc_by_type          = agp_generic_alloc_by_type,
2051         .free_by_type           = agp_generic_free_by_type,
2052         .agp_alloc_page         = agp_generic_alloc_page,
2053         .agp_alloc_pages        = agp_generic_alloc_pages,
2054         .agp_destroy_page       = agp_generic_destroy_page,
2055         .agp_destroy_pages      = agp_generic_destroy_pages,
2056         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2057 };
2058
2059 static const struct agp_bridge_driver intel_830_driver = {
2060         .owner                  = THIS_MODULE,
2061         .aperture_sizes         = intel_i830_sizes,
2062         .size_type              = FIXED_APER_SIZE,
2063         .num_aperture_sizes     = 4,
2064         .needs_scratch_page     = true,
2065         .configure              = intel_i830_configure,
2066         .fetch_size             = intel_i830_fetch_size,
2067         .cleanup                = intel_i830_cleanup,
2068         .tlb_flush              = intel_i810_tlbflush,
2069         .mask_memory            = intel_i810_mask_memory,
2070         .masks                  = intel_i810_masks,
2071         .agp_enable             = intel_i810_agp_enable,
2072         .cache_flush            = global_cache_flush,
2073         .create_gatt_table      = intel_i830_create_gatt_table,
2074         .free_gatt_table        = intel_i830_free_gatt_table,
2075         .insert_memory          = intel_i830_insert_entries,
2076         .remove_memory          = intel_i830_remove_entries,
2077         .alloc_by_type          = intel_i830_alloc_by_type,
2078         .free_by_type           = intel_i810_free_by_type,
2079         .agp_alloc_page         = agp_generic_alloc_page,
2080         .agp_alloc_pages        = agp_generic_alloc_pages,
2081         .agp_destroy_page       = agp_generic_destroy_page,
2082         .agp_destroy_pages      = agp_generic_destroy_pages,
2083         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2084         .chipset_flush          = intel_i830_chipset_flush,
2085 };
2086
2087 static const struct agp_bridge_driver intel_820_driver = {
2088         .owner                  = THIS_MODULE,
2089         .aperture_sizes         = intel_8xx_sizes,
2090         .size_type              = U8_APER_SIZE,
2091         .num_aperture_sizes     = 7,
2092         .configure              = intel_820_configure,
2093         .fetch_size             = intel_8xx_fetch_size,
2094         .cleanup                = intel_820_cleanup,
2095         .tlb_flush              = intel_820_tlbflush,
2096         .mask_memory            = agp_generic_mask_memory,
2097         .masks                  = intel_generic_masks,
2098         .agp_enable             = agp_generic_enable,
2099         .cache_flush            = global_cache_flush,
2100         .create_gatt_table      = agp_generic_create_gatt_table,
2101         .free_gatt_table        = agp_generic_free_gatt_table,
2102         .insert_memory          = agp_generic_insert_memory,
2103         .remove_memory          = agp_generic_remove_memory,
2104         .alloc_by_type          = agp_generic_alloc_by_type,
2105         .free_by_type           = agp_generic_free_by_type,
2106         .agp_alloc_page         = agp_generic_alloc_page,
2107         .agp_alloc_pages        = agp_generic_alloc_pages,
2108         .agp_destroy_page       = agp_generic_destroy_page,
2109         .agp_destroy_pages      = agp_generic_destroy_pages,
2110         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2111 };
2112
2113 static const struct agp_bridge_driver intel_830mp_driver = {
2114         .owner                  = THIS_MODULE,
2115         .aperture_sizes         = intel_830mp_sizes,
2116         .size_type              = U8_APER_SIZE,
2117         .num_aperture_sizes     = 4,
2118         .configure              = intel_830mp_configure,
2119         .fetch_size             = intel_8xx_fetch_size,
2120         .cleanup                = intel_8xx_cleanup,
2121         .tlb_flush              = intel_8xx_tlbflush,
2122         .mask_memory            = agp_generic_mask_memory,
2123         .masks                  = intel_generic_masks,
2124         .agp_enable             = agp_generic_enable,
2125         .cache_flush            = global_cache_flush,
2126         .create_gatt_table      = agp_generic_create_gatt_table,
2127         .free_gatt_table        = agp_generic_free_gatt_table,
2128         .insert_memory          = agp_generic_insert_memory,
2129         .remove_memory          = agp_generic_remove_memory,
2130         .alloc_by_type          = agp_generic_alloc_by_type,
2131         .free_by_type           = agp_generic_free_by_type,
2132         .agp_alloc_page         = agp_generic_alloc_page,
2133         .agp_alloc_pages        = agp_generic_alloc_pages,
2134         .agp_destroy_page       = agp_generic_destroy_page,
2135         .agp_destroy_pages      = agp_generic_destroy_pages,
2136         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2137 };
2138
2139 static const struct agp_bridge_driver intel_840_driver = {
2140         .owner                  = THIS_MODULE,
2141         .aperture_sizes         = intel_8xx_sizes,
2142         .size_type              = U8_APER_SIZE,
2143         .num_aperture_sizes     = 7,
2144         .configure              = intel_840_configure,
2145         .fetch_size             = intel_8xx_fetch_size,
2146         .cleanup                = intel_8xx_cleanup,
2147         .tlb_flush              = intel_8xx_tlbflush,
2148         .mask_memory            = agp_generic_mask_memory,
2149         .masks                  = intel_generic_masks,
2150         .agp_enable             = agp_generic_enable,
2151         .cache_flush            = global_cache_flush,
2152         .create_gatt_table      = agp_generic_create_gatt_table,
2153         .free_gatt_table        = agp_generic_free_gatt_table,
2154         .insert_memory          = agp_generic_insert_memory,
2155         .remove_memory          = agp_generic_remove_memory,
2156         .alloc_by_type          = agp_generic_alloc_by_type,
2157         .free_by_type           = agp_generic_free_by_type,
2158         .agp_alloc_page         = agp_generic_alloc_page,
2159         .agp_alloc_pages        = agp_generic_alloc_pages,
2160         .agp_destroy_page       = agp_generic_destroy_page,
2161         .agp_destroy_pages      = agp_generic_destroy_pages,
2162         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2163 };
2164
2165 static const struct agp_bridge_driver intel_845_driver = {
2166         .owner                  = THIS_MODULE,
2167         .aperture_sizes         = intel_8xx_sizes,
2168         .size_type              = U8_APER_SIZE,
2169         .num_aperture_sizes     = 7,
2170         .configure              = intel_845_configure,
2171         .fetch_size             = intel_8xx_fetch_size,
2172         .cleanup                = intel_8xx_cleanup,
2173         .tlb_flush              = intel_8xx_tlbflush,
2174         .mask_memory            = agp_generic_mask_memory,
2175         .masks                  = intel_generic_masks,
2176         .agp_enable             = agp_generic_enable,
2177         .cache_flush            = global_cache_flush,
2178         .create_gatt_table      = agp_generic_create_gatt_table,
2179         .free_gatt_table        = agp_generic_free_gatt_table,
2180         .insert_memory          = agp_generic_insert_memory,
2181         .remove_memory          = agp_generic_remove_memory,
2182         .alloc_by_type          = agp_generic_alloc_by_type,
2183         .free_by_type           = agp_generic_free_by_type,
2184         .agp_alloc_page         = agp_generic_alloc_page,
2185         .agp_alloc_pages        = agp_generic_alloc_pages,
2186         .agp_destroy_page       = agp_generic_destroy_page,
2187         .agp_destroy_pages      = agp_generic_destroy_pages,
2188         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2189 };
2190
2191 static const struct agp_bridge_driver intel_850_driver = {
2192         .owner                  = THIS_MODULE,
2193         .aperture_sizes         = intel_8xx_sizes,
2194         .size_type              = U8_APER_SIZE,
2195         .num_aperture_sizes     = 7,
2196         .configure              = intel_850_configure,
2197         .fetch_size             = intel_8xx_fetch_size,
2198         .cleanup                = intel_8xx_cleanup,
2199         .tlb_flush              = intel_8xx_tlbflush,
2200         .mask_memory            = agp_generic_mask_memory,
2201         .masks                  = intel_generic_masks,
2202         .agp_enable             = agp_generic_enable,
2203         .cache_flush            = global_cache_flush,
2204         .create_gatt_table      = agp_generic_create_gatt_table,
2205         .free_gatt_table        = agp_generic_free_gatt_table,
2206         .insert_memory          = agp_generic_insert_memory,
2207         .remove_memory          = agp_generic_remove_memory,
2208         .alloc_by_type          = agp_generic_alloc_by_type,
2209         .free_by_type           = agp_generic_free_by_type,
2210         .agp_alloc_page         = agp_generic_alloc_page,
2211         .agp_alloc_pages        = agp_generic_alloc_pages,
2212         .agp_destroy_page       = agp_generic_destroy_page,
2213         .agp_destroy_pages      = agp_generic_destroy_pages,
2214         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2215 };
2216
2217 static const struct agp_bridge_driver intel_860_driver = {
2218         .owner                  = THIS_MODULE,
2219         .aperture_sizes         = intel_8xx_sizes,
2220         .size_type              = U8_APER_SIZE,
2221         .num_aperture_sizes     = 7,
2222         .configure              = intel_860_configure,
2223         .fetch_size             = intel_8xx_fetch_size,
2224         .cleanup                = intel_8xx_cleanup,
2225         .tlb_flush              = intel_8xx_tlbflush,
2226         .mask_memory            = agp_generic_mask_memory,
2227         .masks                  = intel_generic_masks,
2228         .agp_enable             = agp_generic_enable,
2229         .cache_flush            = global_cache_flush,
2230         .create_gatt_table      = agp_generic_create_gatt_table,
2231         .free_gatt_table        = agp_generic_free_gatt_table,
2232         .insert_memory          = agp_generic_insert_memory,
2233         .remove_memory          = agp_generic_remove_memory,
2234         .alloc_by_type          = agp_generic_alloc_by_type,
2235         .free_by_type           = agp_generic_free_by_type,
2236         .agp_alloc_page         = agp_generic_alloc_page,
2237         .agp_alloc_pages        = agp_generic_alloc_pages,
2238         .agp_destroy_page       = agp_generic_destroy_page,
2239         .agp_destroy_pages      = agp_generic_destroy_pages,
2240         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2241 };
2242
2243 static const struct agp_bridge_driver intel_915_driver = {
2244         .owner                  = THIS_MODULE,
2245         .aperture_sizes         = intel_i830_sizes,
2246         .size_type              = FIXED_APER_SIZE,
2247         .num_aperture_sizes     = 4,
2248         .needs_scratch_page     = true,
2249         .configure              = intel_i915_configure,
2250         .fetch_size             = intel_i9xx_fetch_size,
2251         .cleanup                = intel_i915_cleanup,
2252         .tlb_flush              = intel_i810_tlbflush,
2253         .mask_memory            = intel_i810_mask_memory,
2254         .masks                  = intel_i810_masks,
2255         .agp_enable             = intel_i810_agp_enable,
2256         .cache_flush            = global_cache_flush,
2257         .create_gatt_table      = intel_i915_create_gatt_table,
2258         .free_gatt_table        = intel_i830_free_gatt_table,
2259         .insert_memory          = intel_i915_insert_entries,
2260         .remove_memory          = intel_i915_remove_entries,
2261         .alloc_by_type          = intel_i830_alloc_by_type,
2262         .free_by_type           = intel_i810_free_by_type,
2263         .agp_alloc_page         = agp_generic_alloc_page,
2264         .agp_alloc_pages        = agp_generic_alloc_pages,
2265         .agp_destroy_page       = agp_generic_destroy_page,
2266         .agp_destroy_pages      = agp_generic_destroy_pages,
2267         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2268         .chipset_flush          = intel_i915_chipset_flush,
2269 #ifdef USE_PCI_DMA_API
2270         .agp_map_page           = intel_agp_map_page,
2271         .agp_unmap_page         = intel_agp_unmap_page,
2272         .agp_map_memory         = intel_agp_map_memory,
2273         .agp_unmap_memory       = intel_agp_unmap_memory,
2274 #endif
2275 };
2276
2277 static const struct agp_bridge_driver intel_i965_driver = {
2278         .owner                  = THIS_MODULE,
2279         .aperture_sizes         = intel_i830_sizes,
2280         .size_type              = FIXED_APER_SIZE,
2281         .num_aperture_sizes     = 4,
2282         .needs_scratch_page     = true,
2283         .configure              = intel_i915_configure,
2284         .fetch_size             = intel_i9xx_fetch_size,
2285         .cleanup                = intel_i915_cleanup,
2286         .tlb_flush              = intel_i810_tlbflush,
2287         .mask_memory            = intel_i965_mask_memory,
2288         .masks                  = intel_i810_masks,
2289         .agp_enable             = intel_i810_agp_enable,
2290         .cache_flush            = global_cache_flush,
2291         .create_gatt_table      = intel_i965_create_gatt_table,
2292         .free_gatt_table        = intel_i830_free_gatt_table,
2293         .insert_memory          = intel_i915_insert_entries,
2294         .remove_memory          = intel_i915_remove_entries,
2295         .alloc_by_type          = intel_i830_alloc_by_type,
2296         .free_by_type           = intel_i810_free_by_type,
2297         .agp_alloc_page         = agp_generic_alloc_page,
2298         .agp_alloc_pages        = agp_generic_alloc_pages,
2299         .agp_destroy_page       = agp_generic_destroy_page,
2300         .agp_destroy_pages      = agp_generic_destroy_pages,
2301         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2302         .chipset_flush          = intel_i915_chipset_flush,
2303 #ifdef USE_PCI_DMA_API
2304         .agp_map_page           = intel_agp_map_page,
2305         .agp_unmap_page         = intel_agp_unmap_page,
2306         .agp_map_memory         = intel_agp_map_memory,
2307         .agp_unmap_memory       = intel_agp_unmap_memory,
2308 #endif
2309 };
2310
2311 static const struct agp_bridge_driver intel_7505_driver = {
2312         .owner                  = THIS_MODULE,
2313         .aperture_sizes         = intel_8xx_sizes,
2314         .size_type              = U8_APER_SIZE,
2315         .num_aperture_sizes     = 7,
2316         .configure              = intel_7505_configure,
2317         .fetch_size             = intel_8xx_fetch_size,
2318         .cleanup                = intel_8xx_cleanup,
2319         .tlb_flush              = intel_8xx_tlbflush,
2320         .mask_memory            = agp_generic_mask_memory,
2321         .masks                  = intel_generic_masks,
2322         .agp_enable             = agp_generic_enable,
2323         .cache_flush            = global_cache_flush,
2324         .create_gatt_table      = agp_generic_create_gatt_table,
2325         .free_gatt_table        = agp_generic_free_gatt_table,
2326         .insert_memory          = agp_generic_insert_memory,
2327         .remove_memory          = agp_generic_remove_memory,
2328         .alloc_by_type          = agp_generic_alloc_by_type,
2329         .free_by_type           = agp_generic_free_by_type,
2330         .agp_alloc_page         = agp_generic_alloc_page,
2331         .agp_alloc_pages        = agp_generic_alloc_pages,
2332         .agp_destroy_page       = agp_generic_destroy_page,
2333         .agp_destroy_pages      = agp_generic_destroy_pages,
2334         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2335 };
2336
2337 static const struct agp_bridge_driver intel_g33_driver = {
2338         .owner                  = THIS_MODULE,
2339         .aperture_sizes         = intel_i830_sizes,
2340         .size_type              = FIXED_APER_SIZE,
2341         .num_aperture_sizes     = 4,
2342         .needs_scratch_page     = true,
2343         .configure              = intel_i915_configure,
2344         .fetch_size             = intel_i9xx_fetch_size,
2345         .cleanup                = intel_i915_cleanup,
2346         .tlb_flush              = intel_i810_tlbflush,
2347         .mask_memory            = intel_i965_mask_memory,
2348         .masks                  = intel_i810_masks,
2349         .agp_enable             = intel_i810_agp_enable,
2350         .cache_flush            = global_cache_flush,
2351         .create_gatt_table      = intel_i915_create_gatt_table,
2352         .free_gatt_table        = intel_i830_free_gatt_table,
2353         .insert_memory          = intel_i915_insert_entries,
2354         .remove_memory          = intel_i915_remove_entries,
2355         .alloc_by_type          = intel_i830_alloc_by_type,
2356         .free_by_type           = intel_i810_free_by_type,
2357         .agp_alloc_page         = agp_generic_alloc_page,
2358         .agp_alloc_pages        = agp_generic_alloc_pages,
2359         .agp_destroy_page       = agp_generic_destroy_page,
2360         .agp_destroy_pages      = agp_generic_destroy_pages,
2361         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2362         .chipset_flush          = intel_i915_chipset_flush,
2363 #ifdef USE_PCI_DMA_API
2364         .agp_map_page           = intel_agp_map_page,
2365         .agp_unmap_page         = intel_agp_unmap_page,
2366         .agp_map_memory         = intel_agp_map_memory,
2367         .agp_unmap_memory       = intel_agp_unmap_memory,
2368 #endif
2369 };
2370
2371 static int find_gmch(u16 device)
2372 {
2373         struct pci_dev *gmch_device;
2374
2375         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2376         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2377                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
2378                                              device, gmch_device);
2379         }
2380
2381         if (!gmch_device)
2382                 return 0;
2383
2384         intel_private.pcidev = gmch_device;
2385         return 1;
2386 }
2387
2388 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
2389  * driver and gmch_driver must be non-null, and find_gmch will determine
2390  * which one should be used if a gmch_chip_id is present.
2391  */
2392 static const struct intel_driver_description {
2393         unsigned int chip_id;
2394         unsigned int gmch_chip_id;
2395         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2396         char *name;
2397         const struct agp_bridge_driver *driver;
2398         const struct agp_bridge_driver *gmch_driver;
2399 } intel_agp_chipsets[] = {
2400         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2401         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2402         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2403         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2404                 NULL, &intel_810_driver },
2405         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2406                 NULL, &intel_810_driver },
2407         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2408                 NULL, &intel_810_driver },
2409         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2410                 &intel_815_driver, &intel_810_driver },
2411         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2412         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2413         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2414                 &intel_830mp_driver, &intel_830_driver },
2415         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2416         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2417         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2418                 &intel_845_driver, &intel_830_driver },
2419         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2420         { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
2421                 &intel_845_driver, &intel_830_driver },
2422         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2423         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2424                 &intel_845_driver, &intel_830_driver },
2425         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2426         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2427                 &intel_845_driver, &intel_830_driver },
2428         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2429         { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2430                 NULL, &intel_915_driver },
2431         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2432                 NULL, &intel_915_driver },
2433         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2434                 NULL, &intel_915_driver },
2435         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2436                 NULL, &intel_915_driver },
2437         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2438                 NULL, &intel_915_driver },
2439         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2440                 NULL, &intel_915_driver },
2441         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2442                 NULL, &intel_i965_driver },
2443         { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2444                 NULL, &intel_i965_driver },
2445         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2446                 NULL, &intel_i965_driver },
2447         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2448                 NULL, &intel_i965_driver },
2449         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2450                 NULL, &intel_i965_driver },
2451         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2452                 NULL, &intel_i965_driver },
2453         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2454         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2455         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2456                 NULL, &intel_g33_driver },
2457         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2458                 NULL, &intel_g33_driver },
2459         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2460                 NULL, &intel_g33_driver },
2461         { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, 0, "GMA3150",
2462                 NULL, &intel_g33_driver },
2463         { PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, 0, "GMA3150",
2464                 NULL, &intel_g33_driver },
2465         { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2466             "GM45", NULL, &intel_i965_driver },
2467         { PCI_DEVICE_ID_INTEL_EAGLELAKE_HB, PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, 0,
2468             "Eaglelake", NULL, &intel_i965_driver },
2469         { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2470             "Q45/Q43", NULL, &intel_i965_driver },
2471         { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2472             "G45/G43", NULL, &intel_i965_driver },
2473         { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0,
2474             "B43", NULL, &intel_i965_driver },
2475         { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2476             "G41", NULL, &intel_i965_driver },
2477         { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 0,
2478             "HD Graphics", NULL, &intel_i965_driver },
2479         { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2480             "HD Graphics", NULL, &intel_i965_driver },
2481         { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2482             "HD Graphics", NULL, &intel_i965_driver },
2483         { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2484             "HD Graphics", NULL, &intel_i965_driver },
2485         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG, 0,
2486             "Sandybridge", NULL, &intel_i965_driver },
2487         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG, 0,
2488             "Sandybridge", NULL, &intel_i965_driver },
2489         { 0, 0, 0, NULL, NULL, NULL }
2490 };
2491
2492 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2493                                      const struct pci_device_id *ent)
2494 {
2495         struct agp_bridge_data *bridge;
2496         u8 cap_ptr = 0;
2497         struct resource *r;
2498         int i, err;
2499
2500         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2501
2502         bridge = agp_alloc_bridge();
2503         if (!bridge)
2504                 return -ENOMEM;
2505
2506         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2507                 /* In case that multiple models of gfx chip may
2508                    stand on same host bridge type, this can be
2509                    sure we detect the right IGD. */
2510                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2511                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2512                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2513                                 bridge->driver =
2514                                         intel_agp_chipsets[i].gmch_driver;
2515                                 break;
2516                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2517                                 continue;
2518                         } else {
2519                                 bridge->driver = intel_agp_chipsets[i].driver;
2520                                 break;
2521                         }
2522                 }
2523         }
2524
2525         if (intel_agp_chipsets[i].name == NULL) {
2526                 if (cap_ptr)
2527                         dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2528                                  pdev->vendor, pdev->device);
2529                 agp_put_bridge(bridge);
2530                 return -ENODEV;
2531         }
2532
2533         if (bridge->driver == NULL) {
2534                 /* bridge has no AGP and no IGD detected */
2535                 if (cap_ptr)
2536                         dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2537                                  intel_agp_chipsets[i].gmch_chip_id);
2538                 agp_put_bridge(bridge);
2539                 return -ENODEV;
2540         }
2541
2542         bridge->dev = pdev;
2543         bridge->capndx = cap_ptr;
2544         bridge->dev_private_data = &intel_private;
2545
2546         dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
2547
2548         /*
2549         * The following fixes the case where the BIOS has "forgotten" to
2550         * provide an address range for the GART.
2551         * 20030610 - hamish@zot.org
2552         */
2553         r = &pdev->resource[0];
2554         if (!r->start && r->end) {
2555                 if (pci_assign_resource(pdev, 0)) {
2556                         dev_err(&pdev->dev, "can't assign resource 0\n");
2557                         agp_put_bridge(bridge);
2558                         return -ENODEV;
2559                 }
2560         }
2561
2562         /*
2563         * If the device has not been properly setup, the following will catch
2564         * the problem and should stop the system from crashing.
2565         * 20030610 - hamish@zot.org
2566         */
2567         if (pci_enable_device(pdev)) {
2568                 dev_err(&pdev->dev, "can't enable PCI device\n");
2569                 agp_put_bridge(bridge);
2570                 return -ENODEV;
2571         }
2572
2573         /* Fill in the mode register */
2574         if (cap_ptr) {
2575                 pci_read_config_dword(pdev,
2576                                 bridge->capndx+PCI_AGP_STATUS,
2577                                 &bridge->mode);
2578         }
2579
2580         if (bridge->driver->mask_memory == intel_i965_mask_memory) {
2581                 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36)))
2582                         dev_err(&intel_private.pcidev->dev,
2583                                 "set gfx device dma mask 36bit failed!\n");
2584                 else
2585                         pci_set_consistent_dma_mask(intel_private.pcidev,
2586                                                     DMA_BIT_MASK(36));
2587         }
2588
2589         pci_set_drvdata(pdev, bridge);
2590         err = agp_add_bridge(bridge);
2591         if (!err)
2592                 intel_agp_enabled = 1;
2593         return err;
2594 }
2595
2596 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2597 {
2598         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2599
2600         agp_remove_bridge(bridge);
2601
2602         if (intel_private.pcidev)
2603                 pci_dev_put(intel_private.pcidev);
2604
2605         agp_put_bridge(bridge);
2606 }
2607
2608 #ifdef CONFIG_PM
2609 static int agp_intel_resume(struct pci_dev *pdev)
2610 {
2611         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2612         int ret_val;
2613
2614         if (bridge->driver == &intel_generic_driver)
2615                 intel_configure();
2616         else if (bridge->driver == &intel_850_driver)
2617                 intel_850_configure();
2618         else if (bridge->driver == &intel_845_driver)
2619                 intel_845_configure();
2620         else if (bridge->driver == &intel_830mp_driver)
2621                 intel_830mp_configure();
2622         else if (bridge->driver == &intel_915_driver)
2623                 intel_i915_configure();
2624         else if (bridge->driver == &intel_830_driver)
2625                 intel_i830_configure();
2626         else if (bridge->driver == &intel_810_driver)
2627                 intel_i810_configure();
2628         else if (bridge->driver == &intel_i965_driver)
2629                 intel_i915_configure();
2630
2631         ret_val = agp_rebind_memory();
2632         if (ret_val != 0)
2633                 return ret_val;
2634
2635         return 0;
2636 }
2637 #endif
2638
2639 static struct pci_device_id agp_intel_pci_table[] = {
2640 #define ID(x)                                           \
2641         {                                               \
2642         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2643         .class_mask     = ~0,                           \
2644         .vendor         = PCI_VENDOR_ID_INTEL,          \
2645         .device         = x,                            \
2646         .subvendor      = PCI_ANY_ID,                   \
2647         .subdevice      = PCI_ANY_ID,                   \
2648         }
2649         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2650         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2651         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2652         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2653         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2654         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2655         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2656         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2657         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2658         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2659         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2660         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2661         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2662         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2663         ID(PCI_DEVICE_ID_INTEL_82854_HB),
2664         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2665         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2666         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2667         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2668         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2669         ID(PCI_DEVICE_ID_INTEL_7505_0),
2670         ID(PCI_DEVICE_ID_INTEL_7205_0),
2671         ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2672         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2673         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2674         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2675         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2676         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2677         ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB),
2678         ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB),
2679         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2680         ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2681         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2682         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2683         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2684         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2685         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2686         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2687         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2688         ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2689         ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB),
2690         ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2691         ID(PCI_DEVICE_ID_INTEL_G45_HB),
2692         ID(PCI_DEVICE_ID_INTEL_G41_HB),
2693         ID(PCI_DEVICE_ID_INTEL_B43_HB),
2694         ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
2695         ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
2696         ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
2697         ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
2698         ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),
2699         ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB),
2700         { }
2701 };
2702
2703 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2704
2705 static struct pci_driver agp_intel_pci_driver = {
2706         .name           = "agpgart-intel",
2707         .id_table       = agp_intel_pci_table,
2708         .probe          = agp_intel_probe,
2709         .remove         = __devexit_p(agp_intel_remove),
2710 #ifdef CONFIG_PM
2711         .resume         = agp_intel_resume,
2712 #endif
2713 };
2714
2715 static int __init agp_intel_init(void)
2716 {
2717         if (agp_off)
2718                 return -EINVAL;
2719         return pci_register_driver(&agp_intel_pci_driver);
2720 }
2721
2722 static void __exit agp_intel_cleanup(void)
2723 {
2724         pci_unregister_driver(&agp_intel_pci_driver);
2725 }
2726
2727 module_init(agp_intel_init);
2728 module_exit(agp_intel_cleanup);
2729
2730 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2731 MODULE_LICENSE("GPL and additional rights");