6b9fb2179264ee602af0d893c8e1edd71a3f32b9
[sfrench/cifs-2.6.git] / drivers / char / agp / intel-agp.c
1 /*
2  * Intel AGPGART routines.
3  */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
11 #include "agp.h"
12
13 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
14 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
15 #define PCI_DEVICE_ID_INTEL_82965G_1_HB     0x2980
16 #define PCI_DEVICE_ID_INTEL_82965G_1_IG     0x2982
17 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
18 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
19 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
20 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
21
22 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
23                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
24                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
25                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB)
26
27
28 extern int agp_memory_reserved;
29
30
31 /* Intel 815 register */
32 #define INTEL_815_APCONT        0x51
33 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
34
35 /* Intel i820 registers */
36 #define INTEL_I820_RDCR         0x51
37 #define INTEL_I820_ERRSTS       0xc8
38
39 /* Intel i840 registers */
40 #define INTEL_I840_MCHCFG       0x50
41 #define INTEL_I840_ERRSTS       0xc8
42
43 /* Intel i850 registers */
44 #define INTEL_I850_MCHCFG       0x50
45 #define INTEL_I850_ERRSTS       0xc8
46
47 /* intel 915G registers */
48 #define I915_GMADDR     0x18
49 #define I915_MMADDR     0x10
50 #define I915_PTEADDR    0x1C
51 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
52 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
53
54 /* Intel 965G registers */
55 #define I965_MSAC 0x62
56
57 /* Intel 7505 registers */
58 #define INTEL_I7505_APSIZE      0x74
59 #define INTEL_I7505_NCAPID      0x60
60 #define INTEL_I7505_NISTAT      0x6c
61 #define INTEL_I7505_ATTBASE     0x78
62 #define INTEL_I7505_ERRSTS      0x42
63 #define INTEL_I7505_AGPCTRL     0x70
64 #define INTEL_I7505_MCHCFG      0x50
65
66 static struct aper_size_info_fixed intel_i810_sizes[] =
67 {
68         {64, 16384, 4},
69         /* The 32M mode still requires a 64k gatt */
70         {32, 8192, 4}
71 };
72
73 #define AGP_DCACHE_MEMORY       1
74 #define AGP_PHYS_MEMORY         2
75 #define INTEL_AGP_CACHED_MEMORY 3
76
77 static struct gatt_mask intel_i810_masks[] =
78 {
79         {.mask = I810_PTE_VALID, .type = 0},
80         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
81         {.mask = I810_PTE_VALID, .type = 0},
82         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
83          .type = INTEL_AGP_CACHED_MEMORY}
84 };
85
86 static struct _intel_i810_private {
87         struct pci_dev *i810_dev;       /* device one */
88         volatile u8 __iomem *registers;
89         int num_dcache_entries;
90 } intel_i810_private;
91
92
93 static int intel_i810_fetch_size(void)
94 {
95         u32 smram_miscc;
96         struct aper_size_info_fixed *values;
97
98         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
99         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
100
101         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
102                 printk(KERN_WARNING PFX "i810 is disabled\n");
103                 return 0;
104         }
105         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
106                 agp_bridge->previous_size =
107                         agp_bridge->current_size = (void *) (values + 1);
108                 agp_bridge->aperture_size_idx = 1;
109                 return values[1].size;
110         } else {
111                 agp_bridge->previous_size =
112                         agp_bridge->current_size = (void *) (values);
113                 agp_bridge->aperture_size_idx = 0;
114                 return values[0].size;
115         }
116
117         return 0;
118 }
119
120 static int intel_i810_configure(void)
121 {
122         struct aper_size_info_fixed *current_size;
123         u32 temp;
124         int i;
125
126         current_size = A_SIZE_FIX(agp_bridge->current_size);
127
128         if (!intel_i810_private.registers) {
129                 pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp);
130                 temp &= 0xfff80000;
131
132                 intel_i810_private.registers = ioremap(temp, 128 * 4096);
133                 if (!intel_i810_private.registers) {
134                         printk(KERN_ERR PFX "Unable to remap memory.\n");
135                         return -ENOMEM;
136                 }
137         }
138
139         if ((readl(intel_i810_private.registers+I810_DRAM_CTL)
140                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
141                 /* This will need to be dynamically assigned */
142                 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
143                 intel_i810_private.num_dcache_entries = 1024;
144         }
145         pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp);
146         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
147         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_i810_private.registers+I810_PGETBL_CTL);
148         readl(intel_i810_private.registers+I810_PGETBL_CTL);    /* PCI Posting. */
149
150         if (agp_bridge->driver->needs_scratch_page) {
151                 for (i = 0; i < current_size->num_entries; i++) {
152                         writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4));
153                         readl(intel_i810_private.registers+I810_PTE_BASE+(i*4));        /* PCI posting. */
154                 }
155         }
156         global_cache_flush();
157         return 0;
158 }
159
160 static void intel_i810_cleanup(void)
161 {
162         writel(0, intel_i810_private.registers+I810_PGETBL_CTL);
163         readl(intel_i810_private.registers);    /* PCI Posting. */
164         iounmap(intel_i810_private.registers);
165 }
166
167 static void intel_i810_tlbflush(struct agp_memory *mem)
168 {
169         return;
170 }
171
172 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
173 {
174         return;
175 }
176
177 /* Exists to support ARGB cursors */
178 static void *i8xx_alloc_pages(void)
179 {
180         struct page * page;
181
182         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
183         if (page == NULL)
184                 return NULL;
185
186         if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) {
187                 global_flush_tlb();
188                 __free_page(page);
189                 return NULL;
190         }
191         global_flush_tlb();
192         get_page(page);
193         SetPageLocked(page);
194         atomic_inc(&agp_bridge->current_memory_agp);
195         return page_address(page);
196 }
197
198 static void i8xx_destroy_pages(void *addr)
199 {
200         struct page *page;
201
202         if (addr == NULL)
203                 return;
204
205         page = virt_to_page(addr);
206         change_page_attr(page, 4, PAGE_KERNEL);
207         global_flush_tlb();
208         put_page(page);
209         unlock_page(page);
210         free_pages((unsigned long)addr, 2);
211         atomic_dec(&agp_bridge->current_memory_agp);
212 }
213
214 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
215                                         int type)
216 {
217         if (type < AGP_USER_TYPES)
218                 return type;
219         else if (type == AGP_USER_CACHED_MEMORY)
220                 return INTEL_AGP_CACHED_MEMORY;
221         else
222                 return 0;
223 }
224
225 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
226                                 int type)
227 {
228         int i, j, num_entries;
229         void *temp;
230         int ret = -EINVAL;
231         int mask_type;
232
233         if (mem->page_count == 0)
234                 goto out;
235
236         temp = agp_bridge->current_size;
237         num_entries = A_SIZE_FIX(temp)->num_entries;
238
239         if ((pg_start + mem->page_count) > num_entries)
240                 goto out_err;
241
242
243         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
244                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
245                         ret = -EBUSY;
246                         goto out_err;
247                 }
248         }
249
250         if (type != mem->type)
251                 goto out_err;
252
253         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
254
255         switch (mask_type) {
256         case AGP_DCACHE_MEMORY:
257                 if (!mem->is_flushed)
258                         global_cache_flush();
259                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
260                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
261                                intel_i810_private.registers+I810_PTE_BASE+(i*4));
262                 }
263                 readl(intel_i810_private.registers+I810_PTE_BASE+((i-1)*4));
264                 break;
265         case AGP_PHYS_MEMORY:
266         case AGP_NORMAL_MEMORY:
267                 if (!mem->is_flushed)
268                         global_cache_flush();
269                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
270                         writel(agp_bridge->driver->mask_memory(agp_bridge,
271                                                                mem->memory[i],
272                                                                mask_type),
273                                intel_i810_private.registers+I810_PTE_BASE+(j*4));
274                 }
275                 readl(intel_i810_private.registers+I810_PTE_BASE+((j-1)*4));
276                 break;
277         default:
278                 goto out_err;
279         }
280
281         agp_bridge->driver->tlb_flush(mem);
282 out:
283         ret = 0;
284 out_err:
285         mem->is_flushed = 1;
286         return ret;
287 }
288
289 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
290                                 int type)
291 {
292         int i;
293
294         if (mem->page_count == 0)
295                 return 0;
296
297         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
298                 writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4));
299         }
300         readl(intel_i810_private.registers+I810_PTE_BASE+((i-1)*4));
301
302         agp_bridge->driver->tlb_flush(mem);
303         return 0;
304 }
305
306 /*
307  * The i810/i830 requires a physical address to program its mouse
308  * pointer into hardware.
309  * However the Xserver still writes to it through the agp aperture.
310  */
311 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
312 {
313         struct agp_memory *new;
314         void *addr;
315
316         if (pg_count != 1 && pg_count != 4)
317                 return NULL;
318
319         switch (pg_count) {
320         case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
321                 global_flush_tlb();
322                 break;
323         case 4:
324                 /* kludge to get 4 physical pages for ARGB cursor */
325                 addr = i8xx_alloc_pages();
326                 break;
327         default:
328                 return NULL;
329         }
330
331         if (addr == NULL)
332                 return NULL;
333
334         new = agp_create_memory(pg_count);
335         if (new == NULL)
336                 return NULL;
337
338         new->memory[0] = virt_to_gart(addr);
339         if (pg_count == 4) {
340                 /* kludge to get 4 physical pages for ARGB cursor */
341                 new->memory[1] = new->memory[0] + PAGE_SIZE;
342                 new->memory[2] = new->memory[1] + PAGE_SIZE;
343                 new->memory[3] = new->memory[2] + PAGE_SIZE;
344         }
345         new->page_count = pg_count;
346         new->num_scratch_pages = pg_count;
347         new->type = AGP_PHYS_MEMORY;
348         new->physical = new->memory[0];
349         return new;
350 }
351
352 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
353 {
354         struct agp_memory *new;
355
356         if (type == AGP_DCACHE_MEMORY) {
357                 if (pg_count != intel_i810_private.num_dcache_entries)
358                         return NULL;
359
360                 new = agp_create_memory(1);
361                 if (new == NULL)
362                         return NULL;
363
364                 new->type = AGP_DCACHE_MEMORY;
365                 new->page_count = pg_count;
366                 new->num_scratch_pages = 0;
367                 agp_free_page_array(new);
368                 return new;
369         }
370         if (type == AGP_PHYS_MEMORY)
371                 return alloc_agpphysmem_i8xx(pg_count, type);
372         return NULL;
373 }
374
375 static void intel_i810_free_by_type(struct agp_memory *curr)
376 {
377         agp_free_key(curr->key);
378         if (curr->type == AGP_PHYS_MEMORY) {
379                 if (curr->page_count == 4)
380                         i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
381                 else {
382                         agp_bridge->driver->agp_destroy_page(
383                                  gart_to_virt(curr->memory[0]));
384                         global_flush_tlb();
385                 }
386                 agp_free_page_array(curr);
387         }
388         kfree(curr);
389 }
390
391 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
392         unsigned long addr, int type)
393 {
394         /* Type checking must be done elsewhere */
395         return addr | bridge->driver->masks[type].mask;
396 }
397
398 static struct aper_size_info_fixed intel_i830_sizes[] =
399 {
400         {128, 32768, 5},
401         /* The 64M mode still requires a 128k gatt */
402         {64, 16384, 5},
403         {256, 65536, 6},
404         {512, 131072, 7},
405 };
406
407 static struct _intel_i830_private {
408         struct pci_dev *i830_dev;               /* device one */
409         volatile u8 __iomem *registers;
410         volatile u32 __iomem *gtt;              /* I915G */
411         /* gtt_entries is the number of gtt entries that are already mapped
412          * to stolen memory.  Stolen memory is larger than the memory mapped
413          * through gtt_entries, as it includes some reserved space for the BIOS
414          * popup and for the GTT.
415          */
416         int gtt_entries;
417 } intel_i830_private;
418
419 static void intel_i830_init_gtt_entries(void)
420 {
421         u16 gmch_ctrl;
422         int gtt_entries;
423         u8 rdct;
424         int local = 0;
425         static const int ddt[4] = { 0, 16, 32, 64 };
426         int size; /* reserved space (in kb) at the top of stolen memory */
427
428         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
429
430         if (IS_I965) {
431                 u32 pgetbl_ctl;
432
433                 pci_read_config_dword(agp_bridge->dev, I810_PGETBL_CTL,
434                                       &pgetbl_ctl);
435                 /* The 965 has a field telling us the size of the GTT,
436                  * which may be larger than what is necessary to map the
437                  * aperture.
438                  */
439                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
440                 case I965_PGETBL_SIZE_128KB:
441                         size = 128;
442                         break;
443                 case I965_PGETBL_SIZE_256KB:
444                         size = 256;
445                         break;
446                 case I965_PGETBL_SIZE_512KB:
447                         size = 512;
448                         break;
449                 default:
450                         printk(KERN_INFO PFX "Unknown page table size, "
451                                "assuming 512KB\n");
452                         size = 512;
453                 }
454                 size += 4; /* add in BIOS popup space */
455         } else {
456                 /* On previous hardware, the GTT size was just what was
457                  * required to map the aperture.
458                  */
459                 size = agp_bridge->driver->fetch_size() + 4;
460         }
461
462         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
463             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
464                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
465                 case I830_GMCH_GMS_STOLEN_512:
466                         gtt_entries = KB(512) - KB(size);
467                         break;
468                 case I830_GMCH_GMS_STOLEN_1024:
469                         gtt_entries = MB(1) - KB(size);
470                         break;
471                 case I830_GMCH_GMS_STOLEN_8192:
472                         gtt_entries = MB(8) - KB(size);
473                         break;
474                 case I830_GMCH_GMS_LOCAL:
475                         rdct = readb(intel_i830_private.registers+I830_RDRAM_CHANNEL_TYPE);
476                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
477                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
478                         local = 1;
479                         break;
480                 default:
481                         gtt_entries = 0;
482                         break;
483                 }
484         } else {
485                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
486                 case I855_GMCH_GMS_STOLEN_1M:
487                         gtt_entries = MB(1) - KB(size);
488                         break;
489                 case I855_GMCH_GMS_STOLEN_4M:
490                         gtt_entries = MB(4) - KB(size);
491                         break;
492                 case I855_GMCH_GMS_STOLEN_8M:
493                         gtt_entries = MB(8) - KB(size);
494                         break;
495                 case I855_GMCH_GMS_STOLEN_16M:
496                         gtt_entries = MB(16) - KB(size);
497                         break;
498                 case I855_GMCH_GMS_STOLEN_32M:
499                         gtt_entries = MB(32) - KB(size);
500                         break;
501                 case I915_GMCH_GMS_STOLEN_48M:
502                         /* Check it's really I915G */
503                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
504                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
505                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
506                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965 )
507                                 gtt_entries = MB(48) - KB(size);
508                         else
509                                 gtt_entries = 0;
510                         break;
511                 case I915_GMCH_GMS_STOLEN_64M:
512                         /* Check it's really I915G */
513                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
514                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
515                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
516                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965)
517                                 gtt_entries = MB(64) - KB(size);
518                         else
519                                 gtt_entries = 0;
520                 default:
521                         gtt_entries = 0;
522                         break;
523                 }
524         }
525         if (gtt_entries > 0)
526                 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
527                        gtt_entries / KB(1), local ? "local" : "stolen");
528         else
529                 printk(KERN_INFO PFX
530                        "No pre-allocated video memory detected.\n");
531         gtt_entries /= KB(4);
532
533         intel_i830_private.gtt_entries = gtt_entries;
534 }
535
536 /* The intel i830 automatically initializes the agp aperture during POST.
537  * Use the memory already set aside for in the GTT.
538  */
539 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
540 {
541         int page_order;
542         struct aper_size_info_fixed *size;
543         int num_entries;
544         u32 temp;
545
546         size = agp_bridge->current_size;
547         page_order = size->page_order;
548         num_entries = size->num_entries;
549         agp_bridge->gatt_table_real = NULL;
550
551         pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp);
552         temp &= 0xfff80000;
553
554         intel_i830_private.registers = ioremap(temp,128 * 4096);
555         if (!intel_i830_private.registers)
556                 return -ENOMEM;
557
558         temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
559         global_cache_flush();   /* FIXME: ?? */
560
561         /* we have to call this as early as possible after the MMIO base address is known */
562         intel_i830_init_gtt_entries();
563
564         agp_bridge->gatt_table = NULL;
565
566         agp_bridge->gatt_bus_addr = temp;
567
568         return 0;
569 }
570
571 /* Return the gatt table to a sane state. Use the top of stolen
572  * memory for the GTT.
573  */
574 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
575 {
576         return 0;
577 }
578
579 static int intel_i830_fetch_size(void)
580 {
581         u16 gmch_ctrl;
582         struct aper_size_info_fixed *values;
583
584         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
585
586         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
587             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
588                 /* 855GM/852GM/865G has 128MB aperture size */
589                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
590                 agp_bridge->aperture_size_idx = 0;
591                 return values[0].size;
592         }
593
594         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
595
596         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
597                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
598                 agp_bridge->aperture_size_idx = 0;
599                 return values[0].size;
600         } else {
601                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
602                 agp_bridge->aperture_size_idx = 1;
603                 return values[1].size;
604         }
605
606         return 0;
607 }
608
609 static int intel_i830_configure(void)
610 {
611         struct aper_size_info_fixed *current_size;
612         u32 temp;
613         u16 gmch_ctrl;
614         int i;
615
616         current_size = A_SIZE_FIX(agp_bridge->current_size);
617
618         pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp);
619         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
620
621         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
622         gmch_ctrl |= I830_GMCH_ENABLED;
623         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
624
625         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL);
626         readl(intel_i830_private.registers+I810_PGETBL_CTL);    /* PCI Posting. */
627
628         if (agp_bridge->driver->needs_scratch_page) {
629                 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) {
630                         writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4));
631                         readl(intel_i830_private.registers+I810_PTE_BASE+(i*4));        /* PCI Posting. */
632                 }
633         }
634
635         global_cache_flush();
636         return 0;
637 }
638
639 static void intel_i830_cleanup(void)
640 {
641         iounmap(intel_i830_private.registers);
642 }
643
644 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
645 {
646         int i,j,num_entries;
647         void *temp;
648         int ret = -EINVAL;
649         int mask_type;
650
651         if (mem->page_count == 0)
652                 goto out;
653
654         temp = agp_bridge->current_size;
655         num_entries = A_SIZE_FIX(temp)->num_entries;
656
657         if (pg_start < intel_i830_private.gtt_entries) {
658                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n",
659                                 pg_start,intel_i830_private.gtt_entries);
660
661                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
662                 goto out_err;
663         }
664
665         if ((pg_start + mem->page_count) > num_entries)
666                 goto out_err;
667
668         /* The i830 can't check the GTT for entries since its read only,
669          * depend on the caller to make the correct offset decisions.
670          */
671
672         if (type != mem->type)
673                 goto out_err;
674
675         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
676
677         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
678             mask_type != INTEL_AGP_CACHED_MEMORY)
679                 goto out_err;
680
681         if (!mem->is_flushed)
682                 global_cache_flush();
683
684         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
685                 writel(agp_bridge->driver->mask_memory(agp_bridge,
686                                                        mem->memory[i], mask_type),
687                        intel_i830_private.registers+I810_PTE_BASE+(j*4));
688         }
689         readl(intel_i830_private.registers+I810_PTE_BASE+((j-1)*4));
690         agp_bridge->driver->tlb_flush(mem);
691
692 out:
693         ret = 0;
694 out_err:
695         mem->is_flushed = 1;
696         return ret;
697 }
698
699 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
700                                 int type)
701 {
702         int i;
703
704         if (mem->page_count == 0)
705                 return 0;
706
707         if (pg_start < intel_i830_private.gtt_entries) {
708                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
709                 return -EINVAL;
710         }
711
712         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
713                 writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4));
714         }
715         readl(intel_i830_private.registers+I810_PTE_BASE+((i-1)*4));
716
717         agp_bridge->driver->tlb_flush(mem);
718         return 0;
719 }
720
721 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
722 {
723         if (type == AGP_PHYS_MEMORY)
724                 return alloc_agpphysmem_i8xx(pg_count, type);
725         /* always return NULL for other allocation types for now */
726         return NULL;
727 }
728
729 static int intel_i915_configure(void)
730 {
731         struct aper_size_info_fixed *current_size;
732         u32 temp;
733         u16 gmch_ctrl;
734         int i;
735
736         current_size = A_SIZE_FIX(agp_bridge->current_size);
737
738         pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp);
739
740         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
741
742         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
743         gmch_ctrl |= I830_GMCH_ENABLED;
744         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
745
746         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL);
747         readl(intel_i830_private.registers+I810_PGETBL_CTL);    /* PCI Posting. */
748
749         if (agp_bridge->driver->needs_scratch_page) {
750                 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) {
751                         writel(agp_bridge->scratch_page, intel_i830_private.gtt+i);
752                         readl(intel_i830_private.gtt+i);        /* PCI Posting. */
753                 }
754         }
755
756         global_cache_flush();
757         return 0;
758 }
759
760 static void intel_i915_cleanup(void)
761 {
762         iounmap(intel_i830_private.gtt);
763         iounmap(intel_i830_private.registers);
764 }
765
766 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
767                                 int type)
768 {
769         int i,j,num_entries;
770         void *temp;
771         int ret = -EINVAL;
772         int mask_type;
773
774         if (mem->page_count == 0)
775                 goto out;
776
777         temp = agp_bridge->current_size;
778         num_entries = A_SIZE_FIX(temp)->num_entries;
779
780         if (pg_start < intel_i830_private.gtt_entries) {
781                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n",
782                                 pg_start,intel_i830_private.gtt_entries);
783
784                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
785                 goto out_err;
786         }
787
788         if ((pg_start + mem->page_count) > num_entries)
789                 goto out_err;
790
791         /* The i915 can't check the GTT for entries since its read only,
792          * depend on the caller to make the correct offset decisions.
793          */
794
795         if (type != mem->type)
796                 goto out_err;
797
798         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
799
800         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
801             mask_type != INTEL_AGP_CACHED_MEMORY)
802                 goto out_err;
803
804         if (!mem->is_flushed)
805                 global_cache_flush();
806
807         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
808                 writel(agp_bridge->driver->mask_memory(agp_bridge,
809                         mem->memory[i], mask_type), intel_i830_private.gtt+j);
810         }
811
812         readl(intel_i830_private.gtt+j-1);
813         agp_bridge->driver->tlb_flush(mem);
814
815  out:
816         ret = 0;
817  out_err:
818         mem->is_flushed = 1;
819         return ret;
820 }
821
822 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
823                                 int type)
824 {
825         int i;
826
827         if (mem->page_count == 0)
828                 return 0;
829
830         if (pg_start < intel_i830_private.gtt_entries) {
831                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
832                 return -EINVAL;
833         }
834
835         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
836                 writel(agp_bridge->scratch_page, intel_i830_private.gtt+i);
837         }
838         readl(intel_i830_private.gtt+i-1);
839
840         agp_bridge->driver->tlb_flush(mem);
841         return 0;
842 }
843
844 /* Return the aperture size by just checking the resource length.  The effect
845  * described in the spec of the MSAC registers is just changing of the
846  * resource size.
847  */
848 static int intel_i9xx_fetch_size(void)
849 {
850         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
851         int aper_size; /* size in megabytes */
852         int i;
853
854         aper_size = pci_resource_len(intel_i830_private.i830_dev, 2) / MB(1);
855
856         for (i = 0; i < num_sizes; i++) {
857                 if (aper_size == intel_i830_sizes[i].size) {
858                         agp_bridge->current_size = intel_i830_sizes + i;
859                         agp_bridge->previous_size = agp_bridge->current_size;
860                         return aper_size;
861                 }
862         }
863
864         return 0;
865 }
866
867 /* The intel i915 automatically initializes the agp aperture during POST.
868  * Use the memory already set aside for in the GTT.
869  */
870 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
871 {
872         int page_order;
873         struct aper_size_info_fixed *size;
874         int num_entries;
875         u32 temp, temp2;
876
877         size = agp_bridge->current_size;
878         page_order = size->page_order;
879         num_entries = size->num_entries;
880         agp_bridge->gatt_table_real = NULL;
881
882         pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp);
883         pci_read_config_dword(intel_i830_private.i830_dev, I915_PTEADDR,&temp2);
884
885         intel_i830_private.gtt = ioremap(temp2, 256 * 1024);
886         if (!intel_i830_private.gtt)
887                 return -ENOMEM;
888
889         temp &= 0xfff80000;
890
891         intel_i830_private.registers = ioremap(temp,128 * 4096);
892         if (!intel_i830_private.registers)
893                 return -ENOMEM;
894
895         temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
896         global_cache_flush();   /* FIXME: ? */
897
898         /* we have to call this as early as possible after the MMIO base address is known */
899         intel_i830_init_gtt_entries();
900
901         agp_bridge->gatt_table = NULL;
902
903         agp_bridge->gatt_bus_addr = temp;
904
905         return 0;
906 }
907
908 /*
909  * The i965 supports 36-bit physical addresses, but to keep
910  * the format of the GTT the same, the bits that don't fit
911  * in a 32-bit word are shifted down to bits 4..7.
912  *
913  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
914  * is always zero on 32-bit architectures, so no need to make
915  * this conditional.
916  */
917 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
918         unsigned long addr, int type)
919 {
920         /* Shift high bits down */
921         addr |= (addr >> 28) & 0xf0;
922
923         /* Type checking must be done elsewhere */
924         return addr | bridge->driver->masks[type].mask;
925 }
926
927 /* The intel i965 automatically initializes the agp aperture during POST.
928  * Use the memory already set aside for in the GTT.
929  */
930 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
931 {
932        int page_order;
933        struct aper_size_info_fixed *size;
934        int num_entries;
935        u32 temp;
936
937        size = agp_bridge->current_size;
938        page_order = size->page_order;
939        num_entries = size->num_entries;
940        agp_bridge->gatt_table_real = NULL;
941
942        pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp);
943
944        temp &= 0xfff00000;
945        intel_i830_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
946
947        if (!intel_i830_private.gtt)
948                return -ENOMEM;
949
950
951        intel_i830_private.registers = ioremap(temp,128 * 4096);
952        if (!intel_i830_private.registers)
953                return -ENOMEM;
954
955        temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
956        global_cache_flush();   /* FIXME: ? */
957
958        /* we have to call this as early as possible after the MMIO base address is known */
959        intel_i830_init_gtt_entries();
960
961        agp_bridge->gatt_table = NULL;
962
963        agp_bridge->gatt_bus_addr = temp;
964
965        return 0;
966 }
967
968
969 static int intel_fetch_size(void)
970 {
971         int i;
972         u16 temp;
973         struct aper_size_info_16 *values;
974
975         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
976         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
977
978         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
979                 if (temp == values[i].size_value) {
980                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
981                         agp_bridge->aperture_size_idx = i;
982                         return values[i].size;
983                 }
984         }
985
986         return 0;
987 }
988
989 static int __intel_8xx_fetch_size(u8 temp)
990 {
991         int i;
992         struct aper_size_info_8 *values;
993
994         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
995
996         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
997                 if (temp == values[i].size_value) {
998                         agp_bridge->previous_size =
999                                 agp_bridge->current_size = (void *) (values + i);
1000                         agp_bridge->aperture_size_idx = i;
1001                         return values[i].size;
1002                 }
1003         }
1004         return 0;
1005 }
1006
1007 static int intel_8xx_fetch_size(void)
1008 {
1009         u8 temp;
1010
1011         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1012         return __intel_8xx_fetch_size(temp);
1013 }
1014
1015 static int intel_815_fetch_size(void)
1016 {
1017         u8 temp;
1018
1019         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1020          * one non-reserved bit, so mask the others out ... */
1021         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1022         temp &= (1 << 3);
1023
1024         return __intel_8xx_fetch_size(temp);
1025 }
1026
1027 static void intel_tlbflush(struct agp_memory *mem)
1028 {
1029         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1030         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1031 }
1032
1033
1034 static void intel_8xx_tlbflush(struct agp_memory *mem)
1035 {
1036         u32 temp;
1037         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1038         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1039         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1040         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1041 }
1042
1043
1044 static void intel_cleanup(void)
1045 {
1046         u16 temp;
1047         struct aper_size_info_16 *previous_size;
1048
1049         previous_size = A_SIZE_16(agp_bridge->previous_size);
1050         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1051         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1052         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1053 }
1054
1055
1056 static void intel_8xx_cleanup(void)
1057 {
1058         u16 temp;
1059         struct aper_size_info_8 *previous_size;
1060
1061         previous_size = A_SIZE_8(agp_bridge->previous_size);
1062         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1063         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1064         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1065 }
1066
1067
1068 static int intel_configure(void)
1069 {
1070         u32 temp;
1071         u16 temp2;
1072         struct aper_size_info_16 *current_size;
1073
1074         current_size = A_SIZE_16(agp_bridge->current_size);
1075
1076         /* aperture size */
1077         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1078
1079         /* address to map to */
1080         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1081         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1082
1083         /* attbase - aperture base */
1084         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1085
1086         /* agpctrl */
1087         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1088
1089         /* paccfg/nbxcfg */
1090         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1091         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1092                         (temp2 & ~(1 << 10)) | (1 << 9));
1093         /* clear any possible error conditions */
1094         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1095         return 0;
1096 }
1097
1098 static int intel_815_configure(void)
1099 {
1100         u32 temp, addr;
1101         u8 temp2;
1102         struct aper_size_info_8 *current_size;
1103
1104         /* attbase - aperture base */
1105         /* the Intel 815 chipset spec. says that bits 29-31 in the
1106         * ATTBASE register are reserved -> try not to write them */
1107         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1108                 printk (KERN_EMERG PFX "gatt bus addr too high");
1109                 return -EINVAL;
1110         }
1111
1112         current_size = A_SIZE_8(agp_bridge->current_size);
1113
1114         /* aperture size */
1115         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1116                         current_size->size_value);
1117
1118         /* address to map to */
1119         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1120         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1121
1122         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1123         addr &= INTEL_815_ATTBASE_MASK;
1124         addr |= agp_bridge->gatt_bus_addr;
1125         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1126
1127         /* agpctrl */
1128         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1129
1130         /* apcont */
1131         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1132         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1133
1134         /* clear any possible error conditions */
1135         /* Oddness : this chipset seems to have no ERRSTS register ! */
1136         return 0;
1137 }
1138
1139 static void intel_820_tlbflush(struct agp_memory *mem)
1140 {
1141         return;
1142 }
1143
1144 static void intel_820_cleanup(void)
1145 {
1146         u8 temp;
1147         struct aper_size_info_8 *previous_size;
1148
1149         previous_size = A_SIZE_8(agp_bridge->previous_size);
1150         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1151         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1152                         temp & ~(1 << 1));
1153         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1154                         previous_size->size_value);
1155 }
1156
1157
1158 static int intel_820_configure(void)
1159 {
1160         u32 temp;
1161         u8 temp2;
1162         struct aper_size_info_8 *current_size;
1163
1164         current_size = A_SIZE_8(agp_bridge->current_size);
1165
1166         /* aperture size */
1167         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1168
1169         /* address to map to */
1170         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1171         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1172
1173         /* attbase - aperture base */
1174         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1175
1176         /* agpctrl */
1177         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1178
1179         /* global enable aperture access */
1180         /* This flag is not accessed through MCHCFG register as in */
1181         /* i850 chipset. */
1182         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1183         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1184         /* clear any possible AGP-related error conditions */
1185         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1186         return 0;
1187 }
1188
1189 static int intel_840_configure(void)
1190 {
1191         u32 temp;
1192         u16 temp2;
1193         struct aper_size_info_8 *current_size;
1194
1195         current_size = A_SIZE_8(agp_bridge->current_size);
1196
1197         /* aperture size */
1198         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1199
1200         /* address to map to */
1201         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1202         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1203
1204         /* attbase - aperture base */
1205         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1206
1207         /* agpctrl */
1208         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1209
1210         /* mcgcfg */
1211         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1212         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1213         /* clear any possible error conditions */
1214         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1215         return 0;
1216 }
1217
1218 static int intel_845_configure(void)
1219 {
1220         u32 temp;
1221         u8 temp2;
1222         struct aper_size_info_8 *current_size;
1223
1224         current_size = A_SIZE_8(agp_bridge->current_size);
1225
1226         /* aperture size */
1227         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1228
1229         if (agp_bridge->apbase_config != 0) {
1230                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1231                                        agp_bridge->apbase_config);
1232         } else {
1233                 /* address to map to */
1234                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1235                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1236                 agp_bridge->apbase_config = temp;
1237         }
1238
1239         /* attbase - aperture base */
1240         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1241
1242         /* agpctrl */
1243         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1244
1245         /* agpm */
1246         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1247         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1248         /* clear any possible error conditions */
1249         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1250         return 0;
1251 }
1252
1253 static int intel_850_configure(void)
1254 {
1255         u32 temp;
1256         u16 temp2;
1257         struct aper_size_info_8 *current_size;
1258
1259         current_size = A_SIZE_8(agp_bridge->current_size);
1260
1261         /* aperture size */
1262         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1263
1264         /* address to map to */
1265         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1266         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1267
1268         /* attbase - aperture base */
1269         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1270
1271         /* agpctrl */
1272         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1273
1274         /* mcgcfg */
1275         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1276         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1277         /* clear any possible AGP-related error conditions */
1278         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1279         return 0;
1280 }
1281
1282 static int intel_860_configure(void)
1283 {
1284         u32 temp;
1285         u16 temp2;
1286         struct aper_size_info_8 *current_size;
1287
1288         current_size = A_SIZE_8(agp_bridge->current_size);
1289
1290         /* aperture size */
1291         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1292
1293         /* address to map to */
1294         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1295         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1296
1297         /* attbase - aperture base */
1298         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1299
1300         /* agpctrl */
1301         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1302
1303         /* mcgcfg */
1304         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1305         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1306         /* clear any possible AGP-related error conditions */
1307         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1308         return 0;
1309 }
1310
1311 static int intel_830mp_configure(void)
1312 {
1313         u32 temp;
1314         u16 temp2;
1315         struct aper_size_info_8 *current_size;
1316
1317         current_size = A_SIZE_8(agp_bridge->current_size);
1318
1319         /* aperture size */
1320         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1321
1322         /* address to map to */
1323         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1324         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1325
1326         /* attbase - aperture base */
1327         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1328
1329         /* agpctrl */
1330         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1331
1332         /* gmch */
1333         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1334         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1335         /* clear any possible AGP-related error conditions */
1336         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1337         return 0;
1338 }
1339
1340 static int intel_7505_configure(void)
1341 {
1342         u32 temp;
1343         u16 temp2;
1344         struct aper_size_info_8 *current_size;
1345
1346         current_size = A_SIZE_8(agp_bridge->current_size);
1347
1348         /* aperture size */
1349         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1350
1351         /* address to map to */
1352         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1353         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1354
1355         /* attbase - aperture base */
1356         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1357
1358         /* agpctrl */
1359         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1360
1361         /* mchcfg */
1362         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1363         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1364
1365         return 0;
1366 }
1367
1368 /* Setup function */
1369 static struct gatt_mask intel_generic_masks[] =
1370 {
1371         {.mask = 0x00000017, .type = 0}
1372 };
1373
1374 static struct aper_size_info_8 intel_815_sizes[2] =
1375 {
1376         {64, 16384, 4, 0},
1377         {32, 8192, 3, 8},
1378 };
1379
1380 static struct aper_size_info_8 intel_8xx_sizes[7] =
1381 {
1382         {256, 65536, 6, 0},
1383         {128, 32768, 5, 32},
1384         {64, 16384, 4, 48},
1385         {32, 8192, 3, 56},
1386         {16, 4096, 2, 60},
1387         {8, 2048, 1, 62},
1388         {4, 1024, 0, 63}
1389 };
1390
1391 static struct aper_size_info_16 intel_generic_sizes[7] =
1392 {
1393         {256, 65536, 6, 0},
1394         {128, 32768, 5, 32},
1395         {64, 16384, 4, 48},
1396         {32, 8192, 3, 56},
1397         {16, 4096, 2, 60},
1398         {8, 2048, 1, 62},
1399         {4, 1024, 0, 63}
1400 };
1401
1402 static struct aper_size_info_8 intel_830mp_sizes[4] =
1403 {
1404         {256, 65536, 6, 0},
1405         {128, 32768, 5, 32},
1406         {64, 16384, 4, 48},
1407         {32, 8192, 3, 56}
1408 };
1409
1410 static struct agp_bridge_driver intel_generic_driver = {
1411         .owner                  = THIS_MODULE,
1412         .aperture_sizes         = intel_generic_sizes,
1413         .size_type              = U16_APER_SIZE,
1414         .num_aperture_sizes     = 7,
1415         .configure              = intel_configure,
1416         .fetch_size             = intel_fetch_size,
1417         .cleanup                = intel_cleanup,
1418         .tlb_flush              = intel_tlbflush,
1419         .mask_memory            = agp_generic_mask_memory,
1420         .masks                  = intel_generic_masks,
1421         .agp_enable             = agp_generic_enable,
1422         .cache_flush            = global_cache_flush,
1423         .create_gatt_table      = agp_generic_create_gatt_table,
1424         .free_gatt_table        = agp_generic_free_gatt_table,
1425         .insert_memory          = agp_generic_insert_memory,
1426         .remove_memory          = agp_generic_remove_memory,
1427         .alloc_by_type          = agp_generic_alloc_by_type,
1428         .free_by_type           = agp_generic_free_by_type,
1429         .agp_alloc_page         = agp_generic_alloc_page,
1430         .agp_destroy_page       = agp_generic_destroy_page,
1431         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1432 };
1433
1434 static struct agp_bridge_driver intel_810_driver = {
1435         .owner                  = THIS_MODULE,
1436         .aperture_sizes         = intel_i810_sizes,
1437         .size_type              = FIXED_APER_SIZE,
1438         .num_aperture_sizes     = 2,
1439         .needs_scratch_page     = TRUE,
1440         .configure              = intel_i810_configure,
1441         .fetch_size             = intel_i810_fetch_size,
1442         .cleanup                = intel_i810_cleanup,
1443         .tlb_flush              = intel_i810_tlbflush,
1444         .mask_memory            = intel_i810_mask_memory,
1445         .masks                  = intel_i810_masks,
1446         .agp_enable             = intel_i810_agp_enable,
1447         .cache_flush            = global_cache_flush,
1448         .create_gatt_table      = agp_generic_create_gatt_table,
1449         .free_gatt_table        = agp_generic_free_gatt_table,
1450         .insert_memory          = intel_i810_insert_entries,
1451         .remove_memory          = intel_i810_remove_entries,
1452         .alloc_by_type          = intel_i810_alloc_by_type,
1453         .free_by_type           = intel_i810_free_by_type,
1454         .agp_alloc_page         = agp_generic_alloc_page,
1455         .agp_destroy_page       = agp_generic_destroy_page,
1456         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1457 };
1458
1459 static struct agp_bridge_driver intel_815_driver = {
1460         .owner                  = THIS_MODULE,
1461         .aperture_sizes         = intel_815_sizes,
1462         .size_type              = U8_APER_SIZE,
1463         .num_aperture_sizes     = 2,
1464         .configure              = intel_815_configure,
1465         .fetch_size             = intel_815_fetch_size,
1466         .cleanup                = intel_8xx_cleanup,
1467         .tlb_flush              = intel_8xx_tlbflush,
1468         .mask_memory            = agp_generic_mask_memory,
1469         .masks                  = intel_generic_masks,
1470         .agp_enable             = agp_generic_enable,
1471         .cache_flush            = global_cache_flush,
1472         .create_gatt_table      = agp_generic_create_gatt_table,
1473         .free_gatt_table        = agp_generic_free_gatt_table,
1474         .insert_memory          = agp_generic_insert_memory,
1475         .remove_memory          = agp_generic_remove_memory,
1476         .alloc_by_type          = agp_generic_alloc_by_type,
1477         .free_by_type           = agp_generic_free_by_type,
1478         .agp_alloc_page         = agp_generic_alloc_page,
1479         .agp_destroy_page       = agp_generic_destroy_page,
1480         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1481 };
1482
1483 static struct agp_bridge_driver intel_830_driver = {
1484         .owner                  = THIS_MODULE,
1485         .aperture_sizes         = intel_i830_sizes,
1486         .size_type              = FIXED_APER_SIZE,
1487         .num_aperture_sizes     = 4,
1488         .needs_scratch_page     = TRUE,
1489         .configure              = intel_i830_configure,
1490         .fetch_size             = intel_i830_fetch_size,
1491         .cleanup                = intel_i830_cleanup,
1492         .tlb_flush              = intel_i810_tlbflush,
1493         .mask_memory            = intel_i810_mask_memory,
1494         .masks                  = intel_i810_masks,
1495         .agp_enable             = intel_i810_agp_enable,
1496         .cache_flush            = global_cache_flush,
1497         .create_gatt_table      = intel_i830_create_gatt_table,
1498         .free_gatt_table        = intel_i830_free_gatt_table,
1499         .insert_memory          = intel_i830_insert_entries,
1500         .remove_memory          = intel_i830_remove_entries,
1501         .alloc_by_type          = intel_i830_alloc_by_type,
1502         .free_by_type           = intel_i810_free_by_type,
1503         .agp_alloc_page         = agp_generic_alloc_page,
1504         .agp_destroy_page       = agp_generic_destroy_page,
1505         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1506 };
1507
1508 static struct agp_bridge_driver intel_820_driver = {
1509         .owner                  = THIS_MODULE,
1510         .aperture_sizes         = intel_8xx_sizes,
1511         .size_type              = U8_APER_SIZE,
1512         .num_aperture_sizes     = 7,
1513         .configure              = intel_820_configure,
1514         .fetch_size             = intel_8xx_fetch_size,
1515         .cleanup                = intel_820_cleanup,
1516         .tlb_flush              = intel_820_tlbflush,
1517         .mask_memory            = agp_generic_mask_memory,
1518         .masks                  = intel_generic_masks,
1519         .agp_enable             = agp_generic_enable,
1520         .cache_flush            = global_cache_flush,
1521         .create_gatt_table      = agp_generic_create_gatt_table,
1522         .free_gatt_table        = agp_generic_free_gatt_table,
1523         .insert_memory          = agp_generic_insert_memory,
1524         .remove_memory          = agp_generic_remove_memory,
1525         .alloc_by_type          = agp_generic_alloc_by_type,
1526         .free_by_type           = agp_generic_free_by_type,
1527         .agp_alloc_page         = agp_generic_alloc_page,
1528         .agp_destroy_page       = agp_generic_destroy_page,
1529         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1530 };
1531
1532 static struct agp_bridge_driver intel_830mp_driver = {
1533         .owner                  = THIS_MODULE,
1534         .aperture_sizes         = intel_830mp_sizes,
1535         .size_type              = U8_APER_SIZE,
1536         .num_aperture_sizes     = 4,
1537         .configure              = intel_830mp_configure,
1538         .fetch_size             = intel_8xx_fetch_size,
1539         .cleanup                = intel_8xx_cleanup,
1540         .tlb_flush              = intel_8xx_tlbflush,
1541         .mask_memory            = agp_generic_mask_memory,
1542         .masks                  = intel_generic_masks,
1543         .agp_enable             = agp_generic_enable,
1544         .cache_flush            = global_cache_flush,
1545         .create_gatt_table      = agp_generic_create_gatt_table,
1546         .free_gatt_table        = agp_generic_free_gatt_table,
1547         .insert_memory          = agp_generic_insert_memory,
1548         .remove_memory          = agp_generic_remove_memory,
1549         .alloc_by_type          = agp_generic_alloc_by_type,
1550         .free_by_type           = agp_generic_free_by_type,
1551         .agp_alloc_page         = agp_generic_alloc_page,
1552         .agp_destroy_page       = agp_generic_destroy_page,
1553         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1554 };
1555
1556 static struct agp_bridge_driver intel_840_driver = {
1557         .owner                  = THIS_MODULE,
1558         .aperture_sizes         = intel_8xx_sizes,
1559         .size_type              = U8_APER_SIZE,
1560         .num_aperture_sizes     = 7,
1561         .configure              = intel_840_configure,
1562         .fetch_size             = intel_8xx_fetch_size,
1563         .cleanup                = intel_8xx_cleanup,
1564         .tlb_flush              = intel_8xx_tlbflush,
1565         .mask_memory            = agp_generic_mask_memory,
1566         .masks                  = intel_generic_masks,
1567         .agp_enable             = agp_generic_enable,
1568         .cache_flush            = global_cache_flush,
1569         .create_gatt_table      = agp_generic_create_gatt_table,
1570         .free_gatt_table        = agp_generic_free_gatt_table,
1571         .insert_memory          = agp_generic_insert_memory,
1572         .remove_memory          = agp_generic_remove_memory,
1573         .alloc_by_type          = agp_generic_alloc_by_type,
1574         .free_by_type           = agp_generic_free_by_type,
1575         .agp_alloc_page         = agp_generic_alloc_page,
1576         .agp_destroy_page       = agp_generic_destroy_page,
1577         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1578 };
1579
1580 static struct agp_bridge_driver intel_845_driver = {
1581         .owner                  = THIS_MODULE,
1582         .aperture_sizes         = intel_8xx_sizes,
1583         .size_type              = U8_APER_SIZE,
1584         .num_aperture_sizes     = 7,
1585         .configure              = intel_845_configure,
1586         .fetch_size             = intel_8xx_fetch_size,
1587         .cleanup                = intel_8xx_cleanup,
1588         .tlb_flush              = intel_8xx_tlbflush,
1589         .mask_memory            = agp_generic_mask_memory,
1590         .masks                  = intel_generic_masks,
1591         .agp_enable             = agp_generic_enable,
1592         .cache_flush            = global_cache_flush,
1593         .create_gatt_table      = agp_generic_create_gatt_table,
1594         .free_gatt_table        = agp_generic_free_gatt_table,
1595         .insert_memory          = agp_generic_insert_memory,
1596         .remove_memory          = agp_generic_remove_memory,
1597         .alloc_by_type          = agp_generic_alloc_by_type,
1598         .free_by_type           = agp_generic_free_by_type,
1599         .agp_alloc_page         = agp_generic_alloc_page,
1600         .agp_destroy_page       = agp_generic_destroy_page,
1601         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1602 };
1603
1604 static struct agp_bridge_driver intel_850_driver = {
1605         .owner                  = THIS_MODULE,
1606         .aperture_sizes         = intel_8xx_sizes,
1607         .size_type              = U8_APER_SIZE,
1608         .num_aperture_sizes     = 7,
1609         .configure              = intel_850_configure,
1610         .fetch_size             = intel_8xx_fetch_size,
1611         .cleanup                = intel_8xx_cleanup,
1612         .tlb_flush              = intel_8xx_tlbflush,
1613         .mask_memory            = agp_generic_mask_memory,
1614         .masks                  = intel_generic_masks,
1615         .agp_enable             = agp_generic_enable,
1616         .cache_flush            = global_cache_flush,
1617         .create_gatt_table      = agp_generic_create_gatt_table,
1618         .free_gatt_table        = agp_generic_free_gatt_table,
1619         .insert_memory          = agp_generic_insert_memory,
1620         .remove_memory          = agp_generic_remove_memory,
1621         .alloc_by_type          = agp_generic_alloc_by_type,
1622         .free_by_type           = agp_generic_free_by_type,
1623         .agp_alloc_page         = agp_generic_alloc_page,
1624         .agp_destroy_page       = agp_generic_destroy_page,
1625         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1626 };
1627
1628 static struct agp_bridge_driver intel_860_driver = {
1629         .owner                  = THIS_MODULE,
1630         .aperture_sizes         = intel_8xx_sizes,
1631         .size_type              = U8_APER_SIZE,
1632         .num_aperture_sizes     = 7,
1633         .configure              = intel_860_configure,
1634         .fetch_size             = intel_8xx_fetch_size,
1635         .cleanup                = intel_8xx_cleanup,
1636         .tlb_flush              = intel_8xx_tlbflush,
1637         .mask_memory            = agp_generic_mask_memory,
1638         .masks                  = intel_generic_masks,
1639         .agp_enable             = agp_generic_enable,
1640         .cache_flush            = global_cache_flush,
1641         .create_gatt_table      = agp_generic_create_gatt_table,
1642         .free_gatt_table        = agp_generic_free_gatt_table,
1643         .insert_memory          = agp_generic_insert_memory,
1644         .remove_memory          = agp_generic_remove_memory,
1645         .alloc_by_type          = agp_generic_alloc_by_type,
1646         .free_by_type           = agp_generic_free_by_type,
1647         .agp_alloc_page         = agp_generic_alloc_page,
1648         .agp_destroy_page       = agp_generic_destroy_page,
1649         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1650 };
1651
1652 static struct agp_bridge_driver intel_915_driver = {
1653         .owner                  = THIS_MODULE,
1654         .aperture_sizes         = intel_i830_sizes,
1655         .size_type              = FIXED_APER_SIZE,
1656         .num_aperture_sizes     = 4,
1657         .needs_scratch_page     = TRUE,
1658         .configure              = intel_i915_configure,
1659         .fetch_size             = intel_i9xx_fetch_size,
1660         .cleanup                = intel_i915_cleanup,
1661         .tlb_flush              = intel_i810_tlbflush,
1662         .mask_memory            = intel_i810_mask_memory,
1663         .masks                  = intel_i810_masks,
1664         .agp_enable             = intel_i810_agp_enable,
1665         .cache_flush            = global_cache_flush,
1666         .create_gatt_table      = intel_i915_create_gatt_table,
1667         .free_gatt_table        = intel_i830_free_gatt_table,
1668         .insert_memory          = intel_i915_insert_entries,
1669         .remove_memory          = intel_i915_remove_entries,
1670         .alloc_by_type          = intel_i830_alloc_by_type,
1671         .free_by_type           = intel_i810_free_by_type,
1672         .agp_alloc_page         = agp_generic_alloc_page,
1673         .agp_destroy_page       = agp_generic_destroy_page,
1674         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1675 };
1676
1677 static struct agp_bridge_driver intel_i965_driver = {
1678        .owner                  = THIS_MODULE,
1679        .aperture_sizes         = intel_i830_sizes,
1680        .size_type              = FIXED_APER_SIZE,
1681        .num_aperture_sizes     = 4,
1682        .needs_scratch_page     = TRUE,
1683        .configure              = intel_i915_configure,
1684        .fetch_size             = intel_i9xx_fetch_size,
1685        .cleanup                = intel_i915_cleanup,
1686        .tlb_flush              = intel_i810_tlbflush,
1687        .mask_memory            = intel_i965_mask_memory,
1688        .masks                  = intel_i810_masks,
1689        .agp_enable             = intel_i810_agp_enable,
1690        .cache_flush            = global_cache_flush,
1691        .create_gatt_table      = intel_i965_create_gatt_table,
1692        .free_gatt_table        = intel_i830_free_gatt_table,
1693        .insert_memory          = intel_i915_insert_entries,
1694        .remove_memory          = intel_i915_remove_entries,
1695        .alloc_by_type          = intel_i830_alloc_by_type,
1696        .free_by_type           = intel_i810_free_by_type,
1697        .agp_alloc_page         = agp_generic_alloc_page,
1698        .agp_destroy_page       = agp_generic_destroy_page,
1699        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1700 };
1701
1702 static struct agp_bridge_driver intel_7505_driver = {
1703         .owner                  = THIS_MODULE,
1704         .aperture_sizes         = intel_8xx_sizes,
1705         .size_type              = U8_APER_SIZE,
1706         .num_aperture_sizes     = 7,
1707         .configure              = intel_7505_configure,
1708         .fetch_size             = intel_8xx_fetch_size,
1709         .cleanup                = intel_8xx_cleanup,
1710         .tlb_flush              = intel_8xx_tlbflush,
1711         .mask_memory            = agp_generic_mask_memory,
1712         .masks                  = intel_generic_masks,
1713         .agp_enable             = agp_generic_enable,
1714         .cache_flush            = global_cache_flush,
1715         .create_gatt_table      = agp_generic_create_gatt_table,
1716         .free_gatt_table        = agp_generic_free_gatt_table,
1717         .insert_memory          = agp_generic_insert_memory,
1718         .remove_memory          = agp_generic_remove_memory,
1719         .alloc_by_type          = agp_generic_alloc_by_type,
1720         .free_by_type           = agp_generic_free_by_type,
1721         .agp_alloc_page         = agp_generic_alloc_page,
1722         .agp_destroy_page       = agp_generic_destroy_page,
1723         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1724 };
1725
1726 static int find_i810(u16 device)
1727 {
1728         struct pci_dev *i810_dev;
1729
1730         i810_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1731         if (!i810_dev)
1732                 return 0;
1733         intel_i810_private.i810_dev = i810_dev;
1734         return 1;
1735 }
1736
1737 static int find_i830(u16 device)
1738 {
1739         struct pci_dev *i830_dev;
1740
1741         i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1742         if (i830_dev && PCI_FUNC(i830_dev->devfn) != 0) {
1743                 i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
1744                                 device, i830_dev);
1745         }
1746
1747         if (!i830_dev)
1748                 return 0;
1749
1750         intel_i830_private.i830_dev = i830_dev;
1751         return 1;
1752 }
1753
1754 static int __devinit agp_intel_probe(struct pci_dev *pdev,
1755                                      const struct pci_device_id *ent)
1756 {
1757         struct agp_bridge_data *bridge;
1758         char *name = "(unknown)";
1759         u8 cap_ptr = 0;
1760         struct resource *r;
1761
1762         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
1763
1764         bridge = agp_alloc_bridge();
1765         if (!bridge)
1766                 return -ENOMEM;
1767
1768         switch (pdev->device) {
1769         case PCI_DEVICE_ID_INTEL_82443LX_0:
1770                 bridge->driver = &intel_generic_driver;
1771                 name = "440LX";
1772                 break;
1773         case PCI_DEVICE_ID_INTEL_82443BX_0:
1774                 bridge->driver = &intel_generic_driver;
1775                 name = "440BX";
1776                 break;
1777         case PCI_DEVICE_ID_INTEL_82443GX_0:
1778                 bridge->driver = &intel_generic_driver;
1779                 name = "440GX";
1780                 break;
1781         case PCI_DEVICE_ID_INTEL_82810_MC1:
1782                 name = "i810";
1783                 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG1))
1784                         goto fail;
1785                 bridge->driver = &intel_810_driver;
1786                 break;
1787         case PCI_DEVICE_ID_INTEL_82810_MC3:
1788                 name = "i810 DC100";
1789                 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG3))
1790                         goto fail;
1791                 bridge->driver = &intel_810_driver;
1792                 break;
1793         case PCI_DEVICE_ID_INTEL_82810E_MC:
1794                 name = "i810 E";
1795                 if (!find_i810(PCI_DEVICE_ID_INTEL_82810E_IG))
1796                         goto fail;
1797                 bridge->driver = &intel_810_driver;
1798                 break;
1799          case PCI_DEVICE_ID_INTEL_82815_MC:
1800                 /*
1801                  * The i815 can operate either as an i810 style
1802                  * integrated device, or as an AGP4X motherboard.
1803                  */
1804                 if (find_i810(PCI_DEVICE_ID_INTEL_82815_CGC))
1805                         bridge->driver = &intel_810_driver;
1806                 else
1807                         bridge->driver = &intel_815_driver;
1808                 name = "i815";
1809                 break;
1810         case PCI_DEVICE_ID_INTEL_82820_HB:
1811         case PCI_DEVICE_ID_INTEL_82820_UP_HB:
1812                 bridge->driver = &intel_820_driver;
1813                 name = "i820";
1814                 break;
1815         case PCI_DEVICE_ID_INTEL_82830_HB:
1816                 if (find_i830(PCI_DEVICE_ID_INTEL_82830_CGC))
1817                         bridge->driver = &intel_830_driver;
1818                 else
1819                         bridge->driver = &intel_830mp_driver;
1820                 name = "830M";
1821                 break;
1822         case PCI_DEVICE_ID_INTEL_82840_HB:
1823                 bridge->driver = &intel_840_driver;
1824                 name = "i840";
1825                 break;
1826         case PCI_DEVICE_ID_INTEL_82845_HB:
1827                 bridge->driver = &intel_845_driver;
1828                 name = "i845";
1829                 break;
1830         case PCI_DEVICE_ID_INTEL_82845G_HB:
1831                 if (find_i830(PCI_DEVICE_ID_INTEL_82845G_IG))
1832                         bridge->driver = &intel_830_driver;
1833                 else
1834                         bridge->driver = &intel_845_driver;
1835                 name = "845G";
1836                 break;
1837         case PCI_DEVICE_ID_INTEL_82850_HB:
1838                 bridge->driver = &intel_850_driver;
1839                 name = "i850";
1840                 break;
1841         case PCI_DEVICE_ID_INTEL_82855PM_HB:
1842                 bridge->driver = &intel_845_driver;
1843                 name = "855PM";
1844                 break;
1845         case PCI_DEVICE_ID_INTEL_82855GM_HB:
1846                 if (find_i830(PCI_DEVICE_ID_INTEL_82855GM_IG)) {
1847                         bridge->driver = &intel_830_driver;
1848                         name = "855";
1849                 } else {
1850                         bridge->driver = &intel_845_driver;
1851                         name = "855GM";
1852                 }
1853                 break;
1854         case PCI_DEVICE_ID_INTEL_82860_HB:
1855                 bridge->driver = &intel_860_driver;
1856                 name = "i860";
1857                 break;
1858         case PCI_DEVICE_ID_INTEL_82865_HB:
1859                 if (find_i830(PCI_DEVICE_ID_INTEL_82865_IG))
1860                         bridge->driver = &intel_830_driver;
1861                 else
1862                         bridge->driver = &intel_845_driver;
1863                 name = "865";
1864                 break;
1865         case PCI_DEVICE_ID_INTEL_82875_HB:
1866                 bridge->driver = &intel_845_driver;
1867                 name = "i875";
1868                 break;
1869         case PCI_DEVICE_ID_INTEL_82915G_HB:
1870                 if (find_i830(PCI_DEVICE_ID_INTEL_82915G_IG))
1871                         bridge->driver = &intel_915_driver;
1872                 else
1873                         bridge->driver = &intel_845_driver;
1874                 name = "915G";
1875                 break;
1876         case PCI_DEVICE_ID_INTEL_82915GM_HB:
1877                 if (find_i830(PCI_DEVICE_ID_INTEL_82915GM_IG))
1878                         bridge->driver = &intel_915_driver;
1879                 else
1880                         bridge->driver = &intel_845_driver;
1881                 name = "915GM";
1882                 break;
1883         case PCI_DEVICE_ID_INTEL_82945G_HB:
1884                 if (find_i830(PCI_DEVICE_ID_INTEL_82945G_IG))
1885                         bridge->driver = &intel_915_driver;
1886                 else
1887                         bridge->driver = &intel_845_driver;
1888                 name = "945G";
1889                 break;
1890         case PCI_DEVICE_ID_INTEL_82945GM_HB:
1891                 if (find_i830(PCI_DEVICE_ID_INTEL_82945GM_IG))
1892                         bridge->driver = &intel_915_driver;
1893                 else
1894                         bridge->driver = &intel_845_driver;
1895                 name = "945GM";
1896                 break;
1897         case PCI_DEVICE_ID_INTEL_82946GZ_HB:
1898                 if (find_i830(PCI_DEVICE_ID_INTEL_82946GZ_IG))
1899                         bridge->driver = &intel_i965_driver;
1900                 else
1901                         bridge->driver = &intel_845_driver;
1902                 name = "946GZ";
1903                 break;
1904         case PCI_DEVICE_ID_INTEL_82965G_1_HB:
1905                 if (find_i830(PCI_DEVICE_ID_INTEL_82965G_1_IG))
1906                         bridge->driver = &intel_i965_driver;
1907                 else
1908                         bridge->driver = &intel_845_driver;
1909                 name = "965G";
1910                 break;
1911         case PCI_DEVICE_ID_INTEL_82965Q_HB:
1912                 if (find_i830(PCI_DEVICE_ID_INTEL_82965Q_IG))
1913                         bridge->driver = &intel_i965_driver;
1914                 else
1915                         bridge->driver = &intel_845_driver;
1916                 name = "965Q";
1917                 break;
1918         case PCI_DEVICE_ID_INTEL_82965G_HB:
1919                 if (find_i830(PCI_DEVICE_ID_INTEL_82965G_IG))
1920                         bridge->driver = &intel_i965_driver;
1921                 else
1922                         bridge->driver = &intel_845_driver;
1923                 name = "965G";
1924                 break;
1925
1926         case PCI_DEVICE_ID_INTEL_7505_0:
1927                 bridge->driver = &intel_7505_driver;
1928                 name = "E7505";
1929                 break;
1930         case PCI_DEVICE_ID_INTEL_7205_0:
1931                 bridge->driver = &intel_7505_driver;
1932                 name = "E7205";
1933                 break;
1934         default:
1935                 if (cap_ptr)
1936                         printk(KERN_WARNING PFX "Unsupported Intel chipset (device id: %04x)\n",
1937                             pdev->device);
1938                 agp_put_bridge(bridge);
1939                 return -ENODEV;
1940         };
1941
1942         bridge->dev = pdev;
1943         bridge->capndx = cap_ptr;
1944
1945         if (bridge->driver == &intel_810_driver)
1946                 bridge->dev_private_data = &intel_i810_private;
1947         else if (bridge->driver == &intel_830_driver)
1948                 bridge->dev_private_data = &intel_i830_private;
1949
1950         printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", name);
1951
1952         /*
1953         * The following fixes the case where the BIOS has "forgotten" to
1954         * provide an address range for the GART.
1955         * 20030610 - hamish@zot.org
1956         */
1957         r = &pdev->resource[0];
1958         if (!r->start && r->end) {
1959                 if (pci_assign_resource(pdev, 0)) {
1960                         printk(KERN_ERR PFX "could not assign resource 0\n");
1961                         agp_put_bridge(bridge);
1962                         return -ENODEV;
1963                 }
1964         }
1965
1966         /*
1967         * If the device has not been properly setup, the following will catch
1968         * the problem and should stop the system from crashing.
1969         * 20030610 - hamish@zot.org
1970         */
1971         if (pci_enable_device(pdev)) {
1972                 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
1973                 agp_put_bridge(bridge);
1974                 return -ENODEV;
1975         }
1976
1977         /* Fill in the mode register */
1978         if (cap_ptr) {
1979                 pci_read_config_dword(pdev,
1980                                 bridge->capndx+PCI_AGP_STATUS,
1981                                 &bridge->mode);
1982         }
1983
1984         pci_set_drvdata(pdev, bridge);
1985         return agp_add_bridge(bridge);
1986
1987 fail:
1988         printk(KERN_ERR PFX "Detected an Intel %s chipset, "
1989                 "but could not find the secondary device.\n", name);
1990         agp_put_bridge(bridge);
1991         return -ENODEV;
1992 }
1993
1994 static void __devexit agp_intel_remove(struct pci_dev *pdev)
1995 {
1996         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1997
1998         agp_remove_bridge(bridge);
1999
2000         if (intel_i810_private.i810_dev)
2001                 pci_dev_put(intel_i810_private.i810_dev);
2002         if (intel_i830_private.i830_dev)
2003                 pci_dev_put(intel_i830_private.i830_dev);
2004
2005         agp_put_bridge(bridge);
2006 }
2007
2008 #ifdef CONFIG_PM
2009 static int agp_intel_resume(struct pci_dev *pdev)
2010 {
2011         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2012
2013         pci_restore_state(pdev);
2014
2015         /* We should restore our graphics device's config space,
2016          * as host bridge (00:00) resumes before graphics device (02:00),
2017          * then our access to its pci space can work right.
2018          */
2019         if (intel_i810_private.i810_dev)
2020                 pci_restore_state(intel_i810_private.i810_dev);
2021         if (intel_i830_private.i830_dev)
2022                 pci_restore_state(intel_i830_private.i830_dev);
2023
2024         if (bridge->driver == &intel_generic_driver)
2025                 intel_configure();
2026         else if (bridge->driver == &intel_850_driver)
2027                 intel_850_configure();
2028         else if (bridge->driver == &intel_845_driver)
2029                 intel_845_configure();
2030         else if (bridge->driver == &intel_830mp_driver)
2031                 intel_830mp_configure();
2032         else if (bridge->driver == &intel_915_driver)
2033                 intel_i915_configure();
2034         else if (bridge->driver == &intel_830_driver)
2035                 intel_i830_configure();
2036         else if (bridge->driver == &intel_810_driver)
2037                 intel_i810_configure();
2038         else if (bridge->driver == &intel_i965_driver)
2039                 intel_i915_configure();
2040
2041         return 0;
2042 }
2043 #endif
2044
2045 static struct pci_device_id agp_intel_pci_table[] = {
2046 #define ID(x)                                           \
2047         {                                               \
2048         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2049         .class_mask     = ~0,                           \
2050         .vendor         = PCI_VENDOR_ID_INTEL,          \
2051         .device         = x,                            \
2052         .subvendor      = PCI_ANY_ID,                   \
2053         .subdevice      = PCI_ANY_ID,                   \
2054         }
2055         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2056         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2057         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2058         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2059         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2060         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2061         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2062         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2063         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2064         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2065         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2066         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2067         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2068         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2069         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2070         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2071         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2072         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2073         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2074         ID(PCI_DEVICE_ID_INTEL_7505_0),
2075         ID(PCI_DEVICE_ID_INTEL_7205_0),
2076         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2077         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2078         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2079         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2080         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2081         ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
2082         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2083         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2084         { }
2085 };
2086
2087 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2088
2089 static struct pci_driver agp_intel_pci_driver = {
2090         .name           = "agpgart-intel",
2091         .id_table       = agp_intel_pci_table,
2092         .probe          = agp_intel_probe,
2093         .remove         = __devexit_p(agp_intel_remove),
2094 #ifdef CONFIG_PM
2095         .resume         = agp_intel_resume,
2096 #endif
2097 };
2098
2099 static int __init agp_intel_init(void)
2100 {
2101         if (agp_off)
2102                 return -EINVAL;
2103         return pci_register_driver(&agp_intel_pci_driver);
2104 }
2105
2106 static void __exit agp_intel_cleanup(void)
2107 {
2108         pci_unregister_driver(&agp_intel_pci_driver);
2109 }
2110
2111 module_init(agp_intel_init);
2112 module_exit(agp_intel_cleanup);
2113
2114 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2115 MODULE_LICENSE("GPL and additional rights");