drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pagemap.h>
  10 #include <linux/agp_backend.h>
  11 #include "agp.h"
  12
  13 /*
  14  * If we have Intel graphics, we're not going to have anything other than
  15  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  16  * on the Intel IOMMU support (CONFIG_DMAR).
  17  * Only newer chipsets need to bother with this, of course.
  18  */
  19 #ifdef CONFIG_DMAR
  20 #define USE_PCI_DMA_API 1
  21 #endif
  22
  23 #define PCI_DEVICE_ID_INTEL_E7221_HB    0x2588
  24 #define PCI_DEVICE_ID_INTEL_E7221_IG    0x258a
  25 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  26 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  27 #define PCI_DEVICE_ID_INTEL_82G35_HB     0x2980
  28 #define PCI_DEVICE_ID_INTEL_82G35_IG     0x2982
  29 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  30 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  31 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  32 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  33 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
  34 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
  35 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
  36 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
  37 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
  38 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
  39 #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB        0xA010
  40 #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG        0xA011
  41 #define PCI_DEVICE_ID_INTEL_PINEVIEW_HB         0xA000
  42 #define PCI_DEVICE_ID_INTEL_PINEVIEW_IG         0xA001
  43 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
  44 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
  45 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
  46 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
  47 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
  48 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
  49 #define PCI_DEVICE_ID_INTEL_B43_HB          0x2E40
  50 #define PCI_DEVICE_ID_INTEL_B43_IG          0x2E42
  51 #define PCI_DEVICE_ID_INTEL_GM45_HB         0x2A40
  52 #define PCI_DEVICE_ID_INTEL_GM45_IG         0x2A42
  53 #define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB        0x2E00
  54 #define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG        0x2E02
  55 #define PCI_DEVICE_ID_INTEL_Q45_HB          0x2E10
  56 #define PCI_DEVICE_ID_INTEL_Q45_IG          0x2E12
  57 #define PCI_DEVICE_ID_INTEL_G45_HB          0x2E20
  58 #define PCI_DEVICE_ID_INTEL_G45_IG          0x2E22
  59 #define PCI_DEVICE_ID_INTEL_G41_HB          0x2E30
  60 #define PCI_DEVICE_ID_INTEL_G41_IG          0x2E32
  61 #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB           0x0040
  62 #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG           0x0042
  63 #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB           0x0044
  64 #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB          0x0062
  65 #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB    0x006a
  66 #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG           0x0046
  67
  68 /* cover 915 and 945 variants */
  69 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
  70                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
  71                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
  72                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
  73                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
  74                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
  75
  76 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  77                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
  78                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  79                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
  80                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
  81                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
  82
  83 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
  84                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
  85                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
  86                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
  87                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
  88
  89 #define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
  90                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
  91
  92 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
  93                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
  94                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
  95                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
  96                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
  97                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
  98                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \
  99                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \
 100                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
 101                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB)
 102
 103 extern int agp_memory_reserved;
 104
 105
 106 /* Intel 815 register */
 107 #define INTEL_815_APCONT        0x51
 108 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
 109
 110 /* Intel i820 registers */
 111 #define INTEL_I820_RDCR         0x51
 112 #define INTEL_I820_ERRSTS       0xc8
 113
 114 /* Intel i840 registers */
 115 #define INTEL_I840_MCHCFG       0x50
 116 #define INTEL_I840_ERRSTS       0xc8
 117
 118 /* Intel i850 registers */
 119 #define INTEL_I850_MCHCFG       0x50
 120 #define INTEL_I850_ERRSTS       0xc8
 121
 122 /* intel 915G registers */
 123 #define I915_GMADDR     0x18
 124 #define I915_MMADDR     0x10
 125 #define I915_PTEADDR    0x1C
 126 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
 127 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
 128 #define G33_GMCH_GMS_STOLEN_128M        (0x8 << 4)
 129 #define G33_GMCH_GMS_STOLEN_256M        (0x9 << 4)
 130 #define INTEL_GMCH_GMS_STOLEN_96M       (0xa << 4)
 131 #define INTEL_GMCH_GMS_STOLEN_160M      (0xb << 4)
 132 #define INTEL_GMCH_GMS_STOLEN_224M      (0xc << 4)
 133 #define INTEL_GMCH_GMS_STOLEN_352M      (0xd << 4)
 134
 135 #define I915_IFPADDR    0x60
 136
 137 /* Intel 965G registers */
 138 #define I965_MSAC 0x62
 139 #define I965_IFPADDR    0x70
 140
 141 /* Intel 7505 registers */
 142 #define INTEL_I7505_APSIZE      0x74
 143 #define INTEL_I7505_NCAPID      0x60
 144 #define INTEL_I7505_NISTAT      0x6c
 145 #define INTEL_I7505_ATTBASE     0x78
 146 #define INTEL_I7505_ERRSTS      0x42
 147 #define INTEL_I7505_AGPCTRL     0x70
 148 #define INTEL_I7505_MCHCFG      0x50
 149
 150 static const struct aper_size_info_fixed intel_i810_sizes[] =
 151 {
 152         {64, 16384, 4},
 153         /* The 32M mode still requires a 64k gatt */
 154         {32, 8192, 4}
 155 };
 156
 157 #define AGP_DCACHE_MEMORY       1
 158 #define AGP_PHYS_MEMORY         2
 159 #define INTEL_AGP_CACHED_MEMORY 3
 160
 161 static struct gatt_mask intel_i810_masks[] =
 162 {
 163         {.mask = I810_PTE_VALID, .type = 0},
 164         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
 165         {.mask = I810_PTE_VALID, .type = 0},
 166         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
 167          .type = INTEL_AGP_CACHED_MEMORY}
 168 };
 169
 170 static struct _intel_private {
 171         struct pci_dev *pcidev; /* device one */
 172         u8 __iomem *registers;
 173         u32 __iomem *gtt;               /* I915G */
 174         int num_dcache_entries;
 175         /* gtt_entries is the number of gtt entries that are already mapped
 176          * to stolen memory.  Stolen memory is larger than the memory mapped
 177          * through gtt_entries, as it includes some reserved space for the BIOS
 178          * popup and for the GTT.
 179          */
 180         int gtt_entries;                        /* i830+ */
 181         int gtt_total_size;
 182         union {
 183                 void __iomem *i9xx_flush_page;
 184                 void *i8xx_flush_page;
 185         };
 186         struct page *i8xx_page;
 187         struct resource ifp_resource;
 188         int resource_valid;
 189 } intel_private;
 190
 191 #ifdef USE_PCI_DMA_API
 192 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
 193 {
 194         *ret = pci_map_page(intel_private.pcidev, page, 0,
 195                             PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 196         if (pci_dma_mapping_error(intel_private.pcidev, *ret))
 197                 return -EINVAL;
 198         return 0;
 199 }
 200
 201 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
 202 {
 203         pci_unmap_page(intel_private.pcidev, dma,
 204                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 205 }
 206
 207 static void intel_agp_free_sglist(struct agp_memory *mem)
 208 {
 209         struct sg_table st;
 210
 211         st.sgl = mem->sg_list;
 212         st.orig_nents = st.nents = mem->page_count;
 213
 214         sg_free_table(&st);
 215
 216         mem->sg_list = NULL;
 217         mem->num_sg = 0;
 218 }
 219
 220 static int intel_agp_map_memory(struct agp_memory *mem)
 221 {
 222         struct sg_table st;
 223         struct scatterlist *sg;
 224         int i;
 225
 226         DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
 227
 228         if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
 229                 return -ENOMEM;
 230
 231         mem->sg_list = sg = st.sgl;
 232
 233         for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
 234                 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
 235
 236         mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
 237                                  mem->page_count, PCI_DMA_BIDIRECTIONAL);
 238         if (unlikely(!mem->num_sg)) {
 239                 intel_agp_free_sglist(mem);
 240                 return -ENOMEM;
 241         }
 242         return 0;
 243 }
 244
 245 static void intel_agp_unmap_memory(struct agp_memory *mem)
 246 {
 247         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 248
 249         pci_unmap_sg(intel_private.pcidev, mem->sg_list,
 250                      mem->page_count, PCI_DMA_BIDIRECTIONAL);
 251         intel_agp_free_sglist(mem);
 252 }
 253
 254 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 255                                         off_t pg_start, int mask_type)
 256 {
 257         struct scatterlist *sg;
 258         int i, j;
 259
 260         j = pg_start;
 261
 262         WARN_ON(!mem->num_sg);
 263
 264         if (mem->num_sg == mem->page_count) {
 265                 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
 266                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 267                                         sg_dma_address(sg), mask_type),
 268                                         intel_private.gtt+j);
 269                         j++;
 270                 }
 271         } else {
 272                 /* sg may merge pages, but we have to seperate
 273                  * per-page addr for GTT */
 274                 unsigned int len, m;
 275
 276                 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
 277                         len = sg_dma_len(sg) / PAGE_SIZE;
 278                         for (m = 0; m < len; m++) {
 279                                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 280                                                                        sg_dma_address(sg) + m * PAGE_SIZE,
 281                                                                        mask_type),
 282                                        intel_private.gtt+j);
 283                                 j++;
 284                         }
 285                 }
 286         }
 287         readl(intel_private.gtt+j-1);
 288 }
 289
 290 #else
 291
 292 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 293                                         off_t pg_start, int mask_type)
 294 {
 295         int i, j;
 296
 297         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 298                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 299                                 page_to_phys(mem->pages[i]), mask_type),
 300                        intel_private.gtt+j);
 301         }
 302
 303         readl(intel_private.gtt+j-1);
 304 }
 305
 306 #endif
 307
 308 static int intel_i810_fetch_size(void)
 309 {
 310         u32 smram_miscc;
 311         struct aper_size_info_fixed *values;
 312
 313         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
 314         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 315
 316         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 317                 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
 318                 return 0;
 319         }
 320         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 321                 agp_bridge->previous_size =
 322                         agp_bridge->current_size = (void *) (values + 1);
 323                 agp_bridge->aperture_size_idx = 1;
 324                 return values[1].size;
 325         } else {
 326                 agp_bridge->previous_size =
 327                         agp_bridge->current_size = (void *) (values);
 328                 agp_bridge->aperture_size_idx = 0;
 329                 return values[0].size;
 330         }
 331
 332         return 0;
 333 }
 334
 335 static int intel_i810_configure(void)
 336 {
 337         struct aper_size_info_fixed *current_size;
 338         u32 temp;
 339         int i;
 340
 341         current_size = A_SIZE_FIX(agp_bridge->current_size);
 342
 343         if (!intel_private.registers) {
 344                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 345                 temp &= 0xfff80000;
 346
 347                 intel_private.registers = ioremap(temp, 128 * 4096);
 348                 if (!intel_private.registers) {
 349                         dev_err(&intel_private.pcidev->dev,
 350                                 "can't remap memory\n");
 351                         return -ENOMEM;
 352                 }
 353         }
 354
 355         if ((readl(intel_private.registers+I810_DRAM_CTL)
 356                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 357                 /* This will need to be dynamically assigned */
 358                 dev_info(&intel_private.pcidev->dev,
 359                          "detected 4MB dedicated video ram\n");
 360                 intel_private.num_dcache_entries = 1024;
 361         }
 362         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 363         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 364         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 365         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 366
 367         if (agp_bridge->driver->needs_scratch_page) {
 368                 for (i = 0; i < current_size->num_entries; i++) {
 369                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 370                 }
 371                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
 372         }
 373         global_cache_flush();
 374         return 0;
 375 }
 376
 377 static void intel_i810_cleanup(void)
 378 {
 379         writel(0, intel_private.registers+I810_PGETBL_CTL);
 380         readl(intel_private.registers); /* PCI Posting. */
 381         iounmap(intel_private.registers);
 382 }
 383
 384 static void intel_i810_tlbflush(struct agp_memory *mem)
 385 {
 386         return;
 387 }
 388
 389 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 390 {
 391         return;
 392 }
 393
 394 /* Exists to support ARGB cursors */
 395 static struct page *i8xx_alloc_pages(void)
 396 {
 397         struct page *page;
 398
 399         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 400         if (page == NULL)
 401                 return NULL;
 402
 403         if (set_pages_uc(page, 4) < 0) {
 404                 set_pages_wb(page, 4);
 405                 __free_pages(page, 2);
 406                 return NULL;
 407         }
 408         get_page(page);
 409         atomic_inc(&agp_bridge->current_memory_agp);
 410         return page;
 411 }
 412
 413 static void i8xx_destroy_pages(struct page *page)
 414 {
 415         if (page == NULL)
 416                 return;
 417
 418         set_pages_wb(page, 4);
 419         put_page(page);
 420         __free_pages(page, 2);
 421         atomic_dec(&agp_bridge->current_memory_agp);
 422 }
 423
 424 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 425                                         int type)
 426 {
 427         if (type < AGP_USER_TYPES)
 428                 return type;
 429         else if (type == AGP_USER_CACHED_MEMORY)
 430                 return INTEL_AGP_CACHED_MEMORY;
 431         else
 432                 return 0;
 433 }
 434
 435 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 436                                 int type)
 437 {
 438         int i, j, num_entries;
 439         void *temp;
 440         int ret = -EINVAL;
 441         int mask_type;
 442
 443         if (mem->page_count == 0)
 444                 goto out;
 445
 446         temp = agp_bridge->current_size;
 447         num_entries = A_SIZE_FIX(temp)->num_entries;
 448
 449         if ((pg_start + mem->page_count) > num_entries)
 450                 goto out_err;
 451
 452
 453         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 454                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 455                         ret = -EBUSY;
 456                         goto out_err;
 457                 }
 458         }
 459
 460         if (type != mem->type)
 461                 goto out_err;
 462
 463         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 464
 465         switch (mask_type) {
 466         case AGP_DCACHE_MEMORY:
 467                 if (!mem->is_flushed)
 468                         global_cache_flush();
 469                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 470                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 471                                intel_private.registers+I810_PTE_BASE+(i*4));
 472                 }
 473                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 474                 break;
 475         case AGP_PHYS_MEMORY:
 476         case AGP_NORMAL_MEMORY:
 477                 if (!mem->is_flushed)
 478                         global_cache_flush();
 479                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 480                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 481                                         page_to_phys(mem->pages[i]), mask_type),
 482                                intel_private.registers+I810_PTE_BASE+(j*4));
 483                 }
 484                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 485                 break;
 486         default:
 487                 goto out_err;
 488         }
 489
 490         agp_bridge->driver->tlb_flush(mem);
 491 out:
 492         ret = 0;
 493 out_err:
 494         mem->is_flushed = true;
 495         return ret;
 496 }
 497
 498 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 499                                 int type)
 500 {
 501         int i;
 502
 503         if (mem->page_count == 0)
 504                 return 0;
 505
 506         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 507                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 508         }
 509         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 510
 511         agp_bridge->driver->tlb_flush(mem);
 512         return 0;
 513 }
 514
 515 /*
 516  * The i810/i830 requires a physical address to program its mouse
 517  * pointer into hardware.
 518  * However the Xserver still writes to it through the agp aperture.
 519  */
 520 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 521 {
 522         struct agp_memory *new;
 523         struct page *page;
 524
 525         switch (pg_count) {
 526         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 527                 break;
 528         case 4:
 529                 /* kludge to get 4 physical pages for ARGB cursor */
 530                 page = i8xx_alloc_pages();
 531                 break;
 532         default:
 533                 return NULL;
 534         }
 535
 536         if (page == NULL)
 537                 return NULL;
 538
 539         new = agp_create_memory(pg_count);
 540         if (new == NULL)
 541                 return NULL;
 542
 543         new->pages[0] = page;
 544         if (pg_count == 4) {
 545                 /* kludge to get 4 physical pages for ARGB cursor */
 546                 new->pages[1] = new->pages[0] + 1;
 547                 new->pages[2] = new->pages[1] + 1;
 548                 new->pages[3] = new->pages[2] + 1;
 549         }
 550         new->page_count = pg_count;
 551         new->num_scratch_pages = pg_count;
 552         new->type = AGP_PHYS_MEMORY;
 553         new->physical = page_to_phys(new->pages[0]);
 554         return new;
 555 }
 556
 557 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 558 {
 559         struct agp_memory *new;
 560
 561         if (type == AGP_DCACHE_MEMORY) {
 562                 if (pg_count != intel_private.num_dcache_entries)
 563                         return NULL;
 564
 565                 new = agp_create_memory(1);
 566                 if (new == NULL)
 567                         return NULL;
 568
 569                 new->type = AGP_DCACHE_MEMORY;
 570                 new->page_count = pg_count;
 571                 new->num_scratch_pages = 0;
 572                 agp_free_page_array(new);
 573                 return new;
 574         }
 575         if (type == AGP_PHYS_MEMORY)
 576                 return alloc_agpphysmem_i8xx(pg_count, type);
 577         return NULL;
 578 }
 579
 580 static void intel_i810_free_by_type(struct agp_memory *curr)
 581 {
 582         agp_free_key(curr->key);
 583         if (curr->type == AGP_PHYS_MEMORY) {
 584                 if (curr->page_count == 4)
 585                         i8xx_destroy_pages(curr->pages[0]);
 586                 else {
 587                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 588                                                              AGP_PAGE_DESTROY_UNMAP);
 589                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 590                                                              AGP_PAGE_DESTROY_FREE);
 591                 }
 592                 agp_free_page_array(curr);
 593         }
 594         kfree(curr);
 595 }
 596
 597 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 598                                             dma_addr_t addr, int type)
 599 {
 600         /* Type checking must be done elsewhere */
 601         return addr | bridge->driver->masks[type].mask;
 602 }
 603
 604 static struct aper_size_info_fixed intel_i830_sizes[] =
 605 {
 606         {128, 32768, 5},
 607         /* The 64M mode still requires a 128k gatt */
 608         {64, 16384, 5},
 609         {256, 65536, 6},
 610         {512, 131072, 7},
 611 };
 612
 613 static void intel_i830_init_gtt_entries(void)
 614 {
 615         u16 gmch_ctrl;
 616         int gtt_entries;
 617         u8 rdct;
 618         int local = 0;
 619         static const int ddt[4] = { 0, 16, 32, 64 };
 620         int size; /* reserved space (in kb) at the top of stolen memory */
 621
 622         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 623
 624         if (IS_I965) {
 625                 u32 pgetbl_ctl;
 626                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 627
 628                 /* The 965 has a field telling us the size of the GTT,
 629                  * which may be larger than what is necessary to map the
 630                  * aperture.
 631                  */
 632                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 633                 case I965_PGETBL_SIZE_128KB:
 634                         size = 128;
 635                         break;
 636                 case I965_PGETBL_SIZE_256KB:
 637                         size = 256;
 638                         break;
 639                 case I965_PGETBL_SIZE_512KB:
 640                         size = 512;
 641                         break;
 642                 case I965_PGETBL_SIZE_1MB:
 643                         size = 1024;
 644                         break;
 645                 case I965_PGETBL_SIZE_2MB:
 646                         size = 2048;
 647                         break;
 648                 case I965_PGETBL_SIZE_1_5MB:
 649                         size = 1024 + 512;
 650                         break;
 651                 default:
 652                         dev_info(&intel_private.pcidev->dev,
 653                                  "unknown page table size, assuming 512KB\n");
 654                         size = 512;
 655                 }
 656                 size += 4; /* add in BIOS popup space */
 657         } else if (IS_G33 && !IS_PINEVIEW) {
 658         /* G33's GTT size defined in gmch_ctrl */
 659                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
 660                 case G33_PGETBL_SIZE_1M:
 661                         size = 1024;
 662                         break;
 663                 case G33_PGETBL_SIZE_2M:
 664                         size = 2048;
 665                         break;
 666                 default:
 667                         dev_info(&agp_bridge->dev->dev,
 668                                  "unknown page table size 0x%x, assuming 512KB\n",
 669                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
 670                         size = 512;
 671                 }
 672                 size += 4;
 673         } else if (IS_G4X || IS_PINEVIEW) {
 674                 /* On 4 series hardware, GTT stolen is separate from graphics
 675                  * stolen, ignore it in stolen gtt entries counting.  However,
 676                  * 4KB of the stolen memory doesn't get mapped to the GTT.
 677                  */
 678                 size = 4;
 679         } else {
 680                 /* On previous hardware, the GTT size was just what was
 681                  * required to map the aperture.
 682                  */
 683                 size = agp_bridge->driver->fetch_size() + 4;
 684         }
 685
 686         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 687             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 688                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 689                 case I830_GMCH_GMS_STOLEN_512:
 690                         gtt_entries = KB(512) - KB(size);
 691                         break;
 692                 case I830_GMCH_GMS_STOLEN_1024:
 693                         gtt_entries = MB(1) - KB(size);
 694                         break;
 695                 case I830_GMCH_GMS_STOLEN_8192:
 696                         gtt_entries = MB(8) - KB(size);
 697                         break;
 698                 case I830_GMCH_GMS_LOCAL:
 699                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 700                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 701                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 702                         local = 1;
 703                         break;
 704                 default:
 705                         gtt_entries = 0;
 706                         break;
 707                 }
 708         } else {
 709                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 710                 case I855_GMCH_GMS_STOLEN_1M:
 711                         gtt_entries = MB(1) - KB(size);
 712                         break;
 713                 case I855_GMCH_GMS_STOLEN_4M:
 714                         gtt_entries = MB(4) - KB(size);
 715                         break;
 716                 case I855_GMCH_GMS_STOLEN_8M:
 717                         gtt_entries = MB(8) - KB(size);
 718                         break;
 719                 case I855_GMCH_GMS_STOLEN_16M:
 720                         gtt_entries = MB(16) - KB(size);
 721                         break;
 722                 case I855_GMCH_GMS_STOLEN_32M:
 723                         gtt_entries = MB(32) - KB(size);
 724                         break;
 725                 case I915_GMCH_GMS_STOLEN_48M:
 726                         /* Check it's really I915G */
 727                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 728                                 gtt_entries = MB(48) - KB(size);
 729                         else
 730                                 gtt_entries = 0;
 731                         break;
 732                 case I915_GMCH_GMS_STOLEN_64M:
 733                         /* Check it's really I915G */
 734                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 735                                 gtt_entries = MB(64) - KB(size);
 736                         else
 737                                 gtt_entries = 0;
 738                         break;
 739                 case G33_GMCH_GMS_STOLEN_128M:
 740                         if (IS_G33 || IS_I965 || IS_G4X)
 741                                 gtt_entries = MB(128) - KB(size);
 742                         else
 743                                 gtt_entries = 0;
 744                         break;
 745                 case G33_GMCH_GMS_STOLEN_256M:
 746                         if (IS_G33 || IS_I965 || IS_G4X)
 747                                 gtt_entries = MB(256) - KB(size);
 748                         else
 749                                 gtt_entries = 0;
 750                         break;
 751                 case INTEL_GMCH_GMS_STOLEN_96M:
 752                         if (IS_I965 || IS_G4X)
 753                                 gtt_entries = MB(96) - KB(size);
 754                         else
 755                                 gtt_entries = 0;
 756                         break;
 757                 case INTEL_GMCH_GMS_STOLEN_160M:
 758                         if (IS_I965 || IS_G4X)
 759                                 gtt_entries = MB(160) - KB(size);
 760                         else
 761                                 gtt_entries = 0;
 762                         break;
 763                 case INTEL_GMCH_GMS_STOLEN_224M:
 764                         if (IS_I965 || IS_G4X)
 765                                 gtt_entries = MB(224) - KB(size);
 766                         else
 767                                 gtt_entries = 0;
 768                         break;
 769                 case INTEL_GMCH_GMS_STOLEN_352M:
 770                         if (IS_I965 || IS_G4X)
 771                                 gtt_entries = MB(352) - KB(size);
 772                         else
 773                                 gtt_entries = 0;
 774                         break;
 775                 default:
 776                         gtt_entries = 0;
 777                         break;
 778                 }
 779         }
 780         if (gtt_entries > 0) {
 781                 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
 782                        gtt_entries / KB(1), local ? "local" : "stolen");
 783                 gtt_entries /= KB(4);
 784         } else {
 785                 dev_info(&agp_bridge->dev->dev,
 786                        "no pre-allocated video memory detected\n");
 787                 gtt_entries = 0;
 788         }
 789
 790         intel_private.gtt_entries = gtt_entries;
 791 }
 792
 793 static void intel_i830_fini_flush(void)
 794 {
 795         kunmap(intel_private.i8xx_page);
 796         intel_private.i8xx_flush_page = NULL;
 797         unmap_page_from_agp(intel_private.i8xx_page);
 798
 799         __free_page(intel_private.i8xx_page);
 800         intel_private.i8xx_page = NULL;
 801 }
 802
 803 static void intel_i830_setup_flush(void)
 804 {
 805         /* return if we've already set the flush mechanism up */
 806         if (intel_private.i8xx_page)
 807                 return;
 808
 809         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
 810         if (!intel_private.i8xx_page)
 811                 return;
 812
 813         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 814         if (!intel_private.i8xx_flush_page)
 815                 intel_i830_fini_flush();
 816 }
 817
 818 static void
 819 do_wbinvd(void *null)
 820 {
 821         wbinvd();
 822 }
 823
 824 /* The chipset_flush interface needs to get data that has already been
 825  * flushed out of the CPU all the way out to main memory, because the GPU
 826  * doesn't snoop those buffers.
 827  *
 828  * The 8xx series doesn't have the same lovely interface for flushing the
 829  * chipset write buffers that the later chips do. According to the 865
 830  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
 831  * that buffer out, we just fill 1KB and clflush it out, on the assumption
 832  * that it'll push whatever was in there out.  It appears to work.
 833  */
 834 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 835 {
 836         unsigned int *pg = intel_private.i8xx_flush_page;
 837
 838         memset(pg, 0, 1024);
 839
 840         if (cpu_has_clflush) {
 841                 clflush_cache_range(pg, 1024);
 842         } else {
 843                 if (on_each_cpu(do_wbinvd, NULL, 1) != 0)
 844                         printk(KERN_ERR "Timed out waiting for cache flush.\n");
 845         }
 846 }
 847
 848 /* The intel i830 automatically initializes the agp aperture during POST.
 849  * Use the memory already set aside for in the GTT.
 850  */
 851 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 852 {
 853         int page_order;
 854         struct aper_size_info_fixed *size;
 855         int num_entries;
 856         u32 temp;
 857
 858         size = agp_bridge->current_size;
 859         page_order = size->page_order;
 860         num_entries = size->num_entries;
 861         agp_bridge->gatt_table_real = NULL;
 862
 863         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 864         temp &= 0xfff80000;
 865
 866         intel_private.registers = ioremap(temp, 128 * 4096);
 867         if (!intel_private.registers)
 868                 return -ENOMEM;
 869
 870         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 871         global_cache_flush();   /* FIXME: ?? */
 872
 873         /* we have to call this as early as possible after the MMIO base address is known */
 874         intel_i830_init_gtt_entries();
 875
 876         agp_bridge->gatt_table = NULL;
 877
 878         agp_bridge->gatt_bus_addr = temp;
 879
 880         return 0;
 881 }
 882
 883 /* Return the gatt table to a sane state. Use the top of stolen
 884  * memory for the GTT.
 885  */
 886 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 887 {
 888         return 0;
 889 }
 890
 891 static int intel_i830_fetch_size(void)
 892 {
 893         u16 gmch_ctrl;
 894         struct aper_size_info_fixed *values;
 895
 896         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 897
 898         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 899             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 900                 /* 855GM/852GM/865G has 128MB aperture size */
 901                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 902                 agp_bridge->aperture_size_idx = 0;
 903                 return values[0].size;
 904         }
 905
 906         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 907
 908         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 909                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 910                 agp_bridge->aperture_size_idx = 0;
 911                 return values[0].size;
 912         } else {
 913                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
 914                 agp_bridge->aperture_size_idx = 1;
 915                 return values[1].size;
 916         }
 917
 918         return 0;
 919 }
 920
 921 static int intel_i830_configure(void)
 922 {
 923         struct aper_size_info_fixed *current_size;
 924         u32 temp;
 925         u16 gmch_ctrl;
 926         int i;
 927
 928         current_size = A_SIZE_FIX(agp_bridge->current_size);
 929
 930         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 931         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 932
 933         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 934         gmch_ctrl |= I830_GMCH_ENABLED;
 935         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
 936
 937         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 938         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 939
 940         if (agp_bridge->driver->needs_scratch_page) {
 941                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 942                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 943                 }
 944                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
 945         }
 946
 947         global_cache_flush();
 948
 949         intel_i830_setup_flush();
 950         return 0;
 951 }
 952
 953 static void intel_i830_cleanup(void)
 954 {
 955         iounmap(intel_private.registers);
 956 }
 957
 958 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
 959                                      int type)
 960 {
 961         int i, j, num_entries;
 962         void *temp;
 963         int ret = -EINVAL;
 964         int mask_type;
 965
 966         if (mem->page_count == 0)
 967                 goto out;
 968
 969         temp = agp_bridge->current_size;
 970         num_entries = A_SIZE_FIX(temp)->num_entries;
 971
 972         if (pg_start < intel_private.gtt_entries) {
 973                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
 974                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
 975                            pg_start, intel_private.gtt_entries);
 976
 977                 dev_info(&intel_private.pcidev->dev,
 978                          "trying to insert into local/stolen memory\n");
 979                 goto out_err;
 980         }
 981
 982         if ((pg_start + mem->page_count) > num_entries)
 983                 goto out_err;
 984
 985         /* The i830 can't check the GTT for entries since its read only,
 986          * depend on the caller to make the correct offset decisions.
 987          */
 988
 989         if (type != mem->type)
 990                 goto out_err;
 991
 992         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 993
 994         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 995             mask_type != INTEL_AGP_CACHED_MEMORY)
 996                 goto out_err;
 997
 998         if (!mem->is_flushed)
 999                 global_cache_flush();
1000
1001         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1002                 writel(agp_bridge->driver->mask_memory(agp_bridge,
1003                                 page_to_phys(mem->pages[i]), mask_type),
1004                        intel_private.registers+I810_PTE_BASE+(j*4));
1005         }
1006         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
1007         agp_bridge->driver->tlb_flush(mem);
1008
1009 out:
1010         ret = 0;
1011 out_err:
1012         mem->is_flushed = true;
1013         return ret;
1014 }
1015
1016 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
1017                                      int type)
1018 {
1019         int i;
1020
1021         if (mem->page_count == 0)
1022                 return 0;
1023
1024         if (pg_start < intel_private.gtt_entries) {
1025                 dev_info(&intel_private.pcidev->dev,
1026                          "trying to disable local/stolen memory\n");
1027                 return -EINVAL;
1028         }
1029
1030         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1031                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1032         }
1033         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1034
1035         agp_bridge->driver->tlb_flush(mem);
1036         return 0;
1037 }
1038
1039 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
1040 {
1041         if (type == AGP_PHYS_MEMORY)
1042                 return alloc_agpphysmem_i8xx(pg_count, type);
1043         /* always return NULL for other allocation types for now */
1044         return NULL;
1045 }
1046
1047 static int intel_alloc_chipset_flush_resource(void)
1048 {
1049         int ret;
1050         ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1051                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1052                                      pcibios_align_resource, agp_bridge->dev);
1053
1054         return ret;
1055 }
1056
1057 static void intel_i915_setup_chipset_flush(void)
1058 {
1059         int ret;
1060         u32 temp;
1061
1062         pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
1063         if (!(temp & 0x1)) {
1064                 intel_alloc_chipset_flush_resource();
1065                 intel_private.resource_valid = 1;
1066                 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1067         } else {
1068                 temp &= ~1;
1069
1070                 intel_private.resource_valid = 1;
1071                 intel_private.ifp_resource.start = temp;
1072                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1073                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1074                 /* some BIOSes reserve this area in a pnp some don't */
1075                 if (ret)
1076                         intel_private.resource_valid = 0;
1077         }
1078 }
1079
1080 static void intel_i965_g33_setup_chipset_flush(void)
1081 {
1082         u32 temp_hi, temp_lo;
1083         int ret;
1084
1085         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
1086         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
1087
1088         if (!(temp_lo & 0x1)) {
1089
1090                 intel_alloc_chipset_flush_resource();
1091
1092                 intel_private.resource_valid = 1;
1093                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
1094                         upper_32_bits(intel_private.ifp_resource.start));
1095                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1096         } else {
1097                 u64 l64;
1098
1099                 temp_lo &= ~0x1;
1100                 l64 = ((u64)temp_hi << 32) | temp_lo;
1101
1102                 intel_private.resource_valid = 1;
1103                 intel_private.ifp_resource.start = l64;
1104                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1105                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1106                 /* some BIOSes reserve this area in a pnp some don't */
1107                 if (ret)
1108                         intel_private.resource_valid = 0;
1109         }
1110 }
1111
1112 static void intel_i9xx_setup_flush(void)
1113 {
1114         /* return if already configured */
1115         if (intel_private.ifp_resource.start)
1116                 return;
1117
1118         /* setup a resource for this object */
1119         intel_private.ifp_resource.name = "Intel Flush Page";
1120         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1121
1122         /* Setup chipset flush for 915 */
1123         if (IS_I965 || IS_G33 || IS_G4X) {
1124                 intel_i965_g33_setup_chipset_flush();
1125         } else {
1126                 intel_i915_setup_chipset_flush();
1127         }
1128
1129         if (intel_private.ifp_resource.start) {
1130                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1131                 if (!intel_private.i9xx_flush_page)
1132                         dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
1133         }
1134 }
1135
1136 static int intel_i915_configure(void)
1137 {
1138         struct aper_size_info_fixed *current_size;
1139         u32 temp;
1140         u16 gmch_ctrl;
1141         int i;
1142
1143         current_size = A_SIZE_FIX(agp_bridge->current_size);
1144
1145         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1146
1147         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1148
1149         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1150         gmch_ctrl |= I830_GMCH_ENABLED;
1151         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1152
1153         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1154         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1155
1156         if (agp_bridge->driver->needs_scratch_page) {
1157                 for (i = intel_private.gtt_entries; i < intel_private.gtt_total_size; i++) {
1158                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
1159                 }
1160                 readl(intel_private.gtt+i-1);   /* PCI Posting. */
1161         }
1162
1163         global_cache_flush();
1164
1165         intel_i9xx_setup_flush();
1166
1167         return 0;
1168 }
1169
1170 static void intel_i915_cleanup(void)
1171 {
1172         if (intel_private.i9xx_flush_page)
1173                 iounmap(intel_private.i9xx_flush_page);
1174         if (intel_private.resource_valid)
1175                 release_resource(&intel_private.ifp_resource);
1176         intel_private.ifp_resource.start = 0;
1177         intel_private.resource_valid = 0;
1178         iounmap(intel_private.gtt);
1179         iounmap(intel_private.registers);
1180 }
1181
1182 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1183 {
1184         if (intel_private.i9xx_flush_page)
1185                 writel(1, intel_private.i9xx_flush_page);
1186 }
1187
1188 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1189                                      int type)
1190 {
1191         int num_entries;
1192         void *temp;
1193         int ret = -EINVAL;
1194         int mask_type;
1195
1196         if (mem->page_count == 0)
1197                 goto out;
1198
1199         temp = agp_bridge->current_size;
1200         num_entries = A_SIZE_FIX(temp)->num_entries;
1201
1202         if (pg_start < intel_private.gtt_entries) {
1203                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1204                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1205                            pg_start, intel_private.gtt_entries);
1206
1207                 dev_info(&intel_private.pcidev->dev,
1208                          "trying to insert into local/stolen memory\n");
1209                 goto out_err;
1210         }
1211
1212         if ((pg_start + mem->page_count) > num_entries)
1213                 goto out_err;
1214
1215         /* The i915 can't check the GTT for entries since it's read only;
1216          * depend on the caller to make the correct offset decisions.
1217          */
1218
1219         if (type != mem->type)
1220                 goto out_err;
1221
1222         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1223
1224         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1225             mask_type != INTEL_AGP_CACHED_MEMORY)
1226                 goto out_err;
1227
1228         if (!mem->is_flushed)
1229                 global_cache_flush();
1230
1231         intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1232         agp_bridge->driver->tlb_flush(mem);
1233
1234  out:
1235         ret = 0;
1236  out_err:
1237         mem->is_flushed = true;
1238         return ret;
1239 }
1240
1241 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1242                                      int type)
1243 {
1244         int i;
1245
1246         if (mem->page_count == 0)
1247                 return 0;
1248
1249         if (pg_start < intel_private.gtt_entries) {
1250                 dev_info(&intel_private.pcidev->dev,
1251                          "trying to disable local/stolen memory\n");
1252                 return -EINVAL;
1253         }
1254
1255         for (i = pg_start; i < (mem->page_count + pg_start); i++)
1256                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1257
1258         readl(intel_private.gtt+i-1);
1259
1260         agp_bridge->driver->tlb_flush(mem);
1261         return 0;
1262 }
1263
1264 /* Return the aperture size by just checking the resource length.  The effect
1265  * described in the spec of the MSAC registers is just changing of the
1266  * resource size.
1267  */
1268 static int intel_i9xx_fetch_size(void)
1269 {
1270         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1271         int aper_size; /* size in megabytes */
1272         int i;
1273
1274         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1275
1276         for (i = 0; i < num_sizes; i++) {
1277                 if (aper_size == intel_i830_sizes[i].size) {
1278                         agp_bridge->current_size = intel_i830_sizes + i;
1279                         agp_bridge->previous_size = agp_bridge->current_size;
1280                         return aper_size;
1281                 }
1282         }
1283
1284         return 0;
1285 }
1286
1287 /* The intel i915 automatically initializes the agp aperture during POST.
1288  * Use the memory already set aside for in the GTT.
1289  */
1290 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1291 {
1292         int page_order;
1293         struct aper_size_info_fixed *size;
1294         int num_entries;
1295         u32 temp, temp2;
1296         int gtt_map_size = 256 * 1024;
1297
1298         size = agp_bridge->current_size;
1299         page_order = size->page_order;
1300         num_entries = size->num_entries;
1301         agp_bridge->gatt_table_real = NULL;
1302
1303         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1304         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1305
1306         if (IS_G33)
1307             gtt_map_size = 1024 * 1024; /* 1M on G33 */
1308         intel_private.gtt = ioremap(temp2, gtt_map_size);
1309         if (!intel_private.gtt)
1310                 return -ENOMEM;
1311
1312         intel_private.gtt_total_size = gtt_map_size / 4;
1313
1314         temp &= 0xfff80000;
1315
1316         intel_private.registers = ioremap(temp, 128 * 4096);
1317         if (!intel_private.registers) {
1318                 iounmap(intel_private.gtt);
1319                 return -ENOMEM;
1320         }
1321
1322         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1323         global_cache_flush();   /* FIXME: ? */
1324
1325         /* we have to call this as early as possible after the MMIO base address is known */
1326         intel_i830_init_gtt_entries();
1327
1328         agp_bridge->gatt_table = NULL;
1329
1330         agp_bridge->gatt_bus_addr = temp;
1331
1332         return 0;
1333 }
1334
1335 /*
1336  * The i965 supports 36-bit physical addresses, but to keep
1337  * the format of the GTT the same, the bits that don't fit
1338  * in a 32-bit word are shifted down to bits 4..7.
1339  *
1340  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1341  * is always zero on 32-bit architectures, so no need to make
1342  * this conditional.
1343  */
1344 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1345                                             dma_addr_t addr, int type)
1346 {
1347         /* Shift high bits down */
1348         addr |= (addr >> 28) & 0xf0;
1349
1350         /* Type checking must be done elsewhere */
1351         return addr | bridge->driver->masks[type].mask;
1352 }
1353
1354 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1355 {
1356         switch (agp_bridge->dev->device) {
1357         case PCI_DEVICE_ID_INTEL_GM45_HB:
1358         case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
1359         case PCI_DEVICE_ID_INTEL_Q45_HB:
1360         case PCI_DEVICE_ID_INTEL_G45_HB:
1361         case PCI_DEVICE_ID_INTEL_G41_HB:
1362         case PCI_DEVICE_ID_INTEL_B43_HB:
1363         case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB:
1364         case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
1365         case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
1366         case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
1367                 *gtt_offset = *gtt_size = MB(2);
1368                 break;
1369         default:
1370                 *gtt_offset = *gtt_size = KB(512);
1371         }
1372 }
1373
1374 /* The intel i965 automatically initializes the agp aperture during POST.
1375  * Use the memory already set aside for in the GTT.
1376  */
1377 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1378 {
1379         int page_order;
1380         struct aper_size_info_fixed *size;
1381         int num_entries;
1382         u32 temp;
1383         int gtt_offset, gtt_size;
1384
1385         size = agp_bridge->current_size;
1386         page_order = size->page_order;
1387         num_entries = size->num_entries;
1388         agp_bridge->gatt_table_real = NULL;
1389
1390         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1391
1392         temp &= 0xfff00000;
1393
1394         intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1395
1396         intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1397
1398         if (!intel_private.gtt)
1399                 return -ENOMEM;
1400
1401         intel_private.gtt_total_size = gtt_size / 4;
1402
1403         intel_private.registers = ioremap(temp, 128 * 4096);
1404         if (!intel_private.registers) {
1405                 iounmap(intel_private.gtt);
1406                 return -ENOMEM;
1407         }
1408
1409         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1410         global_cache_flush();   /* FIXME: ? */
1411
1412         /* we have to call this as early as possible after the MMIO base address is known */
1413         intel_i830_init_gtt_entries();
1414
1415         agp_bridge->gatt_table = NULL;
1416
1417         agp_bridge->gatt_bus_addr = temp;
1418
1419         return 0;
1420 }
1421
1422
1423 static int intel_fetch_size(void)
1424 {
1425         int i;
1426         u16 temp;
1427         struct aper_size_info_16 *values;
1428
1429         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1430         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1431
1432         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1433                 if (temp == values[i].size_value) {
1434                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1435                         agp_bridge->aperture_size_idx = i;
1436                         return values[i].size;
1437                 }
1438         }
1439
1440         return 0;
1441 }
1442
1443 static int __intel_8xx_fetch_size(u8 temp)
1444 {
1445         int i;
1446         struct aper_size_info_8 *values;
1447
1448         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1449
1450         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1451                 if (temp == values[i].size_value) {
1452                         agp_bridge->previous_size =
1453                                 agp_bridge->current_size = (void *) (values + i);
1454                         agp_bridge->aperture_size_idx = i;
1455                         return values[i].size;
1456                 }
1457         }
1458         return 0;
1459 }
1460
1461 static int intel_8xx_fetch_size(void)
1462 {
1463         u8 temp;
1464
1465         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1466         return __intel_8xx_fetch_size(temp);
1467 }
1468
1469 static int intel_815_fetch_size(void)
1470 {
1471         u8 temp;
1472
1473         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1474          * one non-reserved bit, so mask the others out ... */
1475         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1476         temp &= (1 << 3);
1477
1478         return __intel_8xx_fetch_size(temp);
1479 }
1480
1481 static void intel_tlbflush(struct agp_memory *mem)
1482 {
1483         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1484         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1485 }
1486
1487
1488 static void intel_8xx_tlbflush(struct agp_memory *mem)
1489 {
1490         u32 temp;
1491         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1492         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1493         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1494         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1495 }
1496
1497
1498 static void intel_cleanup(void)
1499 {
1500         u16 temp;
1501         struct aper_size_info_16 *previous_size;
1502
1503         previous_size = A_SIZE_16(agp_bridge->previous_size);
1504         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1505         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1506         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1507 }
1508
1509
1510 static void intel_8xx_cleanup(void)
1511 {
1512         u16 temp;
1513         struct aper_size_info_8 *previous_size;
1514
1515         previous_size = A_SIZE_8(agp_bridge->previous_size);
1516         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1517         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1518         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1519 }
1520
1521
1522 static int intel_configure(void)
1523 {
1524         u32 temp;
1525         u16 temp2;
1526         struct aper_size_info_16 *current_size;
1527
1528         current_size = A_SIZE_16(agp_bridge->current_size);
1529
1530         /* aperture size */
1531         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1532
1533         /* address to map to */
1534         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1535         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1536
1537         /* attbase - aperture base */
1538         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1539
1540         /* agpctrl */
1541         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1542
1543         /* paccfg/nbxcfg */
1544         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1545         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1546                         (temp2 & ~(1 << 10)) | (1 << 9));
1547         /* clear any possible error conditions */
1548         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1549         return 0;
1550 }
1551
1552 static int intel_815_configure(void)
1553 {
1554         u32 temp, addr;
1555         u8 temp2;
1556         struct aper_size_info_8 *current_size;
1557
1558         /* attbase - aperture base */
1559         /* the Intel 815 chipset spec. says that bits 29-31 in the
1560         * ATTBASE register are reserved -> try not to write them */
1561         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1562                 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
1563                 return -EINVAL;
1564         }
1565
1566         current_size = A_SIZE_8(agp_bridge->current_size);
1567
1568         /* aperture size */
1569         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1570                         current_size->size_value);
1571
1572         /* address to map to */
1573         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1574         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1575
1576         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1577         addr &= INTEL_815_ATTBASE_MASK;
1578         addr |= agp_bridge->gatt_bus_addr;
1579         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1580
1581         /* agpctrl */
1582         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1583
1584         /* apcont */
1585         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1586         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1587
1588         /* clear any possible error conditions */
1589         /* Oddness : this chipset seems to have no ERRSTS register ! */
1590         return 0;
1591 }
1592
1593 static void intel_820_tlbflush(struct agp_memory *mem)
1594 {
1595         return;
1596 }
1597
1598 static void intel_820_cleanup(void)
1599 {
1600         u8 temp;
1601         struct aper_size_info_8 *previous_size;
1602
1603         previous_size = A_SIZE_8(agp_bridge->previous_size);
1604         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1605         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1606                         temp & ~(1 << 1));
1607         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1608                         previous_size->size_value);
1609 }
1610
1611
1612 static int intel_820_configure(void)
1613 {
1614         u32 temp;
1615         u8 temp2;
1616         struct aper_size_info_8 *current_size;
1617
1618         current_size = A_SIZE_8(agp_bridge->current_size);
1619
1620         /* aperture size */
1621         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1622
1623         /* address to map to */
1624         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1625         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1626
1627         /* attbase - aperture base */
1628         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1629
1630         /* agpctrl */
1631         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1632
1633         /* global enable aperture access */
1634         /* This flag is not accessed through MCHCFG register as in */
1635         /* i850 chipset. */
1636         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1637         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1638         /* clear any possible AGP-related error conditions */
1639         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1640         return 0;
1641 }
1642
1643 static int intel_840_configure(void)
1644 {
1645         u32 temp;
1646         u16 temp2;
1647         struct aper_size_info_8 *current_size;
1648
1649         current_size = A_SIZE_8(agp_bridge->current_size);
1650
1651         /* aperture size */
1652         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1653
1654         /* address to map to */
1655         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1656         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1657
1658         /* attbase - aperture base */
1659         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1660
1661         /* agpctrl */
1662         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1663
1664         /* mcgcfg */
1665         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1666         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1667         /* clear any possible error conditions */
1668         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1669         return 0;
1670 }
1671
1672 static int intel_845_configure(void)
1673 {
1674         u32 temp;
1675         u8 temp2;
1676         struct aper_size_info_8 *current_size;
1677
1678         current_size = A_SIZE_8(agp_bridge->current_size);
1679
1680         /* aperture size */
1681         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1682
1683         if (agp_bridge->apbase_config != 0) {
1684                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1685                                        agp_bridge->apbase_config);
1686         } else {
1687                 /* address to map to */
1688                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1689                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1690                 agp_bridge->apbase_config = temp;
1691         }
1692
1693         /* attbase - aperture base */
1694         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1695
1696         /* agpctrl */
1697         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1698
1699         /* agpm */
1700         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1701         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1702         /* clear any possible error conditions */
1703         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1704
1705         intel_i830_setup_flush();
1706         return 0;
1707 }
1708
1709 static int intel_850_configure(void)
1710 {
1711         u32 temp;
1712         u16 temp2;
1713         struct aper_size_info_8 *current_size;
1714
1715         current_size = A_SIZE_8(agp_bridge->current_size);
1716
1717         /* aperture size */
1718         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1719
1720         /* address to map to */
1721         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1722         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1723
1724         /* attbase - aperture base */
1725         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1726
1727         /* agpctrl */
1728         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1729
1730         /* mcgcfg */
1731         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1732         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1733         /* clear any possible AGP-related error conditions */
1734         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1735         return 0;
1736 }
1737
1738 static int intel_860_configure(void)
1739 {
1740         u32 temp;
1741         u16 temp2;
1742         struct aper_size_info_8 *current_size;
1743
1744         current_size = A_SIZE_8(agp_bridge->current_size);
1745
1746         /* aperture size */
1747         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1748
1749         /* address to map to */
1750         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1751         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1752
1753         /* attbase - aperture base */
1754         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1755
1756         /* agpctrl */
1757         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1758
1759         /* mcgcfg */
1760         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1761         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1762         /* clear any possible AGP-related error conditions */
1763         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1764         return 0;
1765 }
1766
1767 static int intel_830mp_configure(void)
1768 {
1769         u32 temp;
1770         u16 temp2;
1771         struct aper_size_info_8 *current_size;
1772
1773         current_size = A_SIZE_8(agp_bridge->current_size);
1774
1775         /* aperture size */
1776         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1777
1778         /* address to map to */
1779         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1780         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1781
1782         /* attbase - aperture base */
1783         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1784
1785         /* agpctrl */
1786         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1787
1788         /* gmch */
1789         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1790         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1791         /* clear any possible AGP-related error conditions */
1792         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1793         return 0;
1794 }
1795
1796 static int intel_7505_configure(void)
1797 {
1798         u32 temp;
1799         u16 temp2;
1800         struct aper_size_info_8 *current_size;
1801
1802         current_size = A_SIZE_8(agp_bridge->current_size);
1803
1804         /* aperture size */
1805         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1806
1807         /* address to map to */
1808         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1809         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1810
1811         /* attbase - aperture base */
1812         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1813
1814         /* agpctrl */
1815         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1816
1817         /* mchcfg */
1818         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1819         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1820
1821         return 0;
1822 }
1823
1824 /* Setup function */
1825 static const struct gatt_mask intel_generic_masks[] =
1826 {
1827         {.mask = 0x00000017, .type = 0}
1828 };
1829
1830 static const struct aper_size_info_8 intel_815_sizes[2] =
1831 {
1832         {64, 16384, 4, 0},
1833         {32, 8192, 3, 8},
1834 };
1835
1836 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1837 {
1838         {256, 65536, 6, 0},
1839         {128, 32768, 5, 32},
1840         {64, 16384, 4, 48},
1841         {32, 8192, 3, 56},
1842         {16, 4096, 2, 60},
1843         {8, 2048, 1, 62},
1844         {4, 1024, 0, 63}
1845 };
1846
1847 static const struct aper_size_info_16 intel_generic_sizes[7] =
1848 {
1849         {256, 65536, 6, 0},
1850         {128, 32768, 5, 32},
1851         {64, 16384, 4, 48},
1852         {32, 8192, 3, 56},
1853         {16, 4096, 2, 60},
1854         {8, 2048, 1, 62},
1855         {4, 1024, 0, 63}
1856 };
1857
1858 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1859 {
1860         {256, 65536, 6, 0},
1861         {128, 32768, 5, 32},
1862         {64, 16384, 4, 48},
1863         {32, 8192, 3, 56}
1864 };
1865
1866 static const struct agp_bridge_driver intel_generic_driver = {
1867         .owner                  = THIS_MODULE,
1868         .aperture_sizes         = intel_generic_sizes,
1869         .size_type              = U16_APER_SIZE,
1870         .num_aperture_sizes     = 7,
1871         .configure              = intel_configure,
1872         .fetch_size             = intel_fetch_size,
1873         .cleanup                = intel_cleanup,
1874         .tlb_flush              = intel_tlbflush,
1875         .mask_memory            = agp_generic_mask_memory,
1876         .masks                  = intel_generic_masks,
1877         .agp_enable             = agp_generic_enable,
1878         .cache_flush            = global_cache_flush,
1879         .create_gatt_table      = agp_generic_create_gatt_table,
1880         .free_gatt_table        = agp_generic_free_gatt_table,
1881         .insert_memory          = agp_generic_insert_memory,
1882         .remove_memory          = agp_generic_remove_memory,
1883         .alloc_by_type          = agp_generic_alloc_by_type,
1884         .free_by_type           = agp_generic_free_by_type,
1885         .agp_alloc_page         = agp_generic_alloc_page,
1886         .agp_alloc_pages        = agp_generic_alloc_pages,
1887         .agp_destroy_page       = agp_generic_destroy_page,
1888         .agp_destroy_pages      = agp_generic_destroy_pages,
1889         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1890 };
1891
1892 static const struct agp_bridge_driver intel_810_driver = {
1893         .owner                  = THIS_MODULE,
1894         .aperture_sizes         = intel_i810_sizes,
1895         .size_type              = FIXED_APER_SIZE,
1896         .num_aperture_sizes     = 2,
1897         .needs_scratch_page     = true,
1898         .configure              = intel_i810_configure,
1899         .fetch_size             = intel_i810_fetch_size,
1900         .cleanup                = intel_i810_cleanup,
1901         .tlb_flush              = intel_i810_tlbflush,
1902         .mask_memory            = intel_i810_mask_memory,
1903         .masks                  = intel_i810_masks,
1904         .agp_enable             = intel_i810_agp_enable,
1905         .cache_flush            = global_cache_flush,
1906         .create_gatt_table      = agp_generic_create_gatt_table,
1907         .free_gatt_table        = agp_generic_free_gatt_table,
1908         .insert_memory          = intel_i810_insert_entries,
1909         .remove_memory          = intel_i810_remove_entries,
1910         .alloc_by_type          = intel_i810_alloc_by_type,
1911         .free_by_type           = intel_i810_free_by_type,
1912         .agp_alloc_page         = agp_generic_alloc_page,
1913         .agp_alloc_pages        = agp_generic_alloc_pages,
1914         .agp_destroy_page       = agp_generic_destroy_page,
1915         .agp_destroy_pages      = agp_generic_destroy_pages,
1916         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1917 };
1918
1919 static const struct agp_bridge_driver intel_815_driver = {
1920         .owner                  = THIS_MODULE,
1921         .aperture_sizes         = intel_815_sizes,
1922         .size_type              = U8_APER_SIZE,
1923         .num_aperture_sizes     = 2,
1924         .configure              = intel_815_configure,
1925         .fetch_size             = intel_815_fetch_size,
1926         .cleanup                = intel_8xx_cleanup,
1927         .tlb_flush              = intel_8xx_tlbflush,
1928         .mask_memory            = agp_generic_mask_memory,
1929         .masks                  = intel_generic_masks,
1930         .agp_enable             = agp_generic_enable,
1931         .cache_flush            = global_cache_flush,
1932         .create_gatt_table      = agp_generic_create_gatt_table,
1933         .free_gatt_table        = agp_generic_free_gatt_table,
1934         .insert_memory          = agp_generic_insert_memory,
1935         .remove_memory          = agp_generic_remove_memory,
1936         .alloc_by_type          = agp_generic_alloc_by_type,
1937         .free_by_type           = agp_generic_free_by_type,
1938         .agp_alloc_page         = agp_generic_alloc_page,
1939         .agp_alloc_pages        = agp_generic_alloc_pages,
1940         .agp_destroy_page       = agp_generic_destroy_page,
1941         .agp_destroy_pages      = agp_generic_destroy_pages,
1942         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1943 };
1944
1945 static const struct agp_bridge_driver intel_830_driver = {
1946         .owner                  = THIS_MODULE,
1947         .aperture_sizes         = intel_i830_sizes,
1948         .size_type              = FIXED_APER_SIZE,
1949         .num_aperture_sizes     = 4,
1950         .needs_scratch_page     = true,
1951         .configure              = intel_i830_configure,
1952         .fetch_size             = intel_i830_fetch_size,
1953         .cleanup                = intel_i830_cleanup,
1954         .tlb_flush              = intel_i810_tlbflush,
1955         .mask_memory            = intel_i810_mask_memory,
1956         .masks                  = intel_i810_masks,
1957         .agp_enable             = intel_i810_agp_enable,
1958         .cache_flush            = global_cache_flush,
1959         .create_gatt_table      = intel_i830_create_gatt_table,
1960         .free_gatt_table        = intel_i830_free_gatt_table,
1961         .insert_memory          = intel_i830_insert_entries,
1962         .remove_memory          = intel_i830_remove_entries,
1963         .alloc_by_type          = intel_i830_alloc_by_type,
1964         .free_by_type           = intel_i810_free_by_type,
1965         .agp_alloc_page         = agp_generic_alloc_page,
1966         .agp_alloc_pages        = agp_generic_alloc_pages,
1967         .agp_destroy_page       = agp_generic_destroy_page,
1968         .agp_destroy_pages      = agp_generic_destroy_pages,
1969         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1970         .chipset_flush          = intel_i830_chipset_flush,
1971 };
1972
1973 static const struct agp_bridge_driver intel_820_driver = {
1974         .owner                  = THIS_MODULE,
1975         .aperture_sizes         = intel_8xx_sizes,
1976         .size_type              = U8_APER_SIZE,
1977         .num_aperture_sizes     = 7,
1978         .configure              = intel_820_configure,
1979         .fetch_size             = intel_8xx_fetch_size,
1980         .cleanup                = intel_820_cleanup,
1981         .tlb_flush              = intel_820_tlbflush,
1982         .mask_memory            = agp_generic_mask_memory,
1983         .masks                  = intel_generic_masks,
1984         .agp_enable             = agp_generic_enable,
1985         .cache_flush            = global_cache_flush,
1986         .create_gatt_table      = agp_generic_create_gatt_table,
1987         .free_gatt_table        = agp_generic_free_gatt_table,
1988         .insert_memory          = agp_generic_insert_memory,
1989         .remove_memory          = agp_generic_remove_memory,
1990         .alloc_by_type          = agp_generic_alloc_by_type,
1991         .free_by_type           = agp_generic_free_by_type,
1992         .agp_alloc_page         = agp_generic_alloc_page,
1993         .agp_alloc_pages        = agp_generic_alloc_pages,
1994         .agp_destroy_page       = agp_generic_destroy_page,
1995         .agp_destroy_pages      = agp_generic_destroy_pages,
1996         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1997 };
1998
1999 static const struct agp_bridge_driver intel_830mp_driver = {
2000         .owner                  = THIS_MODULE,
2001         .aperture_sizes         = intel_830mp_sizes,
2002         .size_type              = U8_APER_SIZE,
2003         .num_aperture_sizes     = 4,
2004         .configure              = intel_830mp_configure,
2005         .fetch_size             = intel_8xx_fetch_size,
2006         .cleanup                = intel_8xx_cleanup,
2007         .tlb_flush              = intel_8xx_tlbflush,
2008         .mask_memory            = agp_generic_mask_memory,
2009         .masks                  = intel_generic_masks,
2010         .agp_enable             = agp_generic_enable,
2011         .cache_flush            = global_cache_flush,
2012         .create_gatt_table      = agp_generic_create_gatt_table,
2013         .free_gatt_table        = agp_generic_free_gatt_table,
2014         .insert_memory          = agp_generic_insert_memory,
2015         .remove_memory          = agp_generic_remove_memory,
2016         .alloc_by_type          = agp_generic_alloc_by_type,
2017         .free_by_type           = agp_generic_free_by_type,
2018         .agp_alloc_page         = agp_generic_alloc_page,
2019         .agp_alloc_pages        = agp_generic_alloc_pages,
2020         .agp_destroy_page       = agp_generic_destroy_page,
2021         .agp_destroy_pages      = agp_generic_destroy_pages,
2022         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2023 };
2024
2025 static const struct agp_bridge_driver intel_840_driver = {
2026         .owner                  = THIS_MODULE,
2027         .aperture_sizes         = intel_8xx_sizes,
2028         .size_type              = U8_APER_SIZE,
2029         .num_aperture_sizes     = 7,
2030         .configure              = intel_840_configure,
2031         .fetch_size             = intel_8xx_fetch_size,
2032         .cleanup                = intel_8xx_cleanup,
2033         .tlb_flush              = intel_8xx_tlbflush,
2034         .mask_memory            = agp_generic_mask_memory,
2035         .masks                  = intel_generic_masks,
2036         .agp_enable             = agp_generic_enable,
2037         .cache_flush            = global_cache_flush,
2038         .create_gatt_table      = agp_generic_create_gatt_table,
2039         .free_gatt_table        = agp_generic_free_gatt_table,
2040         .insert_memory          = agp_generic_insert_memory,
2041         .remove_memory          = agp_generic_remove_memory,
2042         .alloc_by_type          = agp_generic_alloc_by_type,
2043         .free_by_type           = agp_generic_free_by_type,
2044         .agp_alloc_page         = agp_generic_alloc_page,
2045         .agp_alloc_pages        = agp_generic_alloc_pages,
2046         .agp_destroy_page       = agp_generic_destroy_page,
2047         .agp_destroy_pages      = agp_generic_destroy_pages,
2048         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2049 };
2050
2051 static const struct agp_bridge_driver intel_845_driver = {
2052         .owner                  = THIS_MODULE,
2053         .aperture_sizes         = intel_8xx_sizes,
2054         .size_type              = U8_APER_SIZE,
2055         .num_aperture_sizes     = 7,
2056         .configure              = intel_845_configure,
2057         .fetch_size             = intel_8xx_fetch_size,
2058         .cleanup                = intel_8xx_cleanup,
2059         .tlb_flush              = intel_8xx_tlbflush,
2060         .mask_memory            = agp_generic_mask_memory,
2061         .masks                  = intel_generic_masks,
2062         .agp_enable             = agp_generic_enable,
2063         .cache_flush            = global_cache_flush,
2064         .create_gatt_table      = agp_generic_create_gatt_table,
2065         .free_gatt_table        = agp_generic_free_gatt_table,
2066         .insert_memory          = agp_generic_insert_memory,
2067         .remove_memory          = agp_generic_remove_memory,
2068         .alloc_by_type          = agp_generic_alloc_by_type,
2069         .free_by_type           = agp_generic_free_by_type,
2070         .agp_alloc_page         = agp_generic_alloc_page,
2071         .agp_alloc_pages        = agp_generic_alloc_pages,
2072         .agp_destroy_page       = agp_generic_destroy_page,
2073         .agp_destroy_pages      = agp_generic_destroy_pages,
2074         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2075         .chipset_flush          = intel_i830_chipset_flush,
2076 };
2077
2078 static const struct agp_bridge_driver intel_850_driver = {
2079         .owner                  = THIS_MODULE,
2080         .aperture_sizes         = intel_8xx_sizes,
2081         .size_type              = U8_APER_SIZE,
2082         .num_aperture_sizes     = 7,
2083         .configure              = intel_850_configure,
2084         .fetch_size             = intel_8xx_fetch_size,
2085         .cleanup                = intel_8xx_cleanup,
2086         .tlb_flush              = intel_8xx_tlbflush,
2087         .mask_memory            = agp_generic_mask_memory,
2088         .masks                  = intel_generic_masks,
2089         .agp_enable             = agp_generic_enable,
2090         .cache_flush            = global_cache_flush,
2091         .create_gatt_table      = agp_generic_create_gatt_table,
2092         .free_gatt_table        = agp_generic_free_gatt_table,
2093         .insert_memory          = agp_generic_insert_memory,
2094         .remove_memory          = agp_generic_remove_memory,
2095         .alloc_by_type          = agp_generic_alloc_by_type,
2096         .free_by_type           = agp_generic_free_by_type,
2097         .agp_alloc_page         = agp_generic_alloc_page,
2098         .agp_alloc_pages        = agp_generic_alloc_pages,
2099         .agp_destroy_page       = agp_generic_destroy_page,
2100         .agp_destroy_pages      = agp_generic_destroy_pages,
2101         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2102 };
2103
2104 static const struct agp_bridge_driver intel_860_driver = {
2105         .owner                  = THIS_MODULE,
2106         .aperture_sizes         = intel_8xx_sizes,
2107         .size_type              = U8_APER_SIZE,
2108         .num_aperture_sizes     = 7,
2109         .configure              = intel_860_configure,
2110         .fetch_size             = intel_8xx_fetch_size,
2111         .cleanup                = intel_8xx_cleanup,
2112         .tlb_flush              = intel_8xx_tlbflush,
2113         .mask_memory            = agp_generic_mask_memory,
2114         .masks                  = intel_generic_masks,
2115         .agp_enable             = agp_generic_enable,
2116         .cache_flush            = global_cache_flush,
2117         .create_gatt_table      = agp_generic_create_gatt_table,
2118         .free_gatt_table        = agp_generic_free_gatt_table,
2119         .insert_memory          = agp_generic_insert_memory,
2120         .remove_memory          = agp_generic_remove_memory,
2121         .alloc_by_type          = agp_generic_alloc_by_type,
2122         .free_by_type           = agp_generic_free_by_type,
2123         .agp_alloc_page         = agp_generic_alloc_page,
2124         .agp_alloc_pages        = agp_generic_alloc_pages,
2125         .agp_destroy_page       = agp_generic_destroy_page,
2126         .agp_destroy_pages      = agp_generic_destroy_pages,
2127         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2128 };
2129
2130 static const struct agp_bridge_driver intel_915_driver = {
2131         .owner                  = THIS_MODULE,
2132         .aperture_sizes         = intel_i830_sizes,
2133         .size_type              = FIXED_APER_SIZE,
2134         .num_aperture_sizes     = 4,
2135         .needs_scratch_page     = true,
2136         .configure              = intel_i915_configure,
2137         .fetch_size             = intel_i9xx_fetch_size,
2138         .cleanup                = intel_i915_cleanup,
2139         .tlb_flush              = intel_i810_tlbflush,
2140         .mask_memory            = intel_i810_mask_memory,
2141         .masks                  = intel_i810_masks,
2142         .agp_enable             = intel_i810_agp_enable,
2143         .cache_flush            = global_cache_flush,
2144         .create_gatt_table      = intel_i915_create_gatt_table,
2145         .free_gatt_table        = intel_i830_free_gatt_table,
2146         .insert_memory          = intel_i915_insert_entries,
2147         .remove_memory          = intel_i915_remove_entries,
2148         .alloc_by_type          = intel_i830_alloc_by_type,
2149         .free_by_type           = intel_i810_free_by_type,
2150         .agp_alloc_page         = agp_generic_alloc_page,
2151         .agp_alloc_pages        = agp_generic_alloc_pages,
2152         .agp_destroy_page       = agp_generic_destroy_page,
2153         .agp_destroy_pages      = agp_generic_destroy_pages,
2154         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2155         .chipset_flush          = intel_i915_chipset_flush,
2156 #ifdef USE_PCI_DMA_API
2157         .agp_map_page           = intel_agp_map_page,
2158         .agp_unmap_page         = intel_agp_unmap_page,
2159         .agp_map_memory         = intel_agp_map_memory,
2160         .agp_unmap_memory       = intel_agp_unmap_memory,
2161 #endif
2162 };
2163
2164 static const struct agp_bridge_driver intel_i965_driver = {
2165         .owner                  = THIS_MODULE,
2166         .aperture_sizes         = intel_i830_sizes,
2167         .size_type              = FIXED_APER_SIZE,
2168         .num_aperture_sizes     = 4,
2169         .needs_scratch_page     = true,
2170         .configure              = intel_i915_configure,
2171         .fetch_size             = intel_i9xx_fetch_size,
2172         .cleanup                = intel_i915_cleanup,
2173         .tlb_flush              = intel_i810_tlbflush,
2174         .mask_memory            = intel_i965_mask_memory,
2175         .masks                  = intel_i810_masks,
2176         .agp_enable             = intel_i810_agp_enable,
2177         .cache_flush            = global_cache_flush,
2178         .create_gatt_table      = intel_i965_create_gatt_table,
2179         .free_gatt_table        = intel_i830_free_gatt_table,
2180         .insert_memory          = intel_i915_insert_entries,
2181         .remove_memory          = intel_i915_remove_entries,
2182         .alloc_by_type          = intel_i830_alloc_by_type,
2183         .free_by_type           = intel_i810_free_by_type,
2184         .agp_alloc_page         = agp_generic_alloc_page,
2185         .agp_alloc_pages        = agp_generic_alloc_pages,
2186         .agp_destroy_page       = agp_generic_destroy_page,
2187         .agp_destroy_pages      = agp_generic_destroy_pages,
2188         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2189         .chipset_flush          = intel_i915_chipset_flush,
2190 #ifdef USE_PCI_DMA_API
2191         .agp_map_page           = intel_agp_map_page,
2192         .agp_unmap_page         = intel_agp_unmap_page,
2193         .agp_map_memory         = intel_agp_map_memory,
2194         .agp_unmap_memory       = intel_agp_unmap_memory,
2195 #endif
2196 };
2197
2198 static const struct agp_bridge_driver intel_7505_driver = {
2199         .owner                  = THIS_MODULE,
2200         .aperture_sizes         = intel_8xx_sizes,
2201         .size_type              = U8_APER_SIZE,
2202         .num_aperture_sizes     = 7,
2203         .configure              = intel_7505_configure,
2204         .fetch_size             = intel_8xx_fetch_size,
2205         .cleanup                = intel_8xx_cleanup,
2206         .tlb_flush              = intel_8xx_tlbflush,
2207         .mask_memory            = agp_generic_mask_memory,
2208         .masks                  = intel_generic_masks,
2209         .agp_enable             = agp_generic_enable,
2210         .cache_flush            = global_cache_flush,
2211         .create_gatt_table      = agp_generic_create_gatt_table,
2212         .free_gatt_table        = agp_generic_free_gatt_table,
2213         .insert_memory          = agp_generic_insert_memory,
2214         .remove_memory          = agp_generic_remove_memory,
2215         .alloc_by_type          = agp_generic_alloc_by_type,
2216         .free_by_type           = agp_generic_free_by_type,
2217         .agp_alloc_page         = agp_generic_alloc_page,
2218         .agp_alloc_pages        = agp_generic_alloc_pages,
2219         .agp_destroy_page       = agp_generic_destroy_page,
2220         .agp_destroy_pages      = agp_generic_destroy_pages,
2221         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2222 };
2223
2224 static const struct agp_bridge_driver intel_g33_driver = {
2225         .owner                  = THIS_MODULE,
2226         .aperture_sizes         = intel_i830_sizes,
2227         .size_type              = FIXED_APER_SIZE,
2228         .num_aperture_sizes     = 4,
2229         .needs_scratch_page     = true,
2230         .configure              = intel_i915_configure,
2231         .fetch_size             = intel_i9xx_fetch_size,
2232         .cleanup                = intel_i915_cleanup,
2233         .tlb_flush              = intel_i810_tlbflush,
2234         .mask_memory            = intel_i965_mask_memory,
2235         .masks                  = intel_i810_masks,
2236         .agp_enable             = intel_i810_agp_enable,
2237         .cache_flush            = global_cache_flush,
2238         .create_gatt_table      = intel_i915_create_gatt_table,
2239         .free_gatt_table        = intel_i830_free_gatt_table,
2240         .insert_memory          = intel_i915_insert_entries,
2241         .remove_memory          = intel_i915_remove_entries,
2242         .alloc_by_type          = intel_i830_alloc_by_type,
2243         .free_by_type           = intel_i810_free_by_type,
2244         .agp_alloc_page         = agp_generic_alloc_page,
2245         .agp_alloc_pages        = agp_generic_alloc_pages,
2246         .agp_destroy_page       = agp_generic_destroy_page,
2247         .agp_destroy_pages      = agp_generic_destroy_pages,
2248         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2249         .chipset_flush          = intel_i915_chipset_flush,
2250 #ifdef USE_PCI_DMA_API
2251         .agp_map_page           = intel_agp_map_page,
2252         .agp_unmap_page         = intel_agp_unmap_page,
2253         .agp_map_memory         = intel_agp_map_memory,
2254         .agp_unmap_memory       = intel_agp_unmap_memory,
2255 #endif
2256 };
2257
2258 static int find_gmch(u16 device)
2259 {
2260         struct pci_dev *gmch_device;
2261
2262         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2263         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2264                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
2265                                              device, gmch_device);
2266         }
2267
2268         if (!gmch_device)
2269                 return 0;
2270
2271         intel_private.pcidev = gmch_device;
2272         return 1;
2273 }
2274
2275 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
2276  * driver and gmch_driver must be non-null, and find_gmch will determine
2277  * which one should be used if a gmch_chip_id is present.
2278  */
2279 static const struct intel_driver_description {
2280         unsigned int chip_id;
2281         unsigned int gmch_chip_id;
2282         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2283         char *name;
2284         const struct agp_bridge_driver *driver;
2285         const struct agp_bridge_driver *gmch_driver;
2286 } intel_agp_chipsets[] = {
2287         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2288         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2289         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2290         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2291                 NULL, &intel_810_driver },
2292         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2293                 NULL, &intel_810_driver },
2294         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2295                 NULL, &intel_810_driver },
2296         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2297                 &intel_815_driver, &intel_810_driver },
2298         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2299         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2300         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2301                 &intel_830mp_driver, &intel_830_driver },
2302         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2303         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2304         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2305                 &intel_845_driver, &intel_830_driver },
2306         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2307         { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
2308                 &intel_845_driver, &intel_830_driver },
2309         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2310         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2311                 &intel_845_driver, &intel_830_driver },
2312         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2313         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2314                 &intel_845_driver, &intel_830_driver },
2315         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2316         { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2317                 NULL, &intel_915_driver },
2318         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2319                 NULL, &intel_915_driver },
2320         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2321                 NULL, &intel_915_driver },
2322         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2323                 NULL, &intel_915_driver },
2324         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2325                 NULL, &intel_915_driver },
2326         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2327                 NULL, &intel_915_driver },
2328         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2329                 NULL, &intel_i965_driver },
2330         { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2331                 NULL, &intel_i965_driver },
2332         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2333                 NULL, &intel_i965_driver },
2334         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2335                 NULL, &intel_i965_driver },
2336         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2337                 NULL, &intel_i965_driver },
2338         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2339                 NULL, &intel_i965_driver },
2340         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2341         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2342         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2343                 NULL, &intel_g33_driver },
2344         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2345                 NULL, &intel_g33_driver },
2346         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2347                 NULL, &intel_g33_driver },
2348         { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, 0, "Pineview",
2349                 NULL, &intel_g33_driver },
2350         { PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, 0, "Pineview",
2351                 NULL, &intel_g33_driver },
2352         { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2353             "GM45", NULL, &intel_i965_driver },
2354         { PCI_DEVICE_ID_INTEL_EAGLELAKE_HB, PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, 0,
2355             "Eaglelake", NULL, &intel_i965_driver },
2356         { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2357             "Q45/Q43", NULL, &intel_i965_driver },
2358         { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2359             "G45/G43", NULL, &intel_i965_driver },
2360         { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0,
2361             "B43", NULL, &intel_i965_driver },
2362         { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2363             "G41", NULL, &intel_i965_driver },
2364         { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 0,
2365             "Ironlake/D", NULL, &intel_i965_driver },
2366         { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2367             "Ironlake/M", NULL, &intel_i965_driver },
2368         { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2369             "Ironlake/MA", NULL, &intel_i965_driver },
2370         { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2371             "Ironlake/MC2", NULL, &intel_i965_driver },
2372         { 0, 0, 0, NULL, NULL, NULL }
2373 };
2374
2375 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2376                                      const struct pci_device_id *ent)
2377 {
2378         struct agp_bridge_data *bridge;
2379         u8 cap_ptr = 0;
2380         struct resource *r;
2381         int i;
2382
2383         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2384
2385         bridge = agp_alloc_bridge();
2386         if (!bridge)
2387                 return -ENOMEM;
2388
2389         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2390                 /* In case that multiple models of gfx chip may
2391                    stand on same host bridge type, this can be
2392                    sure we detect the right IGD. */
2393                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2394                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2395                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2396                                 bridge->driver =
2397                                         intel_agp_chipsets[i].gmch_driver;
2398                                 break;
2399                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2400                                 continue;
2401                         } else {
2402                                 bridge->driver = intel_agp_chipsets[i].driver;
2403                                 break;
2404                         }
2405                 }
2406         }
2407
2408         if (intel_agp_chipsets[i].name == NULL) {
2409                 if (cap_ptr)
2410                         dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2411                                  pdev->vendor, pdev->device);
2412                 agp_put_bridge(bridge);
2413                 return -ENODEV;
2414         }
2415
2416         if (bridge->driver == NULL) {
2417                 /* bridge has no AGP and no IGD detected */
2418                 if (cap_ptr)
2419                         dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2420                                  intel_agp_chipsets[i].gmch_chip_id);
2421                 agp_put_bridge(bridge);
2422                 return -ENODEV;
2423         }
2424
2425         bridge->dev = pdev;
2426         bridge->capndx = cap_ptr;
2427         bridge->dev_private_data = &intel_private;
2428
2429         dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
2430
2431         /*
2432         * The following fixes the case where the BIOS has "forgotten" to
2433         * provide an address range for the GART.
2434         * 20030610 - hamish@zot.org
2435         */
2436         r = &pdev->resource[0];
2437         if (!r->start && r->end) {
2438                 if (pci_assign_resource(pdev, 0)) {
2439                         dev_err(&pdev->dev, "can't assign resource 0\n");
2440                         agp_put_bridge(bridge);
2441                         return -ENODEV;
2442                 }
2443         }
2444
2445         /*
2446         * If the device has not been properly setup, the following will catch
2447         * the problem and should stop the system from crashing.
2448         * 20030610 - hamish@zot.org
2449         */
2450         if (pci_enable_device(pdev)) {
2451                 dev_err(&pdev->dev, "can't enable PCI device\n");
2452                 agp_put_bridge(bridge);
2453                 return -ENODEV;
2454         }
2455
2456         /* Fill in the mode register */
2457         if (cap_ptr) {
2458                 pci_read_config_dword(pdev,
2459                                 bridge->capndx+PCI_AGP_STATUS,
2460                                 &bridge->mode);
2461         }
2462
2463         if (bridge->driver->mask_memory == intel_i965_mask_memory)
2464                 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36)))
2465                         dev_err(&intel_private.pcidev->dev,
2466                                 "set gfx device dma mask 36bit failed!\n");
2467
2468         pci_set_drvdata(pdev, bridge);
2469         return agp_add_bridge(bridge);
2470 }
2471
2472 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2473 {
2474         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2475
2476         agp_remove_bridge(bridge);
2477
2478         if (intel_private.pcidev)
2479                 pci_dev_put(intel_private.pcidev);
2480
2481         agp_put_bridge(bridge);
2482 }
2483
2484 #ifdef CONFIG_PM
2485 static int agp_intel_resume(struct pci_dev *pdev)
2486 {
2487         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2488         int ret_val;
2489
2490         if (bridge->driver == &intel_generic_driver)
2491                 intel_configure();
2492         else if (bridge->driver == &intel_850_driver)
2493                 intel_850_configure();
2494         else if (bridge->driver == &intel_845_driver)
2495                 intel_845_configure();
2496         else if (bridge->driver == &intel_830mp_driver)
2497                 intel_830mp_configure();
2498         else if (bridge->driver == &intel_915_driver)
2499                 intel_i915_configure();
2500         else if (bridge->driver == &intel_830_driver)
2501                 intel_i830_configure();
2502         else if (bridge->driver == &intel_810_driver)
2503                 intel_i810_configure();
2504         else if (bridge->driver == &intel_i965_driver)
2505                 intel_i915_configure();
2506
2507         ret_val = agp_rebind_memory();
2508         if (ret_val != 0)
2509                 return ret_val;
2510
2511         return 0;
2512 }
2513 #endif
2514
2515 static struct pci_device_id agp_intel_pci_table[] = {
2516 #define ID(x)                                           \
2517         {                                               \
2518         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2519         .class_mask     = ~0,                           \
2520         .vendor         = PCI_VENDOR_ID_INTEL,          \
2521         .device         = x,                            \
2522         .subvendor      = PCI_ANY_ID,                   \
2523         .subdevice      = PCI_ANY_ID,                   \
2524         }
2525         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2526         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2527         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2528         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2529         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2530         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2531         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2532         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2533         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2534         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2535         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2536         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2537         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2538         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2539         ID(PCI_DEVICE_ID_INTEL_82854_HB),
2540         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2541         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2542         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2543         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2544         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2545         ID(PCI_DEVICE_ID_INTEL_7505_0),
2546         ID(PCI_DEVICE_ID_INTEL_7205_0),
2547         ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2548         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2549         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2550         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2551         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2552         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2553         ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB),
2554         ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB),
2555         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2556         ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2557         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2558         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2559         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2560         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2561         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2562         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2563         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2564         ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2565         ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB),
2566         ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2567         ID(PCI_DEVICE_ID_INTEL_G45_HB),
2568         ID(PCI_DEVICE_ID_INTEL_G41_HB),
2569         ID(PCI_DEVICE_ID_INTEL_B43_HB),
2570         ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
2571         ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
2572         ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
2573         ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
2574         { }
2575 };
2576
2577 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2578
2579 static struct pci_driver agp_intel_pci_driver = {
2580         .name           = "agpgart-intel",
2581         .id_table       = agp_intel_pci_table,
2582         .probe          = agp_intel_probe,
2583         .remove         = __devexit_p(agp_intel_remove),
2584 #ifdef CONFIG_PM
2585         .resume         = agp_intel_resume,
2586 #endif
2587 };
2588
2589 static int __init agp_intel_init(void)
2590 {
2591         if (agp_off)
2592                 return -EINVAL;
2593         return pci_register_driver(&agp_intel_pci_driver);
2594 }
2595
2596 static void __exit agp_intel_cleanup(void)
2597 {
2598         pci_unregister_driver(&agp_intel_pci_driver);
2599 }
2600
2601 module_init(agp_intel_init);
2602 module_exit(agp_intel_cleanup);
2603
2604 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2605 MODULE_LICENSE("GPL and additional rights");