drivers/char/agp/i460-agp.c

   1 /*
   2  * For documentation on the i460 AGP interface, see Chapter 7 (AGP Subsystem) of
   3  * the "Intel 460GTX Chipset Software Developer's Manual":
   4  * http://developer.intel.com/design/itanium/downloads/24870401s.htm
   5  */
   6 /*
   7  * 460GX support by Chris Ahna <christopher.j.ahna@intel.com>
   8  * Clean up & simplification by David Mosberger-Tang <davidm@hpl.hp.com>
   9  */
  10 #include <linux/module.h>
  11 #include <linux/pci.h>
  12 #include <linux/init.h>
  13 #include <linux/string.h>
  14 #include <linux/slab.h>
  15 #include <linux/agp_backend.h>
  16
  17 #include "agp.h"
  18
  19 #define INTEL_I460_BAPBASE              0x98
  20 #define INTEL_I460_GXBCTL               0xa0
  21 #define INTEL_I460_AGPSIZ               0xa2
  22 #define INTEL_I460_ATTBASE              0xfe200000
  23 #define INTEL_I460_GATT_VALID           (1UL << 24)
  24 #define INTEL_I460_GATT_COHERENT        (1UL << 25)
  25
  26 /*
  27  * The i460 can operate with large (4MB) pages, but there is no sane way to support this
  28  * within the current kernel/DRM environment, so we disable the relevant code for now.
  29  * See also comments in ia64_alloc_page()...
  30  */
  31 #define I460_LARGE_IO_PAGES             0
  32
  33 #if I460_LARGE_IO_PAGES
  34 # define I460_IO_PAGE_SHIFT             i460.io_page_shift
  35 #else
  36 # define I460_IO_PAGE_SHIFT             12
  37 #endif
  38
  39 #define I460_IOPAGES_PER_KPAGE          (PAGE_SIZE >> I460_IO_PAGE_SHIFT)
  40 #define I460_KPAGES_PER_IOPAGE          (1 << (I460_IO_PAGE_SHIFT - PAGE_SHIFT))
  41 #define I460_SRAM_IO_DISABLE            (1 << 4)
  42 #define I460_BAPBASE_ENABLE             (1 << 3)
  43 #define I460_AGPSIZ_MASK                0x7
  44 #define I460_4M_PS                      (1 << 1)
  45
  46 /* Control bits for Out-Of-GART coherency and Burst Write Combining */
  47 #define I460_GXBCTL_OOG         (1UL << 0)
  48 #define I460_GXBCTL_BWC         (1UL << 2)
  49
  50 /*
  51  * gatt_table entries are 32-bits wide on the i460; the generic code ought to declare the
  52  * gatt_table and gatt_table_real pointers a "void *"...
  53  */
  54 #define RD_GATT(index)          readl((u32 *) i460.gatt + (index))
  55 #define WR_GATT(index, val)     writel((val), (u32 *) i460.gatt + (index))
  56 /*
  57  * The 460 spec says we have to read the last location written to make sure that all
  58  * writes have taken effect
  59  */
  60 #define WR_FLUSH_GATT(index)    RD_GATT(index)
  61
  62 #define log2(x)                 ffz(~(x))
  63
  64 static struct {
  65         void *gatt;                             /* ioremap'd GATT area */
  66
  67         /* i460 supports multiple GART page sizes, so GART pageshift is dynamic: */
  68         u8 io_page_shift;
  69
  70         /* BIOS configures chipset to one of 2 possible apbase values: */
  71         u8 dynamic_apbase;
  72
  73         /* structure for tracking partial use of 4MB GART pages: */
  74         struct lp_desc {
  75                 unsigned long *alloced_map;     /* bitmap of kernel-pages in use */
  76                 int refcount;                   /* number of kernel pages using the large page */
  77                 u64 paddr;                      /* physical address of large page */
  78         } *lp_desc;
  79 } i460;
  80
  81 static struct aper_size_info_8 i460_sizes[3] =
  82 {
  83         /*
  84          * The 32GB aperture is only available with a 4M GART page size.  Due to the
  85          * dynamic GART page size, we can't figure out page_order or num_entries until
  86          * runtime.
  87          */
  88         {32768, 0, 0, 4},
  89         {1024, 0, 0, 2},
  90         {256, 0, 0, 1}
  91 };
  92
  93 static struct gatt_mask i460_masks[] =
  94 {
  95         {
  96           .mask = INTEL_I460_GATT_VALID | INTEL_I460_GATT_COHERENT,
  97           .type = 0
  98         }
  99 };
 100
 101 static int i460_fetch_size (void)
 102 {
 103         int i;
 104         u8 temp;
 105         struct aper_size_info_8 *values;
 106
 107         /* Determine the GART page size */
 108         pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &temp);
 109         i460.io_page_shift = (temp & I460_4M_PS) ? 22 : 12;
 110         pr_debug("i460_fetch_size: io_page_shift=%d\n", i460.io_page_shift);
 111
 112         if (i460.io_page_shift != I460_IO_PAGE_SHIFT) {
 113                 printk(KERN_ERR PFX
 114                        "I/O (GART) page-size %ZuKB doesn't match expected size %ZuKB\n",
 115                        1UL << (i460.io_page_shift - 10), 1UL << (I460_IO_PAGE_SHIFT));
 116                 return 0;
 117         }
 118
 119         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
 120
 121         pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
 122
 123         /* Exit now if the IO drivers for the GART SRAMS are turned off */
 124         if (temp & I460_SRAM_IO_DISABLE) {
 125                 printk(KERN_ERR PFX "GART SRAMS disabled on 460GX chipset\n");
 126                 printk(KERN_ERR PFX "AGPGART operation not possible\n");
 127                 return 0;
 128         }
 129
 130         /* Make sure we don't try to create an 2 ^ 23 entry GATT */
 131         if ((i460.io_page_shift == 0) && ((temp & I460_AGPSIZ_MASK) == 4)) {
 132                 printk(KERN_ERR PFX "We can't have a 32GB aperture with 4KB GART pages\n");
 133                 return 0;
 134         }
 135
 136         /* Determine the proper APBASE register */
 137         if (temp & I460_BAPBASE_ENABLE)
 138                 i460.dynamic_apbase = INTEL_I460_BAPBASE;
 139         else
 140                 i460.dynamic_apbase = AGP_APBASE;
 141
 142         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 143                 /*
 144                  * Dynamically calculate the proper num_entries and page_order values for
 145                  * the define aperture sizes. Take care not to shift off the end of
 146                  * values[i].size.
 147                  */
 148                 values[i].num_entries = (values[i].size << 8) >> (I460_IO_PAGE_SHIFT - 12);
 149                 values[i].page_order = log2((sizeof(u32)*values[i].num_entries) >> PAGE_SHIFT);
 150         }
 151
 152         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 153                 /* Neglect control bits when matching up size_value */
 154                 if ((temp & I460_AGPSIZ_MASK) == values[i].size_value) {
 155                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
 156                         agp_bridge->aperture_size_idx = i;
 157                         return values[i].size;
 158                 }
 159         }
 160
 161         return 0;
 162 }
 163
 164 /* There isn't anything to do here since 460 has no GART TLB. */
 165 static void i460_tlb_flush (struct agp_memory *mem)
 166 {
 167         return;
 168 }
 169
 170 /*
 171  * This utility function is needed to prevent corruption of the control bits
 172  * which are stored along with the aperture size in 460's AGPSIZ register
 173  */
 174 static void i460_write_agpsiz (u8 size_value)
 175 {
 176         u8 temp;
 177
 178         pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
 179         pci_write_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ,
 180                               ((temp & ~I460_AGPSIZ_MASK) | size_value));
 181 }
 182
 183 static void i460_cleanup (void)
 184 {
 185         struct aper_size_info_8 *previous_size;
 186
 187         previous_size = A_SIZE_8(agp_bridge->previous_size);
 188         i460_write_agpsiz(previous_size->size_value);
 189
 190         if (I460_IO_PAGE_SHIFT > PAGE_SHIFT)
 191                 kfree(i460.lp_desc);
 192 }
 193
 194 static int i460_configure (void)
 195 {
 196         union {
 197                 u32 small[2];
 198                 u64 large;
 199         } temp;
 200         size_t size;
 201         u8 scratch;
 202         struct aper_size_info_8 *current_size;
 203
 204         temp.large = 0;
 205
 206         current_size = A_SIZE_8(agp_bridge->current_size);
 207         i460_write_agpsiz(current_size->size_value);
 208
 209         /*
 210          * Do the necessary rigmarole to read all eight bytes of APBASE.
 211          * This has to be done since the AGP aperture can be above 4GB on
 212          * 460 based systems.
 213          */
 214         pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase, &(temp.small[0]));
 215         pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase + 4, &(temp.small[1]));
 216
 217         /* Clear BAR control bits */
 218         agp_bridge->gart_bus_addr = temp.large & ~((1UL << 3) - 1);
 219
 220         pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &scratch);
 221         pci_write_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL,
 222                               (scratch & 0x02) | I460_GXBCTL_OOG | I460_GXBCTL_BWC);
 223
 224         /*
 225          * Initialize partial allocation trackers if a GART page is bigger than a kernel
 226          * page.
 227          */
 228         if (I460_IO_PAGE_SHIFT > PAGE_SHIFT) {
 229                 size = current_size->num_entries * sizeof(i460.lp_desc[0]);
 230                 i460.lp_desc = kzalloc(size, GFP_KERNEL);
 231                 if (!i460.lp_desc)
 232                         return -ENOMEM;
 233         }
 234         return 0;
 235 }
 236
 237 static int i460_create_gatt_table (struct agp_bridge_data *bridge)
 238 {
 239         int page_order, num_entries, i;
 240         void *temp;
 241
 242         /*
 243          * Load up the fixed address of the GART SRAMS which hold our GATT table.
 244          */
 245         temp = agp_bridge->current_size;
 246         page_order = A_SIZE_8(temp)->page_order;
 247         num_entries = A_SIZE_8(temp)->num_entries;
 248
 249         i460.gatt = ioremap(INTEL_I460_ATTBASE, PAGE_SIZE << page_order);
 250
 251         /* These are no good, the should be removed from the agp_bridge strucure... */
 252         agp_bridge->gatt_table_real = NULL;
 253         agp_bridge->gatt_table = NULL;
 254         agp_bridge->gatt_bus_addr = 0;
 255
 256         for (i = 0; i < num_entries; ++i)
 257                 WR_GATT(i, 0);
 258         WR_FLUSH_GATT(i - 1);
 259         return 0;
 260 }
 261
 262 static int i460_free_gatt_table (struct agp_bridge_data *bridge)
 263 {
 264         int num_entries, i;
 265         void *temp;
 266
 267         temp = agp_bridge->current_size;
 268
 269         num_entries = A_SIZE_8(temp)->num_entries;
 270
 271         for (i = 0; i < num_entries; ++i)
 272                 WR_GATT(i, 0);
 273         WR_FLUSH_GATT(num_entries - 1);
 274
 275         iounmap(i460.gatt);
 276         return 0;
 277 }
 278
 279 /*
 280  * The following functions are called when the I/O (GART) page size is smaller than
 281  * PAGE_SIZE.
 282  */
 283
 284 static int i460_insert_memory_small_io_page (struct agp_memory *mem,
 285                                 off_t pg_start, int type)
 286 {
 287         unsigned long paddr, io_pg_start, io_page_size;
 288         int i, j, k, num_entries;
 289         void *temp;
 290
 291         pr_debug("i460_insert_memory_small_io_page(mem=%p, pg_start=%ld, type=%d, paddr0=0x%lx)\n",
 292                  mem, pg_start, type, mem->memory[0]);
 293
 294         io_pg_start = I460_IOPAGES_PER_KPAGE * pg_start;
 295
 296         temp = agp_bridge->current_size;
 297         num_entries = A_SIZE_8(temp)->num_entries;
 298
 299         if ((io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count) > num_entries) {
 300                 printk(KERN_ERR PFX "Looks like we're out of AGP memory\n");
 301                 return -EINVAL;
 302         }
 303
 304         j = io_pg_start;
 305         while (j < (io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count)) {
 306                 if (!PGE_EMPTY(agp_bridge, RD_GATT(j))) {
 307                         pr_debug("i460_insert_memory_small_io_page: GATT[%d]=0x%x is busy\n",
 308                                  j, RD_GATT(j));
 309                         return -EBUSY;
 310                 }
 311                 j++;
 312         }
 313
 314         io_page_size = 1UL << I460_IO_PAGE_SHIFT;
 315         for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
 316                 paddr = mem->memory[i];
 317                 for (k = 0; k < I460_IOPAGES_PER_KPAGE; k++, j++, paddr += io_page_size)
 318                         WR_GATT(j, agp_bridge->driver->mask_memory(agp_bridge,
 319                                 paddr, mem->type));
 320         }
 321         WR_FLUSH_GATT(j - 1);
 322         return 0;
 323 }
 324
 325 static int i460_remove_memory_small_io_page(struct agp_memory *mem,
 326                                 off_t pg_start, int type)
 327 {
 328         int i;
 329
 330         pr_debug("i460_remove_memory_small_io_page(mem=%p, pg_start=%ld, type=%d)\n",
 331                  mem, pg_start, type);
 332
 333         pg_start = I460_IOPAGES_PER_KPAGE * pg_start;
 334
 335         for (i = pg_start; i < (pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count); i++)
 336                 WR_GATT(i, 0);
 337         WR_FLUSH_GATT(i - 1);
 338         return 0;
 339 }
 340
 341 #if I460_LARGE_IO_PAGES
 342
 343 /*
 344  * These functions are called when the I/O (GART) page size exceeds PAGE_SIZE.
 345  *
 346  * This situation is interesting since AGP memory allocations that are smaller than a
 347  * single GART page are possible.  The i460.lp_desc array tracks partial allocation of the
 348  * large GART pages to work around this issue.
 349  *
 350  * i460.lp_desc[pg_num].refcount tracks the number of kernel pages in use within GART page
 351  * pg_num.  i460.lp_desc[pg_num].paddr is the physical address of the large page and
 352  * i460.lp_desc[pg_num].alloced_map is a bitmap of kernel pages that are in use (allocated).
 353  */
 354
 355 static int i460_alloc_large_page (struct lp_desc *lp)
 356 {
 357         unsigned long order = I460_IO_PAGE_SHIFT - PAGE_SHIFT;
 358         size_t map_size;
 359         void *lpage;
 360
 361         lpage = (void *) __get_free_pages(GFP_KERNEL, order);
 362         if (!lpage) {
 363                 printk(KERN_ERR PFX "Couldn't alloc 4M GART page...\n");
 364                 return -ENOMEM;
 365         }
 366
 367         map_size = ((I460_KPAGES_PER_IOPAGE + BITS_PER_LONG - 1) & -BITS_PER_LONG)/8;
 368         lp->alloced_map = kzalloc(map_size, GFP_KERNEL);
 369         if (!lp->alloced_map) {
 370                 free_pages((unsigned long) lpage, order);
 371                 printk(KERN_ERR PFX "Out of memory, we're in trouble...\n");
 372                 return -ENOMEM;
 373         }
 374
 375         lp->paddr = virt_to_gart(lpage);
 376         lp->refcount = 0;
 377         atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
 378         return 0;
 379 }
 380
 381 static void i460_free_large_page (struct lp_desc *lp)
 382 {
 383         kfree(lp->alloced_map);
 384         lp->alloced_map = NULL;
 385
 386         free_pages((unsigned long) gart_to_virt(lp->paddr), I460_IO_PAGE_SHIFT - PAGE_SHIFT);
 387         atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
 388 }
 389
 390 static int i460_insert_memory_large_io_page (struct agp_memory *mem,
 391                                 off_t pg_start, int type)
 392 {
 393         int i, start_offset, end_offset, idx, pg, num_entries;
 394         struct lp_desc *start, *end, *lp;
 395         void *temp;
 396
 397         temp = agp_bridge->current_size;
 398         num_entries = A_SIZE_8(temp)->num_entries;
 399
 400         /* Figure out what pg_start means in terms of our large GART pages */
 401         start           = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];
 402         end             = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];
 403         start_offset    = pg_start % I460_KPAGES_PER_IOPAGE;
 404         end_offset      = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;
 405
 406         if (end > i460.lp_desc + num_entries) {
 407                 printk(KERN_ERR PFX "Looks like we're out of AGP memory\n");
 408                 return -EINVAL;
 409         }
 410
 411         /* Check if the requested region of the aperture is free */
 412         for (lp = start; lp <= end; ++lp) {
 413                 if (!lp->alloced_map)
 414                         continue;       /* OK, the entire large page is available... */
 415
 416                 for (idx = ((lp == start) ? start_offset : 0);
 417                      idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
 418                      idx++)
 419                 {
 420                         if (test_bit(idx, lp->alloced_map))
 421                                 return -EBUSY;
 422                 }
 423         }
 424
 425         for (lp = start, i = 0; lp <= end; ++lp) {
 426                 if (!lp->alloced_map) {
 427                         /* Allocate new GART pages... */
 428                         if (i460_alloc_large_page(lp) < 0)
 429                                 return -ENOMEM;
 430                         pg = lp - i460.lp_desc;
 431                         WR_GATT(pg, agp_bridge->driver->mask_memory(agp_bridge,
 432                                 lp->paddr, 0));
 433                         WR_FLUSH_GATT(pg);
 434                 }
 435
 436                 for (idx = ((lp == start) ? start_offset : 0);
 437                      idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
 438                      idx++, i++)
 439                 {
 440                         mem->memory[i] = lp->paddr + idx*PAGE_SIZE;
 441                         __set_bit(idx, lp->alloced_map);
 442                         ++lp->refcount;
 443                 }
 444         }
 445         return 0;
 446 }
 447
 448 static int i460_remove_memory_large_io_page (struct agp_memory *mem,
 449                                 off_t pg_start, int type)
 450 {
 451         int i, pg, start_offset, end_offset, idx, num_entries;
 452         struct lp_desc *start, *end, *lp;
 453         void *temp;
 454
 455         temp = agp_bridge->driver->current_size;
 456         num_entries = A_SIZE_8(temp)->num_entries;
 457
 458         /* Figure out what pg_start means in terms of our large GART pages */
 459         start           = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];
 460         end             = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];
 461         start_offset    = pg_start % I460_KPAGES_PER_IOPAGE;
 462         end_offset      = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;
 463
 464         for (i = 0, lp = start; lp <= end; ++lp) {
 465                 for (idx = ((lp == start) ? start_offset : 0);
 466                      idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
 467                      idx++, i++)
 468                 {
 469                         mem->memory[i] = 0;
 470                         __clear_bit(idx, lp->alloced_map);
 471                         --lp->refcount;
 472                 }
 473
 474                 /* Free GART pages if they are unused */
 475                 if (lp->refcount == 0) {
 476                         pg = lp - i460.lp_desc;
 477                         WR_GATT(pg, 0);
 478                         WR_FLUSH_GATT(pg);
 479                         i460_free_large_page(lp);
 480                 }
 481         }
 482         return 0;
 483 }
 484
 485 /* Wrapper routines to call the approriate {small_io_page,large_io_page} function */
 486
 487 static int i460_insert_memory (struct agp_memory *mem,
 488                                 off_t pg_start, int type)
 489 {
 490         if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT)
 491                 return i460_insert_memory_small_io_page(mem, pg_start, type);
 492         else
 493                 return i460_insert_memory_large_io_page(mem, pg_start, type);
 494 }
 495
 496 static int i460_remove_memory (struct agp_memory *mem,
 497                                 off_t pg_start, int type)
 498 {
 499         if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT)
 500                 return i460_remove_memory_small_io_page(mem, pg_start, type);
 501         else
 502                 return i460_remove_memory_large_io_page(mem, pg_start, type);
 503 }
 504
 505 /*
 506  * If the I/O (GART) page size is bigger than the kernel page size, we don't want to
 507  * allocate memory until we know where it is to be bound in the aperture (a
 508  * multi-kernel-page alloc might fit inside of an already allocated GART page).
 509  *
 510  * Let's just hope nobody counts on the allocated AGP memory being there before bind time
 511  * (I don't think current drivers do)...
 512  */
 513 static void *i460_alloc_page (struct agp_bridge_data *bridge)
 514 {
 515         void *page;
 516
 517         if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT)
 518                 page = agp_generic_alloc_page(agp_bridge);
 519         else
 520                 /* Returning NULL would cause problems */
 521                 /* AK: really dubious code. */
 522                 page = (void *)~0UL;
 523         return page;
 524 }
 525
 526 static void i460_destroy_page (void *page)
 527 {
 528         if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT)
 529                 agp_generic_destroy_page(page);
 530 }
 531
 532 #endif /* I460_LARGE_IO_PAGES */
 533
 534 static unsigned long i460_mask_memory (struct agp_bridge_data *bridge,
 535         unsigned long addr, int type)
 536 {
 537         /* Make sure the returned address is a valid GATT entry */
 538         return bridge->driver->masks[0].mask
 539                 | (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xffffff000) >> 12);
 540 }
 541
 542 struct agp_bridge_driver intel_i460_driver = {
 543         .owner                  = THIS_MODULE,
 544         .aperture_sizes         = i460_sizes,
 545         .size_type              = U8_APER_SIZE,
 546         .num_aperture_sizes     = 3,
 547         .configure              = i460_configure,
 548         .fetch_size             = i460_fetch_size,
 549         .cleanup                = i460_cleanup,
 550         .tlb_flush              = i460_tlb_flush,
 551         .mask_memory            = i460_mask_memory,
 552         .masks                  = i460_masks,
 553         .agp_enable             = agp_generic_enable,
 554         .cache_flush            = global_cache_flush,
 555         .create_gatt_table      = i460_create_gatt_table,
 556         .free_gatt_table        = i460_free_gatt_table,
 557 #if I460_LARGE_IO_PAGES
 558         .insert_memory          = i460_insert_memory,
 559         .remove_memory          = i460_remove_memory,
 560         .agp_alloc_page         = i460_alloc_page,
 561         .agp_destroy_page       = i460_destroy_page,
 562 #else
 563         .insert_memory          = i460_insert_memory_small_io_page,
 564         .remove_memory          = i460_remove_memory_small_io_page,
 565         .agp_alloc_page         = agp_generic_alloc_page,
 566         .agp_destroy_page       = agp_generic_destroy_page,
 567 #endif
 568         .alloc_by_type          = agp_generic_alloc_by_type,
 569         .free_by_type           = agp_generic_free_by_type,
 570         .cant_use_aperture      = 1,
 571 };
 572
 573 static int __devinit agp_intel_i460_probe(struct pci_dev *pdev,
 574                                           const struct pci_device_id *ent)
 575 {
 576         struct agp_bridge_data *bridge;
 577         u8 cap_ptr;
 578
 579         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
 580         if (!cap_ptr)
 581                 return -ENODEV;
 582
 583         bridge = agp_alloc_bridge();
 584         if (!bridge)
 585                 return -ENOMEM;
 586
 587         bridge->driver = &intel_i460_driver;
 588         bridge->dev = pdev;
 589         bridge->capndx = cap_ptr;
 590
 591         printk(KERN_INFO PFX "Detected Intel 460GX chipset\n");
 592
 593         pci_set_drvdata(pdev, bridge);
 594         return agp_add_bridge(bridge);
 595 }
 596
 597 static void __devexit agp_intel_i460_remove(struct pci_dev *pdev)
 598 {
 599         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 600
 601         agp_remove_bridge(bridge);
 602         agp_put_bridge(bridge);
 603 }
 604
 605 static struct pci_device_id agp_intel_i460_pci_table[] = {
 606         {
 607         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 608         .class_mask     = ~0,
 609         .vendor         = PCI_VENDOR_ID_INTEL,
 610         .device         = PCI_DEVICE_ID_INTEL_84460GX,
 611         .subvendor      = PCI_ANY_ID,
 612         .subdevice      = PCI_ANY_ID,
 613         },
 614         { }
 615 };
 616
 617 MODULE_DEVICE_TABLE(pci, agp_intel_i460_pci_table);
 618
 619 static struct pci_driver agp_intel_i460_pci_driver = {
 620         .owner          = THIS_MODULE,
 621         .name           = "agpgart-intel-i460",
 622         .id_table       = agp_intel_i460_pci_table,
 623         .probe          = agp_intel_i460_probe,
 624         .remove         = __devexit_p(agp_intel_i460_remove),
 625 };
 626
 627 static int __init agp_intel_i460_init(void)
 628 {
 629         if (agp_off)
 630                 return -EINVAL;
 631         return pci_register_driver(&agp_intel_i460_pci_driver);
 632 }
 633
 634 static void __exit agp_intel_i460_cleanup(void)
 635 {
 636         pci_unregister_driver(&agp_intel_i460_pci_driver);
 637 }
 638
 639 module_init(agp_intel_i460_init);
 640 module_exit(agp_intel_i460_cleanup);
 641
 642 MODULE_AUTHOR("Chris Ahna <Christopher.J.Ahna@intel.com>");
 643 MODULE_LICENSE("GPL and additional rights");