8d81a3a64c078bb4d2523ac51c2ef6ad6c10e7dc
[sfrench/cifs-2.6.git] / drivers / block / DAC960.c
1 /*
2
3   Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers
4
5   Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
6   Portions Copyright 2002 by Mylex (An IBM Business Unit)
7
8   This program is free software; you may redistribute and/or modify it under
9   the terms of the GNU General Public License Version 2 as published by the
10   Free Software Foundation.
11
12   This program is distributed in the hope that it will be useful, but
13   WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
14   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
15   for complete details.
16
17 */
18
19
20 #define DAC960_DriverVersion                    "2.5.48"
21 #define DAC960_DriverDate                       "14 May 2006"
22
23
24 #include <linux/module.h>
25 #include <linux/types.h>
26 #include <linux/miscdevice.h>
27 #include <linux/blkdev.h>
28 #include <linux/bio.h>
29 #include <linux/completion.h>
30 #include <linux/delay.h>
31 #include <linux/genhd.h>
32 #include <linux/hdreg.h>
33 #include <linux/blkpg.h>
34 #include <linux/interrupt.h>
35 #include <linux/ioport.h>
36 #include <linux/mm.h>
37 #include <linux/slab.h>
38 #include <linux/proc_fs.h>
39 #include <linux/reboot.h>
40 #include <linux/spinlock.h>
41 #include <linux/timer.h>
42 #include <linux/pci.h>
43 #include <linux/init.h>
44 #include <linux/jiffies.h>
45 #include <linux/random.h>
46 #include <asm/io.h>
47 #include <asm/uaccess.h>
48 #include "DAC960.h"
49
50 #define DAC960_GAM_MINOR        252
51
52
53 static DAC960_Controller_T *DAC960_Controllers[DAC960_MaxControllers];
54 static int DAC960_ControllerCount;
55 static struct proc_dir_entry *DAC960_ProcDirectoryEntry;
56
57 static long disk_size(DAC960_Controller_T *p, int drive_nr)
58 {
59         if (p->FirmwareType == DAC960_V1_Controller) {
60                 if (drive_nr >= p->LogicalDriveCount)
61                         return 0;
62                 return p->V1.LogicalDriveInformation[drive_nr].
63                         LogicalDriveSize;
64         } else {
65                 DAC960_V2_LogicalDeviceInfo_T *i =
66                         p->V2.LogicalDeviceInformation[drive_nr];
67                 if (i == NULL)
68                         return 0;
69                 return i->ConfigurableDeviceSize;
70         }
71 }
72
73 static int DAC960_open(struct inode *inode, struct file *file)
74 {
75         struct gendisk *disk = inode->i_bdev->bd_disk;
76         DAC960_Controller_T *p = disk->queue->queuedata;
77         int drive_nr = (long)disk->private_data;
78
79         if (p->FirmwareType == DAC960_V1_Controller) {
80                 if (p->V1.LogicalDriveInformation[drive_nr].
81                     LogicalDriveState == DAC960_V1_LogicalDrive_Offline)
82                         return -ENXIO;
83         } else {
84                 DAC960_V2_LogicalDeviceInfo_T *i =
85                         p->V2.LogicalDeviceInformation[drive_nr];
86                 if (!i || i->LogicalDeviceState == DAC960_V2_LogicalDevice_Offline)
87                         return -ENXIO;
88         }
89
90         check_disk_change(inode->i_bdev);
91
92         if (!get_capacity(p->disks[drive_nr]))
93                 return -ENXIO;
94         return 0;
95 }
96
97 static int DAC960_getgeo(struct block_device *bdev, struct hd_geometry *geo)
98 {
99         struct gendisk *disk = bdev->bd_disk;
100         DAC960_Controller_T *p = disk->queue->queuedata;
101         int drive_nr = (long)disk->private_data;
102
103         if (p->FirmwareType == DAC960_V1_Controller) {
104                 geo->heads = p->V1.GeometryTranslationHeads;
105                 geo->sectors = p->V1.GeometryTranslationSectors;
106                 geo->cylinders = p->V1.LogicalDriveInformation[drive_nr].
107                         LogicalDriveSize / (geo->heads * geo->sectors);
108         } else {
109                 DAC960_V2_LogicalDeviceInfo_T *i =
110                         p->V2.LogicalDeviceInformation[drive_nr];
111                 switch (i->DriveGeometry) {
112                 case DAC960_V2_Geometry_128_32:
113                         geo->heads = 128;
114                         geo->sectors = 32;
115                         break;
116                 case DAC960_V2_Geometry_255_63:
117                         geo->heads = 255;
118                         geo->sectors = 63;
119                         break;
120                 default:
121                         DAC960_Error("Illegal Logical Device Geometry %d\n",
122                                         p, i->DriveGeometry);
123                         return -EINVAL;
124                 }
125
126                 geo->cylinders = i->ConfigurableDeviceSize /
127                         (geo->heads * geo->sectors);
128         }
129         
130         return 0;
131 }
132
133 static int DAC960_media_changed(struct gendisk *disk)
134 {
135         DAC960_Controller_T *p = disk->queue->queuedata;
136         int drive_nr = (long)disk->private_data;
137
138         if (!p->LogicalDriveInitiallyAccessible[drive_nr])
139                 return 1;
140         return 0;
141 }
142
143 static int DAC960_revalidate_disk(struct gendisk *disk)
144 {
145         DAC960_Controller_T *p = disk->queue->queuedata;
146         int unit = (long)disk->private_data;
147
148         set_capacity(disk, disk_size(p, unit));
149         return 0;
150 }
151
152 static struct block_device_operations DAC960_BlockDeviceOperations = {
153         .owner                  = THIS_MODULE,
154         .open                   = DAC960_open,
155         .getgeo                 = DAC960_getgeo,
156         .media_changed          = DAC960_media_changed,
157         .revalidate_disk        = DAC960_revalidate_disk,
158 };
159
160
161 /*
162   DAC960_AnnounceDriver announces the Driver Version and Date, Author's Name,
163   Copyright Notice, and Electronic Mail Address.
164 */
165
166 static void DAC960_AnnounceDriver(DAC960_Controller_T *Controller)
167 {
168   DAC960_Announce("***** DAC960 RAID Driver Version "
169                   DAC960_DriverVersion " of "
170                   DAC960_DriverDate " *****\n", Controller);
171   DAC960_Announce("Copyright 1998-2001 by Leonard N. Zubkoff "
172                   "<lnz@dandelion.com>\n", Controller);
173 }
174
175
176 /*
177   DAC960_Failure prints a standardized error message, and then returns false.
178 */
179
180 static boolean DAC960_Failure(DAC960_Controller_T *Controller,
181                               unsigned char *ErrorMessage)
182 {
183   DAC960_Error("While configuring DAC960 PCI RAID Controller at\n",
184                Controller);
185   if (Controller->IO_Address == 0)
186     DAC960_Error("PCI Bus %d Device %d Function %d I/O Address N/A "
187                  "PCI Address 0x%X\n", Controller,
188                  Controller->Bus, Controller->Device,
189                  Controller->Function, Controller->PCI_Address);
190   else DAC960_Error("PCI Bus %d Device %d Function %d I/O Address "
191                     "0x%X PCI Address 0x%X\n", Controller,
192                     Controller->Bus, Controller->Device,
193                     Controller->Function, Controller->IO_Address,
194                     Controller->PCI_Address);
195   DAC960_Error("%s FAILED - DETACHING\n", Controller, ErrorMessage);
196   return false;
197 }
198
199 /*
200   init_dma_loaf() and slice_dma_loaf() are helper functions for
201   aggregating the dma-mapped memory for a well-known collection of
202   data structures that are of different lengths.
203
204   These routines don't guarantee any alignment.  The caller must
205   include any space needed for alignment in the sizes of the structures
206   that are passed in.
207  */
208
209 static boolean init_dma_loaf(struct pci_dev *dev, struct dma_loaf *loaf,
210                                                                  size_t len)
211 {
212         void *cpu_addr;
213         dma_addr_t dma_handle;
214
215         cpu_addr = pci_alloc_consistent(dev, len, &dma_handle);
216         if (cpu_addr == NULL)
217                 return false;
218         
219         loaf->cpu_free = loaf->cpu_base = cpu_addr;
220         loaf->dma_free =loaf->dma_base = dma_handle;
221         loaf->length = len;
222         memset(cpu_addr, 0, len);
223         return true;
224 }
225
226 static void *slice_dma_loaf(struct dma_loaf *loaf, size_t len,
227                                         dma_addr_t *dma_handle)
228 {
229         void *cpu_end = loaf->cpu_free + len;
230         void *cpu_addr = loaf->cpu_free;
231
232         BUG_ON(cpu_end > loaf->cpu_base + loaf->length);
233         *dma_handle = loaf->dma_free;
234         loaf->cpu_free = cpu_end;
235         loaf->dma_free += len;
236         return cpu_addr;
237 }
238
239 static void free_dma_loaf(struct pci_dev *dev, struct dma_loaf *loaf_handle)
240 {
241         if (loaf_handle->cpu_base != NULL)
242                 pci_free_consistent(dev, loaf_handle->length,
243                         loaf_handle->cpu_base, loaf_handle->dma_base);
244 }
245
246
247 /*
248   DAC960_CreateAuxiliaryStructures allocates and initializes the auxiliary
249   data structures for Controller.  It returns true on success and false on
250   failure.
251 */
252
253 static boolean DAC960_CreateAuxiliaryStructures(DAC960_Controller_T *Controller)
254 {
255   int CommandAllocationLength, CommandAllocationGroupSize;
256   int CommandsRemaining = 0, CommandIdentifier, CommandGroupByteCount;
257   void *AllocationPointer = NULL;
258   void *ScatterGatherCPU = NULL;
259   dma_addr_t ScatterGatherDMA;
260   struct pci_pool *ScatterGatherPool;
261   void *RequestSenseCPU = NULL;
262   dma_addr_t RequestSenseDMA;
263   struct pci_pool *RequestSensePool = NULL;
264
265   if (Controller->FirmwareType == DAC960_V1_Controller)
266     {
267       CommandAllocationLength = offsetof(DAC960_Command_T, V1.EndMarker);
268       CommandAllocationGroupSize = DAC960_V1_CommandAllocationGroupSize;
269       ScatterGatherPool = pci_pool_create("DAC960_V1_ScatterGather",
270                 Controller->PCIDevice,
271         DAC960_V1_ScatterGatherLimit * sizeof(DAC960_V1_ScatterGatherSegment_T),
272         sizeof(DAC960_V1_ScatterGatherSegment_T), 0);
273       if (ScatterGatherPool == NULL)
274             return DAC960_Failure(Controller,
275                         "AUXILIARY STRUCTURE CREATION (SG)");
276       Controller->ScatterGatherPool = ScatterGatherPool;
277     }
278   else
279     {
280       CommandAllocationLength = offsetof(DAC960_Command_T, V2.EndMarker);
281       CommandAllocationGroupSize = DAC960_V2_CommandAllocationGroupSize;
282       ScatterGatherPool = pci_pool_create("DAC960_V2_ScatterGather",
283                 Controller->PCIDevice,
284         DAC960_V2_ScatterGatherLimit * sizeof(DAC960_V2_ScatterGatherSegment_T),
285         sizeof(DAC960_V2_ScatterGatherSegment_T), 0);
286       if (ScatterGatherPool == NULL)
287             return DAC960_Failure(Controller,
288                         "AUXILIARY STRUCTURE CREATION (SG)");
289       RequestSensePool = pci_pool_create("DAC960_V2_RequestSense",
290                 Controller->PCIDevice, sizeof(DAC960_SCSI_RequestSense_T),
291                 sizeof(int), 0);
292       if (RequestSensePool == NULL) {
293             pci_pool_destroy(ScatterGatherPool);
294             return DAC960_Failure(Controller,
295                         "AUXILIARY STRUCTURE CREATION (SG)");
296       }
297       Controller->ScatterGatherPool = ScatterGatherPool;
298       Controller->V2.RequestSensePool = RequestSensePool;
299     }
300   Controller->CommandAllocationGroupSize = CommandAllocationGroupSize;
301   Controller->FreeCommands = NULL;
302   for (CommandIdentifier = 1;
303        CommandIdentifier <= Controller->DriverQueueDepth;
304        CommandIdentifier++)
305     {
306       DAC960_Command_T *Command;
307       if (--CommandsRemaining <= 0)
308         {
309           CommandsRemaining =
310                 Controller->DriverQueueDepth - CommandIdentifier + 1;
311           if (CommandsRemaining > CommandAllocationGroupSize)
312                 CommandsRemaining = CommandAllocationGroupSize;
313           CommandGroupByteCount =
314                 CommandsRemaining * CommandAllocationLength;
315           AllocationPointer = kzalloc(CommandGroupByteCount, GFP_ATOMIC);
316           if (AllocationPointer == NULL)
317                 return DAC960_Failure(Controller,
318                                         "AUXILIARY STRUCTURE CREATION");
319          }
320       Command = (DAC960_Command_T *) AllocationPointer;
321       AllocationPointer += CommandAllocationLength;
322       Command->CommandIdentifier = CommandIdentifier;
323       Command->Controller = Controller;
324       Command->Next = Controller->FreeCommands;
325       Controller->FreeCommands = Command;
326       Controller->Commands[CommandIdentifier-1] = Command;
327       ScatterGatherCPU = pci_pool_alloc(ScatterGatherPool, GFP_ATOMIC,
328                                                         &ScatterGatherDMA);
329       if (ScatterGatherCPU == NULL)
330           return DAC960_Failure(Controller, "AUXILIARY STRUCTURE CREATION");
331
332       if (RequestSensePool != NULL) {
333           RequestSenseCPU = pci_pool_alloc(RequestSensePool, GFP_ATOMIC,
334                                                 &RequestSenseDMA);
335           if (RequestSenseCPU == NULL) {
336                 pci_pool_free(ScatterGatherPool, ScatterGatherCPU,
337                                 ScatterGatherDMA);
338                 return DAC960_Failure(Controller,
339                                         "AUXILIARY STRUCTURE CREATION");
340           }
341         }
342      if (Controller->FirmwareType == DAC960_V1_Controller) {
343         Command->cmd_sglist = Command->V1.ScatterList;
344         Command->V1.ScatterGatherList =
345                 (DAC960_V1_ScatterGatherSegment_T *)ScatterGatherCPU;
346         Command->V1.ScatterGatherListDMA = ScatterGatherDMA;
347       } else {
348         Command->cmd_sglist = Command->V2.ScatterList;
349         Command->V2.ScatterGatherList =
350                 (DAC960_V2_ScatterGatherSegment_T *)ScatterGatherCPU;
351         Command->V2.ScatterGatherListDMA = ScatterGatherDMA;
352         Command->V2.RequestSense =
353                                 (DAC960_SCSI_RequestSense_T *)RequestSenseCPU;
354         Command->V2.RequestSenseDMA = RequestSenseDMA;
355       }
356     }
357   return true;
358 }
359
360
361 /*
362   DAC960_DestroyAuxiliaryStructures deallocates the auxiliary data
363   structures for Controller.
364 */
365
366 static void DAC960_DestroyAuxiliaryStructures(DAC960_Controller_T *Controller)
367 {
368   int i;
369   struct pci_pool *ScatterGatherPool = Controller->ScatterGatherPool;
370   struct pci_pool *RequestSensePool = NULL;
371   void *ScatterGatherCPU;
372   dma_addr_t ScatterGatherDMA;
373   void *RequestSenseCPU;
374   dma_addr_t RequestSenseDMA;
375   DAC960_Command_T *CommandGroup = NULL;
376   
377
378   if (Controller->FirmwareType == DAC960_V2_Controller)
379         RequestSensePool = Controller->V2.RequestSensePool;
380
381   Controller->FreeCommands = NULL;
382   for (i = 0; i < Controller->DriverQueueDepth; i++)
383     {
384       DAC960_Command_T *Command = Controller->Commands[i];
385
386       if (Command == NULL)
387           continue;
388
389       if (Controller->FirmwareType == DAC960_V1_Controller) {
390           ScatterGatherCPU = (void *)Command->V1.ScatterGatherList;
391           ScatterGatherDMA = Command->V1.ScatterGatherListDMA;
392           RequestSenseCPU = NULL;
393           RequestSenseDMA = (dma_addr_t)0;
394       } else {
395           ScatterGatherCPU = (void *)Command->V2.ScatterGatherList;
396           ScatterGatherDMA = Command->V2.ScatterGatherListDMA;
397           RequestSenseCPU = (void *)Command->V2.RequestSense;
398           RequestSenseDMA = Command->V2.RequestSenseDMA;
399       }
400       if (ScatterGatherCPU != NULL)
401           pci_pool_free(ScatterGatherPool, ScatterGatherCPU, ScatterGatherDMA);
402       if (RequestSenseCPU != NULL)
403           pci_pool_free(RequestSensePool, RequestSenseCPU, RequestSenseDMA);
404
405       if ((Command->CommandIdentifier
406            % Controller->CommandAllocationGroupSize) == 1) {
407            /*
408             * We can't free the group of commands until all of the
409             * request sense and scatter gather dma structures are free.
410             * Remember the beginning of the group, but don't free it
411             * until we've reached the beginning of the next group.
412             */
413            kfree(CommandGroup);
414            CommandGroup = Command;
415       }
416       Controller->Commands[i] = NULL;
417     }
418   kfree(CommandGroup);
419
420   if (Controller->CombinedStatusBuffer != NULL)
421     {
422       kfree(Controller->CombinedStatusBuffer);
423       Controller->CombinedStatusBuffer = NULL;
424       Controller->CurrentStatusBuffer = NULL;
425     }
426
427   if (ScatterGatherPool != NULL)
428         pci_pool_destroy(ScatterGatherPool);
429   if (Controller->FirmwareType == DAC960_V1_Controller)
430         return;
431
432   if (RequestSensePool != NULL)
433         pci_pool_destroy(RequestSensePool);
434
435   for (i = 0; i < DAC960_MaxLogicalDrives; i++) {
436         kfree(Controller->V2.LogicalDeviceInformation[i]);
437         Controller->V2.LogicalDeviceInformation[i] = NULL;
438   }
439
440   for (i = 0; i < DAC960_V2_MaxPhysicalDevices; i++)
441     {
442       kfree(Controller->V2.PhysicalDeviceInformation[i]);
443       Controller->V2.PhysicalDeviceInformation[i] = NULL;
444       kfree(Controller->V2.InquiryUnitSerialNumber[i]);
445       Controller->V2.InquiryUnitSerialNumber[i] = NULL;
446     }
447 }
448
449
450 /*
451   DAC960_V1_ClearCommand clears critical fields of Command for DAC960 V1
452   Firmware Controllers.
453 */
454
455 static inline void DAC960_V1_ClearCommand(DAC960_Command_T *Command)
456 {
457   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
458   memset(CommandMailbox, 0, sizeof(DAC960_V1_CommandMailbox_T));
459   Command->V1.CommandStatus = 0;
460 }
461
462
463 /*
464   DAC960_V2_ClearCommand clears critical fields of Command for DAC960 V2
465   Firmware Controllers.
466 */
467
468 static inline void DAC960_V2_ClearCommand(DAC960_Command_T *Command)
469 {
470   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
471   memset(CommandMailbox, 0, sizeof(DAC960_V2_CommandMailbox_T));
472   Command->V2.CommandStatus = 0;
473 }
474
475
476 /*
477   DAC960_AllocateCommand allocates a Command structure from Controller's
478   free list.  During driver initialization, a special initialization command
479   has been placed on the free list to guarantee that command allocation can
480   never fail.
481 */
482
483 static inline DAC960_Command_T *DAC960_AllocateCommand(DAC960_Controller_T
484                                                        *Controller)
485 {
486   DAC960_Command_T *Command = Controller->FreeCommands;
487   if (Command == NULL) return NULL;
488   Controller->FreeCommands = Command->Next;
489   Command->Next = NULL;
490   return Command;
491 }
492
493
494 /*
495   DAC960_DeallocateCommand deallocates Command, returning it to Controller's
496   free list.
497 */
498
499 static inline void DAC960_DeallocateCommand(DAC960_Command_T *Command)
500 {
501   DAC960_Controller_T *Controller = Command->Controller;
502
503   Command->Request = NULL;
504   Command->Next = Controller->FreeCommands;
505   Controller->FreeCommands = Command;
506 }
507
508
509 /*
510   DAC960_WaitForCommand waits for a wake_up on Controller's Command Wait Queue.
511 */
512
513 static void DAC960_WaitForCommand(DAC960_Controller_T *Controller)
514 {
515   spin_unlock_irq(&Controller->queue_lock);
516   __wait_event(Controller->CommandWaitQueue, Controller->FreeCommands);
517   spin_lock_irq(&Controller->queue_lock);
518 }
519
520 /*
521   DAC960_GEM_QueueCommand queues Command for DAC960 GEM Series Controllers.
522 */
523
524 static void DAC960_GEM_QueueCommand(DAC960_Command_T *Command)
525 {
526   DAC960_Controller_T *Controller = Command->Controller;
527   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
528   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
529   DAC960_V2_CommandMailbox_T *NextCommandMailbox =
530       Controller->V2.NextCommandMailbox;
531
532   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
533   DAC960_GEM_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
534
535   if (Controller->V2.PreviousCommandMailbox1->Words[0] == 0 ||
536       Controller->V2.PreviousCommandMailbox2->Words[0] == 0)
537       DAC960_GEM_MemoryMailboxNewCommand(ControllerBaseAddress);
538
539   Controller->V2.PreviousCommandMailbox2 =
540       Controller->V2.PreviousCommandMailbox1;
541   Controller->V2.PreviousCommandMailbox1 = NextCommandMailbox;
542
543   if (++NextCommandMailbox > Controller->V2.LastCommandMailbox)
544       NextCommandMailbox = Controller->V2.FirstCommandMailbox;
545
546   Controller->V2.NextCommandMailbox = NextCommandMailbox;
547 }
548
549 /*
550   DAC960_BA_QueueCommand queues Command for DAC960 BA Series Controllers.
551 */
552
553 static void DAC960_BA_QueueCommand(DAC960_Command_T *Command)
554 {
555   DAC960_Controller_T *Controller = Command->Controller;
556   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
557   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
558   DAC960_V2_CommandMailbox_T *NextCommandMailbox =
559     Controller->V2.NextCommandMailbox;
560   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
561   DAC960_BA_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
562   if (Controller->V2.PreviousCommandMailbox1->Words[0] == 0 ||
563       Controller->V2.PreviousCommandMailbox2->Words[0] == 0)
564     DAC960_BA_MemoryMailboxNewCommand(ControllerBaseAddress);
565   Controller->V2.PreviousCommandMailbox2 =
566     Controller->V2.PreviousCommandMailbox1;
567   Controller->V2.PreviousCommandMailbox1 = NextCommandMailbox;
568   if (++NextCommandMailbox > Controller->V2.LastCommandMailbox)
569     NextCommandMailbox = Controller->V2.FirstCommandMailbox;
570   Controller->V2.NextCommandMailbox = NextCommandMailbox;
571 }
572
573
574 /*
575   DAC960_LP_QueueCommand queues Command for DAC960 LP Series Controllers.
576 */
577
578 static void DAC960_LP_QueueCommand(DAC960_Command_T *Command)
579 {
580   DAC960_Controller_T *Controller = Command->Controller;
581   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
582   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
583   DAC960_V2_CommandMailbox_T *NextCommandMailbox =
584     Controller->V2.NextCommandMailbox;
585   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
586   DAC960_LP_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
587   if (Controller->V2.PreviousCommandMailbox1->Words[0] == 0 ||
588       Controller->V2.PreviousCommandMailbox2->Words[0] == 0)
589     DAC960_LP_MemoryMailboxNewCommand(ControllerBaseAddress);
590   Controller->V2.PreviousCommandMailbox2 =
591     Controller->V2.PreviousCommandMailbox1;
592   Controller->V2.PreviousCommandMailbox1 = NextCommandMailbox;
593   if (++NextCommandMailbox > Controller->V2.LastCommandMailbox)
594     NextCommandMailbox = Controller->V2.FirstCommandMailbox;
595   Controller->V2.NextCommandMailbox = NextCommandMailbox;
596 }
597
598
599 /*
600   DAC960_LA_QueueCommandDualMode queues Command for DAC960 LA Series
601   Controllers with Dual Mode Firmware.
602 */
603
604 static void DAC960_LA_QueueCommandDualMode(DAC960_Command_T *Command)
605 {
606   DAC960_Controller_T *Controller = Command->Controller;
607   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
608   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
609   DAC960_V1_CommandMailbox_T *NextCommandMailbox =
610     Controller->V1.NextCommandMailbox;
611   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
612   DAC960_LA_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
613   if (Controller->V1.PreviousCommandMailbox1->Words[0] == 0 ||
614       Controller->V1.PreviousCommandMailbox2->Words[0] == 0)
615     DAC960_LA_MemoryMailboxNewCommand(ControllerBaseAddress);
616   Controller->V1.PreviousCommandMailbox2 =
617     Controller->V1.PreviousCommandMailbox1;
618   Controller->V1.PreviousCommandMailbox1 = NextCommandMailbox;
619   if (++NextCommandMailbox > Controller->V1.LastCommandMailbox)
620     NextCommandMailbox = Controller->V1.FirstCommandMailbox;
621   Controller->V1.NextCommandMailbox = NextCommandMailbox;
622 }
623
624
625 /*
626   DAC960_LA_QueueCommandSingleMode queues Command for DAC960 LA Series
627   Controllers with Single Mode Firmware.
628 */
629
630 static void DAC960_LA_QueueCommandSingleMode(DAC960_Command_T *Command)
631 {
632   DAC960_Controller_T *Controller = Command->Controller;
633   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
634   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
635   DAC960_V1_CommandMailbox_T *NextCommandMailbox =
636     Controller->V1.NextCommandMailbox;
637   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
638   DAC960_LA_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
639   if (Controller->V1.PreviousCommandMailbox1->Words[0] == 0 ||
640       Controller->V1.PreviousCommandMailbox2->Words[0] == 0)
641     DAC960_LA_HardwareMailboxNewCommand(ControllerBaseAddress);
642   Controller->V1.PreviousCommandMailbox2 =
643     Controller->V1.PreviousCommandMailbox1;
644   Controller->V1.PreviousCommandMailbox1 = NextCommandMailbox;
645   if (++NextCommandMailbox > Controller->V1.LastCommandMailbox)
646     NextCommandMailbox = Controller->V1.FirstCommandMailbox;
647   Controller->V1.NextCommandMailbox = NextCommandMailbox;
648 }
649
650
651 /*
652   DAC960_PG_QueueCommandDualMode queues Command for DAC960 PG Series
653   Controllers with Dual Mode Firmware.
654 */
655
656 static void DAC960_PG_QueueCommandDualMode(DAC960_Command_T *Command)
657 {
658   DAC960_Controller_T *Controller = Command->Controller;
659   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
660   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
661   DAC960_V1_CommandMailbox_T *NextCommandMailbox =
662     Controller->V1.NextCommandMailbox;
663   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
664   DAC960_PG_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
665   if (Controller->V1.PreviousCommandMailbox1->Words[0] == 0 ||
666       Controller->V1.PreviousCommandMailbox2->Words[0] == 0)
667     DAC960_PG_MemoryMailboxNewCommand(ControllerBaseAddress);
668   Controller->V1.PreviousCommandMailbox2 =
669     Controller->V1.PreviousCommandMailbox1;
670   Controller->V1.PreviousCommandMailbox1 = NextCommandMailbox;
671   if (++NextCommandMailbox > Controller->V1.LastCommandMailbox)
672     NextCommandMailbox = Controller->V1.FirstCommandMailbox;
673   Controller->V1.NextCommandMailbox = NextCommandMailbox;
674 }
675
676
677 /*
678   DAC960_PG_QueueCommandSingleMode queues Command for DAC960 PG Series
679   Controllers with Single Mode Firmware.
680 */
681
682 static void DAC960_PG_QueueCommandSingleMode(DAC960_Command_T *Command)
683 {
684   DAC960_Controller_T *Controller = Command->Controller;
685   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
686   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
687   DAC960_V1_CommandMailbox_T *NextCommandMailbox =
688     Controller->V1.NextCommandMailbox;
689   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
690   DAC960_PG_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
691   if (Controller->V1.PreviousCommandMailbox1->Words[0] == 0 ||
692       Controller->V1.PreviousCommandMailbox2->Words[0] == 0)
693     DAC960_PG_HardwareMailboxNewCommand(ControllerBaseAddress);
694   Controller->V1.PreviousCommandMailbox2 =
695     Controller->V1.PreviousCommandMailbox1;
696   Controller->V1.PreviousCommandMailbox1 = NextCommandMailbox;
697   if (++NextCommandMailbox > Controller->V1.LastCommandMailbox)
698     NextCommandMailbox = Controller->V1.FirstCommandMailbox;
699   Controller->V1.NextCommandMailbox = NextCommandMailbox;
700 }
701
702
703 /*
704   DAC960_PD_QueueCommand queues Command for DAC960 PD Series Controllers.
705 */
706
707 static void DAC960_PD_QueueCommand(DAC960_Command_T *Command)
708 {
709   DAC960_Controller_T *Controller = Command->Controller;
710   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
711   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
712   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
713   while (DAC960_PD_MailboxFullP(ControllerBaseAddress))
714     udelay(1);
715   DAC960_PD_WriteCommandMailbox(ControllerBaseAddress, CommandMailbox);
716   DAC960_PD_NewCommand(ControllerBaseAddress);
717 }
718
719
720 /*
721   DAC960_P_QueueCommand queues Command for DAC960 P Series Controllers.
722 */
723
724 static void DAC960_P_QueueCommand(DAC960_Command_T *Command)
725 {
726   DAC960_Controller_T *Controller = Command->Controller;
727   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
728   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
729   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
730   switch (CommandMailbox->Common.CommandOpcode)
731     {
732     case DAC960_V1_Enquiry:
733       CommandMailbox->Common.CommandOpcode = DAC960_V1_Enquiry_Old;
734       break;
735     case DAC960_V1_GetDeviceState:
736       CommandMailbox->Common.CommandOpcode = DAC960_V1_GetDeviceState_Old;
737       break;
738     case DAC960_V1_Read:
739       CommandMailbox->Common.CommandOpcode = DAC960_V1_Read_Old;
740       DAC960_PD_To_P_TranslateReadWriteCommand(CommandMailbox);
741       break;
742     case DAC960_V1_Write:
743       CommandMailbox->Common.CommandOpcode = DAC960_V1_Write_Old;
744       DAC960_PD_To_P_TranslateReadWriteCommand(CommandMailbox);
745       break;
746     case DAC960_V1_ReadWithScatterGather:
747       CommandMailbox->Common.CommandOpcode =
748         DAC960_V1_ReadWithScatterGather_Old;
749       DAC960_PD_To_P_TranslateReadWriteCommand(CommandMailbox);
750       break;
751     case DAC960_V1_WriteWithScatterGather:
752       CommandMailbox->Common.CommandOpcode =
753         DAC960_V1_WriteWithScatterGather_Old;
754       DAC960_PD_To_P_TranslateReadWriteCommand(CommandMailbox);
755       break;
756     default:
757       break;
758     }
759   while (DAC960_PD_MailboxFullP(ControllerBaseAddress))
760     udelay(1);
761   DAC960_PD_WriteCommandMailbox(ControllerBaseAddress, CommandMailbox);
762   DAC960_PD_NewCommand(ControllerBaseAddress);
763 }
764
765
766 /*
767   DAC960_ExecuteCommand executes Command and waits for completion.
768 */
769
770 static void DAC960_ExecuteCommand(DAC960_Command_T *Command)
771 {
772   DAC960_Controller_T *Controller = Command->Controller;
773   DECLARE_COMPLETION_ONSTACK(Completion);
774   unsigned long flags;
775   Command->Completion = &Completion;
776
777   spin_lock_irqsave(&Controller->queue_lock, flags);
778   DAC960_QueueCommand(Command);
779   spin_unlock_irqrestore(&Controller->queue_lock, flags);
780  
781   if (in_interrupt())
782           return;
783   wait_for_completion(&Completion);
784 }
785
786
787 /*
788   DAC960_V1_ExecuteType3 executes a DAC960 V1 Firmware Controller Type 3
789   Command and waits for completion.  It returns true on success and false
790   on failure.
791 */
792
793 static boolean DAC960_V1_ExecuteType3(DAC960_Controller_T *Controller,
794                                       DAC960_V1_CommandOpcode_T CommandOpcode,
795                                       dma_addr_t DataDMA)
796 {
797   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
798   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
799   DAC960_V1_CommandStatus_T CommandStatus;
800   DAC960_V1_ClearCommand(Command);
801   Command->CommandType = DAC960_ImmediateCommand;
802   CommandMailbox->Type3.CommandOpcode = CommandOpcode;
803   CommandMailbox->Type3.BusAddress = DataDMA;
804   DAC960_ExecuteCommand(Command);
805   CommandStatus = Command->V1.CommandStatus;
806   DAC960_DeallocateCommand(Command);
807   return (CommandStatus == DAC960_V1_NormalCompletion);
808 }
809
810
811 /*
812   DAC960_V1_ExecuteTypeB executes a DAC960 V1 Firmware Controller Type 3B
813   Command and waits for completion.  It returns true on success and false
814   on failure.
815 */
816
817 static boolean DAC960_V1_ExecuteType3B(DAC960_Controller_T *Controller,
818                                        DAC960_V1_CommandOpcode_T CommandOpcode,
819                                        unsigned char CommandOpcode2,
820                                        dma_addr_t DataDMA)
821 {
822   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
823   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
824   DAC960_V1_CommandStatus_T CommandStatus;
825   DAC960_V1_ClearCommand(Command);
826   Command->CommandType = DAC960_ImmediateCommand;
827   CommandMailbox->Type3B.CommandOpcode = CommandOpcode;
828   CommandMailbox->Type3B.CommandOpcode2 = CommandOpcode2;
829   CommandMailbox->Type3B.BusAddress = DataDMA;
830   DAC960_ExecuteCommand(Command);
831   CommandStatus = Command->V1.CommandStatus;
832   DAC960_DeallocateCommand(Command);
833   return (CommandStatus == DAC960_V1_NormalCompletion);
834 }
835
836
837 /*
838   DAC960_V1_ExecuteType3D executes a DAC960 V1 Firmware Controller Type 3D
839   Command and waits for completion.  It returns true on success and false
840   on failure.
841 */
842
843 static boolean DAC960_V1_ExecuteType3D(DAC960_Controller_T *Controller,
844                                        DAC960_V1_CommandOpcode_T CommandOpcode,
845                                        unsigned char Channel,
846                                        unsigned char TargetID,
847                                        dma_addr_t DataDMA)
848 {
849   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
850   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
851   DAC960_V1_CommandStatus_T CommandStatus;
852   DAC960_V1_ClearCommand(Command);
853   Command->CommandType = DAC960_ImmediateCommand;
854   CommandMailbox->Type3D.CommandOpcode = CommandOpcode;
855   CommandMailbox->Type3D.Channel = Channel;
856   CommandMailbox->Type3D.TargetID = TargetID;
857   CommandMailbox->Type3D.BusAddress = DataDMA;
858   DAC960_ExecuteCommand(Command);
859   CommandStatus = Command->V1.CommandStatus;
860   DAC960_DeallocateCommand(Command);
861   return (CommandStatus == DAC960_V1_NormalCompletion);
862 }
863
864
865 /*
866   DAC960_V2_GeneralInfo executes a DAC960 V2 Firmware General Information
867   Reading IOCTL Command and waits for completion.  It returns true on success
868   and false on failure.
869
870   Return data in The controller's HealthStatusBuffer, which is dma-able memory
871 */
872
873 static boolean DAC960_V2_GeneralInfo(DAC960_Controller_T *Controller)
874 {
875   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
876   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
877   DAC960_V2_CommandStatus_T CommandStatus;
878   DAC960_V2_ClearCommand(Command);
879   Command->CommandType = DAC960_ImmediateCommand;
880   CommandMailbox->Common.CommandOpcode = DAC960_V2_IOCTL;
881   CommandMailbox->Common.CommandControlBits
882                         .DataTransferControllerToHost = true;
883   CommandMailbox->Common.CommandControlBits
884                         .NoAutoRequestSense = true;
885   CommandMailbox->Common.DataTransferSize = sizeof(DAC960_V2_HealthStatusBuffer_T);
886   CommandMailbox->Common.IOCTL_Opcode = DAC960_V2_GetHealthStatus;
887   CommandMailbox->Common.DataTransferMemoryAddress
888                         .ScatterGatherSegments[0]
889                         .SegmentDataPointer =
890     Controller->V2.HealthStatusBufferDMA;
891   CommandMailbox->Common.DataTransferMemoryAddress
892                         .ScatterGatherSegments[0]
893                         .SegmentByteCount =
894     CommandMailbox->Common.DataTransferSize;
895   DAC960_ExecuteCommand(Command);
896   CommandStatus = Command->V2.CommandStatus;
897   DAC960_DeallocateCommand(Command);
898   return (CommandStatus == DAC960_V2_NormalCompletion);
899 }
900
901
902 /*
903   DAC960_V2_ControllerInfo executes a DAC960 V2 Firmware Controller
904   Information Reading IOCTL Command and waits for completion.  It returns
905   true on success and false on failure.
906
907   Data is returned in the controller's V2.NewControllerInformation dma-able
908   memory buffer.
909 */
910
911 static boolean DAC960_V2_NewControllerInfo(DAC960_Controller_T *Controller)
912 {
913   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
914   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
915   DAC960_V2_CommandStatus_T CommandStatus;
916   DAC960_V2_ClearCommand(Command);
917   Command->CommandType = DAC960_ImmediateCommand;
918   CommandMailbox->ControllerInfo.CommandOpcode = DAC960_V2_IOCTL;
919   CommandMailbox->ControllerInfo.CommandControlBits
920                                 .DataTransferControllerToHost = true;
921   CommandMailbox->ControllerInfo.CommandControlBits
922                                 .NoAutoRequestSense = true;
923   CommandMailbox->ControllerInfo.DataTransferSize = sizeof(DAC960_V2_ControllerInfo_T);
924   CommandMailbox->ControllerInfo.ControllerNumber = 0;
925   CommandMailbox->ControllerInfo.IOCTL_Opcode = DAC960_V2_GetControllerInfo;
926   CommandMailbox->ControllerInfo.DataTransferMemoryAddress
927                                 .ScatterGatherSegments[0]
928                                 .SegmentDataPointer =
929         Controller->V2.NewControllerInformationDMA;
930   CommandMailbox->ControllerInfo.DataTransferMemoryAddress
931                                 .ScatterGatherSegments[0]
932                                 .SegmentByteCount =
933     CommandMailbox->ControllerInfo.DataTransferSize;
934   DAC960_ExecuteCommand(Command);
935   CommandStatus = Command->V2.CommandStatus;
936   DAC960_DeallocateCommand(Command);
937   return (CommandStatus == DAC960_V2_NormalCompletion);
938 }
939
940
941 /*
942   DAC960_V2_LogicalDeviceInfo executes a DAC960 V2 Firmware Controller Logical
943   Device Information Reading IOCTL Command and waits for completion.  It
944   returns true on success and false on failure.
945
946   Data is returned in the controller's V2.NewLogicalDeviceInformation
947 */
948
949 static boolean DAC960_V2_NewLogicalDeviceInfo(DAC960_Controller_T *Controller,
950                                            unsigned short LogicalDeviceNumber)
951 {
952   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
953   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
954   DAC960_V2_CommandStatus_T CommandStatus;
955
956   DAC960_V2_ClearCommand(Command);
957   Command->CommandType = DAC960_ImmediateCommand;
958   CommandMailbox->LogicalDeviceInfo.CommandOpcode =
959                                 DAC960_V2_IOCTL;
960   CommandMailbox->LogicalDeviceInfo.CommandControlBits
961                                    .DataTransferControllerToHost = true;
962   CommandMailbox->LogicalDeviceInfo.CommandControlBits
963                                    .NoAutoRequestSense = true;
964   CommandMailbox->LogicalDeviceInfo.DataTransferSize = 
965                                 sizeof(DAC960_V2_LogicalDeviceInfo_T);
966   CommandMailbox->LogicalDeviceInfo.LogicalDevice.LogicalDeviceNumber =
967     LogicalDeviceNumber;
968   CommandMailbox->LogicalDeviceInfo.IOCTL_Opcode = DAC960_V2_GetLogicalDeviceInfoValid;
969   CommandMailbox->LogicalDeviceInfo.DataTransferMemoryAddress
970                                    .ScatterGatherSegments[0]
971                                    .SegmentDataPointer =
972         Controller->V2.NewLogicalDeviceInformationDMA;
973   CommandMailbox->LogicalDeviceInfo.DataTransferMemoryAddress
974                                    .ScatterGatherSegments[0]
975                                    .SegmentByteCount =
976     CommandMailbox->LogicalDeviceInfo.DataTransferSize;
977   DAC960_ExecuteCommand(Command);
978   CommandStatus = Command->V2.CommandStatus;
979   DAC960_DeallocateCommand(Command);
980   return (CommandStatus == DAC960_V2_NormalCompletion);
981 }
982
983
984 /*
985   DAC960_V2_PhysicalDeviceInfo executes a DAC960 V2 Firmware Controller "Read
986   Physical Device Information" IOCTL Command and waits for completion.  It
987   returns true on success and false on failure.
988
989   The Channel, TargetID, LogicalUnit arguments should be 0 the first time
990   this function is called for a given controller.  This will return data
991   for the "first" device on that controller.  The returned data includes a
992   Channel, TargetID, LogicalUnit that can be passed in to this routine to
993   get data for the NEXT device on that controller.
994
995   Data is stored in the controller's V2.NewPhysicalDeviceInfo dma-able
996   memory buffer.
997
998 */
999
1000 static boolean DAC960_V2_NewPhysicalDeviceInfo(DAC960_Controller_T *Controller,
1001                                             unsigned char Channel,
1002                                             unsigned char TargetID,
1003                                             unsigned char LogicalUnit)
1004 {
1005   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
1006   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
1007   DAC960_V2_CommandStatus_T CommandStatus;
1008
1009   DAC960_V2_ClearCommand(Command);
1010   Command->CommandType = DAC960_ImmediateCommand;
1011   CommandMailbox->PhysicalDeviceInfo.CommandOpcode = DAC960_V2_IOCTL;
1012   CommandMailbox->PhysicalDeviceInfo.CommandControlBits
1013                                     .DataTransferControllerToHost = true;
1014   CommandMailbox->PhysicalDeviceInfo.CommandControlBits
1015                                     .NoAutoRequestSense = true;
1016   CommandMailbox->PhysicalDeviceInfo.DataTransferSize =
1017                                 sizeof(DAC960_V2_PhysicalDeviceInfo_T);
1018   CommandMailbox->PhysicalDeviceInfo.PhysicalDevice.LogicalUnit = LogicalUnit;
1019   CommandMailbox->PhysicalDeviceInfo.PhysicalDevice.TargetID = TargetID;
1020   CommandMailbox->PhysicalDeviceInfo.PhysicalDevice.Channel = Channel;
1021   CommandMailbox->PhysicalDeviceInfo.IOCTL_Opcode =
1022                                         DAC960_V2_GetPhysicalDeviceInfoValid;
1023   CommandMailbox->PhysicalDeviceInfo.DataTransferMemoryAddress
1024                                     .ScatterGatherSegments[0]
1025                                     .SegmentDataPointer =
1026                                         Controller->V2.NewPhysicalDeviceInformationDMA;
1027   CommandMailbox->PhysicalDeviceInfo.DataTransferMemoryAddress
1028                                     .ScatterGatherSegments[0]
1029                                     .SegmentByteCount =
1030     CommandMailbox->PhysicalDeviceInfo.DataTransferSize;
1031   DAC960_ExecuteCommand(Command);
1032   CommandStatus = Command->V2.CommandStatus;
1033   DAC960_DeallocateCommand(Command);
1034   return (CommandStatus == DAC960_V2_NormalCompletion);
1035 }
1036
1037
1038 static void DAC960_V2_ConstructNewUnitSerialNumber(
1039         DAC960_Controller_T *Controller,
1040         DAC960_V2_CommandMailbox_T *CommandMailbox, int Channel, int TargetID,
1041         int LogicalUnit)
1042 {
1043       CommandMailbox->SCSI_10.CommandOpcode = DAC960_V2_SCSI_10_Passthru;
1044       CommandMailbox->SCSI_10.CommandControlBits
1045                              .DataTransferControllerToHost = true;
1046       CommandMailbox->SCSI_10.CommandControlBits
1047                              .NoAutoRequestSense = true;
1048       CommandMailbox->SCSI_10.DataTransferSize =
1049         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T);
1050       CommandMailbox->SCSI_10.PhysicalDevice.LogicalUnit = LogicalUnit;
1051       CommandMailbox->SCSI_10.PhysicalDevice.TargetID = TargetID;
1052       CommandMailbox->SCSI_10.PhysicalDevice.Channel = Channel;
1053       CommandMailbox->SCSI_10.CDBLength = 6;
1054       CommandMailbox->SCSI_10.SCSI_CDB[0] = 0x12; /* INQUIRY */
1055       CommandMailbox->SCSI_10.SCSI_CDB[1] = 1; /* EVPD = 1 */
1056       CommandMailbox->SCSI_10.SCSI_CDB[2] = 0x80; /* Page Code */
1057       CommandMailbox->SCSI_10.SCSI_CDB[3] = 0; /* Reserved */
1058       CommandMailbox->SCSI_10.SCSI_CDB[4] =
1059         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T);
1060       CommandMailbox->SCSI_10.SCSI_CDB[5] = 0; /* Control */
1061       CommandMailbox->SCSI_10.DataTransferMemoryAddress
1062                              .ScatterGatherSegments[0]
1063                              .SegmentDataPointer =
1064                 Controller->V2.NewInquiryUnitSerialNumberDMA;
1065       CommandMailbox->SCSI_10.DataTransferMemoryAddress
1066                              .ScatterGatherSegments[0]
1067                              .SegmentByteCount =
1068                 CommandMailbox->SCSI_10.DataTransferSize;
1069 }
1070
1071
1072 /*
1073   DAC960_V2_NewUnitSerialNumber executes an SCSI pass-through
1074   Inquiry command to a SCSI device identified by Channel number,
1075   Target id, Logical Unit Number.  This function Waits for completion
1076   of the command.
1077
1078   The return data includes Unit Serial Number information for the
1079   specified device.
1080
1081   Data is stored in the controller's V2.NewPhysicalDeviceInfo dma-able
1082   memory buffer.
1083 */
1084
1085 static boolean DAC960_V2_NewInquiryUnitSerialNumber(DAC960_Controller_T *Controller,
1086                         int Channel, int TargetID, int LogicalUnit)
1087 {
1088       DAC960_Command_T *Command;
1089       DAC960_V2_CommandMailbox_T *CommandMailbox;
1090       DAC960_V2_CommandStatus_T CommandStatus;
1091
1092       Command = DAC960_AllocateCommand(Controller);
1093       CommandMailbox = &Command->V2.CommandMailbox;
1094       DAC960_V2_ClearCommand(Command);
1095       Command->CommandType = DAC960_ImmediateCommand;
1096
1097       DAC960_V2_ConstructNewUnitSerialNumber(Controller, CommandMailbox,
1098                         Channel, TargetID, LogicalUnit);
1099
1100       DAC960_ExecuteCommand(Command);
1101       CommandStatus = Command->V2.CommandStatus;
1102       DAC960_DeallocateCommand(Command);
1103       return (CommandStatus == DAC960_V2_NormalCompletion);
1104 }
1105
1106
1107 /*
1108   DAC960_V2_DeviceOperation executes a DAC960 V2 Firmware Controller Device
1109   Operation IOCTL Command and waits for completion.  It returns true on
1110   success and false on failure.
1111 */
1112
1113 static boolean DAC960_V2_DeviceOperation(DAC960_Controller_T *Controller,
1114                                          DAC960_V2_IOCTL_Opcode_T IOCTL_Opcode,
1115                                          DAC960_V2_OperationDevice_T
1116                                            OperationDevice)
1117 {
1118   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
1119   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
1120   DAC960_V2_CommandStatus_T CommandStatus;
1121   DAC960_V2_ClearCommand(Command);
1122   Command->CommandType = DAC960_ImmediateCommand;
1123   CommandMailbox->DeviceOperation.CommandOpcode = DAC960_V2_IOCTL;
1124   CommandMailbox->DeviceOperation.CommandControlBits
1125                                  .DataTransferControllerToHost = true;
1126   CommandMailbox->DeviceOperation.CommandControlBits
1127                                  .NoAutoRequestSense = true;
1128   CommandMailbox->DeviceOperation.IOCTL_Opcode = IOCTL_Opcode;
1129   CommandMailbox->DeviceOperation.OperationDevice = OperationDevice;
1130   DAC960_ExecuteCommand(Command);
1131   CommandStatus = Command->V2.CommandStatus;
1132   DAC960_DeallocateCommand(Command);
1133   return (CommandStatus == DAC960_V2_NormalCompletion);
1134 }
1135
1136
1137 /*
1138   DAC960_V1_EnableMemoryMailboxInterface enables the Memory Mailbox Interface
1139   for DAC960 V1 Firmware Controllers.
1140
1141   PD and P controller types have no memory mailbox, but still need the
1142   other dma mapped memory.
1143 */
1144
1145 static boolean DAC960_V1_EnableMemoryMailboxInterface(DAC960_Controller_T
1146                                                       *Controller)
1147 {
1148   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
1149   DAC960_HardwareType_T hw_type = Controller->HardwareType;
1150   struct pci_dev *PCI_Device = Controller->PCIDevice;
1151   struct dma_loaf *DmaPages = &Controller->DmaPages;
1152   size_t DmaPagesSize;
1153   size_t CommandMailboxesSize;
1154   size_t StatusMailboxesSize;
1155
1156   DAC960_V1_CommandMailbox_T *CommandMailboxesMemory;
1157   dma_addr_t CommandMailboxesMemoryDMA;
1158
1159   DAC960_V1_StatusMailbox_T *StatusMailboxesMemory;
1160   dma_addr_t StatusMailboxesMemoryDMA;
1161
1162   DAC960_V1_CommandMailbox_T CommandMailbox;
1163   DAC960_V1_CommandStatus_T CommandStatus;
1164   int TimeoutCounter;
1165   int i;
1166
1167   
1168   if (pci_set_dma_mask(Controller->PCIDevice, DAC690_V1_PciDmaMask))
1169         return DAC960_Failure(Controller, "DMA mask out of range");
1170   Controller->BounceBufferLimit = DAC690_V1_PciDmaMask;
1171
1172   if ((hw_type == DAC960_PD_Controller) || (hw_type == DAC960_P_Controller)) {
1173     CommandMailboxesSize =  0;
1174     StatusMailboxesSize = 0;
1175   } else {
1176     CommandMailboxesSize =  DAC960_V1_CommandMailboxCount * sizeof(DAC960_V1_CommandMailbox_T);
1177     StatusMailboxesSize = DAC960_V1_StatusMailboxCount * sizeof(DAC960_V1_StatusMailbox_T);
1178   }
1179   DmaPagesSize = CommandMailboxesSize + StatusMailboxesSize + 
1180         sizeof(DAC960_V1_DCDB_T) + sizeof(DAC960_V1_Enquiry_T) +
1181         sizeof(DAC960_V1_ErrorTable_T) + sizeof(DAC960_V1_EventLogEntry_T) +
1182         sizeof(DAC960_V1_RebuildProgress_T) +
1183         sizeof(DAC960_V1_LogicalDriveInformationArray_T) +
1184         sizeof(DAC960_V1_BackgroundInitializationStatus_T) +
1185         sizeof(DAC960_V1_DeviceState_T) + sizeof(DAC960_SCSI_Inquiry_T) +
1186         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T);
1187
1188   if (!init_dma_loaf(PCI_Device, DmaPages, DmaPagesSize))
1189         return false;
1190
1191
1192   if ((hw_type == DAC960_PD_Controller) || (hw_type == DAC960_P_Controller)) 
1193         goto skip_mailboxes;
1194
1195   CommandMailboxesMemory = slice_dma_loaf(DmaPages,
1196                 CommandMailboxesSize, &CommandMailboxesMemoryDMA);
1197   
1198   /* These are the base addresses for the command memory mailbox array */
1199   Controller->V1.FirstCommandMailbox = CommandMailboxesMemory;
1200   Controller->V1.FirstCommandMailboxDMA = CommandMailboxesMemoryDMA;
1201
1202   CommandMailboxesMemory += DAC960_V1_CommandMailboxCount - 1;
1203   Controller->V1.LastCommandMailbox = CommandMailboxesMemory;
1204   Controller->V1.NextCommandMailbox = Controller->V1.FirstCommandMailbox;
1205   Controller->V1.PreviousCommandMailbox1 = Controller->V1.LastCommandMailbox;
1206   Controller->V1.PreviousCommandMailbox2 =
1207                                         Controller->V1.LastCommandMailbox - 1;
1208
1209   /* These are the base addresses for the status memory mailbox array */
1210   StatusMailboxesMemory = slice_dma_loaf(DmaPages,
1211                 StatusMailboxesSize, &StatusMailboxesMemoryDMA);
1212
1213   Controller->V1.FirstStatusMailbox = StatusMailboxesMemory;
1214   Controller->V1.FirstStatusMailboxDMA = StatusMailboxesMemoryDMA;
1215   StatusMailboxesMemory += DAC960_V1_StatusMailboxCount - 1;
1216   Controller->V1.LastStatusMailbox = StatusMailboxesMemory;
1217   Controller->V1.NextStatusMailbox = Controller->V1.FirstStatusMailbox;
1218
1219 skip_mailboxes:
1220   Controller->V1.MonitoringDCDB = slice_dma_loaf(DmaPages,
1221                 sizeof(DAC960_V1_DCDB_T),
1222                 &Controller->V1.MonitoringDCDB_DMA);
1223
1224   Controller->V1.NewEnquiry = slice_dma_loaf(DmaPages,
1225                 sizeof(DAC960_V1_Enquiry_T),
1226                 &Controller->V1.NewEnquiryDMA);
1227
1228   Controller->V1.NewErrorTable = slice_dma_loaf(DmaPages,
1229                 sizeof(DAC960_V1_ErrorTable_T),
1230                 &Controller->V1.NewErrorTableDMA);
1231
1232   Controller->V1.EventLogEntry = slice_dma_loaf(DmaPages,
1233                 sizeof(DAC960_V1_EventLogEntry_T),
1234                 &Controller->V1.EventLogEntryDMA);
1235
1236   Controller->V1.RebuildProgress = slice_dma_loaf(DmaPages,
1237                 sizeof(DAC960_V1_RebuildProgress_T),
1238                 &Controller->V1.RebuildProgressDMA);
1239
1240   Controller->V1.NewLogicalDriveInformation = slice_dma_loaf(DmaPages,
1241                 sizeof(DAC960_V1_LogicalDriveInformationArray_T),
1242                 &Controller->V1.NewLogicalDriveInformationDMA);
1243
1244   Controller->V1.BackgroundInitializationStatus = slice_dma_loaf(DmaPages,
1245                 sizeof(DAC960_V1_BackgroundInitializationStatus_T),
1246                 &Controller->V1.BackgroundInitializationStatusDMA);
1247
1248   Controller->V1.NewDeviceState = slice_dma_loaf(DmaPages,
1249                 sizeof(DAC960_V1_DeviceState_T),
1250                 &Controller->V1.NewDeviceStateDMA);
1251
1252   Controller->V1.NewInquiryStandardData = slice_dma_loaf(DmaPages,
1253                 sizeof(DAC960_SCSI_Inquiry_T),
1254                 &Controller->V1.NewInquiryStandardDataDMA);
1255
1256   Controller->V1.NewInquiryUnitSerialNumber = slice_dma_loaf(DmaPages,
1257                 sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T),
1258                 &Controller->V1.NewInquiryUnitSerialNumberDMA);
1259
1260   if ((hw_type == DAC960_PD_Controller) || (hw_type == DAC960_P_Controller))
1261         return true;
1262  
1263   /* Enable the Memory Mailbox Interface. */
1264   Controller->V1.DualModeMemoryMailboxInterface = true;
1265   CommandMailbox.TypeX.CommandOpcode = 0x2B;
1266   CommandMailbox.TypeX.CommandIdentifier = 0;
1267   CommandMailbox.TypeX.CommandOpcode2 = 0x14;
1268   CommandMailbox.TypeX.CommandMailboxesBusAddress =
1269                                 Controller->V1.FirstCommandMailboxDMA;
1270   CommandMailbox.TypeX.StatusMailboxesBusAddress =
1271                                 Controller->V1.FirstStatusMailboxDMA;
1272 #define TIMEOUT_COUNT 1000000
1273
1274   for (i = 0; i < 2; i++)
1275     switch (Controller->HardwareType)
1276       {
1277       case DAC960_LA_Controller:
1278         TimeoutCounter = TIMEOUT_COUNT;
1279         while (--TimeoutCounter >= 0)
1280           {
1281             if (!DAC960_LA_HardwareMailboxFullP(ControllerBaseAddress))
1282               break;
1283             udelay(10);
1284           }
1285         if (TimeoutCounter < 0) return false;
1286         DAC960_LA_WriteHardwareMailbox(ControllerBaseAddress, &CommandMailbox);
1287         DAC960_LA_HardwareMailboxNewCommand(ControllerBaseAddress);
1288         TimeoutCounter = TIMEOUT_COUNT;
1289         while (--TimeoutCounter >= 0)
1290           {
1291             if (DAC960_LA_HardwareMailboxStatusAvailableP(
1292                   ControllerBaseAddress))
1293               break;
1294             udelay(10);
1295           }
1296         if (TimeoutCounter < 0) return false;
1297         CommandStatus = DAC960_LA_ReadStatusRegister(ControllerBaseAddress);
1298         DAC960_LA_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress);
1299         DAC960_LA_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress);
1300         if (CommandStatus == DAC960_V1_NormalCompletion) return true;
1301         Controller->V1.DualModeMemoryMailboxInterface = false;
1302         CommandMailbox.TypeX.CommandOpcode2 = 0x10;
1303         break;
1304       case DAC960_PG_Controller:
1305         TimeoutCounter = TIMEOUT_COUNT;
1306         while (--TimeoutCounter >= 0)
1307           {
1308             if (!DAC960_PG_HardwareMailboxFullP(ControllerBaseAddress))
1309               break;
1310             udelay(10);
1311           }
1312         if (TimeoutCounter < 0) return false;
1313         DAC960_PG_WriteHardwareMailbox(ControllerBaseAddress, &CommandMailbox);
1314         DAC960_PG_HardwareMailboxNewCommand(ControllerBaseAddress);
1315
1316         TimeoutCounter = TIMEOUT_COUNT;
1317         while (--TimeoutCounter >= 0)
1318           {
1319             if (DAC960_PG_HardwareMailboxStatusAvailableP(
1320                   ControllerBaseAddress))
1321               break;
1322             udelay(10);
1323           }
1324         if (TimeoutCounter < 0) return false;
1325         CommandStatus = DAC960_PG_ReadStatusRegister(ControllerBaseAddress);
1326         DAC960_PG_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress);
1327         DAC960_PG_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress);
1328         if (CommandStatus == DAC960_V1_NormalCompletion) return true;
1329         Controller->V1.DualModeMemoryMailboxInterface = false;
1330         CommandMailbox.TypeX.CommandOpcode2 = 0x10;
1331         break;
1332       default:
1333         DAC960_Failure(Controller, "Unknown Controller Type\n");
1334         break;
1335       }
1336   return false;
1337 }
1338
1339
1340 /*
1341   DAC960_V2_EnableMemoryMailboxInterface enables the Memory Mailbox Interface
1342   for DAC960 V2 Firmware Controllers.
1343
1344   Aggregate the space needed for the controller's memory mailbox and
1345   the other data structures that will be targets of dma transfers with
1346   the controller.  Allocate a dma-mapped region of memory to hold these
1347   structures.  Then, save CPU pointers and dma_addr_t values to reference
1348   the structures that are contained in that region.
1349 */
1350
1351 static boolean DAC960_V2_EnableMemoryMailboxInterface(DAC960_Controller_T
1352                                                       *Controller)
1353 {
1354   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
1355   struct pci_dev *PCI_Device = Controller->PCIDevice;
1356   struct dma_loaf *DmaPages = &Controller->DmaPages;
1357   size_t DmaPagesSize;
1358   size_t CommandMailboxesSize;
1359   size_t StatusMailboxesSize;
1360
1361   DAC960_V2_CommandMailbox_T *CommandMailboxesMemory;
1362   dma_addr_t CommandMailboxesMemoryDMA;
1363
1364   DAC960_V2_StatusMailbox_T *StatusMailboxesMemory;
1365   dma_addr_t StatusMailboxesMemoryDMA;
1366
1367   DAC960_V2_CommandMailbox_T *CommandMailbox;
1368   dma_addr_t    CommandMailboxDMA;
1369   DAC960_V2_CommandStatus_T CommandStatus;
1370
1371   if (pci_set_dma_mask(Controller->PCIDevice, DAC690_V2_PciDmaMask))
1372         return DAC960_Failure(Controller, "DMA mask out of range");
1373   Controller->BounceBufferLimit = DAC690_V2_PciDmaMask;
1374
1375   /* This is a temporary dma mapping, used only in the scope of this function */
1376   CommandMailbox =
1377           (DAC960_V2_CommandMailbox_T *)pci_alloc_consistent( PCI_Device,
1378                 sizeof(DAC960_V2_CommandMailbox_T), &CommandMailboxDMA);
1379   if (CommandMailbox == NULL)
1380           return false;
1381
1382   CommandMailboxesSize = DAC960_V2_CommandMailboxCount * sizeof(DAC960_V2_CommandMailbox_T);
1383   StatusMailboxesSize = DAC960_V2_StatusMailboxCount * sizeof(DAC960_V2_StatusMailbox_T);
1384   DmaPagesSize =
1385     CommandMailboxesSize + StatusMailboxesSize +
1386     sizeof(DAC960_V2_HealthStatusBuffer_T) +
1387     sizeof(DAC960_V2_ControllerInfo_T) +
1388     sizeof(DAC960_V2_LogicalDeviceInfo_T) +
1389     sizeof(DAC960_V2_PhysicalDeviceInfo_T) +
1390     sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T) +
1391     sizeof(DAC960_V2_Event_T) +
1392     sizeof(DAC960_V2_PhysicalToLogicalDevice_T);
1393
1394   if (!init_dma_loaf(PCI_Device, DmaPages, DmaPagesSize)) {
1395         pci_free_consistent(PCI_Device, sizeof(DAC960_V2_CommandMailbox_T),
1396                                         CommandMailbox, CommandMailboxDMA);
1397         return false;
1398   }
1399
1400   CommandMailboxesMemory = slice_dma_loaf(DmaPages,
1401                 CommandMailboxesSize, &CommandMailboxesMemoryDMA);
1402
1403   /* These are the base addresses for the command memory mailbox array */
1404   Controller->V2.FirstCommandMailbox = CommandMailboxesMemory;
1405   Controller->V2.FirstCommandMailboxDMA = CommandMailboxesMemoryDMA;
1406
1407   CommandMailboxesMemory += DAC960_V2_CommandMailboxCount - 1;
1408   Controller->V2.LastCommandMailbox = CommandMailboxesMemory;
1409   Controller->V2.NextCommandMailbox = Controller->V2.FirstCommandMailbox;
1410   Controller->V2.PreviousCommandMailbox1 = Controller->V2.LastCommandMailbox;
1411   Controller->V2.PreviousCommandMailbox2 =
1412                                         Controller->V2.LastCommandMailbox - 1;
1413
1414   /* These are the base addresses for the status memory mailbox array */
1415   StatusMailboxesMemory = slice_dma_loaf(DmaPages,
1416                 StatusMailboxesSize, &StatusMailboxesMemoryDMA);
1417
1418   Controller->V2.FirstStatusMailbox = StatusMailboxesMemory;
1419   Controller->V2.FirstStatusMailboxDMA = StatusMailboxesMemoryDMA;
1420   StatusMailboxesMemory += DAC960_V2_StatusMailboxCount - 1;
1421   Controller->V2.LastStatusMailbox = StatusMailboxesMemory;
1422   Controller->V2.NextStatusMailbox = Controller->V2.FirstStatusMailbox;
1423
1424   Controller->V2.HealthStatusBuffer = slice_dma_loaf(DmaPages,
1425                 sizeof(DAC960_V2_HealthStatusBuffer_T),
1426                 &Controller->V2.HealthStatusBufferDMA);
1427
1428   Controller->V2.NewControllerInformation = slice_dma_loaf(DmaPages,
1429                 sizeof(DAC960_V2_ControllerInfo_T), 
1430                 &Controller->V2.NewControllerInformationDMA);
1431
1432   Controller->V2.NewLogicalDeviceInformation =  slice_dma_loaf(DmaPages,
1433                 sizeof(DAC960_V2_LogicalDeviceInfo_T),
1434                 &Controller->V2.NewLogicalDeviceInformationDMA);
1435
1436   Controller->V2.NewPhysicalDeviceInformation = slice_dma_loaf(DmaPages,
1437                 sizeof(DAC960_V2_PhysicalDeviceInfo_T),
1438                 &Controller->V2.NewPhysicalDeviceInformationDMA);
1439
1440   Controller->V2.NewInquiryUnitSerialNumber = slice_dma_loaf(DmaPages,
1441                 sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T),
1442                 &Controller->V2.NewInquiryUnitSerialNumberDMA);
1443
1444   Controller->V2.Event = slice_dma_loaf(DmaPages,
1445                 sizeof(DAC960_V2_Event_T),
1446                 &Controller->V2.EventDMA);
1447
1448   Controller->V2.PhysicalToLogicalDevice = slice_dma_loaf(DmaPages,
1449                 sizeof(DAC960_V2_PhysicalToLogicalDevice_T),
1450                 &Controller->V2.PhysicalToLogicalDeviceDMA);
1451
1452   /*
1453     Enable the Memory Mailbox Interface.
1454     
1455     I don't know why we can't just use one of the memory mailboxes
1456     we just allocated to do this, instead of using this temporary one.
1457     Try this change later.
1458   */
1459   memset(CommandMailbox, 0, sizeof(DAC960_V2_CommandMailbox_T));
1460   CommandMailbox->SetMemoryMailbox.CommandIdentifier = 1;
1461   CommandMailbox->SetMemoryMailbox.CommandOpcode = DAC960_V2_IOCTL;
1462   CommandMailbox->SetMemoryMailbox.CommandControlBits.NoAutoRequestSense = true;
1463   CommandMailbox->SetMemoryMailbox.FirstCommandMailboxSizeKB =
1464     (DAC960_V2_CommandMailboxCount * sizeof(DAC960_V2_CommandMailbox_T)) >> 10;
1465   CommandMailbox->SetMemoryMailbox.FirstStatusMailboxSizeKB =
1466     (DAC960_V2_StatusMailboxCount * sizeof(DAC960_V2_StatusMailbox_T)) >> 10;
1467   CommandMailbox->SetMemoryMailbox.SecondCommandMailboxSizeKB = 0;
1468   CommandMailbox->SetMemoryMailbox.SecondStatusMailboxSizeKB = 0;
1469   CommandMailbox->SetMemoryMailbox.RequestSenseSize = 0;
1470   CommandMailbox->SetMemoryMailbox.IOCTL_Opcode = DAC960_V2_SetMemoryMailbox;
1471   CommandMailbox->SetMemoryMailbox.HealthStatusBufferSizeKB = 1;
1472   CommandMailbox->SetMemoryMailbox.HealthStatusBufferBusAddress =
1473                                         Controller->V2.HealthStatusBufferDMA;
1474   CommandMailbox->SetMemoryMailbox.FirstCommandMailboxBusAddress =
1475                                         Controller->V2.FirstCommandMailboxDMA;
1476   CommandMailbox->SetMemoryMailbox.FirstStatusMailboxBusAddress =
1477                                         Controller->V2.FirstStatusMailboxDMA;
1478   switch (Controller->HardwareType)
1479     {
1480     case DAC960_GEM_Controller:
1481       while (DAC960_GEM_HardwareMailboxFullP(ControllerBaseAddress))
1482         udelay(1);
1483       DAC960_GEM_WriteHardwareMailbox(ControllerBaseAddress, CommandMailboxDMA);
1484       DAC960_GEM_HardwareMailboxNewCommand(ControllerBaseAddress);
1485       while (!DAC960_GEM_HardwareMailboxStatusAvailableP(ControllerBaseAddress))
1486         udelay(1);
1487       CommandStatus = DAC960_GEM_ReadCommandStatus(ControllerBaseAddress);
1488       DAC960_GEM_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress);
1489       DAC960_GEM_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress);
1490       break;
1491     case DAC960_BA_Controller:
1492       while (DAC960_BA_HardwareMailboxFullP(ControllerBaseAddress))
1493         udelay(1);
1494       DAC960_BA_WriteHardwareMailbox(ControllerBaseAddress, CommandMailboxDMA);
1495       DAC960_BA_HardwareMailboxNewCommand(ControllerBaseAddress);
1496       while (!DAC960_BA_HardwareMailboxStatusAvailableP(ControllerBaseAddress))
1497         udelay(1);
1498       CommandStatus = DAC960_BA_ReadCommandStatus(ControllerBaseAddress);
1499       DAC960_BA_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress);
1500       DAC960_BA_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress);
1501       break;
1502     case DAC960_LP_Controller:
1503       while (DAC960_LP_HardwareMailboxFullP(ControllerBaseAddress))
1504         udelay(1);
1505       DAC960_LP_WriteHardwareMailbox(ControllerBaseAddress, CommandMailboxDMA);
1506       DAC960_LP_HardwareMailboxNewCommand(ControllerBaseAddress);
1507       while (!DAC960_LP_HardwareMailboxStatusAvailableP(ControllerBaseAddress))
1508         udelay(1);
1509       CommandStatus = DAC960_LP_ReadCommandStatus(ControllerBaseAddress);
1510       DAC960_LP_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress);
1511       DAC960_LP_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress);
1512       break;
1513     default:
1514       DAC960_Failure(Controller, "Unknown Controller Type\n");
1515       CommandStatus = DAC960_V2_AbormalCompletion;
1516       break;
1517     }
1518   pci_free_consistent(PCI_Device, sizeof(DAC960_V2_CommandMailbox_T),
1519                                         CommandMailbox, CommandMailboxDMA);
1520   return (CommandStatus == DAC960_V2_NormalCompletion);
1521 }
1522
1523
1524 /*
1525   DAC960_V1_ReadControllerConfiguration reads the Configuration Information
1526   from DAC960 V1 Firmware Controllers and initializes the Controller structure.
1527 */
1528
1529 static boolean DAC960_V1_ReadControllerConfiguration(DAC960_Controller_T
1530                                                      *Controller)
1531 {
1532   DAC960_V1_Enquiry2_T *Enquiry2;
1533   dma_addr_t Enquiry2DMA;
1534   DAC960_V1_Config2_T *Config2;
1535   dma_addr_t Config2DMA;
1536   int LogicalDriveNumber, Channel, TargetID;
1537   struct dma_loaf local_dma;
1538
1539   if (!init_dma_loaf(Controller->PCIDevice, &local_dma,
1540                 sizeof(DAC960_V1_Enquiry2_T) + sizeof(DAC960_V1_Config2_T)))
1541         return DAC960_Failure(Controller, "LOGICAL DEVICE ALLOCATION");
1542
1543   Enquiry2 = slice_dma_loaf(&local_dma, sizeof(DAC960_V1_Enquiry2_T), &Enquiry2DMA);
1544   Config2 = slice_dma_loaf(&local_dma, sizeof(DAC960_V1_Config2_T), &Config2DMA);
1545
1546   if (!DAC960_V1_ExecuteType3(Controller, DAC960_V1_Enquiry,
1547                               Controller->V1.NewEnquiryDMA)) {
1548     free_dma_loaf(Controller->PCIDevice, &local_dma);
1549     return DAC960_Failure(Controller, "ENQUIRY");
1550   }
1551   memcpy(&Controller->V1.Enquiry, Controller->V1.NewEnquiry,
1552                                                 sizeof(DAC960_V1_Enquiry_T));
1553
1554   if (!DAC960_V1_ExecuteType3(Controller, DAC960_V1_Enquiry2, Enquiry2DMA)) {
1555     free_dma_loaf(Controller->PCIDevice, &local_dma);
1556     return DAC960_Failure(Controller, "ENQUIRY2");
1557   }
1558
1559   if (!DAC960_V1_ExecuteType3(Controller, DAC960_V1_ReadConfig2, Config2DMA)) {
1560     free_dma_loaf(Controller->PCIDevice, &local_dma);
1561     return DAC960_Failure(Controller, "READ CONFIG2");
1562   }
1563
1564   if (!DAC960_V1_ExecuteType3(Controller, DAC960_V1_GetLogicalDriveInformation,
1565                               Controller->V1.NewLogicalDriveInformationDMA)) {
1566     free_dma_loaf(Controller->PCIDevice, &local_dma);
1567     return DAC960_Failure(Controller, "GET LOGICAL DRIVE INFORMATION");
1568   }
1569   memcpy(&Controller->V1.LogicalDriveInformation,
1570                 Controller->V1.NewLogicalDriveInformation,
1571                 sizeof(DAC960_V1_LogicalDriveInformationArray_T));
1572
1573   for (Channel = 0; Channel < Enquiry2->ActualChannels; Channel++)
1574     for (TargetID = 0; TargetID < Enquiry2->MaxTargets; TargetID++) {
1575       if (!DAC960_V1_ExecuteType3D(Controller, DAC960_V1_GetDeviceState,
1576                                    Channel, TargetID,
1577                                    Controller->V1.NewDeviceStateDMA)) {
1578                 free_dma_loaf(Controller->PCIDevice, &local_dma);
1579                 return DAC960_Failure(Controller, "GET DEVICE STATE");
1580         }
1581         memcpy(&Controller->V1.DeviceState[Channel][TargetID],
1582                 Controller->V1.NewDeviceState, sizeof(DAC960_V1_DeviceState_T));
1583      }
1584   /*
1585     Initialize the Controller Model Name and Full Model Name fields.
1586   */
1587   switch (Enquiry2->HardwareID.SubModel)
1588     {
1589     case DAC960_V1_P_PD_PU:
1590       if (Enquiry2->SCSICapability.BusSpeed == DAC960_V1_Ultra)
1591         strcpy(Controller->ModelName, "DAC960PU");
1592       else strcpy(Controller->ModelName, "DAC960PD");
1593       break;
1594     case DAC960_V1_PL:
1595       strcpy(Controller->ModelName, "DAC960PL");
1596       break;
1597     case DAC960_V1_PG:
1598       strcpy(Controller->ModelName, "DAC960PG");
1599       break;
1600     case DAC960_V1_PJ:
1601       strcpy(Controller->ModelName, "DAC960PJ");
1602       break;
1603     case DAC960_V1_PR:
1604       strcpy(Controller->ModelName, "DAC960PR");
1605       break;
1606     case DAC960_V1_PT:
1607       strcpy(Controller->ModelName, "DAC960PT");
1608       break;
1609     case DAC960_V1_PTL0:
1610       strcpy(Controller->ModelName, "DAC960PTL0");
1611       break;
1612     case DAC960_V1_PRL:
1613       strcpy(Controller->ModelName, "DAC960PRL");
1614       break;
1615     case DAC960_V1_PTL1:
1616       strcpy(Controller->ModelName, "DAC960PTL1");
1617       break;
1618     case DAC960_V1_1164P:
1619       strcpy(Controller->ModelName, "DAC1164P");
1620       break;
1621     default:
1622       free_dma_loaf(Controller->PCIDevice, &local_dma);
1623       return DAC960_Failure(Controller, "MODEL VERIFICATION");
1624     }
1625   strcpy(Controller->FullModelName, "Mylex ");
1626   strcat(Controller->FullModelName, Controller->ModelName);
1627   /*
1628     Initialize the Controller Firmware Version field and verify that it
1629     is a supported firmware version.  The supported firmware versions are:
1630
1631     DAC1164P                5.06 and above
1632     DAC960PTL/PRL/PJ/PG     4.06 and above
1633     DAC960PU/PD/PL          3.51 and above
1634     DAC960PU/PD/PL/P        2.73 and above
1635   */
1636 #if defined(CONFIG_ALPHA)
1637   /*
1638     DEC Alpha machines were often equipped with DAC960 cards that were
1639     OEMed from Mylex, and had their own custom firmware. Version 2.70,
1640     the last custom FW revision to be released by DEC for these older
1641     controllers, appears to work quite well with this driver.
1642
1643     Cards tested successfully were several versions each of the PD and
1644     PU, called by DEC the KZPSC and KZPAC, respectively, and having
1645     the Manufacturer Numbers (from Mylex), usually on a sticker on the
1646     back of the board, of:
1647
1648     KZPSC:  D040347 (1-channel) or D040348 (2-channel) or D040349 (3-channel)
1649     KZPAC:  D040395 (1-channel) or D040396 (2-channel) or D040397 (3-channel)
1650   */
1651 # define FIRMWARE_27X   "2.70"
1652 #else
1653 # define FIRMWARE_27X   "2.73"
1654 #endif
1655
1656   if (Enquiry2->FirmwareID.MajorVersion == 0)
1657     {
1658       Enquiry2->FirmwareID.MajorVersion =
1659         Controller->V1.Enquiry.MajorFirmwareVersion;
1660       Enquiry2->FirmwareID.MinorVersion =
1661         Controller->V1.Enquiry.MinorFirmwareVersion;
1662       Enquiry2->FirmwareID.FirmwareType = '0';
1663       Enquiry2->FirmwareID.TurnID = 0;
1664     }
1665   sprintf(Controller->FirmwareVersion, "%d.%02d-%c-%02d",
1666           Enquiry2->FirmwareID.MajorVersion, Enquiry2->FirmwareID.MinorVersion,
1667           Enquiry2->FirmwareID.FirmwareType, Enquiry2->FirmwareID.TurnID);
1668   if (!((Controller->FirmwareVersion[0] == '5' &&
1669          strcmp(Controller->FirmwareVersion, "5.06") >= 0) ||
1670         (Controller->FirmwareVersion[0] == '4' &&
1671          strcmp(Controller->FirmwareVersion, "4.06") >= 0) ||
1672         (Controller->FirmwareVersion[0] == '3' &&
1673          strcmp(Controller->FirmwareVersion, "3.51") >= 0) ||
1674         (Controller->FirmwareVersion[0] == '2' &&
1675          strcmp(Controller->FirmwareVersion, FIRMWARE_27X) >= 0)))
1676     {
1677       DAC960_Failure(Controller, "FIRMWARE VERSION VERIFICATION");
1678       DAC960_Error("Firmware Version = '%s'\n", Controller,
1679                    Controller->FirmwareVersion);
1680       free_dma_loaf(Controller->PCIDevice, &local_dma);
1681       return false;
1682     }
1683   /*
1684     Initialize the Controller Channels, Targets, Memory Size, and SAF-TE
1685     Enclosure Management Enabled fields.
1686   */
1687   Controller->Channels = Enquiry2->ActualChannels;
1688   Controller->Targets = Enquiry2->MaxTargets;
1689   Controller->MemorySize = Enquiry2->MemorySize >> 20;
1690   Controller->V1.SAFTE_EnclosureManagementEnabled =
1691     (Enquiry2->FaultManagementType == DAC960_V1_SAFTE);
1692   /*
1693     Initialize the Controller Queue Depth, Driver Queue Depth, Logical Drive
1694     Count, Maximum Blocks per Command, Controller Scatter/Gather Limit, and
1695     Driver Scatter/Gather Limit.  The Driver Queue Depth must be at most one
1696     less than the Controller Queue Depth to allow for an automatic drive
1697     rebuild operation.
1698   */
1699   Controller->ControllerQueueDepth = Controller->V1.Enquiry.MaxCommands;
1700   Controller->DriverQueueDepth = Controller->ControllerQueueDepth - 1;
1701   if (Controller->DriverQueueDepth > DAC960_MaxDriverQueueDepth)
1702     Controller->DriverQueueDepth = DAC960_MaxDriverQueueDepth;
1703   Controller->LogicalDriveCount =
1704     Controller->V1.Enquiry.NumberOfLogicalDrives;
1705   Controller->MaxBlocksPerCommand = Enquiry2->MaxBlocksPerCommand;
1706   Controller->ControllerScatterGatherLimit = Enquiry2->MaxScatterGatherEntries;
1707   Controller->DriverScatterGatherLimit =
1708     Controller->ControllerScatterGatherLimit;
1709   if (Controller->DriverScatterGatherLimit > DAC960_V1_ScatterGatherLimit)
1710     Controller->DriverScatterGatherLimit = DAC960_V1_ScatterGatherLimit;
1711   /*
1712     Initialize the Stripe Size, Segment Size, and Geometry Translation.
1713   */
1714   Controller->V1.StripeSize = Config2->BlocksPerStripe * Config2->BlockFactor
1715                               >> (10 - DAC960_BlockSizeBits);
1716   Controller->V1.SegmentSize = Config2->BlocksPerCacheLine * Config2->BlockFactor
1717                                >> (10 - DAC960_BlockSizeBits);
1718   switch (Config2->DriveGeometry)
1719     {
1720     case DAC960_V1_Geometry_128_32:
1721       Controller->V1.GeometryTranslationHeads = 128;
1722       Controller->V1.GeometryTranslationSectors = 32;
1723       break;
1724     case DAC960_V1_Geometry_255_63:
1725       Controller->V1.GeometryTranslationHeads = 255;
1726       Controller->V1.GeometryTranslationSectors = 63;
1727       break;
1728     default:
1729       free_dma_loaf(Controller->PCIDevice, &local_dma);
1730       return DAC960_Failure(Controller, "CONFIG2 DRIVE GEOMETRY");
1731     }
1732   /*
1733     Initialize the Background Initialization Status.
1734   */
1735   if ((Controller->FirmwareVersion[0] == '4' &&
1736       strcmp(Controller->FirmwareVersion, "4.08") >= 0) ||
1737       (Controller->FirmwareVersion[0] == '5' &&
1738        strcmp(Controller->FirmwareVersion, "5.08") >= 0))
1739     {
1740       Controller->V1.BackgroundInitializationStatusSupported = true;
1741       DAC960_V1_ExecuteType3B(Controller,
1742                               DAC960_V1_BackgroundInitializationControl, 0x20,
1743                               Controller->
1744                                V1.BackgroundInitializationStatusDMA);
1745       memcpy(&Controller->V1.LastBackgroundInitializationStatus,
1746                 Controller->V1.BackgroundInitializationStatus,
1747                 sizeof(DAC960_V1_BackgroundInitializationStatus_T));
1748     }
1749   /*
1750     Initialize the Logical Drive Initially Accessible flag.
1751   */
1752   for (LogicalDriveNumber = 0;
1753        LogicalDriveNumber < Controller->LogicalDriveCount;
1754        LogicalDriveNumber++)
1755     if (Controller->V1.LogicalDriveInformation
1756                        [LogicalDriveNumber].LogicalDriveState !=
1757         DAC960_V1_LogicalDrive_Offline)
1758       Controller->LogicalDriveInitiallyAccessible[LogicalDriveNumber] = true;
1759   Controller->V1.LastRebuildStatus = DAC960_V1_NoRebuildOrCheckInProgress;
1760   free_dma_loaf(Controller->PCIDevice, &local_dma);
1761   return true;
1762 }
1763
1764
1765 /*
1766   DAC960_V2_ReadControllerConfiguration reads the Configuration Information
1767   from DAC960 V2 Firmware Controllers and initializes the Controller structure.
1768 */
1769
1770 static boolean DAC960_V2_ReadControllerConfiguration(DAC960_Controller_T
1771                                                      *Controller)
1772 {
1773   DAC960_V2_ControllerInfo_T *ControllerInfo =
1774                 &Controller->V2.ControllerInformation;
1775   unsigned short LogicalDeviceNumber = 0;
1776   int ModelNameLength;
1777
1778   /* Get data into dma-able area, then copy into permanant location */
1779   if (!DAC960_V2_NewControllerInfo(Controller))
1780     return DAC960_Failure(Controller, "GET CONTROLLER INFO");
1781   memcpy(ControllerInfo, Controller->V2.NewControllerInformation,
1782                         sizeof(DAC960_V2_ControllerInfo_T));
1783          
1784   
1785   if (!DAC960_V2_GeneralInfo(Controller))
1786     return DAC960_Failure(Controller, "GET HEALTH STATUS");
1787
1788   /*
1789     Initialize the Controller Model Name and Full Model Name fields.
1790   */
1791   ModelNameLength = sizeof(ControllerInfo->ControllerName);
1792   if (ModelNameLength > sizeof(Controller->ModelName)-1)
1793     ModelNameLength = sizeof(Controller->ModelName)-1;
1794   memcpy(Controller->ModelName, ControllerInfo->ControllerName,
1795          ModelNameLength);
1796   ModelNameLength--;
1797   while (Controller->ModelName[ModelNameLength] == ' ' ||
1798          Controller->ModelName[ModelNameLength] == '\0')
1799     ModelNameLength--;
1800   Controller->ModelName[++ModelNameLength] = '\0';
1801   strcpy(Controller->FullModelName, "Mylex ");
1802   strcat(Controller->FullModelName, Controller->ModelName);
1803   /*
1804     Initialize the Controller Firmware Version field.
1805   */
1806   sprintf(Controller->FirmwareVersion, "%d.%02d-%02d",
1807           ControllerInfo->FirmwareMajorVersion,
1808           ControllerInfo->FirmwareMinorVersion,
1809           ControllerInfo->FirmwareTurnNumber);
1810   if (ControllerInfo->FirmwareMajorVersion == 6 &&
1811       ControllerInfo->FirmwareMinorVersion == 0 &&
1812       ControllerInfo->FirmwareTurnNumber < 1)
1813     {
1814       DAC960_Info("FIRMWARE VERSION %s DOES NOT PROVIDE THE CONTROLLER\n",
1815                   Controller, Controller->FirmwareVersion);
1816       DAC960_Info("STATUS MONITORING FUNCTIONALITY NEEDED BY THIS DRIVER.\n",
1817                   Controller);
1818       DAC960_Info("PLEASE UPGRADE TO VERSION 6.00-01 OR ABOVE.\n",
1819                   Controller);
1820     }
1821   /*
1822     Initialize the Controller Channels, Targets, and Memory Size.
1823   */
1824   Controller->Channels = ControllerInfo->NumberOfPhysicalChannelsPresent;
1825   Controller->Targets =
1826     ControllerInfo->MaximumTargetsPerChannel
1827                     [ControllerInfo->NumberOfPhysicalChannelsPresent-1];
1828   Controller->MemorySize = ControllerInfo->MemorySizeMB;
1829   /*
1830     Initialize the Controller Queue Depth, Driver Queue Depth, Logical Drive
1831     Count, Maximum Blocks per Command, Controller Scatter/Gather Limit, and
1832     Driver Scatter/Gather Limit.  The Driver Queue Depth must be at most one
1833     less than the Controller Queue Depth to allow for an automatic drive
1834     rebuild operation.
1835   */
1836   Controller->ControllerQueueDepth = ControllerInfo->MaximumParallelCommands;
1837   Controller->DriverQueueDepth = Controller->ControllerQueueDepth - 1;
1838   if (Controller->DriverQueueDepth > DAC960_MaxDriverQueueDepth)
1839     Controller->DriverQueueDepth = DAC960_MaxDriverQueueDepth;
1840   Controller->LogicalDriveCount = ControllerInfo->LogicalDevicesPresent;
1841   Controller->MaxBlocksPerCommand =
1842     ControllerInfo->MaximumDataTransferSizeInBlocks;
1843   Controller->ControllerScatterGatherLimit =
1844     ControllerInfo->MaximumScatterGatherEntries;
1845   Controller->DriverScatterGatherLimit =
1846     Controller->ControllerScatterGatherLimit;
1847   if (Controller->DriverScatterGatherLimit > DAC960_V2_ScatterGatherLimit)
1848     Controller->DriverScatterGatherLimit = DAC960_V2_ScatterGatherLimit;
1849   /*
1850     Initialize the Logical Device Information.
1851   */
1852   while (true)
1853     {
1854       DAC960_V2_LogicalDeviceInfo_T *NewLogicalDeviceInfo =
1855         Controller->V2.NewLogicalDeviceInformation;
1856       DAC960_V2_LogicalDeviceInfo_T *LogicalDeviceInfo;
1857       DAC960_V2_PhysicalDevice_T PhysicalDevice;
1858
1859       if (!DAC960_V2_NewLogicalDeviceInfo(Controller, LogicalDeviceNumber))
1860         break;
1861       LogicalDeviceNumber = NewLogicalDeviceInfo->LogicalDeviceNumber;
1862       if (LogicalDeviceNumber >= DAC960_MaxLogicalDrives) {
1863         DAC960_Error("DAC960: Logical Drive Number %d not supported\n",
1864                        Controller, LogicalDeviceNumber);
1865                 break;
1866       }
1867       if (NewLogicalDeviceInfo->DeviceBlockSizeInBytes != DAC960_BlockSize) {
1868         DAC960_Error("DAC960: Logical Drive Block Size %d not supported\n",
1869               Controller, NewLogicalDeviceInfo->DeviceBlockSizeInBytes);
1870         LogicalDeviceNumber++;
1871         continue;
1872       }
1873       PhysicalDevice.Controller = 0;
1874       PhysicalDevice.Channel = NewLogicalDeviceInfo->Channel;
1875       PhysicalDevice.TargetID = NewLogicalDeviceInfo->TargetID;
1876       PhysicalDevice.LogicalUnit = NewLogicalDeviceInfo->LogicalUnit;
1877       Controller->V2.LogicalDriveToVirtualDevice[LogicalDeviceNumber] =
1878         PhysicalDevice;
1879       if (NewLogicalDeviceInfo->LogicalDeviceState !=
1880           DAC960_V2_LogicalDevice_Offline)
1881         Controller->LogicalDriveInitiallyAccessible[LogicalDeviceNumber] = true;
1882       LogicalDeviceInfo = (DAC960_V2_LogicalDeviceInfo_T *)
1883         kmalloc(sizeof(DAC960_V2_LogicalDeviceInfo_T), GFP_ATOMIC);
1884       if (LogicalDeviceInfo == NULL)
1885         return DAC960_Failure(Controller, "LOGICAL DEVICE ALLOCATION");
1886       Controller->V2.LogicalDeviceInformation[LogicalDeviceNumber] =
1887         LogicalDeviceInfo;
1888       memcpy(LogicalDeviceInfo, NewLogicalDeviceInfo,
1889              sizeof(DAC960_V2_LogicalDeviceInfo_T));
1890       LogicalDeviceNumber++;
1891     }
1892   return true;
1893 }
1894
1895
1896 /*
1897   DAC960_ReportControllerConfiguration reports the Configuration Information
1898   for Controller.
1899 */
1900
1901 static boolean DAC960_ReportControllerConfiguration(DAC960_Controller_T
1902                                                     *Controller)
1903 {
1904   DAC960_Info("Configuring Mylex %s PCI RAID Controller\n",
1905               Controller, Controller->ModelName);
1906   DAC960_Info("  Firmware Version: %s, Channels: %d, Memory Size: %dMB\n",
1907               Controller, Controller->FirmwareVersion,
1908               Controller->Channels, Controller->MemorySize);
1909   DAC960_Info("  PCI Bus: %d, Device: %d, Function: %d, I/O Address: ",
1910               Controller, Controller->Bus,
1911               Controller->Device, Controller->Function);
1912   if (Controller->IO_Address == 0)
1913     DAC960_Info("Unassigned\n", Controller);
1914   else DAC960_Info("0x%X\n", Controller, Controller->IO_Address);
1915   DAC960_Info("  PCI Address: 0x%X mapped at 0x%lX, IRQ Channel: %d\n",
1916               Controller, Controller->PCI_Address,
1917               (unsigned long) Controller->BaseAddress,
1918               Controller->IRQ_Channel);
1919   DAC960_Info("  Controller Queue Depth: %d, "
1920               "Maximum Blocks per Command: %d\n",
1921               Controller, Controller->ControllerQueueDepth,
1922               Controller->MaxBlocksPerCommand);
1923   DAC960_Info("  Driver Queue Depth: %d, "
1924               "Scatter/Gather Limit: %d of %d Segments\n",
1925               Controller, Controller->DriverQueueDepth,
1926               Controller->DriverScatterGatherLimit,
1927               Controller->ControllerScatterGatherLimit);
1928   if (Controller->FirmwareType == DAC960_V1_Controller)
1929     {
1930       DAC960_Info("  Stripe Size: %dKB, Segment Size: %dKB, "
1931                   "BIOS Geometry: %d/%d\n", Controller,
1932                   Controller->V1.StripeSize,
1933                   Controller->V1.SegmentSize,
1934                   Controller->V1.GeometryTranslationHeads,
1935                   Controller->V1.GeometryTranslationSectors);
1936       if (Controller->V1.SAFTE_EnclosureManagementEnabled)
1937         DAC960_Info("  SAF-TE Enclosure Management Enabled\n", Controller);
1938     }
1939   return true;
1940 }
1941
1942
1943 /*
1944   DAC960_V1_ReadDeviceConfiguration reads the Device Configuration Information
1945   for DAC960 V1 Firmware Controllers by requesting the SCSI Inquiry and SCSI
1946   Inquiry Unit Serial Number information for each device connected to
1947   Controller.
1948 */
1949
1950 static boolean DAC960_V1_ReadDeviceConfiguration(DAC960_Controller_T
1951                                                  *Controller)
1952 {
1953   struct dma_loaf local_dma;
1954
1955   dma_addr_t DCDBs_dma[DAC960_V1_MaxChannels];
1956   DAC960_V1_DCDB_T *DCDBs_cpu[DAC960_V1_MaxChannels];
1957
1958   dma_addr_t SCSI_Inquiry_dma[DAC960_V1_MaxChannels];
1959   DAC960_SCSI_Inquiry_T *SCSI_Inquiry_cpu[DAC960_V1_MaxChannels];
1960
1961   dma_addr_t SCSI_NewInquiryUnitSerialNumberDMA[DAC960_V1_MaxChannels];
1962   DAC960_SCSI_Inquiry_UnitSerialNumber_T *SCSI_NewInquiryUnitSerialNumberCPU[DAC960_V1_MaxChannels];
1963
1964   struct completion Completions[DAC960_V1_MaxChannels];
1965   unsigned long flags;
1966   int Channel, TargetID;
1967
1968   if (!init_dma_loaf(Controller->PCIDevice, &local_dma, 
1969                 DAC960_V1_MaxChannels*(sizeof(DAC960_V1_DCDB_T) +
1970                         sizeof(DAC960_SCSI_Inquiry_T) +
1971                         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T))))
1972      return DAC960_Failure(Controller,
1973                         "DMA ALLOCATION FAILED IN ReadDeviceConfiguration"); 
1974    
1975   for (Channel = 0; Channel < Controller->Channels; Channel++) {
1976         DCDBs_cpu[Channel] = slice_dma_loaf(&local_dma,
1977                         sizeof(DAC960_V1_DCDB_T), DCDBs_dma + Channel);
1978         SCSI_Inquiry_cpu[Channel] = slice_dma_loaf(&local_dma,
1979                         sizeof(DAC960_SCSI_Inquiry_T),
1980                         SCSI_Inquiry_dma + Channel);
1981         SCSI_NewInquiryUnitSerialNumberCPU[Channel] = slice_dma_loaf(&local_dma,
1982                         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T),
1983                         SCSI_NewInquiryUnitSerialNumberDMA + Channel);
1984   }
1985                 
1986   for (TargetID = 0; TargetID < Controller->Targets; TargetID++)
1987     {
1988       /*
1989        * For each channel, submit a probe for a device on that channel.
1990        * The timeout interval for a device that is present is 10 seconds.
1991        * With this approach, the timeout periods can elapse in parallel
1992        * on each channel.
1993        */
1994       for (Channel = 0; Channel < Controller->Channels; Channel++)
1995         {
1996           dma_addr_t NewInquiryStandardDataDMA = SCSI_Inquiry_dma[Channel];
1997           DAC960_V1_DCDB_T *DCDB = DCDBs_cpu[Channel];
1998           dma_addr_t DCDB_dma = DCDBs_dma[Channel];
1999           DAC960_Command_T *Command = Controller->Commands[Channel];
2000           struct completion *Completion = &Completions[Channel];
2001
2002           init_completion(Completion);
2003           DAC960_V1_ClearCommand(Command);
2004           Command->CommandType = DAC960_ImmediateCommand;
2005           Command->Completion = Completion;
2006           Command->V1.CommandMailbox.Type3.CommandOpcode = DAC960_V1_DCDB;
2007           Command->V1.CommandMailbox.Type3.BusAddress = DCDB_dma;
2008           DCDB->Channel = Channel;
2009           DCDB->TargetID = TargetID;
2010           DCDB->Direction = DAC960_V1_DCDB_DataTransferDeviceToSystem;
2011           DCDB->EarlyStatus = false;
2012           DCDB->Timeout = DAC960_V1_DCDB_Timeout_10_seconds;
2013           DCDB->NoAutomaticRequestSense = false;
2014           DCDB->DisconnectPermitted = true;
2015           DCDB->TransferLength = sizeof(DAC960_SCSI_Inquiry_T);
2016           DCDB->BusAddress = NewInquiryStandardDataDMA;
2017           DCDB->CDBLength = 6;
2018           DCDB->TransferLengthHigh4 = 0;
2019           DCDB->SenseLength = sizeof(DCDB->SenseData);
2020           DCDB->CDB[0] = 0x12; /* INQUIRY */
2021           DCDB->CDB[1] = 0; /* EVPD = 0 */
2022           DCDB->CDB[2] = 0; /* Page Code */
2023           DCDB->CDB[3] = 0; /* Reserved */
2024           DCDB->CDB[4] = sizeof(DAC960_SCSI_Inquiry_T);
2025           DCDB->CDB[5] = 0; /* Control */
2026
2027           spin_lock_irqsave(&Controller->queue_lock, flags);
2028           DAC960_QueueCommand(Command);
2029           spin_unlock_irqrestore(&Controller->queue_lock, flags);
2030         }
2031       /*
2032        * Wait for the problems submitted in the previous loop
2033        * to complete.  On the probes that are successful, 
2034        * get the serial number of the device that was found.
2035        */
2036       for (Channel = 0; Channel < Controller->Channels; Channel++)
2037         {
2038           DAC960_SCSI_Inquiry_T *InquiryStandardData =
2039             &Controller->V1.InquiryStandardData[Channel][TargetID];
2040           DAC960_SCSI_Inquiry_T *NewInquiryStandardData = SCSI_Inquiry_cpu[Channel];
2041           dma_addr_t NewInquiryUnitSerialNumberDMA =
2042                         SCSI_NewInquiryUnitSerialNumberDMA[Channel];
2043           DAC960_SCSI_Inquiry_UnitSerialNumber_T *NewInquiryUnitSerialNumber =
2044                         SCSI_NewInquiryUnitSerialNumberCPU[Channel];
2045           DAC960_SCSI_Inquiry_UnitSerialNumber_T *InquiryUnitSerialNumber =
2046             &Controller->V1.InquiryUnitSerialNumber[Channel][TargetID];
2047           DAC960_Command_T *Command = Controller->Commands[Channel];
2048           DAC960_V1_DCDB_T *DCDB = DCDBs_cpu[Channel];
2049           struct completion *Completion = &Completions[Channel];
2050
2051           wait_for_completion(Completion);
2052
2053           if (Command->V1.CommandStatus != DAC960_V1_NormalCompletion) {
2054             memset(InquiryStandardData, 0, sizeof(DAC960_SCSI_Inquiry_T));
2055             InquiryStandardData->PeripheralDeviceType = 0x1F;
2056             continue;
2057           } else
2058             memcpy(InquiryStandardData, NewInquiryStandardData, sizeof(DAC960_SCSI_Inquiry_T));
2059         
2060           /* Preserve Channel and TargetID values from the previous loop */
2061           Command->Completion = Completion;
2062           DCDB->TransferLength = sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T);
2063           DCDB->BusAddress = NewInquiryUnitSerialNumberDMA;
2064           DCDB->SenseLength = sizeof(DCDB->SenseData);
2065           DCDB->CDB[0] = 0x12; /* INQUIRY */
2066           DCDB->CDB[1] = 1; /* EVPD = 1 */
2067           DCDB->CDB[2] = 0x80; /* Page Code */
2068           DCDB->CDB[3] = 0; /* Reserved */
2069           DCDB->CDB[4] = sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T);
2070           DCDB->CDB[5] = 0; /* Control */
2071
2072           spin_lock_irqsave(&Controller->queue_lock, flags);
2073           DAC960_QueueCommand(Command);
2074           spin_unlock_irqrestore(&Controller->queue_lock, flags);
2075           wait_for_completion(Completion);
2076
2077           if (Command->V1.CommandStatus != DAC960_V1_NormalCompletion) {
2078                 memset(InquiryUnitSerialNumber, 0,
2079                         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T));
2080                 InquiryUnitSerialNumber->PeripheralDeviceType = 0x1F;
2081           } else
2082                 memcpy(InquiryUnitSerialNumber, NewInquiryUnitSerialNumber,
2083                         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T));
2084         }
2085     }
2086     free_dma_loaf(Controller->PCIDevice, &local_dma);
2087   return true;
2088 }
2089
2090
2091 /*
2092   DAC960_V2_ReadDeviceConfiguration reads the Device Configuration Information
2093   for DAC960 V2 Firmware Controllers by requesting the Physical Device
2094   Information and SCSI Inquiry Unit Serial Number information for each
2095   device connected to Controller.
2096 */
2097
2098 static boolean DAC960_V2_ReadDeviceConfiguration(DAC960_Controller_T
2099                                                  *Controller)
2100 {
2101   unsigned char Channel = 0, TargetID = 0, LogicalUnit = 0;
2102   unsigned short PhysicalDeviceIndex = 0;
2103
2104   while (true)
2105     {
2106       DAC960_V2_PhysicalDeviceInfo_T *NewPhysicalDeviceInfo =
2107                 Controller->V2.NewPhysicalDeviceInformation;
2108       DAC960_V2_PhysicalDeviceInfo_T *PhysicalDeviceInfo;
2109       DAC960_SCSI_Inquiry_UnitSerialNumber_T *NewInquiryUnitSerialNumber =
2110                 Controller->V2.NewInquiryUnitSerialNumber;
2111       DAC960_SCSI_Inquiry_UnitSerialNumber_T *InquiryUnitSerialNumber;
2112
2113       if (!DAC960_V2_NewPhysicalDeviceInfo(Controller, Channel, TargetID, LogicalUnit))
2114           break;
2115
2116       PhysicalDeviceInfo = (DAC960_V2_PhysicalDeviceInfo_T *)
2117                 kmalloc(sizeof(DAC960_V2_PhysicalDeviceInfo_T), GFP_ATOMIC);
2118       if (PhysicalDeviceInfo == NULL)
2119                 return DAC960_Failure(Controller, "PHYSICAL DEVICE ALLOCATION");
2120       Controller->V2.PhysicalDeviceInformation[PhysicalDeviceIndex] =
2121                 PhysicalDeviceInfo;
2122       memcpy(PhysicalDeviceInfo, NewPhysicalDeviceInfo,
2123                 sizeof(DAC960_V2_PhysicalDeviceInfo_T));
2124
2125       InquiryUnitSerialNumber = (DAC960_SCSI_Inquiry_UnitSerialNumber_T *)
2126         kmalloc(sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T), GFP_ATOMIC);
2127       if (InquiryUnitSerialNumber == NULL) {
2128         kfree(PhysicalDeviceInfo);
2129         return DAC960_Failure(Controller, "SERIAL NUMBER ALLOCATION");
2130       }
2131       Controller->V2.InquiryUnitSerialNumber[PhysicalDeviceIndex] =
2132                 InquiryUnitSerialNumber;
2133
2134       Channel = NewPhysicalDeviceInfo->Channel;
2135       TargetID = NewPhysicalDeviceInfo->TargetID;
2136       LogicalUnit = NewPhysicalDeviceInfo->LogicalUnit;
2137
2138       /*
2139          Some devices do NOT have Unit Serial Numbers.
2140          This command fails for them.  But, we still want to
2141          remember those devices are there.  Construct a
2142          UnitSerialNumber structure for the failure case.
2143       */
2144       if (!DAC960_V2_NewInquiryUnitSerialNumber(Controller, Channel, TargetID, LogicalUnit)) {
2145         memset(InquiryUnitSerialNumber, 0,
2146              sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T));
2147         InquiryUnitSerialNumber->PeripheralDeviceType = 0x1F;
2148       } else
2149         memcpy(InquiryUnitSerialNumber, NewInquiryUnitSerialNumber,
2150                 sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T));
2151
2152       PhysicalDeviceIndex++;
2153       LogicalUnit++;
2154     }
2155   return true;
2156 }
2157
2158
2159 /*
2160   DAC960_SanitizeInquiryData sanitizes the Vendor, Model, Revision, and
2161   Product Serial Number fields of the Inquiry Standard Data and Inquiry
2162   Unit Serial Number structures.
2163 */
2164
2165 static void DAC960_SanitizeInquiryData(DAC960_SCSI_Inquiry_T
2166                                          *InquiryStandardData,
2167                                        DAC960_SCSI_Inquiry_UnitSerialNumber_T
2168                                          *InquiryUnitSerialNumber,
2169                                        unsigned char *Vendor,
2170                                        unsigned char *Model,
2171                                        unsigned char *Revision,
2172                                        unsigned char *SerialNumber)
2173 {
2174   int SerialNumberLength, i;
2175   if (InquiryStandardData->PeripheralDeviceType == 0x1F) return;
2176   for (i = 0; i < sizeof(InquiryStandardData->VendorIdentification); i++)
2177     {
2178       unsigned char VendorCharacter =
2179         InquiryStandardData->VendorIdentification[i];
2180       Vendor[i] = (VendorCharacter >= ' ' && VendorCharacter <= '~'
2181                    ? VendorCharacter : ' ');
2182     }
2183   Vendor[sizeof(InquiryStandardData->VendorIdentification)] = '\0';
2184   for (i = 0; i < sizeof(InquiryStandardData->ProductIdentification); i++)
2185     {
2186       unsigned char ModelCharacter =
2187         InquiryStandardData->ProductIdentification[i];
2188       Model[i] = (ModelCharacter >= ' ' && ModelCharacter <= '~'
2189                   ? ModelCharacter : ' ');
2190     }
2191   Model[sizeof(InquiryStandardData->ProductIdentification)] = '\0';
2192   for (i = 0; i < sizeof(InquiryStandardData->ProductRevisionLevel); i++)
2193     {
2194       unsigned char RevisionCharacter =
2195         InquiryStandardData->ProductRevisionLevel[i];
2196       Revision[i] = (RevisionCharacter >= ' ' && RevisionCharacter <= '~'
2197                      ? RevisionCharacter : ' ');
2198     }
2199   Revision[sizeof(InquiryStandardData->ProductRevisionLevel)] = '\0';
2200   if (InquiryUnitSerialNumber->PeripheralDeviceType == 0x1F) return;
2201   SerialNumberLength = InquiryUnitSerialNumber->PageLength;
2202   if (SerialNumberLength >
2203       sizeof(InquiryUnitSerialNumber->ProductSerialNumber))
2204     SerialNumberLength = sizeof(InquiryUnitSerialNumber->ProductSerialNumber);
2205   for (i = 0; i < SerialNumberLength; i++)
2206     {
2207       unsigned char SerialNumberCharacter =
2208         InquiryUnitSerialNumber->ProductSerialNumber[i];
2209       SerialNumber[i] =
2210         (SerialNumberCharacter >= ' ' && SerialNumberCharacter <= '~'
2211          ? SerialNumberCharacter : ' ');
2212     }
2213   SerialNumber[SerialNumberLength] = '\0';
2214 }
2215
2216
2217 /*
2218   DAC960_V1_ReportDeviceConfiguration reports the Device Configuration
2219   Information for DAC960 V1 Firmware Controllers.
2220 */
2221
2222 static boolean DAC960_V1_ReportDeviceConfiguration(DAC960_Controller_T
2223                                                    *Controller)
2224 {
2225   int LogicalDriveNumber, Channel, TargetID;
2226   DAC960_Info("  Physical Devices:\n", Controller);
2227   for (Channel = 0; Channel < Controller->Channels; Channel++)
2228     for (TargetID = 0; TargetID < Controller->Targets; TargetID++)
2229       {
2230         DAC960_SCSI_Inquiry_T *InquiryStandardData =
2231           &Controller->V1.InquiryStandardData[Channel][TargetID];
2232         DAC960_SCSI_Inquiry_UnitSerialNumber_T *InquiryUnitSerialNumber =
2233           &Controller->V1.InquiryUnitSerialNumber[Channel][TargetID];
2234         DAC960_V1_DeviceState_T *DeviceState =
2235           &Controller->V1.DeviceState[Channel][TargetID];
2236         DAC960_V1_ErrorTableEntry_T *ErrorEntry =
2237           &Controller->V1.ErrorTable.ErrorTableEntries[Channel][TargetID];
2238         char Vendor[1+sizeof(InquiryStandardData->VendorIdentification)];
2239         char Model[1+sizeof(InquiryStandardData->ProductIdentification)];
2240         char Revision[1+sizeof(InquiryStandardData->ProductRevisionLevel)];
2241         char SerialNumber[1+sizeof(InquiryUnitSerialNumber
2242                                    ->ProductSerialNumber)];
2243         if (InquiryStandardData->PeripheralDeviceType == 0x1F) continue;
2244         DAC960_SanitizeInquiryData(InquiryStandardData, InquiryUnitSerialNumber,
2245                                    Vendor, Model, Revision, SerialNumber);
2246         DAC960_Info("    %d:%d%s Vendor: %s  Model: %s  Revision: %s\n",
2247                     Controller, Channel, TargetID, (TargetID < 10 ? " " : ""),
2248                     Vendor, Model, Revision);
2249         if (InquiryUnitSerialNumber->PeripheralDeviceType != 0x1F)
2250           DAC960_Info("         Serial Number: %s\n", Controller, SerialNumber);
2251         if (DeviceState->Present &&
2252             DeviceState->DeviceType == DAC960_V1_DiskType)
2253           {
2254             if (Controller->V1.DeviceResetCount[Channel][TargetID] > 0)
2255               DAC960_Info("         Disk Status: %s, %u blocks, %d resets\n",
2256                           Controller,
2257                           (DeviceState->DeviceState == DAC960_V1_Device_Dead
2258                            ? "Dead"
2259                            : DeviceState->DeviceState
2260                              == DAC960_V1_Device_WriteOnly
2261                              ? "Write-Only"
2262                              : DeviceState->DeviceState
2263                                == DAC960_V1_Device_Online
2264                                ? "Online" : "Standby"),
2265                           DeviceState->DiskSize,
2266                           Controller->V1.DeviceResetCount[Channel][TargetID]);
2267             else
2268               DAC960_Info("         Disk Status: %s, %u blocks\n", Controller,
2269                           (DeviceState->DeviceState == DAC960_V1_Device_Dead
2270                            ? "Dead"
2271                            : DeviceState->DeviceState
2272                              == DAC960_V1_Device_WriteOnly
2273                              ? "Write-Only"
2274                              : DeviceState->DeviceState
2275                                == DAC960_V1_Device_Online
2276                                ? "Online" : "Standby"),
2277                           DeviceState->DiskSize);
2278           }
2279         if (ErrorEntry->ParityErrorCount > 0 ||
2280             ErrorEntry->SoftErrorCount > 0 ||
2281             ErrorEntry->HardErrorCount > 0 ||
2282             ErrorEntry->MiscErrorCount > 0)
2283           DAC960_Info("         Errors - Parity: %d, Soft: %d, "
2284                       "Hard: %d, Misc: %d\n", Controller,
2285                       ErrorEntry->ParityErrorCount,
2286                       ErrorEntry->SoftErrorCount,
2287                       ErrorEntry->HardErrorCount,
2288                       ErrorEntry->MiscErrorCount);
2289       }
2290   DAC960_Info("  Logical Drives:\n", Controller);
2291   for (LogicalDriveNumber = 0;
2292        LogicalDriveNumber < Controller->LogicalDriveCount;
2293        LogicalDriveNumber++)
2294     {
2295       DAC960_V1_LogicalDriveInformation_T *LogicalDriveInformation =
2296         &Controller->V1.LogicalDriveInformation[LogicalDriveNumber];
2297       DAC960_Info("    /dev/rd/c%dd%d: RAID-%d, %s, %u blocks, %s\n",
2298                   Controller, Controller->ControllerNumber, LogicalDriveNumber,
2299                   LogicalDriveInformation->RAIDLevel,
2300                   (LogicalDriveInformation->LogicalDriveState
2301                    == DAC960_V1_LogicalDrive_Online
2302                    ? "Online"
2303                    : LogicalDriveInformation->LogicalDriveState
2304                      == DAC960_V1_LogicalDrive_Critical
2305                      ? "Critical" : "Offline"),
2306                   LogicalDriveInformation->LogicalDriveSize,
2307                   (LogicalDriveInformation->WriteBack
2308                    ? "Write Back" : "Write Thru"));
2309     }
2310   return true;
2311 }
2312
2313
2314 /*
2315   DAC960_V2_ReportDeviceConfiguration reports the Device Configuration
2316   Information for DAC960 V2 Firmware Controllers.
2317 */
2318
2319 static boolean DAC960_V2_ReportDeviceConfiguration(DAC960_Controller_T
2320                                                    *Controller)
2321 {
2322   int PhysicalDeviceIndex, LogicalDriveNumber;
2323   DAC960_Info("  Physical Devices:\n", Controller);
2324   for (PhysicalDeviceIndex = 0;
2325        PhysicalDeviceIndex < DAC960_V2_MaxPhysicalDevices;
2326        PhysicalDeviceIndex++)
2327     {
2328       DAC960_V2_PhysicalDeviceInfo_T *PhysicalDeviceInfo =
2329         Controller->V2.PhysicalDeviceInformation[PhysicalDeviceIndex];
2330       DAC960_SCSI_Inquiry_T *InquiryStandardData =
2331         (DAC960_SCSI_Inquiry_T *) &PhysicalDeviceInfo->SCSI_InquiryData;
2332       DAC960_SCSI_Inquiry_UnitSerialNumber_T *InquiryUnitSerialNumber =
2333         Controller->V2.InquiryUnitSerialNumber[PhysicalDeviceIndex];
2334       char Vendor[1+sizeof(InquiryStandardData->VendorIdentification)];
2335       char Model[1+sizeof(InquiryStandardData->ProductIdentification)];
2336       char Revision[1+sizeof(InquiryStandardData->ProductRevisionLevel)];
2337       char SerialNumber[1+sizeof(InquiryUnitSerialNumber->ProductSerialNumber)];
2338       if (PhysicalDeviceInfo == NULL) break;
2339       DAC960_SanitizeInquiryData(InquiryStandardData, InquiryUnitSerialNumber,
2340                                  Vendor, Model, Revision, SerialNumber);
2341       DAC960_Info("    %d:%d%s Vendor: %s  Model: %s  Revision: %s\n",
2342                   Controller,
2343                   PhysicalDeviceInfo->Channel,
2344                   PhysicalDeviceInfo->TargetID,
2345                   (PhysicalDeviceInfo->TargetID < 10 ? " " : ""),
2346                   Vendor, Model, Revision);
2347       if (PhysicalDeviceInfo->NegotiatedSynchronousMegaTransfers == 0)
2348         DAC960_Info("         %sAsynchronous\n", Controller,
2349                     (PhysicalDeviceInfo->NegotiatedDataWidthBits == 16
2350                      ? "Wide " :""));
2351       else
2352         DAC960_Info("         %sSynchronous at %d MB/sec\n", Controller,
2353                     (PhysicalDeviceInfo->NegotiatedDataWidthBits == 16
2354                      ? "Wide " :""),
2355                     (PhysicalDeviceInfo->NegotiatedSynchronousMegaTransfers
2356                      * PhysicalDeviceInfo->NegotiatedDataWidthBits/8));
2357       if (InquiryUnitSerialNumber->PeripheralDeviceType != 0x1F)
2358         DAC960_Info("         Serial Number: %s\n", Controller, SerialNumber);
2359       if (PhysicalDeviceInfo->PhysicalDeviceState ==
2360           DAC960_V2_Device_Unconfigured)
2361         continue;
2362       DAC960_Info("         Disk Status: %s, %u blocks\n", Controller,
2363                   (PhysicalDeviceInfo->PhysicalDeviceState
2364                    == DAC960_V2_Device_Online
2365                    ? "Online"
2366                    : PhysicalDeviceInfo->PhysicalDeviceState
2367                      == DAC960_V2_Device_Rebuild
2368                      ? "Rebuild"
2369                      : PhysicalDeviceInfo->PhysicalDeviceState
2370                        == DAC960_V2_Device_Missing
2371                        ? "Missing"
2372                        : PhysicalDeviceInfo->PhysicalDeviceState
2373                          == DAC960_V2_Device_Critical
2374                          ? "Critical"
2375                          : PhysicalDeviceInfo->PhysicalDeviceState
2376                            == DAC960_V2_Device_Dead
2377                            ? "Dead"
2378                            : PhysicalDeviceInfo->PhysicalDeviceState
2379                              == DAC960_V2_Device_SuspectedDead
2380                              ? "Suspected-Dead"
2381                              : PhysicalDeviceInfo->PhysicalDeviceState
2382                                == DAC960_V2_Device_CommandedOffline
2383                                ? "Commanded-Offline"
2384                                : PhysicalDeviceInfo->PhysicalDeviceState
2385                                  == DAC960_V2_Device_Standby
2386                                  ? "Standby" : "Unknown"),
2387                   PhysicalDeviceInfo->ConfigurableDeviceSize);
2388       if (PhysicalDeviceInfo->ParityErrors == 0 &&
2389           PhysicalDeviceInfo->SoftErrors == 0 &&
2390           PhysicalDeviceInfo->HardErrors == 0 &&
2391           PhysicalDeviceInfo->MiscellaneousErrors == 0 &&
2392           PhysicalDeviceInfo->CommandTimeouts == 0 &&
2393           PhysicalDeviceInfo->Retries == 0 &&
2394           PhysicalDeviceInfo->Aborts == 0 &&
2395           PhysicalDeviceInfo->PredictedFailuresDetected == 0)
2396         continue;
2397       DAC960_Info("         Errors - Parity: %d, Soft: %d, "
2398                   "Hard: %d, Misc: %d\n", Controller,
2399                   PhysicalDeviceInfo->ParityErrors,
2400                   PhysicalDeviceInfo->SoftErrors,
2401                   PhysicalDeviceInfo->HardErrors,
2402                   PhysicalDeviceInfo->MiscellaneousErrors);
2403       DAC960_Info("                  Timeouts: %d, Retries: %d, "
2404                   "Aborts: %d, Predicted: %d\n", Controller,
2405                   PhysicalDeviceInfo->CommandTimeouts,
2406                   PhysicalDeviceInfo->Retries,
2407                   PhysicalDeviceInfo->Aborts,
2408                   PhysicalDeviceInfo->PredictedFailuresDetected);
2409     }
2410   DAC960_Info("  Logical Drives:\n", Controller);
2411   for (LogicalDriveNumber = 0;
2412        LogicalDriveNumber < DAC960_MaxLogicalDrives;
2413        LogicalDriveNumber++)
2414     {
2415       DAC960_V2_LogicalDeviceInfo_T *LogicalDeviceInfo =
2416         Controller->V2.LogicalDeviceInformation[LogicalDriveNumber];
2417       unsigned char *ReadCacheStatus[] = { "Read Cache Disabled",
2418                                            "Read Cache Enabled",
2419                                            "Read Ahead Enabled",
2420                                            "Intelligent Read Ahead Enabled",
2421                                            "-", "-", "-", "-" };
2422       unsigned char *WriteCacheStatus[] = { "Write Cache Disabled",
2423                                             "Logical Device Read Only",
2424                                             "Write Cache Enabled",
2425                                             "Intelligent Write Cache Enabled",
2426                                             "-", "-", "-", "-" };
2427       unsigned char *GeometryTranslation;
2428       if (LogicalDeviceInfo == NULL) continue;
2429       switch (LogicalDeviceInfo->DriveGeometry)
2430         {
2431         case DAC960_V2_Geometry_128_32:
2432           GeometryTranslation = "128/32";
2433           break;
2434         case DAC960_V2_Geometry_255_63:
2435           GeometryTranslation = "255/63";
2436           break;
2437         default:
2438           GeometryTranslation = "Invalid";
2439           DAC960_Error("Illegal Logical Device Geometry %d\n",
2440                        Controller, LogicalDeviceInfo->DriveGeometry);
2441           break;
2442         }
2443       DAC960_Info("    /dev/rd/c%dd%d: RAID-%d, %s, %u blocks\n",
2444                   Controller, Controller->ControllerNumber, LogicalDriveNumber,
2445                   LogicalDeviceInfo->RAIDLevel,
2446                   (LogicalDeviceInfo->LogicalDeviceState
2447                    == DAC960_V2_LogicalDevice_Online
2448                    ? "Online"
2449                    : LogicalDeviceInfo->LogicalDeviceState
2450                      == DAC960_V2_LogicalDevice_Critical
2451                      ? "Critical" : "Offline"),
2452                   LogicalDeviceInfo->ConfigurableDeviceSize);
2453       DAC960_Info("                  Logical Device %s, BIOS Geometry: %s\n",
2454                   Controller,
2455                   (LogicalDeviceInfo->LogicalDeviceControl
2456                                      .LogicalDeviceInitialized
2457                    ? "Initialized" : "Uninitialized"),
2458                   GeometryTranslation);
2459       if (LogicalDeviceInfo->StripeSize == 0)
2460         {
2461           if (LogicalDeviceInfo->CacheLineSize == 0)
2462             DAC960_Info("                  Stripe Size: N/A, "
2463                         "Segment Size: N/A\n", Controller);
2464           else
2465             DAC960_Info("                  Stripe Size: N/A, "
2466                         "Segment Size: %dKB\n", Controller,
2467                         1 << (LogicalDeviceInfo->CacheLineSize - 2));
2468         }
2469       else
2470         {
2471           if (LogicalDeviceInfo->CacheLineSize == 0)
2472             DAC960_Info("                  Stripe Size: %dKB, "
2473                         "Segment Size: N/A\n", Controller,
2474                         1 << (LogicalDeviceInfo->StripeSize - 2));
2475           else
2476             DAC960_Info("                  Stripe Size: %dKB, "
2477                         "Segment Size: %dKB\n", Controller,
2478                         1 << (LogicalDeviceInfo->StripeSize - 2),
2479                         1 << (LogicalDeviceInfo->CacheLineSize - 2));
2480         }
2481       DAC960_Info("                  %s, %s\n", Controller,
2482                   ReadCacheStatus[
2483                     LogicalDeviceInfo->LogicalDeviceControl.ReadCache],
2484                   WriteCacheStatus[
2485                     LogicalDeviceInfo->LogicalDeviceControl.WriteCache]);
2486       if (LogicalDeviceInfo->SoftErrors > 0 ||
2487           LogicalDeviceInfo->CommandsFailed > 0 ||
2488           LogicalDeviceInfo->DeferredWriteErrors)
2489         DAC960_Info("                  Errors - Soft: %d, Failed: %d, "
2490                     "Deferred Write: %d\n", Controller,
2491                     LogicalDeviceInfo->SoftErrors,
2492                     LogicalDeviceInfo->CommandsFailed,
2493                     LogicalDeviceInfo->DeferredWriteErrors);
2494
2495     }
2496   return true;
2497 }
2498
2499 /*
2500   DAC960_RegisterBlockDevice registers the Block Device structures
2501   associated with Controller.
2502 */
2503
2504 static boolean DAC960_RegisterBlockDevice(DAC960_Controller_T *Controller)
2505 {
2506   int MajorNumber = DAC960_MAJOR + Controller->ControllerNumber;
2507   int n;
2508
2509   /*
2510     Register the Block Device Major Number for this DAC960 Controller.
2511   */
2512   if (register_blkdev(MajorNumber, "dac960") < 0)
2513       return false;
2514
2515   for (n = 0; n < DAC960_MaxLogicalDrives; n++) {
2516         struct gendisk *disk = Controller->disks[n];
2517         struct request_queue *RequestQueue;
2518
2519         /* for now, let all request queues share controller's lock */
2520         RequestQueue = blk_init_queue(DAC960_RequestFunction,&Controller->queue_lock);
2521         if (!RequestQueue) {
2522                 printk("DAC960: failure to allocate request queue\n");
2523                 continue;
2524         }
2525         Controller->RequestQueue[n] = RequestQueue;
2526         blk_queue_bounce_limit(RequestQueue, Controller->BounceBufferLimit);
2527         RequestQueue->queuedata = Controller;
2528         blk_queue_max_hw_segments(RequestQueue, Controller->DriverScatterGatherLimit);
2529         blk_queue_max_phys_segments(RequestQueue, Controller->DriverScatterGatherLimit);
2530         blk_queue_max_sectors(RequestQueue, Controller->MaxBlocksPerCommand);
2531         disk->queue = RequestQueue;
2532         sprintf(disk->disk_name, "rd/c%dd%d", Controller->ControllerNumber, n);
2533         disk->major = MajorNumber;
2534         disk->first_minor = n << DAC960_MaxPartitionsBits;
2535         disk->fops = &DAC960_BlockDeviceOperations;
2536    }
2537   /*
2538     Indicate the Block Device Registration completed successfully,
2539   */
2540   return true;
2541 }
2542
2543
2544 /*
2545   DAC960_UnregisterBlockDevice unregisters the Block Device structures
2546   associated with Controller.
2547 */
2548
2549 static void DAC960_UnregisterBlockDevice(DAC960_Controller_T *Controller)
2550 {
2551   int MajorNumber = DAC960_MAJOR + Controller->ControllerNumber;
2552   int disk;
2553
2554   /* does order matter when deleting gendisk and cleanup in request queue? */
2555   for (disk = 0; disk < DAC960_MaxLogicalDrives; disk++) {
2556         del_gendisk(Controller->disks[disk]);
2557         blk_cleanup_queue(Controller->RequestQueue[disk]);
2558         Controller->RequestQueue[disk] = NULL;
2559   }
2560
2561   /*
2562     Unregister the Block Device Major Number for this DAC960 Controller.
2563   */
2564   unregister_blkdev(MajorNumber, "dac960");
2565 }
2566
2567 /*
2568   DAC960_ComputeGenericDiskInfo computes the values for the Generic Disk
2569   Information Partition Sector Counts and Block Sizes.
2570 */
2571
2572 static void DAC960_ComputeGenericDiskInfo(DAC960_Controller_T *Controller)
2573 {
2574         int disk;
2575         for (disk = 0; disk < DAC960_MaxLogicalDrives; disk++)
2576                 set_capacity(Controller->disks[disk], disk_size(Controller, disk));
2577 }
2578
2579 /*
2580   DAC960_ReportErrorStatus reports Controller BIOS Messages passed through
2581   the Error Status Register when the driver performs the BIOS handshaking.
2582   It returns true for fatal errors and false otherwise.
2583 */
2584
2585 static boolean DAC960_ReportErrorStatus(DAC960_Controller_T *Controller,
2586                                         unsigned char ErrorStatus,
2587                                         unsigned char Parameter0,
2588                                         unsigned char Parameter1)
2589 {
2590   switch (ErrorStatus)
2591     {
2592     case 0x00:
2593       DAC960_Notice("Physical Device %d:%d Not Responding\n",
2594                     Controller, Parameter1, Parameter0);
2595       break;
2596     case 0x08:
2597       if (Controller->DriveSpinUpMessageDisplayed) break;
2598       DAC960_Notice("Spinning Up Drives\n", Controller);
2599       Controller->DriveSpinUpMessageDisplayed = true;
2600       break;
2601     case 0x30:
2602       DAC960_Notice("Configuration Checksum Error\n", Controller);
2603       break;
2604     case 0x60:
2605       DAC960_Notice("Mirror Race Recovery Failed\n", Controller);
2606       break;
2607     case 0x70:
2608       DAC960_Notice("Mirror Race Recovery In Progress\n", Controller);
2609       break;
2610     case 0x90:
2611       DAC960_Notice("Physical Device %d:%d COD Mismatch\n",
2612                     Controller, Parameter1, Parameter0);
2613       break;
2614     case 0xA0:
2615       DAC960_Notice("Logical Drive Installation Aborted\n", Controller);
2616       break;
2617     case 0xB0:
2618       DAC960_Notice("Mirror Race On A Critical Logical Drive\n", Controller);
2619       break;
2620     case 0xD0:
2621       DAC960_Notice("New Controller Configuration Found\n", Controller);
2622       break;
2623     case 0xF0:
2624       DAC960_Error("Fatal Memory Parity Error for Controller at\n", Controller);
2625       return true;
2626     default:
2627       DAC960_Error("Unknown Initialization Error %02X for Controller at\n",
2628                    Controller, ErrorStatus);
2629       return true;
2630     }
2631   return false;
2632 }
2633
2634
2635 /*
2636  * DAC960_DetectCleanup releases the resources that were allocated
2637  * during DAC960_DetectController().  DAC960_DetectController can
2638  * has several internal failure points, so not ALL resources may 
2639  * have been allocated.  It's important to free only
2640  * resources that HAVE been allocated.  The code below always
2641  * tests that the resource has been allocated before attempting to
2642  * free it.
2643  */
2644 static void DAC960_DetectCleanup(DAC960_Controller_T *Controller)
2645 {
2646   int i;
2647
2648   /* Free the memory mailbox, status, and related structures */
2649   free_dma_loaf(Controller->PCIDevice, &Controller->DmaPages);
2650   if (Controller->MemoryMappedAddress) {
2651         switch(Controller->HardwareType)
2652         {
2653                 case DAC960_GEM_Controller:
2654                         DAC960_GEM_DisableInterrupts(Controller->BaseAddress);
2655                         break;
2656                 case DAC960_BA_Controller:
2657                         DAC960_BA_DisableInterrupts(Controller->BaseAddress);
2658                         break;
2659                 case DAC960_LP_Controller:
2660                         DAC960_LP_DisableInterrupts(Controller->BaseAddress);
2661                         break;
2662                 case DAC960_LA_Controller:
2663                         DAC960_LA_DisableInterrupts(Controller->BaseAddress);
2664                         break;
2665                 case DAC960_PG_Controller:
2666                         DAC960_PG_DisableInterrupts(Controller->BaseAddress);
2667                         break;
2668                 case DAC960_PD_Controller:
2669                         DAC960_PD_DisableInterrupts(Controller->BaseAddress);
2670                         break;
2671                 case DAC960_P_Controller:
2672                         DAC960_PD_DisableInterrupts(Controller->BaseAddress);
2673                         break;
2674         }
2675         iounmap(Controller->MemoryMappedAddress);
2676   }
2677   if (Controller->IRQ_Channel)
2678         free_irq(Controller->IRQ_Channel, Controller);
2679   if (Controller->IO_Address)
2680         release_region(Controller->IO_Address, 0x80);
2681   pci_disable_device(Controller->PCIDevice);
2682   for (i = 0; (i < DAC960_MaxLogicalDrives) && Controller->disks[i]; i++)
2683        put_disk(Controller->disks[i]);
2684   DAC960_Controllers[Controller->ControllerNumber] = NULL;
2685   kfree(Controller);
2686 }
2687
2688
2689 /*
2690   DAC960_DetectController detects Mylex DAC960/AcceleRAID/eXtremeRAID
2691   PCI RAID Controllers by interrogating the PCI Configuration Space for
2692   Controller Type.
2693 */
2694
2695 static DAC960_Controller_T * 
2696 DAC960_DetectController(struct pci_dev *PCI_Device,
2697                         const struct pci_device_id *entry)
2698 {
2699   struct DAC960_privdata *privdata =
2700                 (struct DAC960_privdata *)entry->driver_data;
2701   irq_handler_t InterruptHandler = privdata->InterruptHandler;
2702   unsigned int MemoryWindowSize = privdata->MemoryWindowSize;
2703   DAC960_Controller_T *Controller = NULL;
2704   unsigned char DeviceFunction = PCI_Device->devfn;
2705   unsigned char ErrorStatus, Parameter0, Parameter1;
2706   unsigned int IRQ_Channel;
2707   void __iomem *BaseAddress;
2708   int i;
2709
2710   Controller = kzalloc(sizeof(DAC960_Controller_T), GFP_ATOMIC);
2711   if (Controller == NULL) {
2712         DAC960_Error("Unable to allocate Controller structure for "
2713                        "Controller at\n", NULL);
2714         return NULL;
2715   }
2716   Controller->ControllerNumber = DAC960_ControllerCount;
2717   DAC960_Controllers[DAC960_ControllerCount++] = Controller;
2718   Controller->Bus = PCI_Device->bus->number;
2719   Controller->FirmwareType = privdata->FirmwareType;
2720   Controller->HardwareType = privdata->HardwareType;
2721   Controller->Device = DeviceFunction >> 3;
2722   Controller->Function = DeviceFunction & 0x7;
2723   Controller->PCIDevice = PCI_Device;
2724   strcpy(Controller->FullModelName, "DAC960");
2725
2726   if (pci_enable_device(PCI_Device))
2727         goto Failure;
2728
2729   switch (Controller->HardwareType)
2730   {
2731         case DAC960_GEM_Controller:
2732           Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2733           break;
2734         case DAC960_BA_Controller:
2735           Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2736           break;
2737         case DAC960_LP_Controller:
2738           Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2739           break;
2740         case DAC960_LA_Controller:
2741           Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2742           break;
2743         case DAC960_PG_Controller:
2744           Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2745           break;
2746         case DAC960_PD_Controller:
2747           Controller->IO_Address = pci_resource_start(PCI_Device, 0);
2748           Controller->PCI_Address = pci_resource_start(PCI_Device, 1);
2749           break;
2750         case DAC960_P_Controller:
2751           Controller->IO_Address = pci_resource_start(PCI_Device, 0);
2752           Controller->PCI_Address = pci_resource_start(PCI_Device, 1);
2753           break;
2754   }
2755
2756   pci_set_drvdata(PCI_Device, (void *)((long)Controller->ControllerNumber));
2757   for (i = 0; i < DAC960_MaxLogicalDrives; i++) {
2758         Controller->disks[i] = alloc_disk(1<<DAC960_MaxPartitionsBits);
2759         if (!Controller->disks[i])
2760                 goto Failure;
2761         Controller->disks[i]->private_data = (void *)((long)i);
2762   }
2763   init_waitqueue_head(&Controller->CommandWaitQueue);
2764   init_waitqueue_head(&Controller->HealthStatusWaitQueue);
2765   spin_lock_init(&Controller->queue_lock);
2766   DAC960_AnnounceDriver(Controller);
2767   /*
2768     Map the Controller Register Window.
2769   */
2770  if (MemoryWindowSize < PAGE_SIZE)
2771         MemoryWindowSize = PAGE_SIZE;
2772   Controller->MemoryMappedAddress =
2773         ioremap_nocache(Controller->PCI_Address & PAGE_MASK, MemoryWindowSize);
2774   Controller->BaseAddress =
2775         Controller->MemoryMappedAddress + (Controller->PCI_Address & ~PAGE_MASK);
2776   if (Controller->MemoryMappedAddress == NULL)
2777   {
2778           DAC960_Error("Unable to map Controller Register Window for "
2779                        "Controller at\n", Controller);
2780           goto Failure;
2781   }
2782   BaseAddress = Controller->BaseAddress;
2783   switch (Controller->HardwareType)
2784   {
2785         case DAC960_GEM_Controller:
2786           DAC960_GEM_DisableInterrupts(BaseAddress);
2787           DAC960_GEM_AcknowledgeHardwareMailboxStatus(BaseAddress);
2788           udelay(1000);
2789           while (DAC960_GEM_InitializationInProgressP(BaseAddress))
2790             {
2791               if (DAC960_GEM_ReadErrorStatus(BaseAddress, &ErrorStatus,
2792                                             &Parameter0, &Parameter1) &&
2793                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2794                                            Parameter0, Parameter1))
2795                 goto Failure;
2796               udelay(10);
2797             }
2798           if (!DAC960_V2_EnableMemoryMailboxInterface(Controller))
2799             {
2800               DAC960_Error("Unable to Enable Memory Mailbox Interface "
2801                            "for Controller at\n", Controller);
2802               goto Failure;
2803             }
2804           DAC960_GEM_EnableInterrupts(BaseAddress);
2805           Controller->QueueCommand = DAC960_GEM_QueueCommand;
2806           Controller->ReadControllerConfiguration =
2807             DAC960_V2_ReadControllerConfiguration;
2808           Controller->ReadDeviceConfiguration =
2809             DAC960_V2_ReadDeviceConfiguration;
2810           Controller->ReportDeviceConfiguration =
2811             DAC960_V2_ReportDeviceConfiguration;
2812           Controller->QueueReadWriteCommand =
2813             DAC960_V2_QueueReadWriteCommand;
2814           break;
2815         case DAC960_BA_Controller:
2816           DAC960_BA_DisableInterrupts(BaseAddress);
2817           DAC960_BA_AcknowledgeHardwareMailboxStatus(BaseAddress);
2818           udelay(1000);
2819           while (DAC960_BA_InitializationInProgressP(BaseAddress))
2820             {
2821               if (DAC960_BA_ReadErrorStatus(BaseAddress, &ErrorStatus,
2822                                             &Parameter0, &Parameter1) &&
2823                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2824                                            Parameter0, Parameter1))
2825                 goto Failure;
2826               udelay(10);
2827             }
2828           if (!DAC960_V2_EnableMemoryMailboxInterface(Controller))
2829             {
2830               DAC960_Error("Unable to Enable Memory Mailbox Interface "
2831                            "for Controller at\n", Controller);
2832               goto Failure;
2833             }
2834           DAC960_BA_EnableInterrupts(BaseAddress);
2835           Controller->QueueCommand = DAC960_BA_QueueCommand;
2836           Controller->ReadControllerConfiguration =
2837             DAC960_V2_ReadControllerConfiguration;
2838           Controller->ReadDeviceConfiguration =
2839             DAC960_V2_ReadDeviceConfiguration;
2840           Controller->ReportDeviceConfiguration =
2841             DAC960_V2_ReportDeviceConfiguration;
2842           Controller->QueueReadWriteCommand =
2843             DAC960_V2_QueueReadWriteCommand;
2844           break;
2845         case DAC960_LP_Controller:
2846           DAC960_LP_DisableInterrupts(BaseAddress);
2847           DAC960_LP_AcknowledgeHardwareMailboxStatus(BaseAddress);
2848           udelay(1000);
2849           while (DAC960_LP_InitializationInProgressP(BaseAddress))
2850             {
2851               if (DAC960_LP_ReadErrorStatus(BaseAddress, &ErrorStatus,
2852                                             &Parameter0, &Parameter1) &&
2853                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2854                                            Parameter0, Parameter1))
2855                 goto Failure;
2856               udelay(10);
2857             }
2858           if (!DAC960_V2_EnableMemoryMailboxInterface(Controller))
2859             {
2860               DAC960_Error("Unable to Enable Memory Mailbox Interface "
2861                            "for Controller at\n", Controller);
2862               goto Failure;
2863             }
2864           DAC960_LP_EnableInterrupts(BaseAddress);
2865           Controller->QueueCommand = DAC960_LP_QueueCommand;
2866           Controller->ReadControllerConfiguration =
2867             DAC960_V2_ReadControllerConfiguration;
2868           Controller->ReadDeviceConfiguration =
2869             DAC960_V2_ReadDeviceConfiguration;
2870           Controller->ReportDeviceConfiguration =
2871             DAC960_V2_ReportDeviceConfiguration;
2872           Controller->QueueReadWriteCommand =
2873             DAC960_V2_QueueReadWriteCommand;
2874           break;
2875         case DAC960_LA_Controller:
2876           DAC960_LA_DisableInterrupts(BaseAddress);
2877           DAC960_LA_AcknowledgeHardwareMailboxStatus(BaseAddress);
2878           udelay(1000);
2879           while (DAC960_LA_InitializationInProgressP(BaseAddress))
2880             {
2881               if (DAC960_LA_ReadErrorStatus(BaseAddress, &ErrorStatus,
2882                                             &Parameter0, &Parameter1) &&
2883                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2884                                            Parameter0, Parameter1))
2885                 goto Failure;
2886               udelay(10);
2887             }
2888           if (!DAC960_V1_EnableMemoryMailboxInterface(Controller))
2889             {
2890               DAC960_Error("Unable to Enable Memory Mailbox Interface "
2891                            "for Controller at\n", Controller);
2892               goto Failure;
2893             }
2894           DAC960_LA_EnableInterrupts(BaseAddress);
2895           if (Controller->V1.DualModeMemoryMailboxInterface)
2896             Controller->QueueCommand = DAC960_LA_QueueCommandDualMode;
2897           else Controller->QueueCommand = DAC960_LA_QueueCommandSingleMode;
2898           Controller->ReadControllerConfiguration =
2899             DAC960_V1_ReadControllerConfiguration;
2900           Controller->ReadDeviceConfiguration =
2901             DAC960_V1_ReadDeviceConfiguration;
2902           Controller->ReportDeviceConfiguration =
2903             DAC960_V1_ReportDeviceConfiguration;
2904           Controller->QueueReadWriteCommand =
2905             DAC960_V1_QueueReadWriteCommand;
2906           break;
2907         case DAC960_PG_Controller:
2908           DAC960_PG_DisableInterrupts(BaseAddress);
2909           DAC960_PG_AcknowledgeHardwareMailboxStatus(BaseAddress);
2910           udelay(1000);
2911           while (DAC960_PG_InitializationInProgressP(BaseAddress))
2912             {
2913               if (DAC960_PG_ReadErrorStatus(BaseAddress, &ErrorStatus,
2914                                             &Parameter0, &Parameter1) &&
2915                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2916                                            Parameter0, Parameter1))
2917                 goto Failure;
2918               udelay(10);
2919             }
2920           if (!DAC960_V1_EnableMemoryMailboxInterface(Controller))
2921             {
2922               DAC960_Error("Unable to Enable Memory Mailbox Interface "
2923                            "for Controller at\n", Controller);
2924               goto Failure;
2925             }
2926           DAC960_PG_EnableInterrupts(BaseAddress);
2927           if (Controller->V1.DualModeMemoryMailboxInterface)
2928             Controller->QueueCommand = DAC960_PG_QueueCommandDualMode;
2929           else Controller->QueueCommand = DAC960_PG_QueueCommandSingleMode;
2930           Controller->ReadControllerConfiguration =
2931             DAC960_V1_ReadControllerConfiguration;
2932           Controller->ReadDeviceConfiguration =
2933             DAC960_V1_ReadDeviceConfiguration;
2934           Controller->ReportDeviceConfiguration =
2935             DAC960_V1_ReportDeviceConfiguration;
2936           Controller->QueueReadWriteCommand =
2937             DAC960_V1_QueueReadWriteCommand;
2938           break;
2939         case DAC960_PD_Controller:
2940           if (!request_region(Controller->IO_Address, 0x80,
2941                               Controller->FullModelName)) {
2942                 DAC960_Error("IO port 0x%d busy for Controller at\n",
2943                              Controller, Controller->IO_Address);
2944                 goto Failure;
2945           }
2946           DAC960_PD_DisableInterrupts(BaseAddress);
2947           DAC960_PD_AcknowledgeStatus(BaseAddress);
2948           udelay(1000);
2949           while (DAC960_PD_InitializationInProgressP(BaseAddress))
2950             {
2951               if (DAC960_PD_ReadErrorStatus(BaseAddress, &ErrorStatus,
2952                                             &Parameter0, &Parameter1) &&
2953                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2954                                            Parameter0, Parameter1))
2955                 goto Failure;
2956               udelay(10);
2957             }
2958           if (!DAC960_V1_EnableMemoryMailboxInterface(Controller))
2959             {
2960               DAC960_Error("Unable to allocate DMA mapped memory "
2961                            "for Controller at\n", Controller);
2962               goto Failure;
2963             }
2964           DAC960_PD_EnableInterrupts(BaseAddress);
2965           Controller->QueueCommand = DAC960_PD_QueueCommand;
2966           Controller->ReadControllerConfiguration =
2967             DAC960_V1_ReadControllerConfiguration;
2968           Controller->ReadDeviceConfiguration =
2969             DAC960_V1_ReadDeviceConfiguration;
2970           Controller->ReportDeviceConfiguration =
2971             DAC960_V1_ReportDeviceConfiguration;
2972           Controller->QueueReadWriteCommand =
2973             DAC960_V1_QueueReadWriteCommand;
2974           break;
2975         case DAC960_P_Controller:
2976           if (!request_region(Controller->IO_Address, 0x80,
2977                               Controller->FullModelName)){
2978                 DAC960_Error("IO port 0x%d busy for Controller at\n",
2979                              Controller, Controller->IO_Address);
2980                 goto Failure;
2981           }
2982           DAC960_PD_DisableInterrupts(BaseAddress);
2983           DAC960_PD_AcknowledgeStatus(BaseAddress);
2984           udelay(1000);
2985           while (DAC960_PD_InitializationInProgressP(BaseAddress))
2986             {
2987               if (DAC960_PD_ReadErrorStatus(BaseAddress, &ErrorStatus,
2988                                             &Parameter0, &Parameter1) &&
2989                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2990                                            Parameter0, Parameter1))
2991                 goto Failure;
2992               udelay(10);
2993             }
2994           if (!DAC960_V1_EnableMemoryMailboxInterface(Controller))
2995             {
2996               DAC960_Error("Unable to allocate DMA mapped memory"
2997                            "for Controller at\n", Controller);
2998               goto Failure;
2999             }
3000           DAC960_PD_EnableInterrupts(BaseAddress);
3001           Controller->QueueCommand = DAC960_P_QueueCommand;
3002           Controller->ReadControllerConfiguration =
3003             DAC960_V1_ReadControllerConfiguration;
3004           Controller->ReadDeviceConfiguration =
3005             DAC960_V1_ReadDeviceConfiguration;
3006           Controller->ReportDeviceConfiguration =
3007             DAC960_V1_ReportDeviceConfiguration;
3008           Controller->QueueReadWriteCommand =
3009             DAC960_V1_QueueReadWriteCommand;
3010           break;
3011   }
3012   /*
3013      Acquire shared access to the IRQ Channel.
3014   */
3015   IRQ_Channel = PCI_Device->irq;
3016   if (request_irq(IRQ_Channel, InterruptHandler, IRQF_SHARED,
3017                       Controller->FullModelName, Controller) < 0)
3018   {
3019         DAC960_Error("Unable to acquire IRQ Channel %d for Controller at\n",
3020                        Controller, Controller->IRQ_Channel);
3021         goto Failure;
3022   }
3023   Controller->IRQ_Channel = IRQ_Channel;
3024   Controller->InitialCommand.CommandIdentifier = 1;
3025   Controller->InitialCommand.Controller = Controller;
3026   Controller->Commands[0] = &Controller->InitialCommand;
3027   Controller->FreeCommands = &Controller->InitialCommand;
3028   return Controller;
3029       
3030 Failure:
3031   if (Controller->IO_Address == 0)
3032         DAC960_Error("PCI Bus %d Device %d Function %d I/O Address N/A "
3033                      "PCI Address 0x%X\n", Controller,
3034                      Controller->Bus, Controller->Device,
3035                      Controller->Function, Controller->PCI_Address);
3036   else
3037         DAC960_Error("PCI Bus %d Device %d Function %d I/O Address "
3038                         "0x%X PCI Address 0x%X\n", Controller,
3039                         Controller->Bus, Controller->Device,
3040                         Controller->Function, Controller->IO_Address,
3041                         Controller->PCI_Address);
3042   DAC960_DetectCleanup(Controller);
3043   DAC960_ControllerCount--;
3044   return NULL;
3045 }
3046
3047 /*
3048   DAC960_InitializeController initializes Controller.
3049 */
3050
3051 static boolean 
3052 DAC960_InitializeController(DAC960_Controller_T *Controller)
3053 {
3054   if (DAC960_ReadControllerConfiguration(Controller) &&
3055       DAC960_ReportControllerConfiguration(Controller) &&
3056       DAC960_CreateAuxiliaryStructures(Controller) &&
3057       DAC960_ReadDeviceConfiguration(Controller) &&
3058       DAC960_ReportDeviceConfiguration(Controller) &&
3059       DAC960_RegisterBlockDevice(Controller))
3060     {
3061       /*
3062         Initialize the Monitoring Timer.
3063       */
3064       init_timer(&Controller->MonitoringTimer);
3065       Controller->MonitoringTimer.expires =
3066         jiffies + DAC960_MonitoringTimerInterval;
3067       Controller->MonitoringTimer.data = (unsigned long) Controller;
3068       Controller->MonitoringTimer.function = DAC960_MonitoringTimerFunction;
3069       add_timer(&Controller->MonitoringTimer);
3070       Controller->ControllerInitialized = true;
3071       return true;
3072     }
3073   return false;
3074 }
3075
3076
3077 /*
3078   DAC960_FinalizeController finalizes Controller.
3079 */
3080
3081 static void DAC960_FinalizeController(DAC960_Controller_T *Controller)
3082 {
3083   if (Controller->ControllerInitialized)
3084     {
3085       unsigned long flags;
3086
3087       /*
3088        * Acquiring and releasing lock here eliminates
3089        * a very low probability race.
3090        *
3091        * The code below allocates controller command structures
3092        * from the free list without holding the controller lock.
3093        * This is safe assuming there is no other activity on
3094        * the controller at the time.
3095        * 
3096        * But, there might be a monitoring command still
3097        * in progress.  Setting the Shutdown flag while holding
3098        * the lock ensures that there is no monitoring command
3099        * in the interrupt handler currently, and any monitoring
3100        * commands that complete from this time on will NOT return
3101        * their command structure to the free list.
3102        */
3103
3104       spin_lock_irqsave(&Controller->queue_lock, flags);
3105       Controller->ShutdownMonitoringTimer = 1;
3106       spin_unlock_irqrestore(&Controller->queue_lock, flags);
3107
3108       del_timer_sync(&Controller->MonitoringTimer);
3109       if (Controller->FirmwareType == DAC960_V1_Controller)
3110         {
3111           DAC960_Notice("Flushing Cache...", Controller);
3112           DAC960_V1_ExecuteType3(Controller, DAC960_V1_Flush, 0);
3113           DAC960_Notice("done\n", Controller);
3114
3115           if (Controller->HardwareType == DAC960_PD_Controller)
3116               release_region(Controller->IO_Address, 0x80);
3117         }
3118       else
3119         {
3120           DAC960_Notice("Flushing Cache...", Controller);
3121           DAC960_V2_DeviceOperation(Controller, DAC960_V2_PauseDevice,
3122                                     DAC960_V2_RAID_Controller);
3123           DAC960_Notice("done\n", Controller);
3124         }
3125     }
3126   DAC960_UnregisterBlockDevice(Controller);
3127   DAC960_DestroyAuxiliaryStructures(Controller);
3128   DAC960_DestroyProcEntries(Controller);
3129   DAC960_DetectCleanup(Controller);
3130 }
3131
3132
3133 /*
3134   DAC960_Probe verifies controller's existence and
3135   initializes the DAC960 Driver for that controller.
3136 */
3137
3138 static int 
3139 DAC960_Probe(struct pci_dev *dev, const struct pci_device_id *entry)
3140 {
3141   int disk;
3142   DAC960_Controller_T *Controller;
3143
3144   if (DAC960_ControllerCount == DAC960_MaxControllers)
3145   {
3146         DAC960_Error("More than %d DAC960 Controllers detected - "
3147                        "ignoring from Controller at\n",
3148                        NULL, DAC960_MaxControllers);
3149         return -ENODEV;
3150   }
3151
3152   Controller = DAC960_DetectController(dev, entry);
3153   if (!Controller)
3154         return -ENODEV;
3155
3156   if (!DAC960_InitializeController(Controller)) {
3157         DAC960_FinalizeController(Controller);
3158         return -ENODEV;
3159   }
3160
3161   for (disk = 0; disk < DAC960_MaxLogicalDrives; disk++) {
3162         set_capacity(Controller->disks[disk], disk_size(Controller, disk));
3163         add_disk(Controller->disks[disk]);
3164   }
3165   DAC960_CreateProcEntries(Controller);
3166   return 0;
3167 }
3168
3169
3170 /*
3171   DAC960_Finalize finalizes the DAC960 Driver.
3172 */
3173
3174 static void DAC960_Remove(struct pci_dev *PCI_Device)
3175 {
3176   int Controller_Number = (long)pci_get_drvdata(PCI_Device);
3177   DAC960_Controller_T *Controller = DAC960_Controllers[Controller_Number];
3178   if (Controller != NULL)
3179       DAC960_FinalizeController(Controller);
3180 }
3181
3182
3183 /*
3184   DAC960_V1_QueueReadWriteCommand prepares and queues a Read/Write Command for
3185   DAC960 V1 Firmware Controllers.
3186 */
3187
3188 static void DAC960_V1_QueueReadWriteCommand(DAC960_Command_T *Command)
3189 {
3190   DAC960_Controller_T *Controller = Command->Controller;
3191   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
3192   DAC960_V1_ScatterGatherSegment_T *ScatterGatherList =
3193                                         Command->V1.ScatterGatherList;
3194   struct scatterlist *ScatterList = Command->V1.ScatterList;
3195
3196   DAC960_V1_ClearCommand(Command);
3197
3198   if (Command->SegmentCount == 1)
3199     {
3200       if (Command->DmaDirection == PCI_DMA_FROMDEVICE)
3201         CommandMailbox->Type5.CommandOpcode = DAC960_V1_Read;
3202       else 
3203         CommandMailbox->Type5.CommandOpcode = DAC960_V1_Write;
3204
3205       CommandMailbox->Type5.LD.TransferLength = Command->BlockCount;
3206       CommandMailbox->Type5.LD.LogicalDriveNumber = Command->LogicalDriveNumber;
3207       CommandMailbox->Type5.LogicalBlockAddress = Command->BlockNumber;
3208       CommandMailbox->Type5.BusAddress =
3209                         (DAC960_BusAddress32_T)sg_dma_address(ScatterList);     
3210     }
3211   else
3212     {
3213       int i;
3214
3215       if (Command->DmaDirection == PCI_DMA_FROMDEVICE)
3216         CommandMailbox->Type5.CommandOpcode = DAC960_V1_ReadWithScatterGather;
3217       else
3218         CommandMailbox->Type5.CommandOpcode = DAC960_V1_WriteWithScatterGather;
3219
3220       CommandMailbox->Type5.LD.TransferLength = Command->BlockCount;
3221       CommandMailbox->Type5.LD.LogicalDriveNumber = Command->LogicalDriveNumber;
3222       CommandMailbox->Type5.LogicalBlockAddress = Command->BlockNumber;
3223       CommandMailbox->Type5.BusAddress = Command->V1.ScatterGatherListDMA;
3224
3225       CommandMailbox->Type5.ScatterGatherCount = Command->SegmentCount;
3226
3227       for (i = 0; i < Command->SegmentCount; i++, ScatterList++, ScatterGatherList++) {
3228                 ScatterGatherList->SegmentDataPointer =
3229                         (DAC960_BusAddress32_T)sg_dma_address(ScatterList);
3230                 ScatterGatherList->SegmentByteCount =
3231                         (DAC960_ByteCount32_T)sg_dma_len(ScatterList);
3232       }
3233     }
3234   DAC960_QueueCommand(Command);
3235 }
3236
3237
3238 /*
3239   DAC960_V2_QueueReadWriteCommand prepares and queues a Read/Write Command for
3240   DAC960 V2 Firmware Controllers.
3241 */
3242
3243 static void DAC960_V2_QueueReadWriteCommand(DAC960_Command_T *Command)
3244 {
3245   DAC960_Controller_T *Controller = Command->Controller;
3246   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
3247   struct scatterlist *ScatterList = Command->V2.ScatterList;
3248
3249   DAC960_V2_ClearCommand(Command);
3250
3251   CommandMailbox->SCSI_10.CommandOpcode = DAC960_V2_SCSI_10;
3252   CommandMailbox->SCSI_10.CommandControlBits.DataTransferControllerToHost =
3253     (Command->DmaDirection == PCI_DMA_FROMDEVICE);
3254   CommandMailbox->SCSI_10.DataTransferSize =
3255     Command->BlockCount << DAC960_BlockSizeBits;
3256   CommandMailbox->SCSI_10.RequestSenseBusAddress = Command->V2.RequestSenseDMA;
3257   CommandMailbox->SCSI_10.PhysicalDevice =
3258     Controller->V2.LogicalDriveToVirtualDevice[Command->LogicalDriveNumber];
3259   CommandMailbox->SCSI_10.RequestSenseSize = sizeof(DAC960_SCSI_RequestSense_T);
3260   CommandMailbox->SCSI_10.CDBLength = 10;
3261   CommandMailbox->SCSI_10.SCSI_CDB[0] =
3262     (Command->DmaDirection == PCI_DMA_FROMDEVICE ? 0x28 : 0x2A);
3263   CommandMailbox->SCSI_10.SCSI_CDB[2] = Command->BlockNumber >> 24;
3264   CommandMailbox->SCSI_10.SCSI_CDB[3] = Command->BlockNumber >> 16;
3265   CommandMailbox->SCSI_10.SCSI_CDB[4] = Command->BlockNumber >> 8;
3266   CommandMailbox->SCSI_10.SCSI_CDB[5] = Command->BlockNumber;
3267   CommandMailbox->SCSI_10.SCSI_CDB[7] = Command->BlockCount >> 8;
3268   CommandMailbox->SCSI_10.SCSI_CDB[8] = Command->BlockCount;
3269
3270   if (Command->SegmentCount == 1)
3271     {
3272       CommandMailbox->SCSI_10.DataTransferMemoryAddress
3273                              .ScatterGatherSegments[0]
3274                              .SegmentDataPointer =
3275         (DAC960_BusAddress64_T)sg_dma_address(ScatterList);
3276       CommandMailbox->SCSI_10.DataTransferMemoryAddress
3277                              .ScatterGatherSegments[0]
3278                              .SegmentByteCount =
3279         CommandMailbox->SCSI_10.DataTransferSize;
3280     }
3281   else
3282     {
3283       DAC960_V2_ScatterGatherSegment_T *ScatterGatherList;
3284       int i;
3285
3286       if (Command->SegmentCount > 2)
3287         {
3288           ScatterGatherList = Command->V2.ScatterGatherList;
3289           CommandMailbox->SCSI_10.CommandControlBits
3290                          .AdditionalScatterGatherListMemory = true;
3291           CommandMailbox->SCSI_10.DataTransferMemoryAddress
3292                 .ExtendedScatterGather.ScatterGatherList0Length = Command->SegmentCount;
3293           CommandMailbox->SCSI_10.DataTransferMemoryAddress
3294                          .ExtendedScatterGather.ScatterGatherList0Address =
3295             Command->V2.ScatterGatherListDMA;
3296         }
3297       else
3298         ScatterGatherList = CommandMailbox->SCSI_10.DataTransferMemoryAddress
3299                                  .ScatterGatherSegments;
3300
3301       for (i = 0; i < Command->SegmentCount; i++, ScatterList++, ScatterGatherList++) {
3302                 ScatterGatherList->SegmentDataPointer =
3303                         (DAC960_BusAddress64_T)sg_dma_address(ScatterList);
3304                 ScatterGatherList->SegmentByteCount =
3305                         (DAC960_ByteCount64_T)sg_dma_len(ScatterList);
3306       }
3307     }
3308   DAC960_QueueCommand(Command);
3309 }
3310
3311
3312 static int DAC960_process_queue(DAC960_Controller_T *Controller, struct request_queue *req_q)
3313 {
3314         struct request *Request;
3315         DAC960_Command_T *Command;
3316
3317    while(1) {
3318         Request = elv_next_request(req_q);
3319         if (!Request)
3320                 return 1;
3321
3322         Command = DAC960_AllocateCommand(Controller);
3323         if (Command == NULL)
3324                 return 0;
3325
3326         if (rq_data_dir(Request) == READ) {
3327                 Command->DmaDirection = PCI_DMA_FROMDEVICE;
3328                 Command->CommandType = DAC960_ReadCommand;
3329         } else {
3330                 Command->DmaDirection = PCI_DMA_TODEVICE;
3331                 Command->CommandType = DAC960_WriteCommand;
3332         }
3333         Command->Completion = Request->end_io_data;
3334         Command->LogicalDriveNumber = (long)Request->rq_disk->private_data;
3335         Command->BlockNumber = Request->sector;
3336         Command->BlockCount = Request->nr_sectors;
3337         Command->Request = Request;
3338         blkdev_dequeue_request(Request);
3339         Command->SegmentCount = blk_rq_map_sg(req_q,
3340                   Command->Request, Command->cmd_sglist);
3341         /* pci_map_sg MAY change the value of SegCount */
3342         Command->SegmentCount = pci_map_sg(Controller->PCIDevice, Command->cmd_sglist,
3343                  Command->SegmentCount, Command->DmaDirection);
3344
3345         DAC960_QueueReadWriteCommand(Command);
3346   }
3347 }
3348
3349 /*
3350   DAC960_ProcessRequest attempts to remove one I/O Request from Controller's
3351   I/O Request Queue and queues it to the Controller.  WaitForCommand is true if
3352   this function should wait for a Command to become available if necessary.
3353   This function returns true if an I/O Request was queued and false otherwise.
3354 */
3355 static void DAC960_ProcessRequest(DAC960_Controller_T *controller)
3356 {
3357         int i;
3358
3359         if (!controller->ControllerInitialized)
3360                 return;
3361
3362         /* Do this better later! */
3363         for (i = controller->req_q_index; i < DAC960_MaxLogicalDrives; i++) {
3364                 struct request_queue *req_q = controller->RequestQueue[i];
3365
3366                 if (req_q == NULL)
3367                         continue;
3368
3369                 if (!DAC960_process_queue(controller, req_q)) {
3370                         controller->req_q_index = i;
3371                         return;
3372                 }
3373         }
3374
3375         if (controller->req_q_index == 0)
3376                 return;
3377
3378         for (i = 0; i < controller->req_q_index; i++) {
3379                 struct request_queue *req_q = controller->RequestQueue[i];
3380
3381                 if (req_q == NULL)
3382                         continue;
3383
3384                 if (!DAC960_process_queue(controller, req_q)) {
3385                         controller->req_q_index = i;
3386                         return;
3387                 }
3388         }
3389 }
3390
3391
3392 /*
3393   DAC960_queue_partial_rw extracts one bio from the request already
3394   associated with argument command, and construct a new command block to retry I/O
3395   only on that bio.  Queue that command to the controller.
3396
3397   This function re-uses a previously-allocated Command,
3398         there is no failure mode from trying to allocate a command.
3399 */
3400
3401 static void DAC960_queue_partial_rw(DAC960_Command_T *Command)
3402 {
3403   DAC960_Controller_T *Controller = Command->Controller;
3404   struct request *Request = Command->Request;
3405   struct request_queue *req_q = Controller->RequestQueue[Command->LogicalDriveNumber];
3406
3407   if (Command->DmaDirection == PCI_DMA_FROMDEVICE)
3408     Command->CommandType = DAC960_ReadRetryCommand;
3409   else
3410     Command->CommandType = DAC960_WriteRetryCommand;
3411
3412   /*
3413    * We could be more efficient with these mapping requests
3414    * and map only the portions that we need.  But since this
3415    * code should almost never be called, just go with a
3416    * simple coding.
3417    */
3418   (void)blk_rq_map_sg(req_q, Command->Request, Command->cmd_sglist);
3419
3420   (void)pci_map_sg(Controller->PCIDevice, Command->cmd_sglist, 1, Command->DmaDirection);
3421   /*
3422    * Resubmitting the request sector at a time is really tedious.
3423    * But, this should almost never happen.  So, we're willing to pay
3424    * this price so that in the end, as much of the transfer is completed
3425    * successfully as possible.
3426    */
3427   Command->SegmentCount = 1;
3428   Command->BlockNumber = Request->sector;
3429   Command->BlockCount = 1;
3430   DAC960_QueueReadWriteCommand(Command);
3431   return;
3432 }
3433
3434 /*
3435   DAC960_RequestFunction is the I/O Request Function for DAC960 Controllers.
3436 */
3437
3438 static void DAC960_RequestFunction(struct request_queue *RequestQueue)
3439 {
3440         DAC960_ProcessRequest(RequestQueue->queuedata);
3441 }
3442
3443 /*
3444   DAC960_ProcessCompletedBuffer performs completion processing for an
3445   individual Buffer.
3446 */
3447
3448 static inline boolean DAC960_ProcessCompletedRequest(DAC960_Command_T *Command,
3449                                                  boolean SuccessfulIO)
3450 {
3451         struct request *Request = Command->Request;
3452         int UpToDate;
3453
3454         UpToDate = 0;
3455         if (SuccessfulIO)
3456                 UpToDate = 1;
3457
3458         pci_unmap_sg(Command->Controller->PCIDevice, Command->cmd_sglist,
3459                 Command->SegmentCount, Command->DmaDirection);
3460
3461          if (!end_that_request_first(Request, UpToDate, Command->BlockCount)) {
3462                 add_disk_randomness(Request->rq_disk);
3463                 end_that_request_last(Request, UpToDate);
3464
3465                 if (Command->Completion) {
3466                         complete(Command->Completion);
3467                         Command->Completion = NULL;
3468                 }
3469                 return true;
3470         }
3471         return false;
3472 }
3473
3474 /*
3475   DAC960_V1_ReadWriteError prints an appropriate error message for Command
3476   when an error occurs on a Read or Write operation.
3477 */
3478
3479 static void DAC960_V1_ReadWriteError(DAC960_Command_T *Command)
3480 {
3481   DAC960_Controller_T *Controller = Command->Controller;
3482   unsigned char *CommandName = "UNKNOWN";
3483   switch (Command->CommandType)
3484     {
3485     case DAC960_ReadCommand:
3486     case DAC960_ReadRetryCommand:
3487       CommandName = "READ";
3488       break;
3489     case DAC960_WriteCommand:
3490     case DAC960_WriteRetryCommand:
3491       CommandName = "WRITE";
3492       break;
3493     case DAC960_MonitoringCommand:
3494     case DAC960_ImmediateCommand:
3495     case DAC960_QueuedCommand:
3496       break;
3497     }
3498   switch (Command->V1.CommandStatus)
3499     {
3500     case DAC960_V1_IrrecoverableDataError:
3501       DAC960_Error("Irrecoverable Data Error on %s:\n",
3502                    Controller, CommandName);
3503       break;
3504     case DAC960_V1_LogicalDriveNonexistentOrOffline:
3505       DAC960_Error("Logical Drive Nonexistent or Offline on %s:\n",
3506                    Controller, CommandName);
3507       break;
3508     case DAC960_V1_AccessBeyondEndOfLogicalDrive:
3509       DAC960_Error("Attempt to Access Beyond End of Logical Drive "
3510                    "on %s:\n", Controller, CommandName);
3511       break;
3512     case DAC960_V1_BadDataEncountered:
3513       DAC960_Error("Bad Data Encountered on %s:\n", Controller, CommandName);
3514       break;
3515     default:
3516       DAC960_Error("Unexpected Error Status %04X on %s:\n",
3517                    Controller, Command->V1.CommandStatus, CommandName);
3518       break;
3519     }
3520   DAC960_Error("  /dev/rd/c%dd%d:   absolute blocks %u..%u\n",
3521                Controller, Controller->ControllerNumber,
3522                Command->LogicalDriveNumber, Command->BlockNumber,
3523                Command->BlockNumber + Command->BlockCount - 1);
3524 }
3525
3526
3527 /*
3528   DAC960_V1_ProcessCompletedCommand performs completion processing for Command
3529   for DAC960 V1 Firmware Controllers.
3530 */
3531
3532 static void DAC960_V1_ProcessCompletedCommand(DAC960_Command_T *Command)
3533 {
3534   DAC960_Controller_T *Controller = Command->Controller;
3535   DAC960_CommandType_T CommandType = Command->CommandType;
3536   DAC960_V1_CommandOpcode_T CommandOpcode =
3537     Command->V1.CommandMailbox.Common.CommandOpcode;
3538   DAC960_V1_CommandStatus_T CommandStatus = Command->V1.CommandStatus;
3539
3540   if (CommandType == DAC960_ReadCommand ||
3541       CommandType == DAC960_WriteCommand)
3542     {
3543
3544 #ifdef FORCE_RETRY_DEBUG
3545       CommandStatus = DAC960_V1_IrrecoverableDataError;
3546 #endif
3547
3548       if (CommandStatus == DAC960_V1_NormalCompletion) {
3549
3550                 if (!DAC960_ProcessCompletedRequest(Command, true))
3551                         BUG();
3552
3553       } else if (CommandStatus == DAC960_V1_IrrecoverableDataError ||
3554                 CommandStatus == DAC960_V1_BadDataEncountered)
3555         {
3556           /*
3557            * break the command down into pieces and resubmit each
3558            * piece, hoping that some of them will succeed.
3559            */
3560            DAC960_queue_partial_rw(Command);
3561            return;
3562         }
3563       else
3564         {
3565           if (CommandStatus != DAC960_V1_LogicalDriveNonexistentOrOffline)
3566             DAC960_V1_ReadWriteError(Command);
3567
3568          if (!DAC960_ProcessCompletedRequest(Command, false))
3569                 BUG();
3570         }
3571     }
3572   else if (CommandType == DAC960_ReadRetryCommand ||
3573            CommandType == DAC960_WriteRetryCommand)
3574     {
3575       boolean normal_completion;
3576 #ifdef FORCE_RETRY_FAILURE_DEBUG
3577       static int retry_count = 1;
3578 #endif
3579       /*
3580         Perform completion processing for the portion that was
3581         retried, and submit the next portion, if any.
3582       */
3583       normal_completion = true;
3584       if (CommandStatus != DAC960_V1_NormalCompletion) {
3585         normal_completion = false;
3586         if (CommandStatus != DAC960_V1_LogicalDriveNonexistentOrOffline)
3587             DAC960_V1_ReadWriteError(Command);
3588       }
3589
3590 #ifdef FORCE_RETRY_FAILURE_DEBUG
3591       if (!(++retry_count % 10000)) {
3592               printk("V1 error retry failure test\n");
3593               normal_completion = false;
3594               DAC960_V1_ReadWriteError(Command);
3595       }
3596 #endif
3597
3598       if (!DAC960_ProcessCompletedRequest(Command, normal_completion)) {
3599         DAC960_queue_partial_rw(Command);
3600         return;
3601       }
3602     }
3603
3604   else if (CommandType == DAC960_MonitoringCommand)
3605     {
3606       if (Controller->ShutdownMonitoringTimer)
3607               return;
3608       if (CommandOpcode == DAC960_V1_Enquiry)
3609         {
3610           DAC960_V1_Enquiry_T *OldEnquiry = &Controller->V1.Enquiry;
3611           DAC960_V1_Enquiry_T *NewEnquiry = Controller->V1.NewEnquiry;
3612           unsigned int OldCriticalLogicalDriveCount =
3613             OldEnquiry->CriticalLogicalDriveCount;
3614           unsigned int NewCriticalLogicalDriveCount =
3615             NewEnquiry->CriticalLogicalDriveCount;
3616           if (NewEnquiry->NumberOfLogicalDrives > Controller->LogicalDriveCount)
3617             {
3618               int LogicalDriveNumber = Controller->LogicalDriveCount - 1;
3619               while (++LogicalDriveNumber < NewEnquiry->NumberOfLogicalDrives)
3620                 DAC960_Critical("Logical Drive %d (/dev/rd/c%dd%d) "
3621                                 "Now Exists\n", Controller,
3622                                 LogicalDriveNumber,
3623                                 Controller->ControllerNumber,
3624                                 LogicalDriveNumber);
3625               Controller->LogicalDriveCount = NewEnquiry->NumberOfLogicalDrives;
3626               DAC960_ComputeGenericDiskInfo(Controller);
3627             }
3628           if (NewEnquiry->NumberOfLogicalDrives < Controller->LogicalDriveCount)
3629             {
3630               int LogicalDriveNumber = NewEnquiry->NumberOfLogicalDrives - 1;
3631               while (++LogicalDriveNumber < Controller->LogicalDriveCount)
3632                 DAC960_Critical("Logical Drive %d (/dev/rd/c%dd%d) "
3633                                 "No Longer Exists\n", Controller,
3634                                 LogicalDriveNumber,
3635                                 Controller->ControllerNumber,
3636                                 LogicalDriveNumber);
3637               Controller->LogicalDriveCount = NewEnquiry->NumberOfLogicalDrives;
3638               DAC960_ComputeGenericDiskInfo(Controller);
3639             }
3640           if (NewEnquiry->StatusFlags.DeferredWriteError !=
3641               OldEnquiry->StatusFlags.DeferredWriteError)
3642             DAC960_Critical("Deferred Write Error Flag is now %s\n", Controller,
3643                             (NewEnquiry->StatusFlags.DeferredWriteError
3644                              ? "TRUE" : "FALSE"));
3645           if ((NewCriticalLogicalDriveCount > 0 ||
3646                NewCriticalLogicalDriveCount != OldCriticalLogicalDriveCount) ||
3647               (NewEnquiry->OfflineLogicalDriveCount > 0 ||
3648                NewEnquiry->OfflineLogicalDriveCount !=
3649                OldEnquiry->OfflineLogicalDriveCount) ||
3650               (NewEnquiry->DeadDriveCount > 0 ||
3651                NewEnquiry->DeadDriveCount !=
3652                OldEnquiry->DeadDriveCount) ||
3653               (NewEnquiry->EventLogSequenceNumber !=
3654                OldEnquiry->EventLogSequenceNumber) ||
3655               Controller->MonitoringTimerCount == 0 ||
3656               time_after_eq(jiffies, Controller->SecondaryMonitoringTime
3657                + DAC960_SecondaryMonitoringInterval))
3658             {
3659               Controller->V1.NeedLogicalDriveInformation = true;
3660               Controller->V1.NewEventLogSequenceNumber =
3661                 NewEnquiry->EventLogSequenceNumber;
3662               Controller->V1.NeedErrorTableInformation = true;
3663               Controller->V1.NeedDeviceStateInformation = true;
3664               Controller->V1.StartDeviceStateScan = true;
3665               Controller->V1.NeedBackgroundInitializationStatus =
3666                 Controller->V1.BackgroundInitializationStatusSupported;
3667               Controller->SecondaryMonitoringTime = jiffies;
3668             }
3669           if (NewEnquiry->RebuildFlag == DAC960_V1_StandbyRebuildInProgress ||
3670               NewEnquiry->RebuildFlag
3671               == DAC960_V1_BackgroundRebuildInProgress ||
3672               OldEnquiry->RebuildFlag == DAC960_V1_StandbyRebuildInProgress ||
3673               OldEnquiry->RebuildFlag == DAC960_V1_BackgroundRebuildInProgress)
3674             {
3675               Controller->V1.NeedRebuildProgress = true;
3676               Controller->V1.RebuildProgressFirst =
3677                 (NewEnquiry->CriticalLogicalDriveCount <
3678                  OldEnquiry->CriticalLogicalDriveCount);
3679             }
3680           if (OldEnquiry->RebuildFlag == DAC960_V1_BackgroundCheckInProgress)
3681             switch (NewEnquiry->RebuildFlag)
3682               {
3683               case DAC960_V1_NoStandbyRebuildOrCheckInProgress:
3684                 DAC960_Progress("Consistency Check Completed Successfully\n",
3685                                 Controller);
3686                 break;
3687               case DAC960_V1_StandbyRebuildInProgress:
3688               case DAC960_V1_BackgroundRebuildInProgress:
3689                 break;
3690               case DAC960_V1_BackgroundCheckInProgress:
3691                 Controller->V1.NeedConsistencyCheckProgress = true;
3692                 break;
3693               case DAC960_V1_StandbyRebuildCompletedWithError:
3694                 DAC960_Progress("Consistency Check Completed with Error\n",
3695                                 Controller);
3696                 break;
3697               case DAC960_V1_BackgroundRebuildOrCheckFailed_DriveFailed:
3698                 DAC960_Progress("Consistency Check Failed - "
3699                                 "Physical Device Failed\n", Controller);
3700                 break;
3701               case DAC960_V1_BackgroundRebuildOrCheckFailed_LogicalDriveFailed:
3702                 DAC960_Progress("Consistency Check Failed - "
3703                                 "Logical Drive Failed\n", Controller);
3704                 break;
3705               case DAC960_V1_BackgroundRebuildOrCheckFailed_OtherCauses:
3706                 DAC960_Progress("Consistency Check Failed - Other Causes\n",
3707                                 Controller);
3708                 break;
3709               case DAC960_V1_BackgroundRebuildOrCheckSuccessfullyTerminated:
3710                 DAC960_Progress("Consistency Check Successfully Terminated\n",
3711                                 Controller);
3712                 break;
3713               }
3714           else if (NewEnquiry->RebuildFlag
3715                    == DAC960_V1_BackgroundCheckInProgress)
3716             Controller->V1.NeedConsistencyCheckProgress = true;
3717           Controller->MonitoringAlertMode =
3718             (NewEnquiry->CriticalLogicalDriveCount > 0 ||
3719              NewEnquiry->OfflineLogicalDriveCount > 0 ||
3720              NewEnquiry->DeadDriveCount > 0);
3721           if (NewEnquiry->RebuildFlag > DAC960_V1_BackgroundCheckInProgress)
3722             {
3723               Controller->V1.PendingRebuildFlag = NewEnquiry->RebuildFlag;
3724               Controller->V1.RebuildFlagPending = true;
3725             }
3726           memcpy(&Controller->V1.Enquiry, &Controller->V1.NewEnquiry,
3727                  sizeof(DAC960_V1_Enquiry_T));
3728         }
3729       else if (CommandOpcode == DAC960_V1_PerformEventLogOperation)
3730         {
3731           static char
3732             *DAC960_EventMessages[] =
3733                { "killed because write recovery failed",
3734                  "killed because of SCSI bus reset failure",
3735                  "killed because of double check condition",
3736                  "killed because it was removed",
3737                  "killed because of gross error on SCSI chip",
3738                  "killed because of bad tag returned from drive",
3739                  "killed because of timeout on SCSI command",
3740                  "killed because of reset SCSI command issued from system",
3741                  "killed because busy or parity error count exceeded limit",
3742                  "killed because of 'kill drive' command from system",
3743                  "killed because of selection timeout",
3744                  "killed due to SCSI phase sequence error",
3745                  "killed due to unknown status" };
3746           DAC960_V1_EventLogEntry_T *EventLogEntry =
3747                 Controller->V1.EventLogEntry;
3748           if (EventLogEntry->SequenceNumber ==
3749               Controller->V1.OldEventLogSequenceNumber)
3750             {
3751               unsigned char SenseKey = EventLogEntry->SenseKey;
3752               unsigned char AdditionalSenseCode =
3753                 EventLogEntry->AdditionalSenseCode;
3754               unsigned char AdditionalSenseCodeQualifier =
3755                 EventLogEntry->AdditionalSenseCodeQualifier;
3756               if (SenseKey == DAC960_SenseKey_VendorSpecific &&
3757                   AdditionalSenseCode == 0x80 &&
3758                   AdditionalSenseCodeQualifier <
3759                   ARRAY_SIZE(DAC960_EventMessages))
3760                 DAC960_Critical("Physical Device %d:%d %s\n", Controller,
3761                                 EventLogEntry->Channel,
3762                                 EventLogEntry->TargetID,
3763                                 DAC960_EventMessages[
3764                                   AdditionalSenseCodeQualifier]);
3765               else if (SenseKey == DAC960_SenseKey_UnitAttention &&
3766                        AdditionalSenseCode == 0x29)
3767                 {
3768                   if (Controller->MonitoringTimerCount > 0)
3769                     Controller->V1.DeviceResetCount[EventLogEntry->Channel]
3770                                                    [EventLogEntry->TargetID]++;
3771                 }
3772               else if (!(SenseKey == DAC960_SenseKey_NoSense ||
3773                          (SenseKey == DAC960_SenseKey_NotReady &&
3774                           AdditionalSenseCode == 0x04 &&
3775                           (AdditionalSenseCodeQualifier == 0x01 ||
3776                            AdditionalSenseCodeQualifier == 0x02))))
3777                 {
3778                   DAC960_Critical("Physical Device %d:%d Error Log: "
3779                                   "Sense Key = %X, ASC = %02X, ASCQ = %02X\n",
3780                                   Controller,
3781                                   EventLogEntry->Channel,
3782                                   EventLogEntry->TargetID,
3783                                   SenseKey,
3784                                   AdditionalSenseCode,
3785                                   AdditionalSenseCodeQualifier);
3786                   DAC960_Critical("Physical Device %d:%d Error Log: "
3787                                   "Information = %02X%02X%02X%02X "
3788                                   "%02X%02X%02X%02X\n",
3789                                   Controller,
3790                                   EventLogEntry->Channel,
3791                                   EventLogEntry->TargetID,
3792                                   EventLogEntry->Information[0],
3793                                   EventLogEntry->Information[1],
3794                                   EventLogEntry->Information[2],
3795                                   EventLogEntry->Information[3],
3796                                   EventLogEntry->CommandSpecificInformation[0],
3797                                   EventLogEntry->CommandSpecificInformation[1],