drivers/block/DAC960.c

   1 /*
   2
   3   Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers
   4
   5   Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
   6   Portions Copyright 2002 by Mylex (An IBM Business Unit)
   7
   8   This program is free software; you may redistribute and/or modify it under
   9   the terms of the GNU General Public License Version 2 as published by the
  10   Free Software Foundation.
  11
  12   This program is distributed in the hope that it will be useful, but
  13   WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
  14   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15   for complete details.
  16
  17 */
  18
  19
  20 #define DAC960_DriverVersion                    "2.5.48"
  21 #define DAC960_DriverDate                       "14 May 2006"
  22
  23
  24 #include <linux/module.h>
  25 #include <linux/types.h>
  26 #include <linux/miscdevice.h>
  27 #include <linux/blkdev.h>
  28 #include <linux/bio.h>
  29 #include <linux/completion.h>
  30 #include <linux/delay.h>
  31 #include <linux/genhd.h>
  32 #include <linux/hdreg.h>
  33 #include <linux/blkpg.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/ioport.h>
  36 #include <linux/mm.h>
  37 #include <linux/slab.h>
  38 #include <linux/proc_fs.h>
  39 #include <linux/reboot.h>
  40 #include <linux/spinlock.h>
  41 #include <linux/timer.h>
  42 #include <linux/pci.h>
  43 #include <linux/init.h>
  44 #include <linux/jiffies.h>
  45 #include <linux/random.h>
  46 #include <asm/io.h>
  47 #include <asm/uaccess.h>
  48 #include "DAC960.h"
  49
  50 #define DAC960_GAM_MINOR        252
  51
  52
  53 static DAC960_Controller_T *DAC960_Controllers[DAC960_MaxControllers];
  54 static int DAC960_ControllerCount;
  55 static struct proc_dir_entry *DAC960_ProcDirectoryEntry;
  56
  57 static long disk_size(DAC960_Controller_T *p, int drive_nr)
  58 {
  59         if (p->FirmwareType == DAC960_V1_Controller) {
  60                 if (drive_nr >= p->LogicalDriveCount)
  61                         return 0;
  62                 return p->V1.LogicalDriveInformation[drive_nr].
  63                         LogicalDriveSize;
  64         } else {
  65                 DAC960_V2_LogicalDeviceInfo_T *i =
  66                         p->V2.LogicalDeviceInformation[drive_nr];
  67                 if (i == NULL)
  68                         return 0;
  69                 return i->ConfigurableDeviceSize;
  70         }
  71 }
  72
  73 static int DAC960_open(struct inode *inode, struct file *file)
  74 {
  75         struct gendisk *disk = inode->i_bdev->bd_disk;
  76         DAC960_Controller_T *p = disk->queue->queuedata;
  77         int drive_nr = (long)disk->private_data;
  78
  79         if (p->FirmwareType == DAC960_V1_Controller) {
  80                 if (p->V1.LogicalDriveInformation[drive_nr].
  81                     LogicalDriveState == DAC960_V1_LogicalDrive_Offline)
  82                         return -ENXIO;
  83         } else {
  84                 DAC960_V2_LogicalDeviceInfo_T *i =
  85                         p->V2.LogicalDeviceInformation[drive_nr];
  86                 if (!i || i->LogicalDeviceState == DAC960_V2_LogicalDevice_Offline)
  87                         return -ENXIO;
  88         }
  89
  90         check_disk_change(inode->i_bdev);
  91
  92         if (!get_capacity(p->disks[drive_nr]))
  93                 return -ENXIO;
  94         return 0;
  95 }
  96
  97 static int DAC960_getgeo(struct block_device *bdev, struct hd_geometry *geo)
  98 {
  99         struct gendisk *disk = bdev->bd_disk;
 100         DAC960_Controller_T *p = disk->queue->queuedata;
 101         int drive_nr = (long)disk->private_data;
 102
 103         if (p->FirmwareType == DAC960_V1_Controller) {
 104                 geo->heads = p->V1.GeometryTranslationHeads;
 105                 geo->sectors = p->V1.GeometryTranslationSectors;
 106                 geo->cylinders = p->V1.LogicalDriveInformation[drive_nr].
 107                         LogicalDriveSize / (geo->heads * geo->sectors);
 108         } else {
 109                 DAC960_V2_LogicalDeviceInfo_T *i =
 110                         p->V2.LogicalDeviceInformation[drive_nr];
 111                 switch (i->DriveGeometry) {
 112                 case DAC960_V2_Geometry_128_32:
 113                         geo->heads = 128;
 114                         geo->sectors = 32;
 115                         break;
 116                 case DAC960_V2_Geometry_255_63:
 117                         geo->heads = 255;
 118                         geo->sectors = 63;
 119                         break;
 120                 default:
 121                         DAC960_Error("Illegal Logical Device Geometry %d\n",
 122                                         p, i->DriveGeometry);
 123                         return -EINVAL;
 124                 }
 125
 126                 geo->cylinders = i->ConfigurableDeviceSize /
 127                         (geo->heads * geo->sectors);
 128         }
 129
 130         return 0;
 131 }
 132
 133 static int DAC960_media_changed(struct gendisk *disk)
 134 {
 135         DAC960_Controller_T *p = disk->queue->queuedata;
 136         int drive_nr = (long)disk->private_data;
 137
 138         if (!p->LogicalDriveInitiallyAccessible[drive_nr])
 139                 return 1;
 140         return 0;
 141 }
 142
 143 static int DAC960_revalidate_disk(struct gendisk *disk)
 144 {
 145         DAC960_Controller_T *p = disk->queue->queuedata;
 146         int unit = (long)disk->private_data;
 147
 148         set_capacity(disk, disk_size(p, unit));
 149         return 0;
 150 }
 151
 152 static struct block_device_operations DAC960_BlockDeviceOperations = {
 153         .owner                  = THIS_MODULE,
 154         .open                   = DAC960_open,
 155         .getgeo                 = DAC960_getgeo,
 156         .media_changed          = DAC960_media_changed,
 157         .revalidate_disk        = DAC960_revalidate_disk,
 158 };
 159
 160
 161 /*
 162   DAC960_AnnounceDriver announces the Driver Version and Date, Author's Name,
 163   Copyright Notice, and Electronic Mail Address.
 164 */
 165
 166 static void DAC960_AnnounceDriver(DAC960_Controller_T *Controller)
 167 {
 168   DAC960_Announce("***** DAC960 RAID Driver Version "
 169                   DAC960_DriverVersion " of "
 170                   DAC960_DriverDate " *****\n", Controller);
 171   DAC960_Announce("Copyright 1998-2001 by Leonard N. Zubkoff "
 172                   "<lnz@dandelion.com>\n", Controller);
 173 }
 174
 175
 176 /*
 177   DAC960_Failure prints a standardized error message, and then returns false.
 178 */
 179
 180 static boolean DAC960_Failure(DAC960_Controller_T *Controller,
 181                               unsigned char *ErrorMessage)
 182 {
 183   DAC960_Error("While configuring DAC960 PCI RAID Controller at\n",
 184                Controller);
 185   if (Controller->IO_Address == 0)
 186     DAC960_Error("PCI Bus %d Device %d Function %d I/O Address N/A "
 187                  "PCI Address 0x%X\n", Controller,
 188                  Controller->Bus, Controller->Device,
 189                  Controller->Function, Controller->PCI_Address);
 190   else DAC960_Error("PCI Bus %d Device %d Function %d I/O Address "
 191                     "0x%X PCI Address 0x%X\n", Controller,
 192                     Controller->Bus, Controller->Device,
 193                     Controller->Function, Controller->IO_Address,
 194                     Controller->PCI_Address);
 195   DAC960_Error("%s FAILED - DETACHING\n", Controller, ErrorMessage);
 196   return false;
 197 }
 198
 199 /*
 200   init_dma_loaf() and slice_dma_loaf() are helper functions for
 201   aggregating the dma-mapped memory for a well-known collection of
 202   data structures that are of different lengths.
 203
 204   These routines don't guarantee any alignment.  The caller must
 205   include any space needed for alignment in the sizes of the structures
 206   that are passed in.
 207  */
 208
 209 static boolean init_dma_loaf(struct pci_dev *dev, struct dma_loaf *loaf,
 210                                                                  size_t len)
 211 {
 212         void *cpu_addr;
 213         dma_addr_t dma_handle;
 214
 215         cpu_addr = pci_alloc_consistent(dev, len, &dma_handle);
 216         if (cpu_addr == NULL)
 217                 return false;
 218
 219         loaf->cpu_free = loaf->cpu_base = cpu_addr;
 220         loaf->dma_free =loaf->dma_base = dma_handle;
 221         loaf->length = len;
 222         memset(cpu_addr, 0, len);
 223         return true;
 224 }
 225
 226 static void *slice_dma_loaf(struct dma_loaf *loaf, size_t len,
 227                                         dma_addr_t *dma_handle)
 228 {
 229         void *cpu_end = loaf->cpu_free + len;
 230         void *cpu_addr = loaf->cpu_free;
 231
 232         BUG_ON(cpu_end > loaf->cpu_base + loaf->length);
 233         *dma_handle = loaf->dma_free;
 234         loaf->cpu_free = cpu_end;
 235         loaf->dma_free += len;
 236         return cpu_addr;
 237 }
 238
 239 static void free_dma_loaf(struct pci_dev *dev, struct dma_loaf *loaf_handle)
 240 {
 241         if (loaf_handle->cpu_base != NULL)
 242                 pci_free_consistent(dev, loaf_handle->length,
 243                         loaf_handle->cpu_base, loaf_handle->dma_base);
 244 }
 245
 246
 247 /*
 248   DAC960_CreateAuxiliaryStructures allocates and initializes the auxiliary
 249   data structures for Controller.  It returns true on success and false on
 250   failure.
 251 */
 252
 253 static boolean DAC960_CreateAuxiliaryStructures(DAC960_Controller_T *Controller)
 254 {
 255   int CommandAllocationLength, CommandAllocationGroupSize;
 256   int CommandsRemaining = 0, CommandIdentifier, CommandGroupByteCount;
 257   void *AllocationPointer = NULL;
 258   void *ScatterGatherCPU = NULL;
 259   dma_addr_t ScatterGatherDMA;
 260   struct pci_pool *ScatterGatherPool;
 261   void *RequestSenseCPU = NULL;
 262   dma_addr_t RequestSenseDMA;
 263   struct pci_pool *RequestSensePool = NULL;
 264
 265   if (Controller->FirmwareType == DAC960_V1_Controller)
 266     {
 267       CommandAllocationLength = offsetof(DAC960_Command_T, V1.EndMarker);
 268       CommandAllocationGroupSize = DAC960_V1_CommandAllocationGroupSize;
 269       ScatterGatherPool = pci_pool_create("DAC960_V1_ScatterGather",
 270                 Controller->PCIDevice,
 271         DAC960_V1_ScatterGatherLimit * sizeof(DAC960_V1_ScatterGatherSegment_T),
 272         sizeof(DAC960_V1_ScatterGatherSegment_T), 0);
 273       if (ScatterGatherPool == NULL)
 274             return DAC960_Failure(Controller,
 275                         "AUXILIARY STRUCTURE CREATION (SG)");
 276       Controller->ScatterGatherPool = ScatterGatherPool;
 277     }
 278   else
 279     {
 280       CommandAllocationLength = offsetof(DAC960_Command_T, V2.EndMarker);
 281       CommandAllocationGroupSize = DAC960_V2_CommandAllocationGroupSize;
 282       ScatterGatherPool = pci_pool_create("DAC960_V2_ScatterGather",
 283                 Controller->PCIDevice,
 284         DAC960_V2_ScatterGatherLimit * sizeof(DAC960_V2_ScatterGatherSegment_T),
 285         sizeof(DAC960_V2_ScatterGatherSegment_T), 0);
 286       if (ScatterGatherPool == NULL)
 287             return DAC960_Failure(Controller,
 288                         "AUXILIARY STRUCTURE CREATION (SG)");
 289       RequestSensePool = pci_pool_create("DAC960_V2_RequestSense",
 290                 Controller->PCIDevice, sizeof(DAC960_SCSI_RequestSense_T),
 291                 sizeof(int), 0);
 292       if (RequestSensePool == NULL) {
 293             pci_pool_destroy(ScatterGatherPool);
 294             return DAC960_Failure(Controller,
 295                         "AUXILIARY STRUCTURE CREATION (SG)");
 296       }
 297       Controller->ScatterGatherPool = ScatterGatherPool;
 298       Controller->V2.RequestSensePool = RequestSensePool;
 299     }
 300   Controller->CommandAllocationGroupSize = CommandAllocationGroupSize;
 301   Controller->FreeCommands = NULL;
 302   for (CommandIdentifier = 1;
 303        CommandIdentifier <= Controller->DriverQueueDepth;
 304        CommandIdentifier++)
 305     {
 306       DAC960_Command_T *Command;
 307       if (--CommandsRemaining <= 0)
 308         {
 309           CommandsRemaining =
 310                 Controller->DriverQueueDepth - CommandIdentifier + 1;
 311           if (CommandsRemaining > CommandAllocationGroupSize)
 312                 CommandsRemaining = CommandAllocationGroupSize;
 313           CommandGroupByteCount =
 314                 CommandsRemaining * CommandAllocationLength;
 315           AllocationPointer = kzalloc(CommandGroupByteCount, GFP_ATOMIC);
 316           if (AllocationPointer == NULL)
 317                 return DAC960_Failure(Controller,
 318                                         "AUXILIARY STRUCTURE CREATION");
 319          }
 320       Command = (DAC960_Command_T *) AllocationPointer;
 321       AllocationPointer += CommandAllocationLength;
 322       Command->CommandIdentifier = CommandIdentifier;
 323       Command->Controller = Controller;
 324       Command->Next = Controller->FreeCommands;
 325       Controller->FreeCommands = Command;
 326       Controller->Commands[CommandIdentifier-1] = Command;
 327       ScatterGatherCPU = pci_pool_alloc(ScatterGatherPool, GFP_ATOMIC,
 328                                                         &ScatterGatherDMA);
 329       if (ScatterGatherCPU == NULL)
 330           return DAC960_Failure(Controller, "AUXILIARY STRUCTURE CREATION");
 331
 332       if (RequestSensePool != NULL) {
 333           RequestSenseCPU = pci_pool_alloc(RequestSensePool, GFP_ATOMIC,
 334                                                 &RequestSenseDMA);
 335           if (RequestSenseCPU == NULL) {
 336                 pci_pool_free(ScatterGatherPool, ScatterGatherCPU,
 337                                 ScatterGatherDMA);
 338                 return DAC960_Failure(Controller,
 339                                         "AUXILIARY STRUCTURE CREATION");
 340           }
 341         }
 342      if (Controller->FirmwareType == DAC960_V1_Controller) {
 343         Command->cmd_sglist = Command->V1.ScatterList;
 344         Command->V1.ScatterGatherList =
 345                 (DAC960_V1_ScatterGatherSegment_T *)ScatterGatherCPU;
 346         Command->V1.ScatterGatherListDMA = ScatterGatherDMA;
 347       } else {
 348         Command->cmd_sglist = Command->V2.ScatterList;
 349         Command->V2.ScatterGatherList =
 350                 (DAC960_V2_ScatterGatherSegment_T *)ScatterGatherCPU;
 351         Command->V2.ScatterGatherListDMA = ScatterGatherDMA;
 352         Command->V2.RequestSense =
 353                                 (DAC960_SCSI_RequestSense_T *)RequestSenseCPU;
 354         Command->V2.RequestSenseDMA = RequestSenseDMA;
 355       }
 356     }
 357   return true;
 358 }
 359
 360
 361 /*
 362   DAC960_DestroyAuxiliaryStructures deallocates the auxiliary data
 363   structures for Controller.
 364 */
 365
 366 static void DAC960_DestroyAuxiliaryStructures(DAC960_Controller_T *Controller)
 367 {
 368   int i;
 369   struct pci_pool *ScatterGatherPool = Controller->ScatterGatherPool;
 370   struct pci_pool *RequestSensePool = NULL;
 371   void *ScatterGatherCPU;
 372   dma_addr_t ScatterGatherDMA;
 373   void *RequestSenseCPU;
 374   dma_addr_t RequestSenseDMA;
 375   DAC960_Command_T *CommandGroup = NULL;
 376
 377
 378   if (Controller->FirmwareType == DAC960_V2_Controller)
 379         RequestSensePool = Controller->V2.RequestSensePool;
 380
 381   Controller->FreeCommands = NULL;
 382   for (i = 0; i < Controller->DriverQueueDepth; i++)
 383     {
 384       DAC960_Command_T *Command = Controller->Commands[i];
 385
 386       if (Command == NULL)
 387           continue;
 388
 389       if (Controller->FirmwareType == DAC960_V1_Controller) {
 390           ScatterGatherCPU = (void *)Command->V1.ScatterGatherList;
 391           ScatterGatherDMA = Command->V1.ScatterGatherListDMA;
 392           RequestSenseCPU = NULL;
 393           RequestSenseDMA = (dma_addr_t)0;
 394       } else {
 395           ScatterGatherCPU = (void *)Command->V2.ScatterGatherList;
 396           ScatterGatherDMA = Command->V2.ScatterGatherListDMA;
 397           RequestSenseCPU = (void *)Command->V2.RequestSense;
 398           RequestSenseDMA = Command->V2.RequestSenseDMA;
 399       }
 400       if (ScatterGatherCPU != NULL)
 401           pci_pool_free(ScatterGatherPool, ScatterGatherCPU, ScatterGatherDMA);
 402       if (RequestSenseCPU != NULL)
 403           pci_pool_free(RequestSensePool, RequestSenseCPU, RequestSenseDMA);
 404
 405       if ((Command->CommandIdentifier
 406            % Controller->CommandAllocationGroupSize) == 1) {
 407            /*
 408             * We can't free the group of commands until all of the
 409             * request sense and scatter gather dma structures are free.
 410             * Remember the beginning of the group, but don't free it
 411             * until we've reached the beginning of the next group.
 412             */
 413            kfree(CommandGroup);
 414            CommandGroup = Command;
 415       }
 416       Controller->Commands[i] = NULL;
 417     }
 418   kfree(CommandGroup);
 419
 420   if (Controller->CombinedStatusBuffer != NULL)
 421     {
 422       kfree(Controller->CombinedStatusBuffer);
 423       Controller->CombinedStatusBuffer = NULL;
 424       Controller->CurrentStatusBuffer = NULL;
 425     }
 426
 427   if (ScatterGatherPool != NULL)
 428         pci_pool_destroy(ScatterGatherPool);
 429   if (Controller->FirmwareType == DAC960_V1_Controller)
 430         return;
 431
 432   if (RequestSensePool != NULL)
 433         pci_pool_destroy(RequestSensePool);
 434
 435   for (i = 0; i < DAC960_MaxLogicalDrives; i++) {
 436         kfree(Controller->V2.LogicalDeviceInformation[i]);
 437         Controller->V2.LogicalDeviceInformation[i] = NULL;
 438   }
 439
 440   for (i = 0; i < DAC960_V2_MaxPhysicalDevices; i++)
 441     {
 442       kfree(Controller->V2.PhysicalDeviceInformation[i]);
 443       Controller->V2.PhysicalDeviceInformation[i] = NULL;
 444       kfree(Controller->V2.InquiryUnitSerialNumber[i]);
 445       Controller->V2.InquiryUnitSerialNumber[i] = NULL;
 446     }
 447 }
 448
 449
 450 /*
 451   DAC960_V1_ClearCommand clears critical fields of Command for DAC960 V1
 452   Firmware Controllers.
 453 */
 454
 455 static inline void DAC960_V1_ClearCommand(DAC960_Command_T *Command)
 456 {
 457   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
 458   memset(CommandMailbox, 0, sizeof(DAC960_V1_CommandMailbox_T));
 459   Command->V1.CommandStatus = 0;
 460 }
 461
 462
 463 /*
 464   DAC960_V2_ClearCommand clears critical fields of Command for DAC960 V2
 465   Firmware Controllers.
 466 */
 467
 468 static inline void DAC960_V2_ClearCommand(DAC960_Command_T *Command)
 469 {
 470   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
 471   memset(CommandMailbox, 0, sizeof(DAC960_V2_CommandMailbox_T));
 472   Command->V2.CommandStatus = 0;
 473 }
 474
 475
 476 /*
 477   DAC960_AllocateCommand allocates a Command structure from Controller's
 478   free list.  During driver initialization, a special initialization command
 479   has been placed on the free list to guarantee that command allocation can
 480   never fail.
 481 */
 482
 483 static inline DAC960_Command_T *DAC960_AllocateCommand(DAC960_Controller_T
 484                                                        *Controller)
 485 {
 486   DAC960_Command_T *Command = Controller->FreeCommands;
 487   if (Command == NULL) return NULL;
 488   Controller->FreeCommands = Command->Next;
 489   Command->Next = NULL;
 490   return Command;
 491 }
 492
 493
 494 /*
 495   DAC960_DeallocateCommand deallocates Command, returning it to Controller's
 496   free list.
 497 */
 498
 499 static inline void DAC960_DeallocateCommand(DAC960_Command_T *Command)
 500 {
 501   DAC960_Controller_T *Controller = Command->Controller;
 502
 503   Command->Request = NULL;
 504   Command->Next = Controller->FreeCommands;
 505   Controller->FreeCommands = Command;
 506 }
 507
 508
 509 /*
 510   DAC960_WaitForCommand waits for a wake_up on Controller's Command Wait Queue.
 511 */
 512
 513 static void DAC960_WaitForCommand(DAC960_Controller_T *Controller)
 514 {
 515   spin_unlock_irq(&Controller->queue_lock);
 516   __wait_event(Controller->CommandWaitQueue, Controller->FreeCommands);
 517   spin_lock_irq(&Controller->queue_lock);
 518 }
 519
 520 /*
 521   DAC960_GEM_QueueCommand queues Command for DAC960 GEM Series Controllers.
 522 */
 523
 524 static void DAC960_GEM_QueueCommand(DAC960_Command_T *Command)
 525 {
 526   DAC960_Controller_T *Controller = Command->Controller;
 527   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
 528   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
 529   DAC960_V2_CommandMailbox_T *NextCommandMailbox =
 530       Controller->V2.NextCommandMailbox;
 531
 532   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
 533   DAC960_GEM_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
 534
 535   if (Controller->V2.PreviousCommandMailbox1->Words[0] == 0 ||
 536       Controller->V2.PreviousCommandMailbox2->Words[0] == 0)
 537       DAC960_GEM_MemoryMailboxNewCommand(ControllerBaseAddress);
 538
 539   Controller->V2.PreviousCommandMailbox2 =
 540       Controller->V2.PreviousCommandMailbox1;
 541   Controller->V2.PreviousCommandMailbox1 = NextCommandMailbox;
 542
 543   if (++NextCommandMailbox > Controller->V2.LastCommandMailbox)
 544       NextCommandMailbox = Controller->V2.FirstCommandMailbox;
 545
 546   Controller->V2.NextCommandMailbox = NextCommandMailbox;
 547 }
 548
 549 /*
 550   DAC960_BA_QueueCommand queues Command for DAC960 BA Series Controllers.
 551 */
 552
 553 static void DAC960_BA_QueueCommand(DAC960_Command_T *Command)
 554 {
 555   DAC960_Controller_T *Controller = Command->Controller;
 556   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
 557   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
 558   DAC960_V2_CommandMailbox_T *NextCommandMailbox =
 559     Controller->V2.NextCommandMailbox;
 560   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
 561   DAC960_BA_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
 562   if (Controller->V2.PreviousCommandMailbox1->Words[0] == 0 ||
 563       Controller->V2.PreviousCommandMailbox2->Words[0] == 0)
 564     DAC960_BA_MemoryMailboxNewCommand(ControllerBaseAddress);
 565   Controller->V2.PreviousCommandMailbox2 =
 566     Controller->V2.PreviousCommandMailbox1;
 567   Controller->V2.PreviousCommandMailbox1 = NextCommandMailbox;
 568   if (++NextCommandMailbox > Controller->V2.LastCommandMailbox)
 569     NextCommandMailbox = Controller->V2.FirstCommandMailbox;
 570   Controller->V2.NextCommandMailbox = NextCommandMailbox;
 571 }
 572
 573
 574 /*
 575   DAC960_LP_QueueCommand queues Command for DAC960 LP Series Controllers.
 576 */
 577
 578 static void DAC960_LP_QueueCommand(DAC960_Command_T *Command)
 579 {
 580   DAC960_Controller_T *Controller = Command->Controller;
 581   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
 582   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
 583   DAC960_V2_CommandMailbox_T *NextCommandMailbox =
 584     Controller->V2.NextCommandMailbox;
 585   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
 586   DAC960_LP_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
 587   if (Controller->V2.PreviousCommandMailbox1->Words[0] == 0 ||
 588       Controller->V2.PreviousCommandMailbox2->Words[0] == 0)
 589     DAC960_LP_MemoryMailboxNewCommand(ControllerBaseAddress);
 590   Controller->V2.PreviousCommandMailbox2 =
 591     Controller->V2.PreviousCommandMailbox1;
 592   Controller->V2.PreviousCommandMailbox1 = NextCommandMailbox;
 593   if (++NextCommandMailbox > Controller->V2.LastCommandMailbox)
 594     NextCommandMailbox = Controller->V2.FirstCommandMailbox;
 595   Controller->V2.NextCommandMailbox = NextCommandMailbox;
 596 }
 597
 598
 599 /*
 600   DAC960_LA_QueueCommandDualMode queues Command for DAC960 LA Series
 601   Controllers with Dual Mode Firmware.
 602 */
 603
 604 static void DAC960_LA_QueueCommandDualMode(DAC960_Command_T *Command)
 605 {
 606   DAC960_Controller_T *Controller = Command->Controller;
 607   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
 608   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
 609   DAC960_V1_CommandMailbox_T *NextCommandMailbox =
 610     Controller->V1.NextCommandMailbox;
 611   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
 612   DAC960_LA_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
 613   if (Controller->V1.PreviousCommandMailbox1->Words[0] == 0 ||
 614       Controller->V1.PreviousCommandMailbox2->Words[0] == 0)
 615     DAC960_LA_MemoryMailboxNewCommand(ControllerBaseAddress);
 616   Controller->V1.PreviousCommandMailbox2 =
 617     Controller->V1.PreviousCommandMailbox1;
 618   Controller->V1.PreviousCommandMailbox1 = NextCommandMailbox;
 619   if (++NextCommandMailbox > Controller->V1.LastCommandMailbox)
 620     NextCommandMailbox = Controller->V1.FirstCommandMailbox;
 621   Controller->V1.NextCommandMailbox = NextCommandMailbox;
 622 }
 623
 624
 625 /*
 626   DAC960_LA_QueueCommandSingleMode queues Command for DAC960 LA Series
 627   Controllers with Single Mode Firmware.
 628 */
 629
 630 static void DAC960_LA_QueueCommandSingleMode(DAC960_Command_T *Command)
 631 {
 632   DAC960_Controller_T *Controller = Command->Controller;
 633   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
 634   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
 635   DAC960_V1_CommandMailbox_T *NextCommandMailbox =
 636     Controller->V1.NextCommandMailbox;
 637   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
 638   DAC960_LA_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
 639   if (Controller->V1.PreviousCommandMailbox1->Words[0] == 0 ||
 640       Controller->V1.PreviousCommandMailbox2->Words[0] == 0)
 641     DAC960_LA_HardwareMailboxNewCommand(ControllerBaseAddress);
 642   Controller->V1.PreviousCommandMailbox2 =
 643     Controller->V1.PreviousCommandMailbox1;
 644   Controller->V1.PreviousCommandMailbox1 = NextCommandMailbox;
 645   if (++NextCommandMailbox > Controller->V1.LastCommandMailbox)
 646     NextCommandMailbox = Controller->V1.FirstCommandMailbox;
 647   Controller->V1.NextCommandMailbox = NextCommandMailbox;
 648 }
 649
 650
 651 /*
 652   DAC960_PG_QueueCommandDualMode queues Command for DAC960 PG Series
 653   Controllers with Dual Mode Firmware.
 654 */
 655
 656 static void DAC960_PG_QueueCommandDualMode(DAC960_Command_T *Command)
 657 {
 658   DAC960_Controller_T *Controller = Command->Controller;
 659   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
 660   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
 661   DAC960_V1_CommandMailbox_T *NextCommandMailbox =
 662     Controller->V1.NextCommandMailbox;
 663   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
 664   DAC960_PG_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
 665   if (Controller->V1.PreviousCommandMailbox1->Words[0] == 0 ||
 666       Controller->V1.PreviousCommandMailbox2->Words[0] == 0)
 667     DAC960_PG_MemoryMailboxNewCommand(ControllerBaseAddress);
 668   Controller->V1.PreviousCommandMailbox2 =
 669     Controller->V1.PreviousCommandMailbox1;
 670   Controller->V1.PreviousCommandMailbox1 = NextCommandMailbox;
 671   if (++NextCommandMailbox > Controller->V1.LastCommandMailbox)
 672     NextCommandMailbox = Controller->V1.FirstCommandMailbox;
 673   Controller->V1.NextCommandMailbox = NextCommandMailbox;
 674 }
 675
 676
 677 /*
 678   DAC960_PG_QueueCommandSingleMode queues Command for DAC960 PG Series
 679   Controllers with Single Mode Firmware.
 680 */
 681
 682 static void DAC960_PG_QueueCommandSingleMode(DAC960_Command_T *Command)
 683 {
 684   DAC960_Controller_T *Controller = Command->Controller;
 685   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
 686   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
 687   DAC960_V1_CommandMailbox_T *NextCommandMailbox =
 688     Controller->V1.NextCommandMailbox;
 689   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
 690   DAC960_PG_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
 691   if (Controller->V1.PreviousCommandMailbox1->Words[0] == 0 ||
 692       Controller->V1.PreviousCommandMailbox2->Words[0] == 0)
 693     DAC960_PG_HardwareMailboxNewCommand(ControllerBaseAddress);
 694   Controller->V1.PreviousCommandMailbox2 =
 695     Controller->V1.PreviousCommandMailbox1;
 696   Controller->V1.PreviousCommandMailbox1 = NextCommandMailbox;
 697   if (++NextCommandMailbox > Controller->V1.LastCommandMailbox)
 698     NextCommandMailbox = Controller->V1.FirstCommandMailbox;
 699   Controller->V1.NextCommandMailbox = NextCommandMailbox;
 700 }
 701
 702
 703 /*
 704   DAC960_PD_QueueCommand queues Command for DAC960 PD Series Controllers.
 705 */
 706
 707 static void DAC960_PD_QueueCommand(DAC960_Command_T *Command)
 708 {
 709   DAC960_Controller_T *Controller = Command->Controller;
 710   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
 711   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
 712   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
 713   while (DAC960_PD_MailboxFullP(ControllerBaseAddress))
 714     udelay(1);
 715   DAC960_PD_WriteCommandMailbox(ControllerBaseAddress, CommandMailbox);
 716   DAC960_PD_NewCommand(ControllerBaseAddress);
 717 }
 718
 719
 720 /*
 721   DAC960_P_QueueCommand queues Command for DAC960 P Series Controllers.
 722 */
 723
 724 static void DAC960_P_QueueCommand(DAC960_Command_T *Command)
 725 {
 726   DAC960_Controller_T *Controller = Command->Controller;
 727   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
 728   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
 729   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
 730   switch (CommandMailbox->Common.CommandOpcode)
 731     {
 732     case DAC960_V1_Enquiry:
 733       CommandMailbox->Common.CommandOpcode = DAC960_V1_Enquiry_Old;
 734       break;
 735     case DAC960_V1_GetDeviceState:
 736       CommandMailbox->Common.CommandOpcode = DAC960_V1_GetDeviceState_Old;
 737       break;
 738     case DAC960_V1_Read:
 739       CommandMailbox->Common.CommandOpcode = DAC960_V1_Read_Old;
 740       DAC960_PD_To_P_TranslateReadWriteCommand(CommandMailbox);
 741       break;
 742     case DAC960_V1_Write:
 743       CommandMailbox->Common.CommandOpcode = DAC960_V1_Write_Old;
 744       DAC960_PD_To_P_TranslateReadWriteCommand(CommandMailbox);
 745       break;
 746     case DAC960_V1_ReadWithScatterGather:
 747       CommandMailbox->Common.CommandOpcode =
 748         DAC960_V1_ReadWithScatterGather_Old;
 749       DAC960_PD_To_P_TranslateReadWriteCommand(CommandMailbox);
 750       break;
 751     case DAC960_V1_WriteWithScatterGather:
 752       CommandMailbox->Common.CommandOpcode =
 753         DAC960_V1_WriteWithScatterGather_Old;
 754       DAC960_PD_To_P_TranslateReadWriteCommand(CommandMailbox);
 755       break;
 756     default:
 757       break;
 758     }
 759   while (DAC960_PD_MailboxFullP(ControllerBaseAddress))
 760     udelay(1);
 761   DAC960_PD_WriteCommandMailbox(ControllerBaseAddress, CommandMailbox);
 762   DAC960_PD_NewCommand(ControllerBaseAddress);
 763 }
 764
 765
 766 /*
 767   DAC960_ExecuteCommand executes Command and waits for completion.
 768 */
 769
 770 static void DAC960_ExecuteCommand(DAC960_Command_T *Command)
 771 {
 772   DAC960_Controller_T *Controller = Command->Controller;
 773   DECLARE_COMPLETION_ONSTACK(Completion);
 774   unsigned long flags;
 775   Command->Completion = &Completion;
 776
 777   spin_lock_irqsave(&Controller->queue_lock, flags);
 778   DAC960_QueueCommand(Command);
 779   spin_unlock_irqrestore(&Controller->queue_lock, flags);
 780
 781   if (in_interrupt())
 782           return;
 783   wait_for_completion(&Completion);
 784 }
 785
 786
 787 /*
 788   DAC960_V1_ExecuteType3 executes a DAC960 V1 Firmware Controller Type 3
 789   Command and waits for completion.  It returns true on success and false
 790   on failure.
 791 */
 792
 793 static boolean DAC960_V1_ExecuteType3(DAC960_Controller_T *Controller,
 794                                       DAC960_V1_CommandOpcode_T CommandOpcode,
 795                                       dma_addr_t DataDMA)
 796 {
 797   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
 798   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
 799   DAC960_V1_CommandStatus_T CommandStatus;
 800   DAC960_V1_ClearCommand(Command);
 801   Command->CommandType = DAC960_ImmediateCommand;
 802   CommandMailbox->Type3.CommandOpcode = CommandOpcode;
 803   CommandMailbox->Type3.BusAddress = DataDMA;
 804   DAC960_ExecuteCommand(Command);
 805   CommandStatus = Command->V1.CommandStatus;
 806   DAC960_DeallocateCommand(Command);
 807   return (CommandStatus == DAC960_V1_NormalCompletion);
 808 }
 809
 810
 811 /*
 812   DAC960_V1_ExecuteTypeB executes a DAC960 V1 Firmware Controller Type 3B
 813   Command and waits for completion.  It returns true on success and false
 814   on failure.
 815 */
 816
 817 static boolean DAC960_V1_ExecuteType3B(DAC960_Controller_T *Controller,
 818                                        DAC960_V1_CommandOpcode_T CommandOpcode,
 819                                        unsigned char CommandOpcode2,
 820                                        dma_addr_t DataDMA)
 821 {
 822   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
 823   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
 824   DAC960_V1_CommandStatus_T CommandStatus;
 825   DAC960_V1_ClearCommand(Command);
 826   Command->CommandType = DAC960_ImmediateCommand;
 827   CommandMailbox->Type3B.CommandOpcode = CommandOpcode;
 828   CommandMailbox->Type3B.CommandOpcode2 = CommandOpcode2;
 829   CommandMailbox->Type3B.BusAddress = DataDMA;
 830   DAC960_ExecuteCommand(Command);
 831   CommandStatus = Command->V1.CommandStatus;
 832   DAC960_DeallocateCommand(Command);
 833   return (CommandStatus == DAC960_V1_NormalCompletion);
 834 }
 835
 836
 837 /*
 838   DAC960_V1_ExecuteType3D executes a DAC960 V1 Firmware Controller Type 3D
 839   Command and waits for completion.  It returns true on success and false
 840   on failure.
 841 */
 842
 843 static boolean DAC960_V1_ExecuteType3D(DAC960_Controller_T *Controller,
 844                                        DAC960_V1_CommandOpcode_T CommandOpcode,
 845                                        unsigned char Channel,
 846                                        unsigned char TargetID,
 847                                        dma_addr_t DataDMA)
 848 {
 849   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
 850   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
 851   DAC960_V1_CommandStatus_T CommandStatus;
 852   DAC960_V1_ClearCommand(Command);
 853   Command->CommandType = DAC960_ImmediateCommand;
 854   CommandMailbox->Type3D.CommandOpcode = CommandOpcode;
 855   CommandMailbox->Type3D.Channel = Channel;
 856   CommandMailbox->Type3D.TargetID = TargetID;
 857   CommandMailbox->Type3D.BusAddress = DataDMA;
 858   DAC960_ExecuteCommand(Command);
 859   CommandStatus = Command->V1.CommandStatus;
 860   DAC960_DeallocateCommand(Command);
 861   return (CommandStatus == DAC960_V1_NormalCompletion);
 862 }
 863
 864
 865 /*
 866   DAC960_V2_GeneralInfo executes a DAC960 V2 Firmware General Information
 867   Reading IOCTL Command and waits for completion.  It returns true on success
 868   and false on failure.
 869
 870   Return data in The controller's HealthStatusBuffer, which is dma-able memory
 871 */
 872
 873 static boolean DAC960_V2_GeneralInfo(DAC960_Controller_T *Controller)
 874 {
 875   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
 876   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
 877   DAC960_V2_CommandStatus_T CommandStatus;
 878   DAC960_V2_ClearCommand(Command);
 879   Command->CommandType = DAC960_ImmediateCommand;
 880   CommandMailbox->Common.CommandOpcode = DAC960_V2_IOCTL;
 881   CommandMailbox->Common.CommandControlBits
 882                         .DataTransferControllerToHost = true;
 883   CommandMailbox->Common.CommandControlBits
 884                         .NoAutoRequestSense = true;
 885   CommandMailbox->Common.DataTransferSize = sizeof(DAC960_V2_HealthStatusBuffer_T);
 886   CommandMailbox->Common.IOCTL_Opcode = DAC960_V2_GetHealthStatus;
 887   CommandMailbox->Common.DataTransferMemoryAddress
 888                         .ScatterGatherSegments[0]
 889                         .SegmentDataPointer =
 890     Controller->V2.HealthStatusBufferDMA;
 891   CommandMailbox->Common.DataTransferMemoryAddress
 892                         .ScatterGatherSegments[0]
 893                         .SegmentByteCount =
 894     CommandMailbox->Common.DataTransferSize;
 895   DAC960_ExecuteCommand(Command);
 896   CommandStatus = Command->V2.CommandStatus;
 897   DAC960_DeallocateCommand(Command);
 898   return (CommandStatus == DAC960_V2_NormalCompletion);
 899 }
 900
 901
 902 /*
 903   DAC960_V2_ControllerInfo executes a DAC960 V2 Firmware Controller
 904   Information Reading IOCTL Command and waits for completion.  It returns
 905   true on success and false on failure.
 906
 907   Data is returned in the controller's V2.NewControllerInformation dma-able
 908   memory buffer.
 909 */
 910
 911 static boolean DAC960_V2_NewControllerInfo(DAC960_Controller_T *Controller)
 912 {
 913   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
 914   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
 915   DAC960_V2_CommandStatus_T CommandStatus;
 916   DAC960_V2_ClearCommand(Command);
 917   Command->CommandType = DAC960_ImmediateCommand;
 918   CommandMailbox->ControllerInfo.CommandOpcode = DAC960_V2_IOCTL;
 919   CommandMailbox->ControllerInfo.CommandControlBits
 920                                 .DataTransferControllerToHost = true;
 921   CommandMailbox->ControllerInfo.CommandControlBits
 922                                 .NoAutoRequestSense = true;
 923   CommandMailbox->ControllerInfo.DataTransferSize = sizeof(DAC960_V2_ControllerInfo_T);
 924   CommandMailbox->ControllerInfo.ControllerNumber = 0;
 925   CommandMailbox->ControllerInfo.IOCTL_Opcode = DAC960_V2_GetControllerInfo;
 926   CommandMailbox->ControllerInfo.DataTransferMemoryAddress
 927                                 .ScatterGatherSegments[0]
 928                                 .SegmentDataPointer =
 929         Controller->V2.NewControllerInformationDMA;
 930   CommandMailbox->ControllerInfo.DataTransferMemoryAddress
 931                                 .ScatterGatherSegments[0]
 932                                 .SegmentByteCount =
 933     CommandMailbox->ControllerInfo.DataTransferSize;
 934   DAC960_ExecuteCommand(Command);
 935   CommandStatus = Command->V2.CommandStatus;
 936   DAC960_DeallocateCommand(Command);
 937   return (CommandStatus == DAC960_V2_NormalCompletion);
 938 }
 939
 940
 941 /*
 942   DAC960_V2_LogicalDeviceInfo executes a DAC960 V2 Firmware Controller Logical
 943   Device Information Reading IOCTL Command and waits for completion.  It
 944   returns true on success and false on failure.
 945
 946   Data is returned in the controller's V2.NewLogicalDeviceInformation
 947 */
 948
 949 static boolean DAC960_V2_NewLogicalDeviceInfo(DAC960_Controller_T *Controller,
 950                                            unsigned short LogicalDeviceNumber)
 951 {
 952   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
 953   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
 954   DAC960_V2_CommandStatus_T CommandStatus;
 955
 956   DAC960_V2_ClearCommand(Command);
 957   Command->CommandType = DAC960_ImmediateCommand;
 958   CommandMailbox->LogicalDeviceInfo.CommandOpcode =
 959                                 DAC960_V2_IOCTL;
 960   CommandMailbox->LogicalDeviceInfo.CommandControlBits
 961                                    .DataTransferControllerToHost = true;
 962   CommandMailbox->LogicalDeviceInfo.CommandControlBits
 963                                    .NoAutoRequestSense = true;
 964   CommandMailbox->LogicalDeviceInfo.DataTransferSize =
 965                                 sizeof(DAC960_V2_LogicalDeviceInfo_T);
 966   CommandMailbox->LogicalDeviceInfo.LogicalDevice.LogicalDeviceNumber =
 967     LogicalDeviceNumber;
 968   CommandMailbox->LogicalDeviceInfo.IOCTL_Opcode = DAC960_V2_GetLogicalDeviceInfoValid;
 969   CommandMailbox->LogicalDeviceInfo.DataTransferMemoryAddress
 970                                    .ScatterGatherSegments[0]
 971                                    .SegmentDataPointer =
 972         Controller->V2.NewLogicalDeviceInformationDMA;
 973   CommandMailbox->LogicalDeviceInfo.DataTransferMemoryAddress
 974                                    .ScatterGatherSegments[0]
 975                                    .SegmentByteCount =
 976     CommandMailbox->LogicalDeviceInfo.DataTransferSize;
 977   DAC960_ExecuteCommand(Command);
 978   CommandStatus = Command->V2.CommandStatus;
 979   DAC960_DeallocateCommand(Command);
 980   return (CommandStatus == DAC960_V2_NormalCompletion);
 981 }
 982
 983
 984 /*
 985   DAC960_V2_PhysicalDeviceInfo executes a DAC960 V2 Firmware Controller "Read
 986   Physical Device Information" IOCTL Command and waits for completion.  It
 987   returns true on success and false on failure.
 988
 989   The Channel, TargetID, LogicalUnit arguments should be 0 the first time
 990   this function is called for a given controller.  This will return data
 991   for the "first" device on that controller.  The returned data includes a
 992   Channel, TargetID, LogicalUnit that can be passed in to this routine to
 993   get data for the NEXT device on that controller.
 994
 995   Data is stored in the controller's V2.NewPhysicalDeviceInfo dma-able
 996   memory buffer.
 997
 998 */
 999
1000 static boolean DAC960_V2_NewPhysicalDeviceInfo(DAC960_Controller_T *Controller,
1001                                             unsigned char Channel,
1002                                             unsigned char TargetID,
1003                                             unsigned char LogicalUnit)
1004 {
1005   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
1006   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
1007   DAC960_V2_CommandStatus_T CommandStatus;
1008
1009   DAC960_V2_ClearCommand(Command);
1010   Command->CommandType = DAC960_ImmediateCommand;
1011   CommandMailbox->PhysicalDeviceInfo.CommandOpcode = DAC960_V2_IOCTL;
1012   CommandMailbox->PhysicalDeviceInfo.CommandControlBits
1013                                     .DataTransferControllerToHost = true;
1014   CommandMailbox->PhysicalDeviceInfo.CommandControlBits
1015                                     .NoAutoRequestSense = true;
1016   CommandMailbox->PhysicalDeviceInfo.DataTransferSize =
1017                                 sizeof(DAC960_V2_PhysicalDeviceInfo_T);
1018   CommandMailbox->PhysicalDeviceInfo.PhysicalDevice.LogicalUnit = LogicalUnit;
1019   CommandMailbox->PhysicalDeviceInfo.PhysicalDevice.TargetID = TargetID;
1020   CommandMailbox->PhysicalDeviceInfo.PhysicalDevice.Channel = Channel;
1021   CommandMailbox->PhysicalDeviceInfo.IOCTL_Opcode =
1022                                         DAC960_V2_GetPhysicalDeviceInfoValid;
1023   CommandMailbox->PhysicalDeviceInfo.DataTransferMemoryAddress
1024                                     .ScatterGatherSegments[0]
1025                                     .SegmentDataPointer =
1026                                         Controller->V2.NewPhysicalDeviceInformationDMA;
1027   CommandMailbox->PhysicalDeviceInfo.DataTransferMemoryAddress
1028                                     .ScatterGatherSegments[0]
1029                                     .SegmentByteCount =
1030     CommandMailbox->PhysicalDeviceInfo.DataTransferSize;
1031   DAC960_ExecuteCommand(Command);
1032   CommandStatus = Command->V2.CommandStatus;
1033   DAC960_DeallocateCommand(Command);
1034   return (CommandStatus == DAC960_V2_NormalCompletion);
1035 }
1036
1037
1038 static void DAC960_V2_ConstructNewUnitSerialNumber(
1039         DAC960_Controller_T *Controller,
1040         DAC960_V2_CommandMailbox_T *CommandMailbox, int Channel, int TargetID,
1041         int LogicalUnit)
1042 {
1043       CommandMailbox->SCSI_10.CommandOpcode = DAC960_V2_SCSI_10_Passthru;
1044       CommandMailbox->SCSI_10.CommandControlBits
1045                              .DataTransferControllerToHost = true;
1046       CommandMailbox->SCSI_10.CommandControlBits
1047                              .NoAutoRequestSense = true;
1048       CommandMailbox->SCSI_10.DataTransferSize =
1049         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T);
1050       CommandMailbox->SCSI_10.PhysicalDevice.LogicalUnit = LogicalUnit;
1051       CommandMailbox->SCSI_10.PhysicalDevice.TargetID = TargetID;
1052       CommandMailbox->SCSI_10.PhysicalDevice.Channel = Channel;
1053       CommandMailbox->SCSI_10.CDBLength = 6;
1054       CommandMailbox->SCSI_10.SCSI_CDB[0] = 0x12; /* INQUIRY */
1055       CommandMailbox->SCSI_10.SCSI_CDB[1] = 1; /* EVPD = 1 */
1056       CommandMailbox->SCSI_10.SCSI_CDB[2] = 0x80; /* Page Code */
1057       CommandMailbox->SCSI_10.SCSI_CDB[3] = 0; /* Reserved */
1058       CommandMailbox->SCSI_10.SCSI_CDB[4] =
1059         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T);
1060       CommandMailbox->SCSI_10.SCSI_CDB[5] = 0; /* Control */
1061       CommandMailbox->SCSI_10.DataTransferMemoryAddress
1062                              .ScatterGatherSegments[0]
1063                              .SegmentDataPointer =
1064                 Controller->V2.NewInquiryUnitSerialNumberDMA;
1065       CommandMailbox->SCSI_10.DataTransferMemoryAddress
1066                              .ScatterGatherSegments[0]
1067                              .SegmentByteCount =
1068                 CommandMailbox->SCSI_10.DataTransferSize;
1069 }
1070
1071
1072 /*
1073   DAC960_V2_NewUnitSerialNumber executes an SCSI pass-through
1074   Inquiry command to a SCSI device identified by Channel number,
1075   Target id, Logical Unit Number.  This function Waits for completion
1076   of the command.
1077
1078   The return data includes Unit Serial Number information for the
1079   specified device.
1080
1081   Data is stored in the controller's V2.NewPhysicalDeviceInfo dma-able
1082   memory buffer.
1083 */
1084
1085 static boolean DAC960_V2_NewInquiryUnitSerialNumber(DAC960_Controller_T *Controller,
1086                         int Channel, int TargetID, int LogicalUnit)
1087 {
1088       DAC960_Command_T *Command;
1089       DAC960_V2_CommandMailbox_T *CommandMailbox;
1090       DAC960_V2_CommandStatus_T CommandStatus;
1091
1092       Command = DAC960_AllocateCommand(Controller);
1093       CommandMailbox = &Command->V2.CommandMailbox;
1094       DAC960_V2_ClearCommand(Command);
1095       Command->CommandType = DAC960_ImmediateCommand;
1096
1097       DAC960_V2_ConstructNewUnitSerialNumber(Controller, CommandMailbox,
1098                         Channel, TargetID, LogicalUnit);
1099
1100       DAC960_ExecuteCommand(Command);
1101       CommandStatus = Command->V2.CommandStatus;
1102       DAC960_DeallocateCommand(Command);
1103       return (CommandStatus == DAC960_V2_NormalCompletion);
1104 }
1105
1106
1107 /*
1108   DAC960_V2_DeviceOperation executes a DAC960 V2 Firmware Controller Device
1109   Operation IOCTL Command and waits for completion.  It returns true on
1110   success and false on failure.
1111 */
1112
1113 static boolean DAC960_V2_DeviceOperation(DAC960_Controller_T *Controller,
1114                                          DAC960_V2_IOCTL_Opcode_T IOCTL_Opcode,
1115                                          DAC960_V2_OperationDevice_T
1116                                            OperationDevice)
1117 {
1118   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
1119   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
1120   DAC960_V2_CommandStatus_T CommandStatus;
1121   DAC960_V2_ClearCommand(Command);
1122   Command->CommandType = DAC960_ImmediateCommand;
1123   CommandMailbox->DeviceOperation.CommandOpcode = DAC960_V2_IOCTL;
1124   CommandMailbox->DeviceOperation.CommandControlBits
1125                                  .DataTransferControllerToHost = true;
1126   CommandMailbox->DeviceOperation.CommandControlBits
1127                                  .NoAutoRequestSense = true;
1128   CommandMailbox->DeviceOperation.IOCTL_Opcode = IOCTL_Opcode;
1129   CommandMailbox->DeviceOperation.OperationDevice = OperationDevice;
1130   DAC960_ExecuteCommand(Command);
1131   CommandStatus = Command->V2.CommandStatus;
1132   DAC960_DeallocateCommand(Command);
1133   return (CommandStatus == DAC960_V2_NormalCompletion);
1134 }
1135
1136
1137 /*
1138   DAC960_V1_EnableMemoryMailboxInterface enables the Memory Mailbox Interface
1139   for DAC960 V1 Firmware Controllers.
1140
1141   PD and P controller types have no memory mailbox, but still need the
1142   other dma mapped memory.
1143 */
1144
1145 static boolean DAC960_V1_EnableMemoryMailboxInterface(DAC960_Controller_T
1146                                                       *Controller)
1147 {
1148   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
1149   DAC960_HardwareType_T hw_type = Controller->HardwareType;
1150   struct pci_dev *PCI_Device = Controller->PCIDevice;
1151   struct dma_loaf *DmaPages = &Controller->DmaPages;
1152   size_t DmaPagesSize;
1153   size_t CommandMailboxesSize;
1154   size_t StatusMailboxesSize;
1155
1156   DAC960_V1_CommandMailbox_T *CommandMailboxesMemory;
1157   dma_addr_t CommandMailboxesMemoryDMA;
1158
1159   DAC960_V1_StatusMailbox_T *StatusMailboxesMemory;
1160   dma_addr_t StatusMailboxesMemoryDMA;
1161
1162   DAC960_V1_CommandMailbox_T CommandMailbox;
1163   DAC960_V1_CommandStatus_T CommandStatus;
1164   int TimeoutCounter;
1165   int i;
1166
1167
1168   if (pci_set_dma_mask(Controller->PCIDevice, DAC690_V1_PciDmaMask))
1169         return DAC960_Failure(Controller, "DMA mask out of range");
1170   Controller->BounceBufferLimit = DAC690_V1_PciDmaMask;
1171
1172   if ((hw_type == DAC960_PD_Controller) || (hw_type == DAC960_P_Controller)) {
1173     CommandMailboxesSize =  0;
1174     StatusMailboxesSize = 0;
1175   } else {
1176     CommandMailboxesSize =  DAC960_V1_CommandMailboxCount * sizeof(DAC960_V1_CommandMailbox_T);
1177     StatusMailboxesSize = DAC960_V1_StatusMailboxCount * sizeof(DAC960_V1_StatusMailbox_T);
1178   }
1179   DmaPagesSize = CommandMailboxesSize + StatusMailboxesSize +
1180         sizeof(DAC960_V1_DCDB_T) + sizeof(DAC960_V1_Enquiry_T) +
1181         sizeof(DAC960_V1_ErrorTable_T) + sizeof(DAC960_V1_EventLogEntry_T) +
1182         sizeof(DAC960_V1_RebuildProgress_T) +
1183         sizeof(DAC960_V1_LogicalDriveInformationArray_T) +
1184         sizeof(DAC960_V1_BackgroundInitializationStatus_T) +
1185         sizeof(DAC960_V1_DeviceState_T) + sizeof(DAC960_SCSI_Inquiry_T) +
1186         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T);
1187
1188   if (!init_dma_loaf(PCI_Device, DmaPages, DmaPagesSize))
1189         return false;
1190
1191
1192   if ((hw_type == DAC960_PD_Controller) || (hw_type == DAC960_P_Controller))
1193         goto skip_mailboxes;
1194
1195   CommandMailboxesMemory = slice_dma_loaf(DmaPages,
1196                 CommandMailboxesSize, &CommandMailboxesMemoryDMA);
1197
1198   /* These are the base addresses for the command memory mailbox array */
1199   Controller->V1.FirstCommandMailbox = CommandMailboxesMemory;
1200   Controller->V1.FirstCommandMailboxDMA = CommandMailboxesMemoryDMA;
1201
1202   CommandMailboxesMemory += DAC960_V1_CommandMailboxCount - 1;
1203   Controller->V1.LastCommandMailbox = CommandMailboxesMemory;
1204   Controller->V1.NextCommandMailbox = Controller->V1.FirstCommandMailbox;
1205   Controller->V1.PreviousCommandMailbox1 = Controller->V1.LastCommandMailbox;
1206   Controller->V1.PreviousCommandMailbox2 =
1207                                         Controller->V1.LastCommandMailbox - 1;
1208
1209   /* These are the base addresses for the status memory mailbox array */
1210   StatusMailboxesMemory = slice_dma_loaf(DmaPages,
1211                 StatusMailboxesSize, &StatusMailboxesMemoryDMA);
1212
1213   Controller->V1.FirstStatusMailbox = StatusMailboxesMemory;
1214   Controller->V1.FirstStatusMailboxDMA = StatusMailboxesMemoryDMA;
1215   StatusMailboxesMemory += DAC960_V1_StatusMailboxCount - 1;
1216   Controller->V1.LastStatusMailbox = StatusMailboxesMemory;
1217   Controller->V1.NextStatusMailbox = Controller->V1.FirstStatusMailbox;
1218
1219 skip_mailboxes:
1220   Controller->V1.MonitoringDCDB = slice_dma_loaf(DmaPages,
1221                 sizeof(DAC960_V1_DCDB_T),
1222                 &Controller->V1.MonitoringDCDB_DMA);
1223
1224   Controller->V1.NewEnquiry = slice_dma_loaf(DmaPages,
1225                 sizeof(DAC960_V1_Enquiry_T),
1226                 &Controller->V1.NewEnquiryDMA);
1227
1228   Controller->V1.NewErrorTable = slice_dma_loaf(DmaPages,
1229                 sizeof(DAC960_V1_ErrorTable_T),
1230                 &Controller->V1.NewErrorTableDMA);
1231
1232   Controller->V1.EventLogEntry = slice_dma_loaf(DmaPages,
1233                 sizeof(DAC960_V1_EventLogEntry_T),
1234                 &Controller->V1.EventLogEntryDMA);
1235
1236   Controller->V1.RebuildProgress = slice_dma_loaf(DmaPages,
1237                 sizeof(DAC960_V1_RebuildProgress_T),
1238                 &Controller->V1.RebuildProgressDMA);
1239
1240   Controller->V1.NewLogicalDriveInformation = slice_dma_loaf(DmaPages,
1241                 sizeof(DAC960_V1_LogicalDriveInformationArray_T),
1242                 &Controller->V1.NewLogicalDriveInformationDMA);
1243
1244   Controller->V1.BackgroundInitializationStatus = slice_dma_loaf(DmaPages,
1245                 sizeof(DAC960_V1_BackgroundInitializationStatus_T),
1246                 &Controller->V1.BackgroundInitializationStatusDMA);
1247
1248   Controller->V1.NewDeviceState = slice_dma_loaf(DmaPages,
1249                 sizeof(DAC960_V1_DeviceState_T),
1250                 &Controller->V1.NewDeviceStateDMA);
1251
1252   Controller->V1.NewInquiryStandardData = slice_dma_loaf(DmaPages,
1253                 sizeof(DAC960_SCSI_Inquiry_T),
1254                 &Controller->V1.NewInquiryStandardDataDMA);
1255
1256   Controller->V1.NewInquiryUnitSerialNumber = slice_dma_loaf(DmaPages,
1257                 sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T),
1258                 &Controller->V1.NewInquiryUnitSerialNumberDMA);
1259
1260   if ((hw_type == DAC960_PD_Controller) || (hw_type == DAC960_P_Controller))
1261         return true;
1262
1263   /* Enable the Memory Mailbox Interface. */
1264   Controller->V1.DualModeMemoryMailboxInterface = true;
1265   CommandMailbox.TypeX.CommandOpcode = 0x2B;
1266   CommandMailbox.TypeX.CommandIdentifier = 0;
1267   CommandMailbox.TypeX.CommandOpcode2 = 0x14;
1268   CommandMailbox.TypeX.CommandMailboxesBusAddress =
1269                                 Controller->V1.FirstCommandMailboxDMA;
1270   CommandMailbox.TypeX.StatusMailboxesBusAddress =
1271                                 Controller->V1.FirstStatusMailboxDMA;
1272 #define TIMEOUT_COUNT 1000000
1273
1274   for (i = 0; i < 2; i++)
1275     switch (Controller->HardwareType)
1276       {
1277       case DAC960_LA_Controller:
1278         TimeoutCounter = TIMEOUT_COUNT;
1279         while (--TimeoutCounter >= 0)
1280           {
1281             if (!DAC960_LA_HardwareMailboxFullP(ControllerBaseAddress))
1282               break;
1283             udelay(10);
1284           }
1285         if (TimeoutCounter < 0) return false;
1286         DAC960_LA_WriteHardwareMailbox(ControllerBaseAddress, &CommandMailbox);
1287         DAC960_LA_HardwareMailboxNewCommand(ControllerBaseAddress);
1288         TimeoutCounter = TIMEOUT_COUNT;
1289         while (--TimeoutCounter >= 0)
1290           {
1291             if (DAC960_LA_HardwareMailboxStatusAvailableP(
1292                   ControllerBaseAddress))
1293               break;
1294             udelay(10);
1295           }
1296         if (TimeoutCounter < 0) return false;
1297         CommandStatus = DAC960_LA_ReadStatusRegister(ControllerBaseAddress);
1298         DAC960_LA_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress);
1299         DAC960_LA_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress);
1300         if (CommandStatus == DAC960_V1_NormalCompletion) return true;
1301         Controller->V1.DualModeMemoryMailboxInterface = false;
1302         CommandMailbox.TypeX.CommandOpcode2 = 0x10;
1303         break;
1304       case DAC960_PG_Controller:
1305         TimeoutCounter = TIMEOUT_COUNT;
1306         while (--TimeoutCounter >= 0)
1307           {
1308             if (!DAC960_PG_HardwareMailboxFullP(ControllerBaseAddress))
1309               break;
1310             udelay(10);
1311           }
1312         if (TimeoutCounter < 0) return false;
1313         DAC960_PG_WriteHardwareMailbox(ControllerBaseAddress, &CommandMailbox);
1314         DAC960_PG_HardwareMailboxNewCommand(ControllerBaseAddress);
1315
1316         TimeoutCounter = TIMEOUT_COUNT;
1317         while (--TimeoutCounter >= 0)
1318           {
1319             if (DAC960_PG_HardwareMailboxStatusAvailableP(
1320                   ControllerBaseAddress))
1321               break;
1322             udelay(10);
1323           }
1324         if (TimeoutCounter < 0) return false;
1325         CommandStatus = DAC960_PG_ReadStatusRegister(ControllerBaseAddress);
1326         DAC960_PG_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress);
1327         DAC960_PG_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress);
1328         if (CommandStatus == DAC960_V1_NormalCompletion) return true;
1329         Controller->V1.DualModeMemoryMailboxInterface = false;
1330         CommandMailbox.TypeX.CommandOpcode2 = 0x10;
1331         break;
1332       default:
1333         DAC960_Failure(Controller, "Unknown Controller Type\n");
1334         break;
1335       }
1336   return false;
1337 }
1338
1339
1340 /*
1341   DAC960_V2_EnableMemoryMailboxInterface enables the Memory Mailbox Interface
1342   for DAC960 V2 Firmware Controllers.
1343
1344   Aggregate the space needed for the controller's memory mailbox and
1345   the other data structures that will be targets of dma transfers with
1346   the controller.  Allocate a dma-mapped region of memory to hold these
1347   structures.  Then, save CPU pointers and dma_addr_t values to reference
1348   the structures that are contained in that region.
1349 */
1350
1351 static boolean DAC960_V2_EnableMemoryMailboxInterface(DAC960_Controller_T
1352                                                       *Controller)
1353 {
1354   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
1355   struct pci_dev *PCI_Device = Controller->PCIDevice;
1356   struct dma_loaf *DmaPages = &Controller->DmaPages;
1357   size_t DmaPagesSize;
1358   size_t CommandMailboxesSize;
1359   size_t StatusMailboxesSize;
1360
1361   DAC960_V2_CommandMailbox_T *CommandMailboxesMemory;
1362   dma_addr_t CommandMailboxesMemoryDMA;
1363
1364   DAC960_V2_StatusMailbox_T *StatusMailboxesMemory;
1365   dma_addr_t StatusMailboxesMemoryDMA;
1366
1367   DAC960_V2_CommandMailbox_T *CommandMailbox;
1368   dma_addr_t    CommandMailboxDMA;
1369   DAC960_V2_CommandStatus_T CommandStatus;
1370
1371   if (pci_set_dma_mask(Controller->PCIDevice, DAC690_V2_PciDmaMask))
1372         return DAC960_Failure(Controller, "DMA mask out of range");
1373   Controller->BounceBufferLimit = DAC690_V2_PciDmaMask;
1374
1375   /* This is a temporary dma mapping, used only in the scope of this function */
1376   CommandMailbox = pci_alloc_consistent(PCI_Device,
1377                 sizeof(DAC960_V2_CommandMailbox_T), &CommandMailboxDMA);
1378   if (CommandMailbox == NULL)
1379           return false;
1380
1381   CommandMailboxesSize = DAC960_V2_CommandMailboxCount * sizeof(DAC960_V2_CommandMailbox_T);
1382   StatusMailboxesSize = DAC960_V2_StatusMailboxCount * sizeof(DAC960_V2_StatusMailbox_T);
1383   DmaPagesSize =
1384     CommandMailboxesSize + StatusMailboxesSize +
1385     sizeof(DAC960_V2_HealthStatusBuffer_T) +
1386     sizeof(DAC960_V2_ControllerInfo_T) +
1387     sizeof(DAC960_V2_LogicalDeviceInfo_T) +
1388     sizeof(DAC960_V2_PhysicalDeviceInfo_T) +
1389     sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T) +
1390     sizeof(DAC960_V2_Event_T) +
1391     sizeof(DAC960_V2_PhysicalToLogicalDevice_T);
1392
1393   if (!init_dma_loaf(PCI_Device, DmaPages, DmaPagesSize)) {
1394         pci_free_consistent(PCI_Device, sizeof(DAC960_V2_CommandMailbox_T),
1395                                         CommandMailbox, CommandMailboxDMA);
1396         return false;
1397   }
1398
1399   CommandMailboxesMemory = slice_dma_loaf(DmaPages,
1400                 CommandMailboxesSize, &CommandMailboxesMemoryDMA);
1401
1402   /* These are the base addresses for the command memory mailbox array */
1403   Controller->V2.FirstCommandMailbox = CommandMailboxesMemory;
1404   Controller->V2.FirstCommandMailboxDMA = CommandMailboxesMemoryDMA;
1405
1406   CommandMailboxesMemory += DAC960_V2_CommandMailboxCount - 1;
1407   Controller->V2.LastCommandMailbox = CommandMailboxesMemory;
1408   Controller->V2.NextCommandMailbox = Controller->V2.FirstCommandMailbox;
1409   Controller->V2.PreviousCommandMailbox1 = Controller->V2.LastCommandMailbox;
1410   Controller->V2.PreviousCommandMailbox2 =
1411                                         Controller->V2.LastCommandMailbox - 1;
1412
1413   /* These are the base addresses for the status memory mailbox array */
1414   StatusMailboxesMemory = slice_dma_loaf(DmaPages,
1415                 StatusMailboxesSize, &StatusMailboxesMemoryDMA);
1416
1417   Controller->V2.FirstStatusMailbox = StatusMailboxesMemory;
1418   Controller->V2.FirstStatusMailboxDMA = StatusMailboxesMemoryDMA;
1419   StatusMailboxesMemory += DAC960_V2_StatusMailboxCount - 1;
1420   Controller->V2.LastStatusMailbox = StatusMailboxesMemory;
1421   Controller->V2.NextStatusMailbox = Controller->V2.FirstStatusMailbox;
1422
1423   Controller->V2.HealthStatusBuffer = slice_dma_loaf(DmaPages,
1424                 sizeof(DAC960_V2_HealthStatusBuffer_T),
1425                 &Controller->V2.HealthStatusBufferDMA);
1426
1427   Controller->V2.NewControllerInformation = slice_dma_loaf(DmaPages,
1428                 sizeof(DAC960_V2_ControllerInfo_T),
1429                 &Controller->V2.NewControllerInformationDMA);
1430
1431   Controller->V2.NewLogicalDeviceInformation =  slice_dma_loaf(DmaPages,
1432                 sizeof(DAC960_V2_LogicalDeviceInfo_T),
1433                 &Controller->V2.NewLogicalDeviceInformationDMA);
1434
1435   Controller->V2.NewPhysicalDeviceInformation = slice_dma_loaf(DmaPages,
1436                 sizeof(DAC960_V2_PhysicalDeviceInfo_T),
1437                 &Controller->V2.NewPhysicalDeviceInformationDMA);
1438
1439   Controller->V2.NewInquiryUnitSerialNumber = slice_dma_loaf(DmaPages,
1440                 sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T),
1441                 &Controller->V2.NewInquiryUnitSerialNumberDMA);
1442
1443   Controller->V2.Event = slice_dma_loaf(DmaPages,
1444                 sizeof(DAC960_V2_Event_T),
1445                 &Controller->V2.EventDMA);
1446
1447   Controller->V2.PhysicalToLogicalDevice = slice_dma_loaf(DmaPages,
1448                 sizeof(DAC960_V2_PhysicalToLogicalDevice_T),
1449                 &Controller->V2.PhysicalToLogicalDeviceDMA);
1450
1451   /*
1452     Enable the Memory Mailbox Interface.
1453
1454     I don't know why we can't just use one of the memory mailboxes
1455     we just allocated to do this, instead of using this temporary one.
1456     Try this change later.
1457   */
1458   memset(CommandMailbox, 0, sizeof(DAC960_V2_CommandMailbox_T));
1459   CommandMailbox->SetMemoryMailbox.CommandIdentifier = 1;
1460   CommandMailbox->SetMemoryMailbox.CommandOpcode = DAC960_V2_IOCTL;
1461   CommandMailbox->SetMemoryMailbox.CommandControlBits.NoAutoRequestSense = true;
1462   CommandMailbox->SetMemoryMailbox.FirstCommandMailboxSizeKB =
1463     (DAC960_V2_CommandMailboxCount * sizeof(DAC960_V2_CommandMailbox_T)) >> 10;
1464   CommandMailbox->SetMemoryMailbox.FirstStatusMailboxSizeKB =
1465     (DAC960_V2_StatusMailboxCount * sizeof(DAC960_V2_StatusMailbox_T)) >> 10;
1466   CommandMailbox->SetMemoryMailbox.SecondCommandMailboxSizeKB = 0;
1467   CommandMailbox->SetMemoryMailbox.SecondStatusMailboxSizeKB = 0;
1468   CommandMailbox->SetMemoryMailbox.RequestSenseSize = 0;
1469   CommandMailbox->SetMemoryMailbox.IOCTL_Opcode = DAC960_V2_SetMemoryMailbox;
1470   CommandMailbox->SetMemoryMailbox.HealthStatusBufferSizeKB = 1;
1471   CommandMailbox->SetMemoryMailbox.HealthStatusBufferBusAddress =
1472                                         Controller->V2.HealthStatusBufferDMA;
1473   CommandMailbox->SetMemoryMailbox.FirstCommandMailboxBusAddress =
1474                                         Controller->V2.FirstCommandMailboxDMA;
1475   CommandMailbox->SetMemoryMailbox.FirstStatusMailboxBusAddress =
1476                                         Controller->V2.FirstStatusMailboxDMA;
1477   switch (Controller->HardwareType)
1478     {
1479     case DAC960_GEM_Controller:
1480       while (DAC960_GEM_HardwareMailboxFullP(ControllerBaseAddress))
1481         udelay(1);
1482       DAC960_GEM_WriteHardwareMailbox(ControllerBaseAddress, CommandMailboxDMA);
1483       DAC960_GEM_HardwareMailboxNewCommand(ControllerBaseAddress);
1484       while (!DAC960_GEM_HardwareMailboxStatusAvailableP(ControllerBaseAddress))
1485         udelay(1);
1486       CommandStatus = DAC960_GEM_ReadCommandStatus(ControllerBaseAddress);
1487       DAC960_GEM_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress);
1488       DAC960_GEM_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress);
1489       break;
1490     case DAC960_BA_Controller:
1491       while (DAC960_BA_HardwareMailboxFullP(ControllerBaseAddress))
1492         udelay(1);
1493       DAC960_BA_WriteHardwareMailbox(ControllerBaseAddress, CommandMailboxDMA);
1494       DAC960_BA_HardwareMailboxNewCommand(ControllerBaseAddress);
1495       while (!DAC960_BA_HardwareMailboxStatusAvailableP(ControllerBaseAddress))
1496         udelay(1);
1497       CommandStatus = DAC960_BA_ReadCommandStatus(ControllerBaseAddress);
1498       DAC960_BA_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress);
1499       DAC960_BA_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress);
1500       break;
1501     case DAC960_LP_Controller:
1502       while (DAC960_LP_HardwareMailboxFullP(ControllerBaseAddress))
1503         udelay(1);
1504       DAC960_LP_WriteHardwareMailbox(ControllerBaseAddress, CommandMailboxDMA);
1505       DAC960_LP_HardwareMailboxNewCommand(ControllerBaseAddress);
1506       while (!DAC960_LP_HardwareMailboxStatusAvailableP(ControllerBaseAddress))
1507         udelay(1);
1508       CommandStatus = DAC960_LP_ReadCommandStatus(ControllerBaseAddress);
1509       DAC960_LP_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress);
1510       DAC960_LP_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress);
1511       break;
1512     default:
1513       DAC960_Failure(Controller, "Unknown Controller Type\n");
1514       CommandStatus = DAC960_V2_AbormalCompletion;
1515       break;
1516     }
1517   pci_free_consistent(PCI_Device, sizeof(DAC960_V2_CommandMailbox_T),
1518                                         CommandMailbox, CommandMailboxDMA);
1519   return (CommandStatus == DAC960_V2_NormalCompletion);
1520 }
1521
1522
1523 /*
1524   DAC960_V1_ReadControllerConfiguration reads the Configuration Information
1525   from DAC960 V1 Firmware Controllers and initializes the Controller structure.
1526 */
1527
1528 static boolean DAC960_V1_ReadControllerConfiguration(DAC960_Controller_T
1529                                                      *Controller)
1530 {
1531   DAC960_V1_Enquiry2_T *Enquiry2;
1532   dma_addr_t Enquiry2DMA;
1533   DAC960_V1_Config2_T *Config2;
1534   dma_addr_t Config2DMA;
1535   int LogicalDriveNumber, Channel, TargetID;
1536   struct dma_loaf local_dma;
1537
1538   if (!init_dma_loaf(Controller->PCIDevice, &local_dma,
1539                 sizeof(DAC960_V1_Enquiry2_T) + sizeof(DAC960_V1_Config2_T)))
1540         return DAC960_Failure(Controller, "LOGICAL DEVICE ALLOCATION");
1541
1542   Enquiry2 = slice_dma_loaf(&local_dma, sizeof(DAC960_V1_Enquiry2_T), &Enquiry2DMA);
1543   Config2 = slice_dma_loaf(&local_dma, sizeof(DAC960_V1_Config2_T), &Config2DMA);
1544
1545   if (!DAC960_V1_ExecuteType3(Controller, DAC960_V1_Enquiry,
1546                               Controller->V1.NewEnquiryDMA)) {
1547     free_dma_loaf(Controller->PCIDevice, &local_dma);
1548     return DAC960_Failure(Controller, "ENQUIRY");
1549   }
1550   memcpy(&Controller->V1.Enquiry, Controller->V1.NewEnquiry,
1551                                                 sizeof(DAC960_V1_Enquiry_T));
1552
1553   if (!DAC960_V1_ExecuteType3(Controller, DAC960_V1_Enquiry2, Enquiry2DMA)) {
1554     free_dma_loaf(Controller->PCIDevice, &local_dma);
1555     return DAC960_Failure(Controller, "ENQUIRY2");
1556   }
1557
1558   if (!DAC960_V1_ExecuteType3(Controller, DAC960_V1_ReadConfig2, Config2DMA)) {
1559     free_dma_loaf(Controller->PCIDevice, &local_dma);
1560     return DAC960_Failure(Controller, "READ CONFIG2");
1561   }
1562
1563   if (!DAC960_V1_ExecuteType3(Controller, DAC960_V1_GetLogicalDriveInformation,
1564                               Controller->V1.NewLogicalDriveInformationDMA)) {
1565     free_dma_loaf(Controller->PCIDevice, &local_dma);
1566     return DAC960_Failure(Controller, "GET LOGICAL DRIVE INFORMATION");
1567   }
1568   memcpy(&Controller->V1.LogicalDriveInformation,
1569                 Controller->V1.NewLogicalDriveInformation,
1570                 sizeof(DAC960_V1_LogicalDriveInformationArray_T));
1571
1572   for (Channel = 0; Channel < Enquiry2->ActualChannels; Channel++)
1573     for (TargetID = 0; TargetID < Enquiry2->MaxTargets; TargetID++) {
1574       if (!DAC960_V1_ExecuteType3D(Controller, DAC960_V1_GetDeviceState,
1575                                    Channel, TargetID,
1576                                    Controller->V1.NewDeviceStateDMA)) {
1577                 free_dma_loaf(Controller->PCIDevice, &local_dma);
1578                 return DAC960_Failure(Controller, "GET DEVICE STATE");
1579         }
1580         memcpy(&Controller->V1.DeviceState[Channel][TargetID],
1581                 Controller->V1.NewDeviceState, sizeof(DAC960_V1_DeviceState_T));
1582      }
1583   /*
1584     Initialize the Controller Model Name and Full Model Name fields.
1585   */
1586   switch (Enquiry2->HardwareID.SubModel)
1587     {
1588     case DAC960_V1_P_PD_PU:
1589       if (Enquiry2->SCSICapability.BusSpeed == DAC960_V1_Ultra)
1590         strcpy(Controller->ModelName, "DAC960PU");
1591       else strcpy(Controller->ModelName, "DAC960PD");
1592       break;
1593     case DAC960_V1_PL:
1594       strcpy(Controller->ModelName, "DAC960PL");
1595       break;
1596     case DAC960_V1_PG:
1597       strcpy(Controller->ModelName, "DAC960PG");
1598       break;
1599     case DAC960_V1_PJ:
1600       strcpy(Controller->ModelName, "DAC960PJ");
1601       break;
1602     case DAC960_V1_PR:
1603       strcpy(Controller->ModelName, "DAC960PR");
1604       break;
1605     case DAC960_V1_PT:
1606       strcpy(Controller->ModelName, "DAC960PT");
1607       break;
1608     case DAC960_V1_PTL0:
1609       strcpy(Controller->ModelName, "DAC960PTL0");
1610       break;
1611     case DAC960_V1_PRL:
1612       strcpy(Controller->ModelName, "DAC960PRL");
1613       break;
1614     case DAC960_V1_PTL1:
1615       strcpy(Controller->ModelName, "DAC960PTL1");
1616       break;
1617     case DAC960_V1_1164P:
1618       strcpy(Controller->ModelName, "DAC1164P");
1619       break;
1620     default:
1621       free_dma_loaf(Controller->PCIDevice, &local_dma);
1622       return DAC960_Failure(Controller, "MODEL VERIFICATION");
1623     }
1624   strcpy(Controller->FullModelName, "Mylex ");
1625   strcat(Controller->FullModelName, Controller->ModelName);
1626   /*
1627     Initialize the Controller Firmware Version field and verify that it
1628     is a supported firmware version.  The supported firmware versions are:
1629
1630     DAC1164P                5.06 and above
1631     DAC960PTL/PRL/PJ/PG     4.06 and above
1632     DAC960PU/PD/PL          3.51 and above
1633     DAC960PU/PD/PL/P        2.73 and above
1634   */
1635 #if defined(CONFIG_ALPHA)
1636   /*
1637     DEC Alpha machines were often equipped with DAC960 cards that were
1638     OEMed from Mylex, and had their own custom firmware. Version 2.70,
1639     the last custom FW revision to be released by DEC for these older
1640     controllers, appears to work quite well with this driver.
1641
1642     Cards tested successfully were several versions each of the PD and
1643     PU, called by DEC the KZPSC and KZPAC, respectively, and having
1644     the Manufacturer Numbers (from Mylex), usually on a sticker on the
1645     back of the board, of:
1646
1647     KZPSC:  D040347 (1-channel) or D040348 (2-channel) or D040349 (3-channel)
1648     KZPAC:  D040395 (1-channel) or D040396 (2-channel) or D040397 (3-channel)
1649   */
1650 # define FIRMWARE_27X   "2.70"
1651 #else
1652 # define FIRMWARE_27X   "2.73"
1653 #endif
1654
1655   if (Enquiry2->FirmwareID.MajorVersion == 0)
1656     {
1657       Enquiry2->FirmwareID.MajorVersion =
1658         Controller->V1.Enquiry.MajorFirmwareVersion;
1659       Enquiry2->FirmwareID.MinorVersion =
1660         Controller->V1.Enquiry.MinorFirmwareVersion;
1661       Enquiry2->FirmwareID.FirmwareType = '0';
1662       Enquiry2->FirmwareID.TurnID = 0;
1663     }
1664   sprintf(Controller->FirmwareVersion, "%d.%02d-%c-%02d",
1665           Enquiry2->FirmwareID.MajorVersion, Enquiry2->FirmwareID.MinorVersion,
1666           Enquiry2->FirmwareID.FirmwareType, Enquiry2->FirmwareID.TurnID);
1667   if (!((Controller->FirmwareVersion[0] == '5' &&
1668          strcmp(Controller->FirmwareVersion, "5.06") >= 0) ||
1669         (Controller->FirmwareVersion[0] == '4' &&
1670          strcmp(Controller->FirmwareVersion, "4.06") >= 0) ||
1671         (Controller->FirmwareVersion[0] == '3' &&
1672          strcmp(Controller->FirmwareVersion, "3.51") >= 0) ||
1673         (Controller->FirmwareVersion[0] == '2' &&
1674          strcmp(Controller->FirmwareVersion, FIRMWARE_27X) >= 0)))
1675     {
1676       DAC960_Failure(Controller, "FIRMWARE VERSION VERIFICATION");
1677       DAC960_Error("Firmware Version = '%s'\n", Controller,
1678                    Controller->FirmwareVersion);
1679       free_dma_loaf(Controller->PCIDevice, &local_dma);
1680       return false;
1681     }
1682   /*
1683     Initialize the Controller Channels, Targets, Memory Size, and SAF-TE
1684     Enclosure Management Enabled fields.
1685   */
1686   Controller->Channels = Enquiry2->ActualChannels;
1687   Controller->Targets = Enquiry2->MaxTargets;
1688   Controller->MemorySize = Enquiry2->MemorySize >> 20;
1689   Controller->V1.SAFTE_EnclosureManagementEnabled =
1690     (Enquiry2->FaultManagementType == DAC960_V1_SAFTE);
1691   /*
1692     Initialize the Controller Queue Depth, Driver Queue Depth, Logical Drive
1693     Count, Maximum Blocks per Command, Controller Scatter/Gather Limit, and
1694     Driver Scatter/Gather Limit.  The Driver Queue Depth must be at most one
1695     less than the Controller Queue Depth to allow for an automatic drive
1696     rebuild operation.
1697   */
1698   Controller->ControllerQueueDepth = Controller->V1.Enquiry.MaxCommands;
1699   Controller->DriverQueueDepth = Controller->ControllerQueueDepth - 1;
1700   if (Controller->DriverQueueDepth > DAC960_MaxDriverQueueDepth)
1701     Controller->DriverQueueDepth = DAC960_MaxDriverQueueDepth;
1702   Controller->LogicalDriveCount =
1703     Controller->V1.Enquiry.NumberOfLogicalDrives;
1704   Controller->MaxBlocksPerCommand = Enquiry2->MaxBlocksPerCommand;
1705   Controller->ControllerScatterGatherLimit = Enquiry2->MaxScatterGatherEntries;
1706   Controller->DriverScatterGatherLimit =
1707     Controller->ControllerScatterGatherLimit;
1708   if (Controller->DriverScatterGatherLimit > DAC960_V1_ScatterGatherLimit)
1709     Controller->DriverScatterGatherLimit = DAC960_V1_ScatterGatherLimit;
1710   /*
1711     Initialize the Stripe Size, Segment Size, and Geometry Translation.
1712   */
1713   Controller->V1.StripeSize = Config2->BlocksPerStripe * Config2->BlockFactor
1714                               >> (10 - DAC960_BlockSizeBits);
1715   Controller->V1.SegmentSize = Config2->BlocksPerCacheLine * Config2->BlockFactor
1716                                >> (10 - DAC960_BlockSizeBits);
1717   switch (Config2->DriveGeometry)
1718     {
1719     case DAC960_V1_Geometry_128_32:
1720       Controller->V1.GeometryTranslationHeads = 128;
1721       Controller->V1.GeometryTranslationSectors = 32;
1722       break;
1723     case DAC960_V1_Geometry_255_63:
1724       Controller->V1.GeometryTranslationHeads = 255;
1725       Controller->V1.GeometryTranslationSectors = 63;
1726       break;
1727     default:
1728       free_dma_loaf(Controller->PCIDevice, &local_dma);
1729       return DAC960_Failure(Controller, "CONFIG2 DRIVE GEOMETRY");
1730     }
1731   /*
1732     Initialize the Background Initialization Status.
1733   */
1734   if ((Controller->FirmwareVersion[0] == '4' &&
1735       strcmp(Controller->FirmwareVersion, "4.08") >= 0) ||
1736       (Controller->FirmwareVersion[0] == '5' &&
1737        strcmp(Controller->FirmwareVersion, "5.08") >= 0))
1738     {
1739       Controller->V1.BackgroundInitializationStatusSupported = true;
1740       DAC960_V1_ExecuteType3B(Controller,
1741                               DAC960_V1_BackgroundInitializationControl, 0x20,
1742                               Controller->
1743                                V1.BackgroundInitializationStatusDMA);
1744       memcpy(&Controller->V1.LastBackgroundInitializationStatus,
1745                 Controller->V1.BackgroundInitializationStatus,
1746                 sizeof(DAC960_V1_BackgroundInitializationStatus_T));
1747     }
1748   /*
1749     Initialize the Logical Drive Initially Accessible flag.
1750   */
1751   for (LogicalDriveNumber = 0;
1752        LogicalDriveNumber < Controller->LogicalDriveCount;
1753        LogicalDriveNumber++)
1754     if (Controller->V1.LogicalDriveInformation
1755                        [LogicalDriveNumber].LogicalDriveState !=
1756         DAC960_V1_LogicalDrive_Offline)
1757       Controller->LogicalDriveInitiallyAccessible[LogicalDriveNumber] = true;
1758   Controller->V1.LastRebuildStatus = DAC960_V1_NoRebuildOrCheckInProgress;
1759   free_dma_loaf(Controller->PCIDevice, &local_dma);
1760   return true;
1761 }
1762
1763
1764 /*
1765   DAC960_V2_ReadControllerConfiguration reads the Configuration Information
1766   from DAC960 V2 Firmware Controllers and initializes the Controller structure.
1767 */
1768
1769 static boolean DAC960_V2_ReadControllerConfiguration(DAC960_Controller_T
1770                                                      *Controller)
1771 {
1772   DAC960_V2_ControllerInfo_T *ControllerInfo =
1773                 &Controller->V2.ControllerInformation;
1774   unsigned short LogicalDeviceNumber = 0;
1775   int ModelNameLength;
1776
1777   /* Get data into dma-able area, then copy into permanant location */
1778   if (!DAC960_V2_NewControllerInfo(Controller))
1779     return DAC960_Failure(Controller, "GET CONTROLLER INFO");
1780   memcpy(ControllerInfo, Controller->V2.NewControllerInformation,
1781                         sizeof(DAC960_V2_ControllerInfo_T));
1782
1783
1784   if (!DAC960_V2_GeneralInfo(Controller))
1785     return DAC960_Failure(Controller, "GET HEALTH STATUS");
1786
1787   /*
1788     Initialize the Controller Model Name and Full Model Name fields.
1789   */
1790   ModelNameLength = sizeof(ControllerInfo->ControllerName);
1791   if (ModelNameLength > sizeof(Controller->ModelName)-1)
1792     ModelNameLength = sizeof(Controller->ModelName)-1;
1793   memcpy(Controller->ModelName, ControllerInfo->ControllerName,
1794          ModelNameLength);
1795   ModelNameLength--;
1796   while (Controller->ModelName[ModelNameLength] == ' ' ||
1797          Controller->ModelName[ModelNameLength] == '\0')
1798     ModelNameLength--;
1799   Controller->ModelName[++ModelNameLength] = '\0';
1800   strcpy(Controller->FullModelName, "Mylex ");
1801   strcat(Controller->FullModelName, Controller->ModelName);
1802   /*
1803     Initialize the Controller Firmware Version field.
1804   */
1805   sprintf(Controller->FirmwareVersion, "%d.%02d-%02d",
1806           ControllerInfo->FirmwareMajorVersion,
1807           ControllerInfo->FirmwareMinorVersion,
1808           ControllerInfo->FirmwareTurnNumber);
1809   if (ControllerInfo->FirmwareMajorVersion == 6 &&
1810       ControllerInfo->FirmwareMinorVersion == 0 &&
1811       ControllerInfo->FirmwareTurnNumber < 1)
1812     {
1813       DAC960_Info("FIRMWARE VERSION %s DOES NOT PROVIDE THE CONTROLLER\n",
1814                   Controller, Controller->FirmwareVersion);
1815       DAC960_Info("STATUS MONITORING FUNCTIONALITY NEEDED BY THIS DRIVER.\n",
1816                   Controller);
1817       DAC960_Info("PLEASE UPGRADE TO VERSION 6.00-01 OR ABOVE.\n",
1818                   Controller);
1819     }
1820   /*
1821     Initialize the Controller Channels, Targets, and Memory Size.
1822   */
1823   Controller->Channels = ControllerInfo->NumberOfPhysicalChannelsPresent;
1824   Controller->Targets =
1825     ControllerInfo->MaximumTargetsPerChannel
1826                     [ControllerInfo->NumberOfPhysicalChannelsPresent-1];
1827   Controller->MemorySize = ControllerInfo->MemorySizeMB;
1828   /*
1829     Initialize the Controller Queue Depth, Driver Queue Depth, Logical Drive
1830     Count, Maximum Blocks per Command, Controller Scatter/Gather Limit, and
1831     Driver Scatter/Gather Limit.  The Driver Queue Depth must be at most one
1832     less than the Controller Queue Depth to allow for an automatic drive
1833     rebuild operation.
1834   */
1835   Controller->ControllerQueueDepth = ControllerInfo->MaximumParallelCommands;
1836   Controller->DriverQueueDepth = Controller->ControllerQueueDepth - 1;
1837   if (Controller->DriverQueueDepth > DAC960_MaxDriverQueueDepth)
1838     Controller->DriverQueueDepth = DAC960_MaxDriverQueueDepth;
1839   Controller->LogicalDriveCount = ControllerInfo->LogicalDevicesPresent;
1840   Controller->MaxBlocksPerCommand =
1841     ControllerInfo->MaximumDataTransferSizeInBlocks;
1842   Controller->ControllerScatterGatherLimit =
1843     ControllerInfo->MaximumScatterGatherEntries;
1844   Controller->DriverScatterGatherLimit =
1845     Controller->ControllerScatterGatherLimit;
1846   if (Controller->DriverScatterGatherLimit > DAC960_V2_ScatterGatherLimit)
1847     Controller->DriverScatterGatherLimit = DAC960_V2_ScatterGatherLimit;
1848   /*
1849     Initialize the Logical Device Information.
1850   */
1851   while (true)
1852     {
1853       DAC960_V2_LogicalDeviceInfo_T *NewLogicalDeviceInfo =
1854         Controller->V2.NewLogicalDeviceInformation;
1855       DAC960_V2_LogicalDeviceInfo_T *LogicalDeviceInfo;
1856       DAC960_V2_PhysicalDevice_T PhysicalDevice;
1857
1858       if (!DAC960_V2_NewLogicalDeviceInfo(Controller, LogicalDeviceNumber))
1859         break;
1860       LogicalDeviceNumber = NewLogicalDeviceInfo->LogicalDeviceNumber;
1861       if (LogicalDeviceNumber >= DAC960_MaxLogicalDrives) {
1862         DAC960_Error("DAC960: Logical Drive Number %d not supported\n",
1863                        Controller, LogicalDeviceNumber);
1864                 break;
1865       }
1866       if (NewLogicalDeviceInfo->DeviceBlockSizeInBytes != DAC960_BlockSize) {
1867         DAC960_Error("DAC960: Logical Drive Block Size %d not supported\n",
1868               Controller, NewLogicalDeviceInfo->DeviceBlockSizeInBytes);
1869         LogicalDeviceNumber++;
1870         continue;
1871       }
1872       PhysicalDevice.Controller = 0;
1873       PhysicalDevice.Channel = NewLogicalDeviceInfo->Channel;
1874       PhysicalDevice.TargetID = NewLogicalDeviceInfo->TargetID;
1875       PhysicalDevice.LogicalUnit = NewLogicalDeviceInfo->LogicalUnit;
1876       Controller->V2.LogicalDriveToVirtualDevice[LogicalDeviceNumber] =
1877         PhysicalDevice;
1878       if (NewLogicalDeviceInfo->LogicalDeviceState !=
1879           DAC960_V2_LogicalDevice_Offline)
1880         Controller->LogicalDriveInitiallyAccessible[LogicalDeviceNumber] = true;
1881       LogicalDeviceInfo = kmalloc(sizeof(DAC960_V2_LogicalDeviceInfo_T),
1882                                    GFP_ATOMIC);
1883       if (LogicalDeviceInfo == NULL)
1884         return DAC960_Failure(Controller, "LOGICAL DEVICE ALLOCATION");
1885       Controller->V2.LogicalDeviceInformation[LogicalDeviceNumber] =
1886         LogicalDeviceInfo;
1887       memcpy(LogicalDeviceInfo, NewLogicalDeviceInfo,
1888              sizeof(DAC960_V2_LogicalDeviceInfo_T));
1889       LogicalDeviceNumber++;
1890     }
1891   return true;
1892 }
1893
1894
1895 /*
1896   DAC960_ReportControllerConfiguration reports the Configuration Information
1897   for Controller.
1898 */
1899
1900 static boolean DAC960_ReportControllerConfiguration(DAC960_Controller_T
1901                                                     *Controller)
1902 {
1903   DAC960_Info("Configuring Mylex %s PCI RAID Controller\n",
1904               Controller, Controller->ModelName);
1905   DAC960_Info("  Firmware Version: %s, Channels: %d, Memory Size: %dMB\n",
1906               Controller, Controller->FirmwareVersion,
1907               Controller->Channels, Controller->MemorySize);
1908   DAC960_Info("  PCI Bus: %d, Device: %d, Function: %d, I/O Address: ",
1909               Controller, Controller->Bus,
1910               Controller->Device, Controller->Function);
1911   if (Controller->IO_Address == 0)
1912     DAC960_Info("Unassigned\n", Controller);
1913   else DAC960_Info("0x%X\n", Controller, Controller->IO_Address);
1914   DAC960_Info("  PCI Address: 0x%X mapped at 0x%lX, IRQ Channel: %d\n",
1915               Controller, Controller->PCI_Address,
1916               (unsigned long) Controller->BaseAddress,
1917               Controller->IRQ_Channel);
1918   DAC960_Info("  Controller Queue Depth: %d, "
1919               "Maximum Blocks per Command: %d\n",
1920               Controller, Controller->ControllerQueueDepth,
1921               Controller->MaxBlocksPerCommand);
1922   DAC960_Info("  Driver Queue Depth: %d, "
1923               "Scatter/Gather Limit: %d of %d Segments\n",
1924               Controller, Controller->DriverQueueDepth,
1925               Controller->DriverScatterGatherLimit,
1926               Controller->ControllerScatterGatherLimit);
1927   if (Controller->FirmwareType == DAC960_V1_Controller)
1928     {
1929       DAC960_Info("  Stripe Size: %dKB, Segment Size: %dKB, "
1930                   "BIOS Geometry: %d/%d\n", Controller,
1931                   Controller->V1.StripeSize,
1932                   Controller->V1.SegmentSize,
1933                   Controller->V1.GeometryTranslationHeads,
1934                   Controller->V1.GeometryTranslationSectors);
1935       if (Controller->V1.SAFTE_EnclosureManagementEnabled)
1936         DAC960_Info("  SAF-TE Enclosure Management Enabled\n", Controller);
1937     }
1938   return true;
1939 }
1940
1941
1942 /*
1943   DAC960_V1_ReadDeviceConfiguration reads the Device Configuration Information
1944   for DAC960 V1 Firmware Controllers by requesting the SCSI Inquiry and SCSI
1945   Inquiry Unit Serial Number information for each device connected to
1946   Controller.
1947 */
1948
1949 static boolean DAC960_V1_ReadDeviceConfiguration(DAC960_Controller_T
1950                                                  *Controller)
1951 {
1952   struct dma_loaf local_dma;
1953
1954   dma_addr_t DCDBs_dma[DAC960_V1_MaxChannels];
1955   DAC960_V1_DCDB_T *DCDBs_cpu[DAC960_V1_MaxChannels];
1956
1957   dma_addr_t SCSI_Inquiry_dma[DAC960_V1_MaxChannels];
1958   DAC960_SCSI_Inquiry_T *SCSI_Inquiry_cpu[DAC960_V1_MaxChannels];
1959
1960   dma_addr_t SCSI_NewInquiryUnitSerialNumberDMA[DAC960_V1_MaxChannels];
1961   DAC960_SCSI_Inquiry_UnitSerialNumber_T *SCSI_NewInquiryUnitSerialNumberCPU[DAC960_V1_MaxChannels];
1962
1963   struct completion Completions[DAC960_V1_MaxChannels];
1964   unsigned long flags;
1965   int Channel, TargetID;
1966
1967   if (!init_dma_loaf(Controller->PCIDevice, &local_dma,
1968                 DAC960_V1_MaxChannels*(sizeof(DAC960_V1_DCDB_T) +
1969                         sizeof(DAC960_SCSI_Inquiry_T) +
1970                         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T))))
1971      return DAC960_Failure(Controller,
1972                         "DMA ALLOCATION FAILED IN ReadDeviceConfiguration");
1973
1974   for (Channel = 0; Channel < Controller->Channels; Channel++) {
1975         DCDBs_cpu[Channel] = slice_dma_loaf(&local_dma,
1976                         sizeof(DAC960_V1_DCDB_T), DCDBs_dma + Channel);
1977         SCSI_Inquiry_cpu[Channel] = slice_dma_loaf(&local_dma,
1978                         sizeof(DAC960_SCSI_Inquiry_T),
1979                         SCSI_Inquiry_dma + Channel);
1980         SCSI_NewInquiryUnitSerialNumberCPU[Channel] = slice_dma_loaf(&local_dma,
1981                         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T),
1982                         SCSI_NewInquiryUnitSerialNumberDMA + Channel);
1983   }
1984
1985   for (TargetID = 0; TargetID < Controller->Targets; TargetID++)
1986     {
1987       /*
1988        * For each channel, submit a probe for a device on that channel.
1989        * The timeout interval for a device that is present is 10 seconds.
1990        * With this approach, the timeout periods can elapse in parallel
1991        * on each channel.
1992        */
1993       for (Channel = 0; Channel < Controller->Channels; Channel++)
1994         {
1995           dma_addr_t NewInquiryStandardDataDMA = SCSI_Inquiry_dma[Channel];
1996           DAC960_V1_DCDB_T *DCDB = DCDBs_cpu[Channel];
1997           dma_addr_t DCDB_dma = DCDBs_dma[Channel];
1998           DAC960_Command_T *Command = Controller->Commands[Channel];
1999           struct completion *Completion = &Completions[Channel];
2000
2001           init_completion(Completion);
2002           DAC960_V1_ClearCommand(Command);
2003           Command->CommandType = DAC960_ImmediateCommand;
2004           Command->Completion = Completion;
2005           Command->V1.CommandMailbox.Type3.CommandOpcode = DAC960_V1_DCDB;
2006           Command->V1.CommandMailbox.Type3.BusAddress = DCDB_dma;
2007           DCDB->Channel = Channel;
2008           DCDB->TargetID = TargetID;
2009           DCDB->Direction = DAC960_V1_DCDB_DataTransferDeviceToSystem;
2010           DCDB->EarlyStatus = false;
2011           DCDB->Timeout = DAC960_V1_DCDB_Timeout_10_seconds;
2012           DCDB->NoAutomaticRequestSense = false;
2013           DCDB->DisconnectPermitted = true;
2014           DCDB->TransferLength = sizeof(DAC960_SCSI_Inquiry_T);
2015           DCDB->BusAddress = NewInquiryStandardDataDMA;
2016           DCDB->CDBLength = 6;
2017           DCDB->TransferLengthHigh4 = 0;
2018           DCDB->SenseLength = sizeof(DCDB->SenseData);
2019           DCDB->CDB[0] = 0x12; /* INQUIRY */
2020           DCDB->CDB[1] = 0; /* EVPD = 0 */
2021           DCDB->CDB[2] = 0; /* Page Code */
2022           DCDB->CDB[3] = 0; /* Reserved */
2023           DCDB->CDB[4] = sizeof(DAC960_SCSI_Inquiry_T);
2024           DCDB->CDB[5] = 0; /* Control */
2025
2026           spin_lock_irqsave(&Controller->queue_lock, flags);
2027           DAC960_QueueCommand(Command);
2028           spin_unlock_irqrestore(&Controller->queue_lock, flags);
2029         }
2030       /*
2031        * Wait for the problems submitted in the previous loop
2032        * to complete.  On the probes that are successful,
2033        * get the serial number of the device that was found.
2034        */
2035       for (Channel = 0; Channel < Controller->Channels; Channel++)
2036         {
2037           DAC960_SCSI_Inquiry_T *InquiryStandardData =
2038             &Controller->V1.InquiryStandardData[Channel][TargetID];
2039           DAC960_SCSI_Inquiry_T *NewInquiryStandardData = SCSI_Inquiry_cpu[Channel];
2040           dma_addr_t NewInquiryUnitSerialNumberDMA =
2041                         SCSI_NewInquiryUnitSerialNumberDMA[Channel];
2042           DAC960_SCSI_Inquiry_UnitSerialNumber_T *NewInquiryUnitSerialNumber =
2043                         SCSI_NewInquiryUnitSerialNumberCPU[Channel];
2044           DAC960_SCSI_Inquiry_UnitSerialNumber_T *InquiryUnitSerialNumber =
2045             &Controller->V1.InquiryUnitSerialNumber[Channel][TargetID];
2046           DAC960_Command_T *Command = Controller->Commands[Channel];
2047           DAC960_V1_DCDB_T *DCDB = DCDBs_cpu[Channel];
2048           struct completion *Completion = &Completions[Channel];
2049
2050           wait_for_completion(Completion);
2051
2052           if (Command->V1.CommandStatus != DAC960_V1_NormalCompletion) {
2053             memset(InquiryStandardData, 0, sizeof(DAC960_SCSI_Inquiry_T));
2054             InquiryStandardData->PeripheralDeviceType = 0x1F;
2055             continue;
2056           } else
2057             memcpy(InquiryStandardData, NewInquiryStandardData, sizeof(DAC960_SCSI_Inquiry_T));
2058
2059           /* Preserve Channel and TargetID values from the previous loop */
2060           Command->Completion = Completion;
2061           DCDB->TransferLength = sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T);
2062           DCDB->BusAddress = NewInquiryUnitSerialNumberDMA;
2063           DCDB->SenseLength = sizeof(DCDB->SenseData);
2064           DCDB->CDB[0] = 0x12; /* INQUIRY */
2065           DCDB->CDB[1] = 1; /* EVPD = 1 */
2066           DCDB->CDB[2] = 0x80; /* Page Code */
2067           DCDB->CDB[3] = 0; /* Reserved */
2068           DCDB->CDB[4] = sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T);
2069           DCDB->CDB[5] = 0; /* Control */
2070
2071           spin_lock_irqsave(&Controller->queue_lock, flags);
2072           DAC960_QueueCommand(Command);
2073           spin_unlock_irqrestore(&Controller->queue_lock, flags);
2074           wait_for_completion(Completion);
2075
2076           if (Command->V1.CommandStatus != DAC960_V1_NormalCompletion) {
2077                 memset(InquiryUnitSerialNumber, 0,
2078                         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T));
2079                 InquiryUnitSerialNumber->PeripheralDeviceType = 0x1F;
2080           } else
2081                 memcpy(InquiryUnitSerialNumber, NewInquiryUnitSerialNumber,
2082                         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T));
2083         }
2084     }
2085     free_dma_loaf(Controller->PCIDevice, &local_dma);
2086   return true;
2087 }
2088
2089
2090 /*
2091   DAC960_V2_ReadDeviceConfiguration reads the Device Configuration Information
2092   for DAC960 V2 Firmware Controllers by requesting the Physical Device
2093   Information and SCSI Inquiry Unit Serial Number information for each
2094   device connected to Controller.
2095 */
2096
2097 static boolean DAC960_V2_ReadDeviceConfiguration(DAC960_Controller_T
2098                                                  *Controller)
2099 {
2100   unsigned char Channel = 0, TargetID = 0, LogicalUnit = 0;
2101   unsigned short PhysicalDeviceIndex = 0;
2102
2103   while (true)
2104     {
2105       DAC960_V2_PhysicalDeviceInfo_T *NewPhysicalDeviceInfo =
2106                 Controller->V2.NewPhysicalDeviceInformation;
2107       DAC960_V2_PhysicalDeviceInfo_T *PhysicalDeviceInfo;
2108       DAC960_SCSI_Inquiry_UnitSerialNumber_T *NewInquiryUnitSerialNumber =
2109                 Controller->V2.NewInquiryUnitSerialNumber;
2110       DAC960_SCSI_Inquiry_UnitSerialNumber_T *InquiryUnitSerialNumber;
2111
2112       if (!DAC960_V2_NewPhysicalDeviceInfo(Controller, Channel, TargetID, LogicalUnit))
2113           break;
2114
2115       PhysicalDeviceInfo = kmalloc(sizeof(DAC960_V2_PhysicalDeviceInfo_T),
2116                                     GFP_ATOMIC);
2117       if (PhysicalDeviceInfo == NULL)
2118                 return DAC960_Failure(Controller, "PHYSICAL DEVICE ALLOCATION");
2119       Controller->V2.PhysicalDeviceInformation[PhysicalDeviceIndex] =
2120                 PhysicalDeviceInfo;
2121       memcpy(PhysicalDeviceInfo, NewPhysicalDeviceInfo,
2122                 sizeof(DAC960_V2_PhysicalDeviceInfo_T));
2123
2124       InquiryUnitSerialNumber = kmalloc(
2125               sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T), GFP_ATOMIC);
2126       if (InquiryUnitSerialNumber == NULL) {
2127         kfree(PhysicalDeviceInfo);
2128         return DAC960_Failure(Controller, "SERIAL NUMBER ALLOCATION");
2129       }
2130       Controller->V2.InquiryUnitSerialNumber[PhysicalDeviceIndex] =
2131                 InquiryUnitSerialNumber;
2132
2133       Channel = NewPhysicalDeviceInfo->Channel;
2134       TargetID = NewPhysicalDeviceInfo->TargetID;
2135       LogicalUnit = NewPhysicalDeviceInfo->LogicalUnit;
2136
2137       /*
2138          Some devices do NOT have Unit Serial Numbers.
2139          This command fails for them.  But, we still want to
2140          remember those devices are there.  Construct a
2141          UnitSerialNumber structure for the failure case.
2142       */
2143       if (!DAC960_V2_NewInquiryUnitSerialNumber(Controller, Channel, TargetID, LogicalUnit)) {
2144         memset(InquiryUnitSerialNumber, 0,
2145              sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T));
2146         InquiryUnitSerialNumber->PeripheralDeviceType = 0x1F;
2147       } else
2148         memcpy(InquiryUnitSerialNumber, NewInquiryUnitSerialNumber,
2149                 sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T));
2150
2151       PhysicalDeviceIndex++;
2152       LogicalUnit++;
2153     }
2154   return true;
2155 }
2156
2157
2158 /*
2159   DAC960_SanitizeInquiryData sanitizes the Vendor, Model, Revision, and
2160   Product Serial Number fields of the Inquiry Standard Data and Inquiry
2161   Unit Serial Number structures.
2162 */
2163
2164 static void DAC960_SanitizeInquiryData(DAC960_SCSI_Inquiry_T
2165                                          *InquiryStandardData,
2166                                        DAC960_SCSI_Inquiry_UnitSerialNumber_T
2167                                          *InquiryUnitSerialNumber,
2168                                        unsigned char *Vendor,
2169                                        unsigned char *Model,
2170                                        unsigned char *Revision,
2171                                        unsigned char *SerialNumber)
2172 {
2173   int SerialNumberLength, i;
2174   if (InquiryStandardData->PeripheralDeviceType == 0x1F) return;
2175   for (i = 0; i < sizeof(InquiryStandardData->VendorIdentification); i++)
2176     {
2177       unsigned char VendorCharacter =
2178         InquiryStandardData->VendorIdentification[i];
2179       Vendor[i] = (VendorCharacter >= ' ' && VendorCharacter <= '~'
2180                    ? VendorCharacter : ' ');
2181     }
2182   Vendor[sizeof(InquiryStandardData->VendorIdentification)] = '\0';
2183   for (i = 0; i < sizeof(InquiryStandardData->ProductIdentification); i++)
2184     {
2185       unsigned char ModelCharacter =
2186         InquiryStandardData->ProductIdentification[i];
2187       Model[i] = (ModelCharacter >= ' ' && ModelCharacter <= '~'
2188                   ? ModelCharacter : ' ');
2189     }
2190   Model[sizeof(InquiryStandardData->ProductIdentification)] = '\0';
2191   for (i = 0; i < sizeof(InquiryStandardData->ProductRevisionLevel); i++)
2192     {
2193       unsigned char RevisionCharacter =
2194         InquiryStandardData->ProductRevisionLevel[i];
2195       Revision[i] = (RevisionCharacter >= ' ' && RevisionCharacter <= '~'
2196                      ? RevisionCharacter : ' ');
2197     }
2198   Revision[sizeof(InquiryStandardData->ProductRevisionLevel)] = '\0';
2199   if (InquiryUnitSerialNumber->PeripheralDeviceType == 0x1F) return;
2200   SerialNumberLength = InquiryUnitSerialNumber->PageLength;
2201   if (SerialNumberLength >
2202       sizeof(InquiryUnitSerialNumber->ProductSerialNumber))
2203     SerialNumberLength = sizeof(InquiryUnitSerialNumber->ProductSerialNumber);
2204   for (i = 0; i < SerialNumberLength; i++)
2205     {
2206       unsigned char SerialNumberCharacter =
2207         InquiryUnitSerialNumber->ProductSerialNumber[i];
2208       SerialNumber[i] =
2209         (SerialNumberCharacter >= ' ' && SerialNumberCharacter <= '~'
2210          ? SerialNumberCharacter : ' ');
2211     }
2212   SerialNumber[SerialNumberLength] = '\0';
2213 }
2214
2215
2216 /*
2217   DAC960_V1_ReportDeviceConfiguration reports the Device Configuration
2218   Information for DAC960 V1 Firmware Controllers.
2219 */
2220
2221 static boolean DAC960_V1_ReportDeviceConfiguration(DAC960_Controller_T
2222                                                    *Controller)
2223 {
2224   int LogicalDriveNumber, Channel, TargetID;
2225   DAC960_Info("  Physical Devices:\n", Controller);
2226   for (Channel = 0; Channel < Controller->Channels; Channel++)
2227     for (TargetID = 0; TargetID < Controller->Targets; TargetID++)
2228       {
2229         DAC960_SCSI_Inquiry_T *InquiryStandardData =
2230           &Controller->V1.InquiryStandardData[Channel][TargetID];
2231         DAC960_SCSI_Inquiry_UnitSerialNumber_T *InquiryUnitSerialNumber =
2232           &Controller->V1.InquiryUnitSerialNumber[Channel][TargetID];
2233         DAC960_V1_DeviceState_T *DeviceState =
2234           &Controller->V1.DeviceState[Channel][TargetID];
2235         DAC960_V1_ErrorTableEntry_T *ErrorEntry =
2236           &Controller->V1.ErrorTable.ErrorTableEntries[Channel][TargetID];
2237         char Vendor[1+sizeof(InquiryStandardData->VendorIdentification)];
2238         char Model[1+sizeof(InquiryStandardData->ProductIdentification)];
2239         char Revision[1+sizeof(InquiryStandardData->ProductRevisionLevel)];
2240         char SerialNumber[1+sizeof(InquiryUnitSerialNumber
2241                                    ->ProductSerialNumber)];
2242         if (InquiryStandardData->PeripheralDeviceType == 0x1F) continue;
2243         DAC960_SanitizeInquiryData(InquiryStandardData, InquiryUnitSerialNumber,
2244                                    Vendor, Model, Revision, SerialNumber);
2245         DAC960_Info("    %d:%d%s Vendor: %s  Model: %s  Revision: %s\n",
2246                     Controller, Channel, TargetID, (TargetID < 10 ? " " : ""),
2247                     Vendor, Model, Revision);
2248         if (InquiryUnitSerialNumber->PeripheralDeviceType != 0x1F)
2249           DAC960_Info("         Serial Number: %s\n", Controller, SerialNumber);
2250         if (DeviceState->Present &&
2251             DeviceState->DeviceType == DAC960_V1_DiskType)
2252           {
2253             if (Controller->V1.DeviceResetCount[Channel][TargetID] > 0)
2254               DAC960_Info("         Disk Status: %s, %u blocks, %d resets\n",
2255                           Controller,
2256                           (DeviceState->DeviceState == DAC960_V1_Device_Dead
2257                            ? "Dead"
2258                            : DeviceState->DeviceState
2259                              == DAC960_V1_Device_WriteOnly
2260                              ? "Write-Only"
2261                              : DeviceState->DeviceState
2262                                == DAC960_V1_Device_Online
2263                                ? "Online" : "Standby"),
2264                           DeviceState->DiskSize,
2265                           Controller->V1.DeviceResetCount[Channel][TargetID]);
2266             else
2267               DAC960_Info("         Disk Status: %s, %u blocks\n", Controller,
2268                           (DeviceState->DeviceState == DAC960_V1_Device_Dead
2269                            ? "Dead"
2270                            : DeviceState->DeviceState
2271                              == DAC960_V1_Device_WriteOnly
2272                              ? "Write-Only"
2273                              : DeviceState->DeviceState
2274                                == DAC960_V1_Device_Online
2275                                ? "Online" : "Standby"),
2276                           DeviceState->DiskSize);
2277           }
2278         if (ErrorEntry->ParityErrorCount > 0 ||
2279             ErrorEntry->SoftErrorCount > 0 ||
2280             ErrorEntry->HardErrorCount > 0 ||
2281             ErrorEntry->MiscErrorCount > 0)
2282           DAC960_Info("         Errors - Parity: %d, Soft: %d, "
2283                       "Hard: %d, Misc: %d\n", Controller,
2284                       ErrorEntry->ParityErrorCount,
2285                       ErrorEntry->SoftErrorCount,
2286                       ErrorEntry->HardErrorCount,
2287                       ErrorEntry->MiscErrorCount);
2288       }
2289   DAC960_Info("  Logical Drives:\n", Controller);
2290   for (LogicalDriveNumber = 0;
2291        LogicalDriveNumber < Controller->LogicalDriveCount;
2292        LogicalDriveNumber++)
2293     {
2294       DAC960_V1_LogicalDriveInformation_T *LogicalDriveInformation =
2295         &Controller->V1.LogicalDriveInformation[LogicalDriveNumber];
2296       DAC960_Info("    /dev/rd/c%dd%d: RAID-%d, %s, %u blocks, %s\n",
2297                   Controller, Controller->ControllerNumber, LogicalDriveNumber,
2298                   LogicalDriveInformation->RAIDLevel,
2299                   (LogicalDriveInformation->LogicalDriveState
2300                    == DAC960_V1_LogicalDrive_Online
2301                    ? "Online"
2302                    : LogicalDriveInformation->LogicalDriveState
2303                      == DAC960_V1_LogicalDrive_Critical
2304                      ? "Critical" : "Offline"),
2305                   LogicalDriveInformation->LogicalDriveSize,
2306                   (LogicalDriveInformation->WriteBack
2307                    ? "Write Back" : "Write Thru"));
2308     }
2309   return true;
2310 }
2311
2312
2313 /*
2314   DAC960_V2_ReportDeviceConfiguration reports the Device Configuration
2315   Information for DAC960 V2 Firmware Controllers.
2316 */
2317
2318 static boolean DAC960_V2_ReportDeviceConfiguration(DAC960_Controller_T
2319                                                    *Controller)
2320 {
2321   int PhysicalDeviceIndex, LogicalDriveNumber;
2322   DAC960_Info("  Physical Devices:\n", Controller);
2323   for (PhysicalDeviceIndex = 0;
2324        PhysicalDeviceIndex < DAC960_V2_MaxPhysicalDevices;
2325        PhysicalDeviceIndex++)
2326     {
2327       DAC960_V2_PhysicalDeviceInfo_T *PhysicalDeviceInfo =
2328         Controller->V2.PhysicalDeviceInformation[PhysicalDeviceIndex];
2329       DAC960_SCSI_Inquiry_T *InquiryStandardData =
2330         (DAC960_SCSI_Inquiry_T *) &PhysicalDeviceInfo->SCSI_InquiryData;
2331       DAC960_SCSI_Inquiry_UnitSerialNumber_T *InquiryUnitSerialNumber =
2332         Controller->V2.InquiryUnitSerialNumber[PhysicalDeviceIndex];
2333       char Vendor[1+sizeof(InquiryStandardData->VendorIdentification)];
2334       char Model[1+sizeof(InquiryStandardData->ProductIdentification)];
2335       char Revision[1+sizeof(InquiryStandardData->ProductRevisionLevel)];
2336       char SerialNumber[1+sizeof(InquiryUnitSerialNumber->ProductSerialNumber)];
2337       if (PhysicalDeviceInfo == NULL) break;
2338       DAC960_SanitizeInquiryData(InquiryStandardData, InquiryUnitSerialNumber,
2339                                  Vendor, Model, Revision, SerialNumber);
2340       DAC960_Info("    %d:%d%s Vendor: %s  Model: %s  Revision: %s\n",
2341                   Controller,
2342                   PhysicalDeviceInfo->Channel,
2343                   PhysicalDeviceInfo->TargetID,
2344                   (PhysicalDeviceInfo->TargetID < 10 ? " " : ""),
2345                   Vendor, Model, Revision);
2346       if (PhysicalDeviceInfo->NegotiatedSynchronousMegaTransfers == 0)
2347         DAC960_Info("         %sAsynchronous\n", Controller,
2348                     (PhysicalDeviceInfo->NegotiatedDataWidthBits == 16
2349                      ? "Wide " :""));
2350       else
2351         DAC960_Info("         %sSynchronous at %d MB/sec\n", Controller,
2352                     (PhysicalDeviceInfo->NegotiatedDataWidthBits == 16
2353                      ? "Wide " :""),
2354                     (PhysicalDeviceInfo->NegotiatedSynchronousMegaTransfers
2355                      * PhysicalDeviceInfo->NegotiatedDataWidthBits/8));
2356       if (InquiryUnitSerialNumber->PeripheralDeviceType != 0x1F)
2357         DAC960_Info("         Serial Number: %s\n", Controller, SerialNumber);
2358       if (PhysicalDeviceInfo->PhysicalDeviceState ==
2359           DAC960_V2_Device_Unconfigured)
2360         continue;
2361       DAC960_Info("         Disk Status: %s, %u blocks\n", Controller,
2362                   (PhysicalDeviceInfo->PhysicalDeviceState
2363                    == DAC960_V2_Device_Online
2364                    ? "Online"
2365                    : PhysicalDeviceInfo->PhysicalDeviceState
2366                      == DAC960_V2_Device_Rebuild
2367                      ? "Rebuild"
2368                      : PhysicalDeviceInfo->PhysicalDeviceState
2369                        == DAC960_V2_Device_Missing
2370                        ? "Missing"
2371                        : PhysicalDeviceInfo->PhysicalDeviceState
2372                          == DAC960_V2_Device_Critical
2373                          ? "Critical"
2374                          : PhysicalDeviceInfo->PhysicalDeviceState
2375                            == DAC960_V2_Device_Dead
2376                            ? "Dead"
2377                            : PhysicalDeviceInfo->PhysicalDeviceState
2378                              == DAC960_V2_Device_SuspectedDead
2379                              ? "Suspected-Dead"
2380                              : PhysicalDeviceInfo->PhysicalDeviceState
2381                                == DAC960_V2_Device_CommandedOffline
2382                                ? "Commanded-Offline"
2383                                : PhysicalDeviceInfo->PhysicalDeviceState
2384                                  == DAC960_V2_Device_Standby
2385                                  ? "Standby" : "Unknown"),
2386                   PhysicalDeviceInfo->ConfigurableDeviceSize);
2387       if (PhysicalDeviceInfo->ParityErrors == 0 &&
2388           PhysicalDeviceInfo->SoftErrors == 0 &&
2389           PhysicalDeviceInfo->HardErrors == 0 &&
2390           PhysicalDeviceInfo->MiscellaneousErrors == 0 &&
2391           PhysicalDeviceInfo->CommandTimeouts == 0 &&
2392           PhysicalDeviceInfo->Retries == 0 &&
2393           PhysicalDeviceInfo->Aborts == 0 &&
2394           PhysicalDeviceInfo->PredictedFailuresDetected == 0)
2395         continue;
2396       DAC960_Info("         Errors - Parity: %d, Soft: %d, "
2397                   "Hard: %d, Misc: %d\n", Controller,
2398                   PhysicalDeviceInfo->ParityErrors,
2399                   PhysicalDeviceInfo->SoftErrors,
2400                   PhysicalDeviceInfo->HardErrors,
2401                   PhysicalDeviceInfo->MiscellaneousErrors);
2402       DAC960_Info("                  Timeouts: %d, Retries: %d, "
2403                   "Aborts: %d, Predicted: %d\n", Controller,
2404                   PhysicalDeviceInfo->CommandTimeouts,
2405                   PhysicalDeviceInfo->Retries,
2406                   PhysicalDeviceInfo->Aborts,
2407                   PhysicalDeviceInfo->PredictedFailuresDetected);
2408     }
2409   DAC960_Info("  Logical Drives:\n", Controller);
2410   for (LogicalDriveNumber = 0;
2411        LogicalDriveNumber < DAC960_MaxLogicalDrives;
2412        LogicalDriveNumber++)
2413     {
2414       DAC960_V2_LogicalDeviceInfo_T *LogicalDeviceInfo =
2415         Controller->V2.LogicalDeviceInformation[LogicalDriveNumber];
2416       unsigned char *ReadCacheStatus[] = { "Read Cache Disabled",
2417                                            "Read Cache Enabled",
2418                                            "Read Ahead Enabled",
2419                                            "Intelligent Read Ahead Enabled",
2420                                            "-", "-", "-", "-" };
2421       unsigned char *WriteCacheStatus[] = { "Write Cache Disabled",
2422                                             "Logical Device Read Only",
2423                                             "Write Cache Enabled",
2424                                             "Intelligent Write Cache Enabled",
2425                                             "-", "-", "-", "-" };
2426       unsigned char *GeometryTranslation;
2427       if (LogicalDeviceInfo == NULL) continue;
2428       switch (LogicalDeviceInfo->DriveGeometry)
2429         {
2430         case DAC960_V2_Geometry_128_32:
2431           GeometryTranslation = "128/32";
2432           break;
2433         case DAC960_V2_Geometry_255_63:
2434           GeometryTranslation = "255/63";
2435           break;
2436         default:
2437           GeometryTranslation = "Invalid";
2438           DAC960_Error("Illegal Logical Device Geometry %d\n",
2439                        Controller, LogicalDeviceInfo->DriveGeometry);
2440           break;
2441         }
2442       DAC960_Info("    /dev/rd/c%dd%d: RAID-%d, %s, %u blocks\n",
2443                   Controller, Controller->ControllerNumber, LogicalDriveNumber,
2444                   LogicalDeviceInfo->RAIDLevel,
2445                   (LogicalDeviceInfo->LogicalDeviceState
2446                    == DAC960_V2_LogicalDevice_Online
2447                    ? "Online"
2448                    : LogicalDeviceInfo->LogicalDeviceState
2449                      == DAC960_V2_LogicalDevice_Critical
2450                      ? "Critical" : "Offline"),
2451                   LogicalDeviceInfo->ConfigurableDeviceSize);
2452       DAC960_Info("                  Logical Device %s, BIOS Geometry: %s\n",
2453                   Controller,
2454                   (LogicalDeviceInfo->LogicalDeviceControl
2455                                      .LogicalDeviceInitialized
2456                    ? "Initialized" : "Uninitialized"),
2457                   GeometryTranslation);
2458       if (LogicalDeviceInfo->StripeSize == 0)
2459         {
2460           if (LogicalDeviceInfo->CacheLineSize == 0)
2461             DAC960_Info("                  Stripe Size: N/A, "
2462                         "Segment Size: N/A\n", Controller);
2463           else
2464             DAC960_Info("                  Stripe Size: N/A, "
2465                         "Segment Size: %dKB\n", Controller,
2466                         1 << (LogicalDeviceInfo->CacheLineSize - 2));
2467         }
2468       else
2469         {
2470           if (LogicalDeviceInfo->CacheLineSize == 0)
2471             DAC960_Info("                  Stripe Size: %dKB, "
2472                         "Segment Size: N/A\n", Controller,
2473                         1 << (LogicalDeviceInfo->StripeSize - 2));
2474           else
2475             DAC960_Info("                  Stripe Size: %dKB, "
2476                         "Segment Size: %dKB\n", Controller,
2477                         1 << (LogicalDeviceInfo->StripeSize - 2),
2478                         1 << (LogicalDeviceInfo->CacheLineSize - 2));
2479         }
2480       DAC960_Info("                  %s, %s\n", Controller,
2481                   ReadCacheStatus[
2482                     LogicalDeviceInfo->LogicalDeviceControl.ReadCache],
2483                   WriteCacheStatus[
2484                     LogicalDeviceInfo->LogicalDeviceControl.WriteCache]);
2485       if (LogicalDeviceInfo->SoftErrors > 0 ||
2486           LogicalDeviceInfo->CommandsFailed > 0 ||
2487           LogicalDeviceInfo->DeferredWriteErrors)
2488         DAC960_Info("                  Errors - Soft: %d, Failed: %d, "
2489                     "Deferred Write: %d\n", Controller,
2490                     LogicalDeviceInfo->SoftErrors,
2491                     LogicalDeviceInfo->CommandsFailed,
2492                     LogicalDeviceInfo->DeferredWriteErrors);
2493
2494     }
2495   return true;
2496 }
2497
2498 /*
2499   DAC960_RegisterBlockDevice registers the Block Device structures
2500   associated with Controller.
2501 */
2502
2503 static boolean DAC960_RegisterBlockDevice(DAC960_Controller_T *Controller)
2504 {
2505   int MajorNumber = DAC960_MAJOR + Controller->ControllerNumber;
2506   int n;
2507
2508   /*
2509     Register the Block Device Major Number for this DAC960 Controller.
2510   */
2511   if (register_blkdev(MajorNumber, "dac960") < 0)
2512       return false;
2513
2514   for (n = 0; n < DAC960_MaxLogicalDrives; n++) {
2515         struct gendisk *disk = Controller->disks[n];
2516         struct request_queue *RequestQueue;
2517
2518         /* for now, let all request queues share controller's lock */
2519         RequestQueue = blk_init_queue(DAC960_RequestFunction,&Controller->queue_lock);
2520         if (!RequestQueue) {
2521                 printk("DAC960: failure to allocate request queue\n");
2522                 continue;
2523         }
2524         Controller->RequestQueue[n] = RequestQueue;
2525         blk_queue_bounce_limit(RequestQueue, Controller->BounceBufferLimit);
2526         RequestQueue->queuedata = Controller;
2527         blk_queue_max_hw_segments(RequestQueue, Controller->DriverScatterGatherLimit);
2528         blk_queue_max_phys_segments(RequestQueue, Controller->DriverScatterGatherLimit);
2529         blk_queue_max_sectors(RequestQueue, Controller->MaxBlocksPerCommand);
2530         disk->queue = RequestQueue;
2531         sprintf(disk->disk_name, "rd/c%dd%d", Controller->ControllerNumber, n);
2532         disk->major = MajorNumber;
2533         disk->first_minor = n << DAC960_MaxPartitionsBits;
2534         disk->fops = &DAC960_BlockDeviceOperations;
2535    }
2536   /*
2537     Indicate the Block Device Registration completed successfully,
2538   */
2539   return true;
2540 }
2541
2542
2543 /*
2544   DAC960_UnregisterBlockDevice unregisters the Block Device structures
2545   associated with Controller.
2546 */
2547
2548 static void DAC960_UnregisterBlockDevice(DAC960_Controller_T *Controller)
2549 {
2550   int MajorNumber = DAC960_MAJOR + Controller->ControllerNumber;
2551   int disk;
2552
2553   /* does order matter when deleting gendisk and cleanup in request queue? */
2554   for (disk = 0; disk < DAC960_MaxLogicalDrives; disk++) {
2555         del_gendisk(Controller->disks[disk]);
2556         blk_cleanup_queue(Controller->RequestQueue[disk]);
2557         Controller->RequestQueue[disk] = NULL;
2558   }
2559
2560   /*
2561     Unregister the Block Device Major Number for this DAC960 Controller.
2562   */
2563   unregister_blkdev(MajorNumber, "dac960");
2564 }
2565
2566 /*
2567   DAC960_ComputeGenericDiskInfo computes the values for the Generic Disk
2568   Information Partition Sector Counts and Block Sizes.
2569 */
2570
2571 static void DAC960_ComputeGenericDiskInfo(DAC960_Controller_T *Controller)
2572 {
2573         int disk;
2574         for (disk = 0; disk < DAC960_MaxLogicalDrives; disk++)
2575                 set_capacity(Controller->disks[disk], disk_size(Controller, disk));
2576 }
2577
2578 /*
2579   DAC960_ReportErrorStatus reports Controller BIOS Messages passed through
2580   the Error Status Register when the driver performs the BIOS handshaking.
2581   It returns true for fatal errors and false otherwise.
2582 */
2583
2584 static boolean DAC960_ReportErrorStatus(DAC960_Controller_T *Controller,
2585                                         unsigned char ErrorStatus,
2586                                         unsigned char Parameter0,
2587                                         unsigned char Parameter1)
2588 {
2589   switch (ErrorStatus)
2590     {
2591     case 0x00:
2592       DAC960_Notice("Physical Device %d:%d Not Responding\n",
2593                     Controller, Parameter1, Parameter0);
2594       break;
2595     case 0x08:
2596       if (Controller->DriveSpinUpMessageDisplayed) break;
2597       DAC960_Notice("Spinning Up Drives\n", Controller);
2598       Controller->DriveSpinUpMessageDisplayed = true;
2599       break;
2600     case 0x30:
2601       DAC960_Notice("Configuration Checksum Error\n", Controller);
2602       break;
2603     case 0x60:
2604       DAC960_Notice("Mirror Race Recovery Failed\n", Controller);
2605       break;
2606     case 0x70:
2607       DAC960_Notice("Mirror Race Recovery In Progress\n", Controller);
2608       break;
2609     case 0x90:
2610       DAC960_Notice("Physical Device %d:%d COD Mismatch\n",
2611                     Controller, Parameter1, Parameter0);
2612       break;
2613     case 0xA0:
2614       DAC960_Notice("Logical Drive Installation Aborted\n", Controller);
2615       break;
2616     case 0xB0:
2617       DAC960_Notice("Mirror Race On A Critical Logical Drive\n", Controller);
2618       break;
2619     case 0xD0:
2620       DAC960_Notice("New Controller Configuration Found\n", Controller);
2621       break;
2622     case 0xF0:
2623       DAC960_Error("Fatal Memory Parity Error for Controller at\n", Controller);
2624       return true;
2625     default:
2626       DAC960_Error("Unknown Initialization Error %02X for Controller at\n",
2627                    Controller, ErrorStatus);
2628       return true;
2629     }
2630   return false;
2631 }
2632
2633
2634 /*
2635  * DAC960_DetectCleanup releases the resources that were allocated
2636  * during DAC960_DetectController().  DAC960_DetectController can
2637  * has several internal failure points, so not ALL resources may
2638  * have been allocated.  It's important to free only
2639  * resources that HAVE been allocated.  The code below always
2640  * tests that the resource has been allocated before attempting to
2641  * free it.
2642  */
2643 static void DAC960_DetectCleanup(DAC960_Controller_T *Controller)
2644 {
2645   int i;
2646
2647   /* Free the memory mailbox, status, and related structures */
2648   free_dma_loaf(Controller->PCIDevice, &Controller->DmaPages);
2649   if (Controller->MemoryMappedAddress) {
2650         switch(Controller->HardwareType)
2651         {
2652                 case DAC960_GEM_Controller:
2653                         DAC960_GEM_DisableInterrupts(Controller->BaseAddress);
2654                         break;
2655                 case DAC960_BA_Controller:
2656                         DAC960_BA_DisableInterrupts(Controller->BaseAddress);
2657                         break;
2658                 case DAC960_LP_Controller:
2659                         DAC960_LP_DisableInterrupts(Controller->BaseAddress);
2660                         break;
2661                 case DAC960_LA_Controller:
2662                         DAC960_LA_DisableInterrupts(Controller->BaseAddress);
2663                         break;
2664                 case DAC960_PG_Controller:
2665                         DAC960_PG_DisableInterrupts(Controller->BaseAddress);
2666                         break;
2667                 case DAC960_PD_Controller:
2668                         DAC960_PD_DisableInterrupts(Controller->BaseAddress);
2669                         break;
2670                 case DAC960_P_Controller:
2671                         DAC960_PD_DisableInterrupts(Controller->BaseAddress);
2672                         break;
2673         }
2674         iounmap(Controller->MemoryMappedAddress);
2675   }
2676   if (Controller->IRQ_Channel)
2677         free_irq(Controller->IRQ_Channel, Controller);
2678   if (Controller->IO_Address)
2679         release_region(Controller->IO_Address, 0x80);
2680   pci_disable_device(Controller->PCIDevice);
2681   for (i = 0; (i < DAC960_MaxLogicalDrives) && Controller->disks[i]; i++)
2682        put_disk(Controller->disks[i]);
2683   DAC960_Controllers[Controller->ControllerNumber] = NULL;
2684   kfree(Controller);
2685 }
2686
2687
2688 /*
2689   DAC960_DetectController detects Mylex DAC960/AcceleRAID/eXtremeRAID
2690   PCI RAID Controllers by interrogating the PCI Configuration Space for
2691   Controller Type.
2692 */
2693
2694 static DAC960_Controller_T *
2695 DAC960_DetectController(struct pci_dev *PCI_Device,
2696                         const struct pci_device_id *entry)
2697 {
2698   struct DAC960_privdata *privdata =
2699                 (struct DAC960_privdata *)entry->driver_data;
2700   irq_handler_t InterruptHandler = privdata->InterruptHandler;
2701   unsigned int MemoryWindowSize = privdata->MemoryWindowSize;
2702   DAC960_Controller_T *Controller = NULL;
2703   unsigned char DeviceFunction = PCI_Device->devfn;
2704   unsigned char ErrorStatus, Parameter0, Parameter1;
2705   unsigned int IRQ_Channel;
2706   void __iomem *BaseAddress;
2707   int i;
2708
2709   Controller = kzalloc(sizeof(DAC960_Controller_T), GFP_ATOMIC);
2710   if (Controller == NULL) {
2711         DAC960_Error("Unable to allocate Controller structure for "
2712                        "Controller at\n", NULL);
2713         return NULL;
2714   }
2715   Controller->ControllerNumber = DAC960_ControllerCount;
2716   DAC960_Controllers[DAC960_ControllerCount++] = Controller;
2717   Controller->Bus = PCI_Device->bus->number;
2718   Controller->FirmwareType = privdata->FirmwareType;
2719   Controller->HardwareType = privdata->HardwareType;
2720   Controller->Device = DeviceFunction >> 3;
2721   Controller->Function = DeviceFunction & 0x7;
2722   Controller->PCIDevice = PCI_Device;
2723   strcpy(Controller->FullModelName, "DAC960");
2724
2725   if (pci_enable_device(PCI_Device))
2726         goto Failure;
2727
2728   switch (Controller->HardwareType)
2729   {
2730         case DAC960_GEM_Controller:
2731           Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2732           break;
2733         case DAC960_BA_Controller:
2734           Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2735           break;
2736         case DAC960_LP_Controller:
2737           Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2738           break;
2739         case DAC960_LA_Controller:
2740           Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2741           break;
2742         case DAC960_PG_Controller:
2743           Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2744           break;
2745         case DAC960_PD_Controller:
2746           Controller->IO_Address = pci_resource_start(PCI_Device, 0);
2747           Controller->PCI_Address = pci_resource_start(PCI_Device, 1);
2748           break;
2749         case DAC960_P_Controller:
2750           Controller->IO_Address = pci_resource_start(PCI_Device, 0);
2751           Controller->PCI_Address = pci_resource_start(PCI_Device, 1);
2752           break;
2753   }
2754
2755   pci_set_drvdata(PCI_Device, (void *)((long)Controller->ControllerNumber));
2756   for (i = 0; i < DAC960_MaxLogicalDrives; i++) {
2757         Controller->disks[i] = alloc_disk(1<<DAC960_MaxPartitionsBits);
2758         if (!Controller->disks[i])
2759                 goto Failure;
2760         Controller->disks[i]->private_data = (void *)((long)i);
2761   }
2762   init_waitqueue_head(&Controller->CommandWaitQueue);
2763   init_waitqueue_head(&Controller->HealthStatusWaitQueue);
2764   spin_lock_init(&Controller->queue_lock);
2765   DAC960_AnnounceDriver(Controller);
2766   /*
2767     Map the Controller Register Window.
2768   */
2769  if (MemoryWindowSize < PAGE_SIZE)
2770         MemoryWindowSize = PAGE_SIZE;
2771   Controller->MemoryMappedAddress =
2772         ioremap_nocache(Controller->PCI_Address & PAGE_MASK, MemoryWindowSize);
2773   Controller->BaseAddress =
2774         Controller->MemoryMappedAddress + (Controller->PCI_Address & ~PAGE_MASK);
2775   if (Controller->MemoryMappedAddress == NULL)
2776   {
2777           DAC960_Error("Unable to map Controller Register Window for "
2778                        "Controller at\n", Controller);
2779           goto Failure;
2780   }
2781   BaseAddress = Controller->BaseAddress;
2782   switch (Controller->HardwareType)
2783   {
2784         case DAC960_GEM_Controller:
2785           DAC960_GEM_DisableInterrupts(BaseAddress);
2786           DAC960_GEM_AcknowledgeHardwareMailboxStatus(BaseAddress);
2787           udelay(1000);
2788           while (DAC960_GEM_InitializationInProgressP(BaseAddress))
2789             {
2790               if (DAC960_GEM_ReadErrorStatus(BaseAddress, &ErrorStatus,
2791                                             &Parameter0, &Parameter1) &&
2792                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2793                                            Parameter0, Parameter1))
2794                 goto Failure;
2795               udelay(10);
2796             }
2797           if (!DAC960_V2_EnableMemoryMailboxInterface(Controller))
2798             {
2799               DAC960_Error("Unable to Enable Memory Mailbox Interface "
2800                            "for Controller at\n", Controller);
2801               goto Failure;
2802             }
2803           DAC960_GEM_EnableInterrupts(BaseAddress);
2804           Controller->QueueCommand = DAC960_GEM_QueueCommand;
2805           Controller->ReadControllerConfiguration =
2806             DAC960_V2_ReadControllerConfiguration;
2807           Controller->ReadDeviceConfiguration =
2808             DAC960_V2_ReadDeviceConfiguration;
2809           Controller->ReportDeviceConfiguration =
2810             DAC960_V2_ReportDeviceConfiguration;
2811           Controller->QueueReadWriteCommand =
2812             DAC960_V2_QueueReadWriteCommand;
2813           break;
2814         case DAC960_BA_Controller:
2815           DAC960_BA_DisableInterrupts(BaseAddress);
2816           DAC960_BA_AcknowledgeHardwareMailboxStatus(BaseAddress);
2817           udelay(1000);
2818           while (DAC960_BA_InitializationInProgressP(BaseAddress))
2819             {
2820               if (DAC960_BA_ReadErrorStatus(BaseAddress, &ErrorStatus,
2821                                             &Parameter0, &Parameter1) &&
2822                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2823                                            Parameter0, Parameter1))
2824                 goto Failure;
2825               udelay(10);
2826             }
2827           if (!DAC960_V2_EnableMemoryMailboxInterface(Controller))
2828             {
2829               DAC960_Error("Unable to Enable Memory Mailbox Interface "
2830                            "for Controller at\n", Controller);
2831               goto Failure;
2832             }
2833           DAC960_BA_EnableInterrupts(BaseAddress);
2834           Controller->QueueCommand = DAC960_BA_QueueCommand;
2835           Controller->ReadControllerConfiguration =
2836             DAC960_V2_ReadControllerConfiguration;
2837           Controller->ReadDeviceConfiguration =
2838             DAC960_V2_ReadDeviceConfiguration;
2839           Controller->ReportDeviceConfiguration =
2840             DAC960_V2_ReportDeviceConfiguration;
2841           Controller->QueueReadWriteCommand =
2842             DAC960_V2_QueueReadWriteCommand;
2843           break;
2844         case DAC960_LP_Controller:
2845           DAC960_LP_DisableInterrupts(BaseAddress);
2846           DAC960_LP_AcknowledgeHardwareMailboxStatus(BaseAddress);
2847           udelay(1000);
2848           while (DAC960_LP_InitializationInProgressP(BaseAddress))
2849             {
2850               if (DAC960_LP_ReadErrorStatus(BaseAddress, &ErrorStatus,
2851                                             &Parameter0, &Parameter1) &&
2852                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2853                                            Parameter0, Parameter1))
2854                 goto Failure;
2855               udelay(10);
2856             }
2857           if (!DAC960_V2_EnableMemoryMailboxInterface(Controller))
2858             {
2859               DAC960_Error("Unable to Enable Memory Mailbox Interface "
2860                            "for Controller at\n", Controller);
2861               goto Failure;
2862             }
2863           DAC960_LP_EnableInterrupts(BaseAddress);
2864           Controller->QueueCommand = DAC960_LP_QueueCommand;
2865           Controller->ReadControllerConfiguration =
2866             DAC960_V2_ReadControllerConfiguration;
2867           Controller->ReadDeviceConfiguration =
2868             DAC960_V2_ReadDeviceConfiguration;
2869           Controller->ReportDeviceConfiguration =
2870             DAC960_V2_ReportDeviceConfiguration;
2871           Controller->QueueReadWriteCommand =
2872             DAC960_V2_QueueReadWriteCommand;
2873           break;
2874         case DAC960_LA_Controller:
2875           DAC960_LA_DisableInterrupts(BaseAddress);
2876           DAC960_LA_AcknowledgeHardwareMailboxStatus(BaseAddress);
2877           udelay(1000);
2878           while (DAC960_LA_InitializationInProgressP(BaseAddress))
2879             {
2880               if (DAC960_LA_ReadErrorStatus(BaseAddress, &ErrorStatus,
2881                                             &Parameter0, &Parameter1) &&
2882                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2883                                            Parameter0, Parameter1))
2884                 goto Failure;
2885               udelay(10);
2886             }
2887           if (!DAC960_V1_EnableMemoryMailboxInterface(Controller))
2888             {
2889               DAC960_Error("Unable to Enable Memory Mailbox Interface "
2890                            "for Controller at\n", Controller);
2891               goto Failure;
2892             }
2893           DAC960_LA_EnableInterrupts(BaseAddress);
2894           if (Controller->V1.DualModeMemoryMailboxInterface)
2895             Controller->QueueCommand = DAC960_LA_QueueCommandDualMode;
2896           else Controller->QueueCommand = DAC960_LA_QueueCommandSingleMode;
2897           Controller->ReadControllerConfiguration =
2898             DAC960_V1_ReadControllerConfiguration;
2899           Controller->ReadDeviceConfiguration =
2900             DAC960_V1_ReadDeviceConfiguration;
2901           Controller->ReportDeviceConfiguration =
2902             DAC960_V1_ReportDeviceConfiguration;
2903           Controller->QueueReadWriteCommand =
2904             DAC960_V1_QueueReadWriteCommand;
2905           break;
2906         case DAC960_PG_Controller:
2907           DAC960_PG_DisableInterrupts(BaseAddress);
2908           DAC960_PG_AcknowledgeHardwareMailboxStatus(BaseAddress);
2909           udelay(1000);
2910           while (DAC960_PG_InitializationInProgressP(BaseAddress))
2911             {
2912               if (DAC960_PG_ReadErrorStatus(BaseAddress, &ErrorStatus,
2913                                             &Parameter0, &Parameter1) &&
2914                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2915                                            Parameter0, Parameter1))
2916                 goto Failure;
2917               udelay(10);
2918             }
2919           if (!DAC960_V1_EnableMemoryMailboxInterface(Controller))
2920             {
2921               DAC960_Error("Unable to Enable Memory Mailbox Interface "
2922                            "for Controller at\n", Controller);
2923               goto Failure;
2924             }
2925           DAC960_PG_EnableInterrupts(BaseAddress);
2926           if (Controller->V1.DualModeMemoryMailboxInterface)
2927             Controller->QueueCommand = DAC960_PG_QueueCommandDualMode;
2928           else Controller->QueueCommand = DAC960_PG_QueueCommandSingleMode;
2929           Controller->ReadControllerConfiguration =
2930             DAC960_V1_ReadControllerConfiguration;
2931           Controller->ReadDeviceConfiguration =
2932             DAC960_V1_ReadDeviceConfiguration;
2933           Controller->ReportDeviceConfiguration =
2934             DAC960_V1_ReportDeviceConfiguration;
2935           Controller->QueueReadWriteCommand =
2936             DAC960_V1_QueueReadWriteCommand;
2937           break;
2938         case DAC960_PD_Controller:
2939           if (!request_region(Controller->IO_Address, 0x80,
2940                               Controller->FullModelName)) {
2941                 DAC960_Error("IO port 0x%d busy for Controller at\n",
2942                              Controller, Controller->IO_Address);
2943                 goto Failure;
2944           }
2945           DAC960_PD_DisableInterrupts(BaseAddress);
2946           DAC960_PD_AcknowledgeStatus(BaseAddress);
2947           udelay(1000);
2948           while (DAC960_PD_InitializationInProgressP(BaseAddress))
2949             {
2950               if (DAC960_PD_ReadErrorStatus(BaseAddress, &ErrorStatus,
2951                                             &Parameter0, &Parameter1) &&
2952                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2953                                            Parameter0, Parameter1))
2954                 goto Failure;
2955               udelay(10);
2956             }
2957           if (!DAC960_V1_EnableMemoryMailboxInterface(Controller))
2958             {
2959               DAC960_Error("Unable to allocate DMA mapped memory "
2960                            "for Controller at\n", Controller);
2961               goto Failure;
2962             }
2963           DAC960_PD_EnableInterrupts(BaseAddress);
2964           Controller->QueueCommand = DAC960_PD_QueueCommand;
2965           Controller->ReadControllerConfiguration =
2966             DAC960_V1_ReadControllerConfiguration;
2967           Controller->ReadDeviceConfiguration =
2968             DAC960_V1_ReadDeviceConfiguration;
2969           Controller->ReportDeviceConfiguration =
2970             DAC960_V1_ReportDeviceConfiguration;
2971           Controller->QueueReadWriteCommand =
2972             DAC960_V1_QueueReadWriteCommand;
2973           break;
2974         case DAC960_P_Controller:
2975           if (!request_region(Controller->IO_Address, 0x80,
2976                               Controller->FullModelName)){
2977                 DAC960_Error("IO port 0x%d busy for Controller at\n",
2978                              Controller, Controller->IO_Address);
2979                 goto Failure;
2980           }
2981           DAC960_PD_DisableInterrupts(BaseAddress);
2982           DAC960_PD_AcknowledgeStatus(BaseAddress);
2983           udelay(1000);
2984           while (DAC960_PD_InitializationInProgressP(BaseAddress))
2985             {
2986               if (DAC960_PD_ReadErrorStatus(BaseAddress, &ErrorStatus,
2987                                             &Parameter0, &Parameter1) &&
2988                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2989                                            Parameter0, Parameter1))
2990                 goto Failure;
2991               udelay(10);
2992             }
2993           if (!DAC960_V1_EnableMemoryMailboxInterface(Controller))
2994             {
2995               DAC960_Error("Unable to allocate DMA mapped memory"
2996                            "for Controller at\n", Controller);
2997               goto Failure;
2998             }
2999           DAC960_PD_EnableInterrupts(BaseAddress);
3000           Controller->QueueCommand = DAC960_P_QueueCommand;
3001           Controller->ReadControllerConfiguration =
3002             DAC960_V1_ReadControllerConfiguration;
3003           Controller->ReadDeviceConfiguration =
3004             DAC960_V1_ReadDeviceConfiguration;
3005           Controller->ReportDeviceConfiguration =
3006             DAC960_V1_ReportDeviceConfiguration;
3007           Controller->QueueReadWriteCommand =
3008             DAC960_V1_QueueReadWriteCommand;
3009           break;
3010   }
3011   /*
3012      Acquire shared access to the IRQ Channel.
3013   */
3014   IRQ_Channel = PCI_Device->irq;
3015   if (request_irq(IRQ_Channel, InterruptHandler, IRQF_SHARED,
3016                       Controller->FullModelName, Controller) < 0)
3017   {
3018         DAC960_Error("Unable to acquire IRQ Channel %d for Controller at\n",
3019                        Controller, Controller->IRQ_Channel);
3020         goto Failure;
3021   }
3022   Controller->IRQ_Channel = IRQ_Channel;
3023   Controller->InitialCommand.CommandIdentifier = 1;
3024   Controller->InitialCommand.Controller = Controller;
3025   Controller->Commands[0] = &Controller->InitialCommand;
3026   Controller->FreeCommands = &Controller->InitialCommand;
3027   return Controller;
3028
3029 Failure:
3030   if (Controller->IO_Address == 0)
3031         DAC960_Error("PCI Bus %d Device %d Function %d I/O Address N/A "
3032                      "PCI Address 0x%X\n", Controller,
3033                      Controller->Bus, Controller->Device,
3034                      Controller->Function, Controller->PCI_Address);
3035   else
3036         DAC960_Error("PCI Bus %d Device %d Function %d I/O Address "
3037                         "0x%X PCI Address 0x%X\n", Controller,
3038                         Controller->Bus, Controller->Device,
3039                         Controller->Function, Controller->IO_Address,
3040                         Controller->PCI_Address);
3041   DAC960_DetectCleanup(Controller);
3042   DAC960_ControllerCount--;
3043   return NULL;
3044 }
3045
3046 /*
3047   DAC960_InitializeController initializes Controller.
3048 */
3049
3050 static boolean
3051 DAC960_InitializeController(DAC960_Controller_T *Controller)
3052 {
3053   if (DAC960_ReadControllerConfiguration(Controller) &&
3054       DAC960_ReportControllerConfiguration(Controller) &&
3055       DAC960_CreateAuxiliaryStructures(Controller) &&
3056       DAC960_ReadDeviceConfiguration(Controller) &&
3057       DAC960_ReportDeviceConfiguration(Controller) &&
3058       DAC960_RegisterBlockDevice(Controller))
3059     {
3060       /*
3061         Initialize the Monitoring Timer.
3062       */
3063       init_timer(&Controller->MonitoringTimer);
3064       Controller->MonitoringTimer.expires =
3065         jiffies + DAC960_MonitoringTimerInterval;
3066       Controller->MonitoringTimer.data = (unsigned long) Controller;
3067       Controller->MonitoringTimer.function = DAC960_MonitoringTimerFunction;
3068       add_timer(&Controller->MonitoringTimer);
3069       Controller->ControllerInitialized = true;
3070       return true;
3071     }
3072   return false;
3073 }
3074
3075
3076 /*
3077   DAC960_FinalizeController finalizes Controller.
3078 */
3079
3080 static void DAC960_FinalizeController(DAC960_Controller_T *Controller)
3081 {
3082   if (Controller->ControllerInitialized)
3083     {
3084       unsigned long flags;
3085
3086       /*
3087        * Acquiring and releasing lock here eliminates
3088        * a very low probability race.
3089        *
3090        * The code below allocates controller command structures
3091        * from the free list without holding the controller lock.
3092        * This is safe assuming there is no other activity on
3093        * the controller at the time.
3094        *
3095        * But, there might be a monitoring command still
3096        * in progress.  Setting the Shutdown flag while holding
3097        * the lock ensures that there is no monitoring command
3098        * in the interrupt handler currently, and any monitoring
3099        * commands that complete from this time on will NOT return
3100        * their command structure to the free list.
3101        */
3102
3103       spin_lock_irqsave(&Controller->queue_lock, flags);
3104       Controller->ShutdownMonitoringTimer = 1;
3105       spin_unlock_irqrestore(&Controller->queue_lock, flags);
3106
3107       del_timer_sync(&Controller->MonitoringTimer);
3108       if (Controller->FirmwareType == DAC960_V1_Controller)
3109         {
3110           DAC960_Notice("Flushing Cache...", Controller);
3111           DAC960_V1_ExecuteType3(Controller, DAC960_V1_Flush, 0);
3112           DAC960_Notice("done\n", Controller);
3113
3114           if (Controller->HardwareType == DAC960_PD_Controller)
3115               release_region(Controller->IO_Address, 0x80);
3116         }
3117       else
3118         {
3119           DAC960_Notice("Flushing Cache...", Controller);
3120           DAC960_V2_DeviceOperation(Controller, DAC960_V2_PauseDevice,
3121                                     DAC960_V2_RAID_Controller);
3122           DAC960_Notice("done\n", Controller);
3123         }
3124     }
3125   DAC960_UnregisterBlockDevice(Controller);
3126   DAC960_DestroyAuxiliaryStructures(Controller);
3127   DAC960_DestroyProcEntries(Controller);
3128   DAC960_DetectCleanup(Controller);
3129 }
3130
3131
3132 /*
3133   DAC960_Probe verifies controller's existence and
3134   initializes the DAC960 Driver for that controller.
3135 */
3136
3137 static int
3138 DAC960_Probe(struct pci_dev *dev, const struct pci_device_id *entry)
3139 {
3140   int disk;
3141   DAC960_Controller_T *Controller;
3142
3143   if (DAC960_ControllerCount == DAC960_MaxControllers)
3144   {
3145         DAC960_Error("More than %d DAC960 Controllers detected - "
3146                        "ignoring from Controller at\n",
3147                        NULL, DAC960_MaxControllers);
3148         return -ENODEV;
3149   }
3150
3151   Controller = DAC960_DetectController(dev, entry);
3152   if (!Controller)
3153         return -ENODEV;
3154
3155   if (!DAC960_InitializeController(Controller)) {
3156         DAC960_FinalizeController(Controller);
3157         return -ENODEV;
3158   }
3159
3160   for (disk = 0; disk < DAC960_MaxLogicalDrives; disk++) {
3161         set_capacity(Controller->disks[disk], disk_size(Controller, disk));
3162         add_disk(Controller->disks[disk]);
3163   }
3164   DAC960_CreateProcEntries(Controller);
3165   return 0;
3166 }
3167
3168
3169 /*
3170   DAC960_Finalize finalizes the DAC960 Driver.
3171 */
3172
3173 static void DAC960_Remove(struct pci_dev *PCI_Device)
3174 {
3175   int Controller_Number = (long)pci_get_drvdata(PCI_Device);
3176   DAC960_Controller_T *Controller = DAC960_Controllers[Controller_Number];
3177   if (Controller != NULL)
3178       DAC960_FinalizeController(Controller);
3179 }
3180
3181
3182 /*
3183   DAC960_V1_QueueReadWriteCommand prepares and queues a Read/Write Command for
3184   DAC960 V1 Firmware Controllers.
3185 */
3186
3187 static void DAC960_V1_QueueReadWriteCommand(DAC960_Command_T *Command)
3188 {
3189   DAC960_Controller_T *Controller = Command->Controller;
3190   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
3191   DAC960_V1_ScatterGatherSegment_T *ScatterGatherList =
3192                                         Command->V1.ScatterGatherList;
3193   struct scatterlist *ScatterList = Command->V1.ScatterList;
3194
3195   DAC960_V1_ClearCommand(Command);
3196
3197   if (Command->SegmentCount == 1)
3198     {
3199       if (Command->DmaDirection == PCI_DMA_FROMDEVICE)
3200         CommandMailbox->Type5.CommandOpcode = DAC960_V1_Read;
3201       else
3202         CommandMailbox->Type5.CommandOpcode = DAC960_V1_Write;
3203
3204       CommandMailbox->Type5.LD.TransferLength = Command->BlockCount;
3205       CommandMailbox->Type5.LD.LogicalDriveNumber = Command->LogicalDriveNumber;
3206       CommandMailbox->Type5.LogicalBlockAddress = Command->BlockNumber;
3207       CommandMailbox->Type5.BusAddress =
3208                         (DAC960_BusAddress32_T)sg_dma_address(ScatterList);
3209     }
3210   else
3211     {
3212       int i;
3213
3214       if (Command->DmaDirection == PCI_DMA_FROMDEVICE)
3215         CommandMailbox->Type5.CommandOpcode = DAC960_V1_ReadWithScatterGather;
3216       else
3217         CommandMailbox->Type5.CommandOpcode = DAC960_V1_WriteWithScatterGather;
3218
3219       CommandMailbox->Type5.LD.TransferLength = Command->BlockCount;
3220       CommandMailbox->Type5.LD.LogicalDriveNumber = Command->LogicalDriveNumber;
3221       CommandMailbox->Type5.LogicalBlockAddress = Command->BlockNumber;
3222       CommandMailbox->Type5.BusAddress = Command->V1.ScatterGatherListDMA;
3223
3224       CommandMailbox->Type5.ScatterGatherCount = Command->SegmentCount;
3225
3226       for (i = 0; i < Command->SegmentCount; i++, ScatterList++, ScatterGatherList++) {
3227                 ScatterGatherList->SegmentDataPointer =
3228                         (DAC960_BusAddress32_T)sg_dma_address(ScatterList);
3229                 ScatterGatherList->SegmentByteCount =
3230                         (DAC960_ByteCount32_T)sg_dma_len(ScatterList);
3231       }
3232     }
3233   DAC960_QueueCommand(Command);
3234 }
3235
3236
3237 /*
3238   DAC960_V2_QueueReadWriteCommand prepares and queues a Read/Write Command for
3239   DAC960 V2 Firmware Controllers.
3240 */
3241
3242 static void DAC960_V2_QueueReadWriteCommand(DAC960_Command_T *Command)
3243 {
3244   DAC960_Controller_T *Controller = Command->Controller;
3245   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
3246   struct scatterlist *ScatterList = Command->V2.ScatterList;
3247
3248   DAC960_V2_ClearCommand(Command);
3249
3250   CommandMailbox->SCSI_10.CommandOpcode = DAC960_V2_SCSI_10;
3251   CommandMailbox->SCSI_10.CommandControlBits.DataTransferControllerToHost =
3252     (Command->DmaDirection == PCI_DMA_FROMDEVICE);
3253   CommandMailbox->SCSI_10.DataTransferSize =
3254     Command->BlockCount << DAC960_BlockSizeBits;
3255   CommandMailbox->SCSI_10.RequestSenseBusAddress = Command->V2.RequestSenseDMA;
3256   CommandMailbox->SCSI_10.PhysicalDevice =
3257     Controller->V2.LogicalDriveToVirtualDevice[Command->LogicalDriveNumber];
3258   CommandMailbox->SCSI_10.RequestSenseSize = sizeof(DAC960_SCSI_RequestSense_T);
3259   CommandMailbox->SCSI_10.CDBLength = 10;
3260   CommandMailbox->SCSI_10.SCSI_CDB[0] =
3261     (Command->DmaDirection == PCI_DMA_FROMDEVICE ? 0x28 : 0x2A);
3262   CommandMailbox->SCSI_10.SCSI_CDB[2] = Command->BlockNumber >> 24;
3263   CommandMailbox->SCSI_10.SCSI_CDB[3] = Command->BlockNumber >> 16;
3264   CommandMailbox->SCSI_10.SCSI_CDB[4] = Command->BlockNumber >> 8;
3265   CommandMailbox->SCSI_10.SCSI_CDB[5] = Command->BlockNumber;
3266   CommandMailbox->SCSI_10.SCSI_CDB[7] = Command->BlockCount >> 8;
3267   CommandMailbox->SCSI_10.SCSI_CDB[8] = Command->BlockCount;
3268
3269   if (Command->SegmentCount == 1)
3270     {
3271       CommandMailbox->SCSI_10.DataTransferMemoryAddress
3272                              .ScatterGatherSegments[0]
3273                              .SegmentDataPointer =
3274         (DAC960_BusAddress64_T)sg_dma_address(ScatterList);
3275       CommandMailbox->SCSI_10.DataTransferMemoryAddress
3276                              .ScatterGatherSegments[0]
3277                              .SegmentByteCount =
3278         CommandMailbox->SCSI_10.DataTransferSize;
3279     }
3280   else
3281     {
3282       DAC960_V2_ScatterGatherSegment_T *ScatterGatherList;
3283       int i;
3284
3285       if (Command->SegmentCount > 2)
3286         {
3287           ScatterGatherList = Command->V2.ScatterGatherList;
3288           CommandMailbox->SCSI_10.CommandControlBits
3289                          .AdditionalScatterGatherListMemory = true;
3290           CommandMailbox->SCSI_10.DataTransferMemoryAddress
3291                 .ExtendedScatterGather.ScatterGatherList0Length = Command->SegmentCount;
3292           CommandMailbox->SCSI_10.DataTransferMemoryAddress
3293                          .ExtendedScatterGather.ScatterGatherList0Address =