2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include "sata_promise.h"
47 #define DRV_NAME "sata_promise"
48 #define DRV_VERSION "1.05"
54 /* register offsets */
55 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
56 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
57 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
58 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
59 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
60 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
61 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
62 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
63 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
64 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
65 PDC_FLASH_CTL = 0x44, /* Flash control register */
66 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
67 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
68 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
69 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
70 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
71 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
73 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
74 (1<<8) | (1<<9) | (1<<10),
76 board_2037x = 0, /* FastTrak S150 TX2plus */
77 board_20319 = 1, /* FastTrak S150 TX4 */
78 board_20619 = 2, /* FastTrak TX4000 */
79 board_2057x = 3, /* SATAII150 Tx2plus */
80 board_40518 = 4, /* SATAII150 Tx4 */
82 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
84 /* Sequence counter control registers bit definitions */
85 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
87 /* Feature register values */
88 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
89 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
91 /* Device/Head register values */
92 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
94 /* PDC_CTLSTAT bit definitions */
95 PDC_DMA_ENABLE = (1 << 7),
96 PDC_IRQ_DISABLE = (1 << 10),
97 PDC_RESET = (1 << 11), /* HDMA reset */
99 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
101 ATA_FLAG_PIO_POLLING,
104 PDC_FLAG_GEN_II = (1 << 0),
108 struct pdc_port_priv {
113 struct pdc_host_priv {
115 unsigned long port_flags[ATA_MAX_PORTS];
118 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
119 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
120 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
121 static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
122 static void pdc_eng_timeout(struct ata_port *ap);
123 static int pdc_port_start(struct ata_port *ap);
124 static void pdc_pata_phy_reset(struct ata_port *ap);
125 static void pdc_qc_prep(struct ata_queued_cmd *qc);
126 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
127 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
128 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
129 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc);
130 static void pdc_irq_clear(struct ata_port *ap);
131 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
132 static void pdc_freeze(struct ata_port *ap);
133 static void pdc_thaw(struct ata_port *ap);
134 static void pdc_error_handler(struct ata_port *ap);
135 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
138 static struct scsi_host_template pdc_ata_sht = {
139 .module = THIS_MODULE,
141 .ioctl = ata_scsi_ioctl,
142 .queuecommand = ata_scsi_queuecmd,
143 .can_queue = ATA_DEF_QUEUE,
144 .this_id = ATA_SHT_THIS_ID,
145 .sg_tablesize = LIBATA_MAX_PRD,
146 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
147 .emulated = ATA_SHT_EMULATED,
148 .use_clustering = ATA_SHT_USE_CLUSTERING,
149 .proc_name = DRV_NAME,
150 .dma_boundary = ATA_DMA_BOUNDARY,
151 .slave_configure = ata_scsi_slave_config,
152 .slave_destroy = ata_scsi_slave_destroy,
153 .bios_param = ata_std_bios_param,
156 static const struct ata_port_operations pdc_sata_ops = {
157 .port_disable = ata_port_disable,
158 .tf_load = pdc_tf_load_mmio,
159 .tf_read = ata_tf_read,
160 .check_status = ata_check_status,
161 .exec_command = pdc_exec_command_mmio,
162 .dev_select = ata_std_dev_select,
163 .check_atapi_dma = pdc_check_atapi_dma,
165 .qc_prep = pdc_qc_prep,
166 .qc_issue = pdc_qc_issue_prot,
167 .freeze = pdc_freeze,
169 .error_handler = pdc_error_handler,
170 .post_internal_cmd = pdc_post_internal_cmd,
171 .data_xfer = ata_data_xfer,
172 .irq_handler = pdc_interrupt,
173 .irq_clear = pdc_irq_clear,
174 .irq_on = ata_irq_on,
175 .irq_ack = ata_irq_ack,
177 .scr_read = pdc_sata_scr_read,
178 .scr_write = pdc_sata_scr_write,
179 .port_start = pdc_port_start,
182 /* First-generation chips need a more restrictive ->check_atapi_dma op */
183 static const struct ata_port_operations pdc_old_sata_ops = {
184 .port_disable = ata_port_disable,
185 .tf_load = pdc_tf_load_mmio,
186 .tf_read = ata_tf_read,
187 .check_status = ata_check_status,
188 .exec_command = pdc_exec_command_mmio,
189 .dev_select = ata_std_dev_select,
190 .check_atapi_dma = pdc_old_check_atapi_dma,
192 .qc_prep = pdc_qc_prep,
193 .qc_issue = pdc_qc_issue_prot,
194 .freeze = pdc_freeze,
196 .error_handler = pdc_error_handler,
197 .post_internal_cmd = pdc_post_internal_cmd,
198 .data_xfer = ata_data_xfer,
199 .irq_handler = pdc_interrupt,
200 .irq_clear = pdc_irq_clear,
201 .irq_on = ata_irq_on,
202 .irq_ack = ata_irq_ack,
204 .scr_read = pdc_sata_scr_read,
205 .scr_write = pdc_sata_scr_write,
206 .port_start = pdc_port_start,
209 static const struct ata_port_operations pdc_pata_ops = {
210 .port_disable = ata_port_disable,
211 .tf_load = pdc_tf_load_mmio,
212 .tf_read = ata_tf_read,
213 .check_status = ata_check_status,
214 .exec_command = pdc_exec_command_mmio,
215 .dev_select = ata_std_dev_select,
216 .check_atapi_dma = pdc_check_atapi_dma,
218 .phy_reset = pdc_pata_phy_reset,
220 .qc_prep = pdc_qc_prep,
221 .qc_issue = pdc_qc_issue_prot,
222 .data_xfer = ata_data_xfer,
223 .eng_timeout = pdc_eng_timeout,
224 .irq_handler = pdc_interrupt,
225 .irq_clear = pdc_irq_clear,
226 .irq_on = ata_irq_on,
227 .irq_ack = ata_irq_ack,
229 .port_start = pdc_port_start,
232 static const struct ata_port_info pdc_port_info[] = {
236 .flags = PDC_COMMON_FLAGS,
237 .pio_mask = 0x1f, /* pio0-4 */
238 .mwdma_mask = 0x07, /* mwdma0-2 */
239 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
240 .port_ops = &pdc_old_sata_ops,
246 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
247 .pio_mask = 0x1f, /* pio0-4 */
248 .mwdma_mask = 0x07, /* mwdma0-2 */
249 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
250 .port_ops = &pdc_old_sata_ops,
256 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
257 .pio_mask = 0x1f, /* pio0-4 */
258 .mwdma_mask = 0x07, /* mwdma0-2 */
259 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
260 .port_ops = &pdc_pata_ops,
266 .flags = PDC_COMMON_FLAGS,
267 .pio_mask = 0x1f, /* pio0-4 */
268 .mwdma_mask = 0x07, /* mwdma0-2 */
269 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
270 .port_ops = &pdc_sata_ops,
276 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
277 .pio_mask = 0x1f, /* pio0-4 */
278 .mwdma_mask = 0x07, /* mwdma0-2 */
279 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
280 .port_ops = &pdc_sata_ops,
284 static const struct pci_device_id pdc_ata_pci_tbl[] = {
285 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
286 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
287 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
288 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
289 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
290 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
291 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
292 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
293 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
294 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
296 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
297 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
298 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
299 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
300 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
301 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
303 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
305 { } /* terminate list */
309 static struct pci_driver pdc_ata_pci_driver = {
311 .id_table = pdc_ata_pci_tbl,
312 .probe = pdc_ata_init_one,
313 .remove = ata_pci_remove_one,
317 static int pdc_port_start(struct ata_port *ap)
319 struct device *dev = ap->host->dev;
320 struct pdc_host_priv *hp = ap->host->private_data;
321 struct pdc_port_priv *pp;
324 /* fix up port flags and cable type for SATA+PATA chips */
325 ap->flags |= hp->port_flags[ap->port_no];
326 if (ap->flags & ATA_FLAG_SATA)
327 ap->cbl = ATA_CBL_SATA;
329 rc = ata_port_start(ap);
333 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
337 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
341 ap->private_data = pp;
343 /* fix up PHYMODE4 align timing */
344 if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
345 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
348 tmp = readl(mmio + 0x014);
349 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
350 writel(tmp, mmio + 0x014);
356 static void pdc_reset_port(struct ata_port *ap)
358 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
362 for (i = 11; i > 0; i--) {
375 readl(mmio); /* flush */
378 static void pdc_pata_cbl_detect(struct ata_port *ap)
381 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
386 ap->cbl = ATA_CBL_PATA40;
387 ap->udma_mask &= ATA_UDMA_MASK_40C;
389 ap->cbl = ATA_CBL_PATA80;
392 static void pdc_pata_phy_reset(struct ata_port *ap)
394 pdc_pata_cbl_detect(ap);
400 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
402 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
404 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
408 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
411 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
413 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
416 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
418 struct ata_port *ap = qc->ap;
419 dma_addr_t sg_table = ap->prd_dma;
420 unsigned int cdb_len = qc->dev->cdb_len;
422 struct pdc_port_priv *pp = ap->private_data;
424 u32 *buf32 = (u32 *) buf;
425 unsigned int dev_sel, feature, nbytes;
427 /* set control bits (byte 0), zero delay seq id (byte 3),
428 * and seq id (byte 2)
430 switch (qc->tf.protocol) {
431 case ATA_PROT_ATAPI_DMA:
432 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
433 buf32[0] = cpu_to_le32(PDC_PKT_READ);
437 case ATA_PROT_ATAPI_NODATA:
438 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
444 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
445 buf32[2] = 0; /* no next-packet */
448 if (sata_scr_valid(ap)) {
449 dev_sel = PDC_DEVICE_SATA;
451 dev_sel = ATA_DEVICE_OBS;
452 if (qc->dev->devno != 0)
455 buf[12] = (1 << 5) | ATA_REG_DEVICE;
457 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
458 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
460 buf[16] = (1 << 5) | ATA_REG_NSECT;
462 buf[18] = (1 << 5) | ATA_REG_LBAL;
465 /* set feature and byte counter registers */
466 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
467 feature = PDC_FEATURE_ATAPI_PIO;
468 /* set byte counter register to real transfer byte count */
473 feature = PDC_FEATURE_ATAPI_DMA;
474 /* set byte counter register to 0 */
477 buf[20] = (1 << 5) | ATA_REG_FEATURE;
479 buf[22] = (1 << 5) | ATA_REG_BYTEL;
480 buf[23] = nbytes & 0xFF;
481 buf[24] = (1 << 5) | ATA_REG_BYTEH;
482 buf[25] = (nbytes >> 8) & 0xFF;
484 /* send ATAPI packet command 0xA0 */
485 buf[26] = (1 << 5) | ATA_REG_CMD;
486 buf[27] = ATA_CMD_PACKET;
488 /* select drive and check DRQ */
489 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
492 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
493 BUG_ON(cdb_len & ~0x1E);
495 /* append the CDB as the final part */
496 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
497 memcpy(buf+31, cdb, cdb_len);
500 static void pdc_qc_prep(struct ata_queued_cmd *qc)
502 struct pdc_port_priv *pp = qc->ap->private_data;
507 switch (qc->tf.protocol) {
512 case ATA_PROT_NODATA:
513 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
514 qc->dev->devno, pp->pkt);
516 if (qc->tf.flags & ATA_TFLAG_LBA48)
517 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
519 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
521 pdc_pkt_footer(&qc->tf, pp->pkt, i);
528 case ATA_PROT_ATAPI_DMA:
531 case ATA_PROT_ATAPI_NODATA:
540 static void pdc_freeze(struct ata_port *ap)
542 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
545 tmp = readl(mmio + PDC_CTLSTAT);
546 tmp |= PDC_IRQ_DISABLE;
547 tmp &= ~PDC_DMA_ENABLE;
548 writel(tmp, mmio + PDC_CTLSTAT);
549 readl(mmio + PDC_CTLSTAT); /* flush */
552 static void pdc_thaw(struct ata_port *ap)
554 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
558 readl(mmio + PDC_INT_SEQMASK);
560 /* turn IRQ back on */
561 tmp = readl(mmio + PDC_CTLSTAT);
562 tmp &= ~PDC_IRQ_DISABLE;
563 writel(tmp, mmio + PDC_CTLSTAT);
564 readl(mmio + PDC_CTLSTAT); /* flush */
567 static void pdc_error_handler(struct ata_port *ap)
569 ata_reset_fn_t hardreset;
571 if (!(ap->pflags & ATA_PFLAG_FROZEN))
575 if (sata_scr_valid(ap))
576 hardreset = sata_std_hardreset;
578 /* perform recovery */
579 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
583 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
585 struct ata_port *ap = qc->ap;
587 if (qc->flags & ATA_QCFLAG_FAILED)
588 qc->err_mask |= AC_ERR_OTHER;
590 /* make DMA engine forget about the failed command */
595 static void pdc_eng_timeout(struct ata_port *ap)
597 struct ata_host *host = ap->host;
599 struct ata_queued_cmd *qc;
604 spin_lock_irqsave(&host->lock, flags);
606 qc = ata_qc_from_tag(ap, ap->active_tag);
608 switch (qc->tf.protocol) {
610 case ATA_PROT_NODATA:
611 ata_port_printk(ap, KERN_ERR, "command timeout\n");
612 drv_stat = ata_wait_idle(ap);
613 qc->err_mask |= __ac_err_mask(drv_stat);
617 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
619 ata_port_printk(ap, KERN_ERR,
620 "unknown timeout, cmd 0x%x stat 0x%x\n",
621 qc->tf.command, drv_stat);
623 qc->err_mask |= ac_err_mask(drv_stat);
627 spin_unlock_irqrestore(&host->lock, flags);
628 ata_eh_qc_complete(qc);
632 static inline unsigned int pdc_host_intr( struct ata_port *ap,
633 struct ata_queued_cmd *qc)
635 unsigned int handled = 0;
637 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
640 if (tmp & PDC_ERR_MASK) {
641 qc->err_mask |= AC_ERR_DEV;
645 switch (qc->tf.protocol) {
647 case ATA_PROT_NODATA:
648 case ATA_PROT_ATAPI_DMA:
649 case ATA_PROT_ATAPI_NODATA:
650 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
656 ap->stats.idle_irq++;
663 static void pdc_irq_clear(struct ata_port *ap)
665 struct ata_host *host = ap->host;
666 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
668 readl(mmio + PDC_INT_SEQMASK);
671 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
673 struct ata_host *host = dev_instance;
677 unsigned int handled = 0;
678 void __iomem *mmio_base;
682 if (!host || !host->iomap[PDC_MMIO_BAR]) {
683 VPRINTK("QUICK EXIT\n");
687 mmio_base = host->iomap[PDC_MMIO_BAR];
689 /* reading should also clear interrupts */
690 mask = readl(mmio_base + PDC_INT_SEQMASK);
692 if (mask == 0xffffffff) {
693 VPRINTK("QUICK EXIT 2\n");
697 spin_lock(&host->lock);
699 mask &= 0xffff; /* only 16 tags possible */
701 VPRINTK("QUICK EXIT 3\n");
705 writel(mask, mmio_base + PDC_INT_SEQMASK);
707 for (i = 0; i < host->n_ports; i++) {
708 VPRINTK("port %u\n", i);
710 tmp = mask & (1 << (i + 1));
712 !(ap->flags & ATA_FLAG_DISABLED)) {
713 struct ata_queued_cmd *qc;
715 qc = ata_qc_from_tag(ap, ap->active_tag);
716 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
717 handled += pdc_host_intr(ap, qc);
724 spin_unlock(&host->lock);
725 return IRQ_RETVAL(handled);
728 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
730 struct ata_port *ap = qc->ap;
731 struct pdc_port_priv *pp = ap->private_data;
732 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
733 unsigned int port_no = ap->port_no;
734 u8 seq = (u8) (port_no + 1);
736 VPRINTK("ENTER, ap %p\n", ap);
738 writel(0x00000001, mmio + (seq * 4));
739 readl(mmio + (seq * 4)); /* flush */
742 wmb(); /* flush PRD, pkt writes */
743 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
744 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
747 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
749 switch (qc->tf.protocol) {
750 case ATA_PROT_ATAPI_NODATA:
751 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
754 case ATA_PROT_ATAPI_DMA:
756 case ATA_PROT_NODATA:
757 pdc_packet_start(qc);
764 return ata_qc_issue_prot(qc);
767 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
769 WARN_ON (tf->protocol == ATA_PROT_DMA ||
770 tf->protocol == ATA_PROT_NODATA);
775 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
777 WARN_ON (tf->protocol == ATA_PROT_DMA ||
778 tf->protocol == ATA_PROT_NODATA);
779 ata_exec_command(ap, tf);
782 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
784 u8 *scsicmd = qc->scsicmd->cmnd;
785 int pio = 1; /* atapi dma off by default */
787 /* Whitelist commands that may use DMA. */
788 switch (scsicmd[0]) {
795 case 0xad: /* READ_DVD_STRUCTURE */
796 case 0xbe: /* READ_CD */
799 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
800 if (scsicmd[0] == WRITE_10) {
802 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
803 if (lba >= 0xFFFF4FA2)
809 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc)
811 struct ata_port *ap = qc->ap;
813 /* First generation chips cannot use ATAPI DMA on SATA ports */
814 if (sata_scr_valid(ap))
816 return pdc_check_atapi_dma(qc);
819 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
821 port->cmd_addr = base;
822 port->data_addr = base;
824 port->error_addr = base + 0x4;
825 port->nsect_addr = base + 0x8;
826 port->lbal_addr = base + 0xc;
827 port->lbam_addr = base + 0x10;
828 port->lbah_addr = base + 0x14;
829 port->device_addr = base + 0x18;
831 port->status_addr = base + 0x1c;
832 port->altstatus_addr =
833 port->ctl_addr = base + 0x38;
837 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
839 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
840 struct pdc_host_priv *hp = pe->private_data;
844 if (hp->flags & PDC_FLAG_GEN_II)
845 hotplug_offset = PDC2_SATA_PLUG_CSR;
847 hotplug_offset = PDC_SATA_PLUG_CSR;
850 * Except for the hotplug stuff, this is voodoo from the
851 * Promise driver. Label this entire section
852 * "TODO: figure out why we do this"
855 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
856 tmp = readl(mmio + PDC_FLASH_CTL);
857 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
858 if (!(hp->flags & PDC_FLAG_GEN_II))
859 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
860 writel(tmp, mmio + PDC_FLASH_CTL);
862 /* clear plug/unplug flags for all ports */
863 tmp = readl(mmio + hotplug_offset);
864 writel(tmp | 0xff, mmio + hotplug_offset);
866 /* mask plug/unplug ints */
867 tmp = readl(mmio + hotplug_offset);
868 writel(tmp | 0xff0000, mmio + hotplug_offset);
870 /* don't initialise TBG or SLEW on 2nd generation chips */
871 if (hp->flags & PDC_FLAG_GEN_II)
874 /* reduce TBG clock to 133 Mhz. */
875 tmp = readl(mmio + PDC_TBG_MODE);
876 tmp &= ~0x30000; /* clear bit 17, 16*/
877 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
878 writel(tmp, mmio + PDC_TBG_MODE);
880 readl(mmio + PDC_TBG_MODE); /* flush */
883 /* adjust slew rate control register. */
884 tmp = readl(mmio + PDC_SLEW_CTL);
885 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
886 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
887 writel(tmp, mmio + PDC_SLEW_CTL);
890 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
892 static int printed_version;
893 struct ata_probe_ent *probe_ent;
894 struct pdc_host_priv *hp;
896 unsigned int board_idx = (unsigned int) ent->driver_data;
900 if (!printed_version++)
901 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
903 rc = pcim_enable_device(pdev);
907 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
909 pcim_pin_device(pdev);
913 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
916 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
920 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
921 if (probe_ent == NULL)
924 probe_ent->dev = pci_dev_to_dev(pdev);
925 INIT_LIST_HEAD(&probe_ent->node);
927 hp = devm_kzalloc(&pdev->dev, sizeof(*hp), GFP_KERNEL);
931 probe_ent->private_data = hp;
933 probe_ent->sht = pdc_port_info[board_idx].sht;
934 probe_ent->port_flags = pdc_port_info[board_idx].flags;
935 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
936 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
937 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
938 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
940 probe_ent->irq = pdev->irq;
941 probe_ent->irq_flags = IRQF_SHARED;
942 probe_ent->iomap = pcim_iomap_table(pdev);
944 base = probe_ent->iomap[PDC_MMIO_BAR];
946 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
947 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
949 probe_ent->port[0].scr_addr = base + 0x400;
950 probe_ent->port[1].scr_addr = base + 0x500;
952 /* notice 4-port boards */
955 hp->flags |= PDC_FLAG_GEN_II;
958 probe_ent->n_ports = 4;
960 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
961 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
963 probe_ent->port[2].scr_addr = base + 0x600;
964 probe_ent->port[3].scr_addr = base + 0x700;
967 hp->flags |= PDC_FLAG_GEN_II;
970 /* TX2plus boards also have a PATA port */
971 tmp = readb(base + PDC_FLASH_CTL+1);
973 probe_ent->n_ports = 3;
974 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
975 hp->port_flags[2] = ATA_FLAG_SLAVE_POSS;
976 printk(KERN_INFO DRV_NAME " PATA port found\n");
978 probe_ent->n_ports = 2;
979 hp->port_flags[0] = ATA_FLAG_SATA;
980 hp->port_flags[1] = ATA_FLAG_SATA;
983 probe_ent->n_ports = 4;
985 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
986 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
988 probe_ent->port[2].scr_addr = base + 0x600;
989 probe_ent->port[3].scr_addr = base + 0x700;
996 pci_set_master(pdev);
998 /* initialize adapter */
999 pdc_host_init(board_idx, probe_ent);
1001 if (!ata_device_add(probe_ent))
1004 devm_kfree(&pdev->dev, probe_ent);
1009 static int __init pdc_ata_init(void)
1011 return pci_register_driver(&pdc_ata_pci_driver);
1015 static void __exit pdc_ata_exit(void)
1017 pci_unregister_driver(&pdc_ata_pci_driver);
1021 MODULE_AUTHOR("Jeff Garzik");
1022 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1023 MODULE_LICENSE("GPL");
1024 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1025 MODULE_VERSION(DRV_VERSION);
1027 module_init(pdc_ata_init);
1028 module_exit(pdc_ata_exit);