drivers/ata/ahci_brcm.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Broadcom SATA3 AHCI Controller Driver
   4  *
   5  * Copyright © 2009-2015 Broadcom Corporation
   6  */
   7
   8 #include <linux/ahci_platform.h>
   9 #include <linux/compiler.h>
  10 #include <linux/device.h>
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/libata.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/reset.h>
  20 #include <linux/string.h>
  21
  22 #include "ahci.h"
  23
  24 #define DRV_NAME                                        "brcm-ahci"
  25
  26 #define SATA_TOP_CTRL_VERSION                           0x0
  27 #define SATA_TOP_CTRL_BUS_CTRL                          0x4
  28  #define MMIO_ENDIAN_SHIFT                              0 /* CPU->AHCI */
  29  #define DMADESC_ENDIAN_SHIFT                           2 /* AHCI->DDR */
  30  #define DMADATA_ENDIAN_SHIFT                           4 /* AHCI->DDR */
  31  #define PIODATA_ENDIAN_SHIFT                           6
  32   #define ENDIAN_SWAP_NONE                              0
  33   #define ENDIAN_SWAP_FULL                              2
  34 #define SATA_TOP_CTRL_TP_CTRL                           0x8
  35 #define SATA_TOP_CTRL_PHY_CTRL                          0xc
  36  #define SATA_TOP_CTRL_PHY_CTRL_1                       0x0
  37   #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE       BIT(14)
  38  #define SATA_TOP_CTRL_PHY_CTRL_2                       0x4
  39   #define SATA_TOP_CTRL_2_SW_RST_MDIOREG                BIT(0)
  40   #define SATA_TOP_CTRL_2_SW_RST_OOB                    BIT(1)
  41   #define SATA_TOP_CTRL_2_SW_RST_RX                     BIT(2)
  42   #define SATA_TOP_CTRL_2_SW_RST_TX                     BIT(3)
  43   #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET              BIT(14)
  44  #define SATA_TOP_CTRL_PHY_OFFS                         0x8
  45  #define SATA_TOP_MAX_PHYS                              2
  46
  47 #define SATA_FIRST_PORT_CTRL                            0x700
  48 #define SATA_NEXT_PORT_CTRL_OFFSET                      0x80
  49 #define SATA_PORT_PCTRL6(reg_base)                      (reg_base + 0x18)
  50
  51 /* On big-endian MIPS, buses are reversed to big endian, so switch them back */
  52 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
  53 #define DATA_ENDIAN                      2 /* AHCI->DDR inbound accesses */
  54 #define MMIO_ENDIAN                      2 /* CPU->AHCI outbound accesses */
  55 #else
  56 #define DATA_ENDIAN                      0
  57 #define MMIO_ENDIAN                      0
  58 #endif
  59
  60 #define BUS_CTRL_ENDIAN_CONF                            \
  61         ((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) |        \
  62         (DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) |         \
  63         (MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
  64
  65 #define BUS_CTRL_ENDIAN_NSP_CONF                        \
  66         (0x02 << DMADATA_ENDIAN_SHIFT | 0x02 << DMADESC_ENDIAN_SHIFT)
  67
  68 #define BUS_CTRL_ENDIAN_CONF_MASK                       \
  69         (0x3 << MMIO_ENDIAN_SHIFT | 0x3 << DMADESC_ENDIAN_SHIFT |       \
  70          0x3 << DMADATA_ENDIAN_SHIFT | 0x3 << PIODATA_ENDIAN_SHIFT)
  71
  72 enum brcm_ahci_version {
  73         BRCM_SATA_BCM7425 = 1,
  74         BRCM_SATA_BCM7445,
  75         BRCM_SATA_NSP,
  76 };
  77
  78 enum brcm_ahci_quirks {
  79         BRCM_AHCI_QUIRK_NO_NCQ          = BIT(0),
  80         BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(1),
  81 };
  82
  83 struct brcm_ahci_priv {
  84         struct device *dev;
  85         void __iomem *top_ctrl;
  86         u32 port_mask;
  87         u32 quirks;
  88         enum brcm_ahci_version version;
  89         struct reset_control *rcdev;
  90 };
  91
  92 static inline u32 brcm_sata_readreg(void __iomem *addr)
  93 {
  94         /*
  95          * MIPS endianness is configured by boot strap, which also reverses all
  96          * bus endianness (i.e., big-endian CPU + big endian bus ==> native
  97          * endian I/O).
  98          *
  99          * Other architectures (e.g., ARM) either do not support big endian, or
 100          * else leave I/O in little endian mode.
 101          */
 102         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
 103                 return __raw_readl(addr);
 104         else
 105                 return readl_relaxed(addr);
 106 }
 107
 108 static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
 109 {
 110         /* See brcm_sata_readreg() comments */
 111         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
 112                 __raw_writel(val, addr);
 113         else
 114                 writel_relaxed(val, addr);
 115 }
 116
 117 static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv)
 118 {
 119         struct brcm_ahci_priv *priv = hpriv->plat_data;
 120         u32 port_ctrl, host_caps;
 121         int i;
 122
 123         /* Enable support for ALPM */
 124         host_caps = readl(hpriv->mmio + HOST_CAP);
 125         if (!(host_caps & HOST_CAP_ALPM))
 126                 hpriv->flags |= AHCI_HFLAG_YES_ALPM;
 127
 128         /*
 129          * Adjust timeout to allow PLL sufficient time to lock while waking
 130          * up from slumber mode.
 131          */
 132         for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL;
 133              i < SATA_TOP_MAX_PHYS;
 134              i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET) {
 135                 if (priv->port_mask & BIT(i))
 136                         writel(0xff1003fc,
 137                                hpriv->mmio + SATA_PORT_PCTRL6(port_ctrl));
 138         }
 139 }
 140
 141 static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
 142 {
 143         void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
 144                                 (port * SATA_TOP_CTRL_PHY_OFFS);
 145         void __iomem *p;
 146         u32 reg;
 147
 148         if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
 149                 return;
 150
 151         /* clear PHY_DEFAULT_POWER_STATE */
 152         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
 153         reg = brcm_sata_readreg(p);
 154         reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
 155         brcm_sata_writereg(reg, p);
 156
 157         /* reset the PHY digital logic */
 158         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
 159         reg = brcm_sata_readreg(p);
 160         reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
 161                  SATA_TOP_CTRL_2_SW_RST_RX);
 162         reg |= SATA_TOP_CTRL_2_SW_RST_TX;
 163         brcm_sata_writereg(reg, p);
 164         reg = brcm_sata_readreg(p);
 165         reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
 166         brcm_sata_writereg(reg, p);
 167         reg = brcm_sata_readreg(p);
 168         reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
 169         brcm_sata_writereg(reg, p);
 170         (void)brcm_sata_readreg(p);
 171 }
 172
 173 static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
 174 {
 175         void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
 176                                 (port * SATA_TOP_CTRL_PHY_OFFS);
 177         void __iomem *p;
 178         u32 reg;
 179
 180         if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
 181                 return;
 182
 183         /* power-off the PHY digital logic */
 184         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
 185         reg = brcm_sata_readreg(p);
 186         reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
 187                 SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX |
 188                 SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
 189         brcm_sata_writereg(reg, p);
 190
 191         /* set PHY_DEFAULT_POWER_STATE */
 192         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
 193         reg = brcm_sata_readreg(p);
 194         reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
 195         brcm_sata_writereg(reg, p);
 196 }
 197
 198 static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv)
 199 {
 200         int i;
 201
 202         for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
 203                 if (priv->port_mask & BIT(i))
 204                         brcm_sata_phy_enable(priv, i);
 205 }
 206
 207 static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv)
 208 {
 209         int i;
 210
 211         for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
 212                 if (priv->port_mask & BIT(i))
 213                         brcm_sata_phy_disable(priv, i);
 214 }
 215
 216 static u32 brcm_ahci_get_portmask(struct platform_device *pdev,
 217                                   struct brcm_ahci_priv *priv)
 218 {
 219         void __iomem *ahci;
 220         struct resource *res;
 221         u32 impl;
 222
 223         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci");
 224         ahci = devm_ioremap_resource(&pdev->dev, res);
 225         if (IS_ERR(ahci))
 226                 return 0;
 227
 228         impl = readl(ahci + HOST_PORTS_IMPL);
 229
 230         if (fls(impl) > SATA_TOP_MAX_PHYS)
 231                 dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n",
 232                          impl);
 233         else if (!impl)
 234                 dev_info(priv->dev, "no ports found\n");
 235
 236         devm_iounmap(&pdev->dev, ahci);
 237         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
 238
 239         return impl;
 240 }
 241
 242 static void brcm_sata_init(struct brcm_ahci_priv *priv)
 243 {
 244         void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL;
 245         u32 data;
 246
 247         /* Configure endianness */
 248         data = brcm_sata_readreg(ctrl);
 249         data &= ~BUS_CTRL_ENDIAN_CONF_MASK;
 250         if (priv->version == BRCM_SATA_NSP)
 251                 data |= BUS_CTRL_ENDIAN_NSP_CONF;
 252         else
 253                 data |= BUS_CTRL_ENDIAN_CONF;
 254         brcm_sata_writereg(data, ctrl);
 255 }
 256
 257 static unsigned int brcm_ahci_read_id(struct ata_device *dev,
 258                                       struct ata_taskfile *tf, u16 *id)
 259 {
 260         struct ata_port *ap = dev->link->ap;
 261         struct ata_host *host = ap->host;
 262         struct ahci_host_priv *hpriv = host->private_data;
 263         struct brcm_ahci_priv *priv = hpriv->plat_data;
 264         void __iomem *mmio = hpriv->mmio;
 265         unsigned int err_mask;
 266         unsigned long flags;
 267         int i, rc;
 268         u32 ctl;
 269
 270         /* Try to read the device ID and, if this fails, proceed with the
 271          * recovery sequence below
 272          */
 273         err_mask = ata_do_dev_read_id(dev, tf, id);
 274         if (likely(!err_mask))
 275                 return err_mask;
 276
 277         /* Disable host interrupts */
 278         spin_lock_irqsave(&host->lock, flags);
 279         ctl = readl(mmio + HOST_CTL);
 280         ctl &= ~HOST_IRQ_EN;
 281         writel(ctl, mmio + HOST_CTL);
 282         readl(mmio + HOST_CTL); /* flush */
 283         spin_unlock_irqrestore(&host->lock, flags);
 284
 285         /* Perform the SATA PHY reset sequence */
 286         brcm_sata_phy_disable(priv, ap->port_no);
 287
 288         /* Bring the PHY back on */
 289         brcm_sata_phy_enable(priv, ap->port_no);
 290
 291         /* Re-initialize and calibrate the PHY */
 292         for (i = 0; i < hpriv->nports; i++) {
 293                 rc = phy_init(hpriv->phys[i]);
 294                 if (rc)
 295                         goto disable_phys;
 296
 297                 rc = phy_calibrate(hpriv->phys[i]);
 298                 if (rc) {
 299                         phy_exit(hpriv->phys[i]);
 300                         goto disable_phys;
 301                 }
 302         }
 303
 304         /* Re-enable host interrupts */
 305         spin_lock_irqsave(&host->lock, flags);
 306         ctl = readl(mmio + HOST_CTL);
 307         ctl |= HOST_IRQ_EN;
 308         writel(ctl, mmio + HOST_CTL);
 309         readl(mmio + HOST_CTL); /* flush */
 310         spin_unlock_irqrestore(&host->lock, flags);
 311
 312         return ata_do_dev_read_id(dev, tf, id);
 313
 314 disable_phys:
 315         while (--i >= 0) {
 316                 phy_power_off(hpriv->phys[i]);
 317                 phy_exit(hpriv->phys[i]);
 318         }
 319
 320         return AC_ERR_OTHER;
 321 }
 322
 323 static void brcm_ahci_host_stop(struct ata_host *host)
 324 {
 325         struct ahci_host_priv *hpriv = host->private_data;
 326
 327         ahci_platform_disable_resources(hpriv);
 328 }
 329
 330 static struct ata_port_operations ahci_brcm_platform_ops = {
 331         .inherits       = &ahci_ops,
 332         .host_stop      = brcm_ahci_host_stop,
 333         .read_id        = brcm_ahci_read_id,
 334 };
 335
 336 static const struct ata_port_info ahci_brcm_port_info = {
 337         .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
 338         .link_flags     = ATA_LFLAG_NO_DB_DELAY,
 339         .pio_mask       = ATA_PIO4,
 340         .udma_mask      = ATA_UDMA6,
 341         .port_ops       = &ahci_brcm_platform_ops,
 342 };
 343
 344 #ifdef CONFIG_PM_SLEEP
 345 static int brcm_ahci_suspend(struct device *dev)
 346 {
 347         struct ata_host *host = dev_get_drvdata(dev);
 348         struct ahci_host_priv *hpriv = host->private_data;
 349         struct brcm_ahci_priv *priv = hpriv->plat_data;
 350         int ret;
 351
 352         ret = ahci_platform_suspend(dev);
 353         brcm_sata_phys_disable(priv);
 354         return ret;
 355 }
 356
 357 static int brcm_ahci_resume(struct device *dev)
 358 {
 359         struct ata_host *host = dev_get_drvdata(dev);
 360         struct ahci_host_priv *hpriv = host->private_data;
 361         struct brcm_ahci_priv *priv = hpriv->plat_data;
 362
 363         brcm_sata_init(priv);
 364         brcm_sata_phys_enable(priv);
 365         brcm_sata_alpm_init(hpriv);
 366         return ahci_platform_resume(dev);
 367 }
 368 #endif
 369
 370 static struct scsi_host_template ahci_platform_sht = {
 371         AHCI_SHT(DRV_NAME),
 372 };
 373
 374 static const struct of_device_id ahci_of_match[] = {
 375         {.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
 376         {.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
 377         {.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445},
 378         {.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
 379         {},
 380 };
 381 MODULE_DEVICE_TABLE(of, ahci_of_match);
 382
 383 static int brcm_ahci_probe(struct platform_device *pdev)
 384 {
 385         const struct of_device_id *of_id;
 386         struct device *dev = &pdev->dev;
 387         struct brcm_ahci_priv *priv;
 388         struct ahci_host_priv *hpriv;
 389         struct resource *res;
 390         int ret;
 391
 392         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 393         if (!priv)
 394                 return -ENOMEM;
 395
 396         of_id = of_match_node(ahci_of_match, pdev->dev.of_node);
 397         if (!of_id)
 398                 return -ENODEV;
 399
 400         priv->version = (enum brcm_ahci_version)of_id->data;
 401         priv->dev = dev;
 402
 403         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
 404         priv->top_ctrl = devm_ioremap_resource(dev, res);
 405         if (IS_ERR(priv->top_ctrl))
 406                 return PTR_ERR(priv->top_ctrl);
 407
 408         /* Reset is optional depending on platform */
 409         priv->rcdev = devm_reset_control_get(&pdev->dev, "ahci");
 410         if (!IS_ERR_OR_NULL(priv->rcdev))
 411                 reset_control_deassert(priv->rcdev);
 412
 413         if ((priv->version == BRCM_SATA_BCM7425) ||
 414                 (priv->version == BRCM_SATA_NSP)) {
 415                 priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
 416                 priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
 417         }
 418
 419         brcm_sata_init(priv);
 420
 421         priv->port_mask = brcm_ahci_get_portmask(pdev, priv);
 422         if (!priv->port_mask)
 423                 return -ENODEV;
 424
 425         brcm_sata_phys_enable(priv);
 426
 427         hpriv = ahci_platform_get_resources(pdev, 0);
 428         if (IS_ERR(hpriv))
 429                 return PTR_ERR(hpriv);
 430         hpriv->plat_data = priv;
 431         hpriv->flags = AHCI_HFLAG_WAKE_BEFORE_STOP;
 432
 433         brcm_sata_alpm_init(hpriv);
 434
 435         ret = ahci_platform_enable_resources(hpriv);
 436         if (ret)
 437                 return ret;
 438
 439         if (priv->quirks & BRCM_AHCI_QUIRK_NO_NCQ)
 440                 hpriv->flags |= AHCI_HFLAG_NO_NCQ;
 441         hpriv->flags |= AHCI_HFLAG_NO_WRITE_TO_RO;
 442
 443         ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
 444                                       &ahci_platform_sht);
 445         if (ret)
 446                 return ret;
 447
 448         dev_info(dev, "Broadcom AHCI SATA3 registered\n");
 449
 450         return 0;
 451 }
 452
 453 static int brcm_ahci_remove(struct platform_device *pdev)
 454 {
 455         struct ata_host *host = dev_get_drvdata(&pdev->dev);
 456         struct ahci_host_priv *hpriv = host->private_data;
 457         struct brcm_ahci_priv *priv = hpriv->plat_data;
 458         int ret;
 459
 460         ret = ata_platform_remove_one(pdev);
 461         if (ret)
 462                 return ret;
 463
 464         brcm_sata_phys_disable(priv);
 465
 466         return 0;
 467 }
 468
 469 static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
 470
 471 static struct platform_driver brcm_ahci_driver = {
 472         .probe = brcm_ahci_probe,
 473         .remove = brcm_ahci_remove,
 474         .driver = {
 475                 .name = DRV_NAME,
 476                 .of_match_table = ahci_of_match,
 477                 .pm = &ahci_brcm_pm_ops,
 478         },
 479 };
 480 module_platform_driver(brcm_ahci_driver);
 481
 482 MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
 483 MODULE_AUTHOR("Brian Norris");
 484 MODULE_LICENSE("GPL");
 485 MODULE_ALIAS("platform:sata-brcmstb");