Merge branch 'for-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq
[sfrench/cifs-2.6.git] / drivers / ata / ahci_brcm.c
1 /*
2  * Broadcom SATA3 AHCI Controller Driver
3  *
4  * Copyright © 2009-2015 Broadcom Corporation
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2, or (at your option)
9  * any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16
17 #include <linux/ahci_platform.h>
18 #include <linux/compiler.h>
19 #include <linux/device.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/kernel.h>
24 #include <linux/libata.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/platform_device.h>
28 #include <linux/string.h>
29
30 #include "ahci.h"
31
32 #define DRV_NAME                                        "brcm-ahci"
33
34 #define SATA_TOP_CTRL_VERSION                           0x0
35 #define SATA_TOP_CTRL_BUS_CTRL                          0x4
36  #define MMIO_ENDIAN_SHIFT                              0 /* CPU->AHCI */
37  #define DMADESC_ENDIAN_SHIFT                           2 /* AHCI->DDR */
38  #define DMADATA_ENDIAN_SHIFT                           4 /* AHCI->DDR */
39  #define PIODATA_ENDIAN_SHIFT                           6
40   #define ENDIAN_SWAP_NONE                              0
41   #define ENDIAN_SWAP_FULL                              2
42 #define SATA_TOP_CTRL_TP_CTRL                           0x8
43 #define SATA_TOP_CTRL_PHY_CTRL                          0xc
44  #define SATA_TOP_CTRL_PHY_CTRL_1                       0x0
45   #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE       BIT(14)
46  #define SATA_TOP_CTRL_PHY_CTRL_2                       0x4
47   #define SATA_TOP_CTRL_2_SW_RST_MDIOREG                BIT(0)
48   #define SATA_TOP_CTRL_2_SW_RST_OOB                    BIT(1)
49   #define SATA_TOP_CTRL_2_SW_RST_RX                     BIT(2)
50   #define SATA_TOP_CTRL_2_SW_RST_TX                     BIT(3)
51   #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET              BIT(14)
52  #define SATA_TOP_CTRL_PHY_OFFS                         0x8
53  #define SATA_TOP_MAX_PHYS                              2
54
55 #define SATA_FIRST_PORT_CTRL                            0x700
56 #define SATA_NEXT_PORT_CTRL_OFFSET                      0x80
57 #define SATA_PORT_PCTRL6(reg_base)                      (reg_base + 0x18)
58
59 /* On big-endian MIPS, buses are reversed to big endian, so switch them back */
60 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
61 #define DATA_ENDIAN                      2 /* AHCI->DDR inbound accesses */
62 #define MMIO_ENDIAN                      2 /* CPU->AHCI outbound accesses */
63 #else
64 #define DATA_ENDIAN                      0
65 #define MMIO_ENDIAN                      0
66 #endif
67
68 #define BUS_CTRL_ENDIAN_CONF                            \
69         ((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) |        \
70         (DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) |         \
71         (MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
72
73 enum brcm_ahci_version {
74         BRCM_SATA_BCM7425 = 1,
75         BRCM_SATA_BCM7445,
76         BRCM_SATA_NSP,
77 };
78
79 enum brcm_ahci_quirks {
80         BRCM_AHCI_QUIRK_NO_NCQ          = BIT(0),
81         BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(1),
82 };
83
84 struct brcm_ahci_priv {
85         struct device *dev;
86         void __iomem *top_ctrl;
87         u32 port_mask;
88         u32 quirks;
89         enum brcm_ahci_version version;
90 };
91
92 static const struct ata_port_info ahci_brcm_port_info = {
93         .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
94         .link_flags     = ATA_LFLAG_NO_DB_DELAY,
95         .pio_mask       = ATA_PIO4,
96         .udma_mask      = ATA_UDMA6,
97         .port_ops       = &ahci_platform_ops,
98 };
99
100 static inline u32 brcm_sata_readreg(void __iomem *addr)
101 {
102         /*
103          * MIPS endianness is configured by boot strap, which also reverses all
104          * bus endianness (i.e., big-endian CPU + big endian bus ==> native
105          * endian I/O).
106          *
107          * Other architectures (e.g., ARM) either do not support big endian, or
108          * else leave I/O in little endian mode.
109          */
110         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
111                 return __raw_readl(addr);
112         else
113                 return readl_relaxed(addr);
114 }
115
116 static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
117 {
118         /* See brcm_sata_readreg() comments */
119         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
120                 __raw_writel(val, addr);
121         else
122                 writel_relaxed(val, addr);
123 }
124
125 static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv)
126 {
127         struct brcm_ahci_priv *priv = hpriv->plat_data;
128         u32 port_ctrl, host_caps;
129         int i;
130
131         /* Enable support for ALPM */
132         host_caps = readl(hpriv->mmio + HOST_CAP);
133         if (!(host_caps & HOST_CAP_ALPM))
134                 hpriv->flags |= AHCI_HFLAG_YES_ALPM;
135
136         /*
137          * Adjust timeout to allow PLL sufficient time to lock while waking
138          * up from slumber mode.
139          */
140         for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL;
141              i < SATA_TOP_MAX_PHYS;
142              i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET) {
143                 if (priv->port_mask & BIT(i))
144                         writel(0xff1003fc,
145                                hpriv->mmio + SATA_PORT_PCTRL6(port_ctrl));
146         }
147 }
148
149 static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
150 {
151         void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
152                                 (port * SATA_TOP_CTRL_PHY_OFFS);
153         void __iomem *p;
154         u32 reg;
155
156         if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
157                 return;
158
159         /* clear PHY_DEFAULT_POWER_STATE */
160         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
161         reg = brcm_sata_readreg(p);
162         reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
163         brcm_sata_writereg(reg, p);
164
165         /* reset the PHY digital logic */
166         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
167         reg = brcm_sata_readreg(p);
168         reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
169                  SATA_TOP_CTRL_2_SW_RST_RX);
170         reg |= SATA_TOP_CTRL_2_SW_RST_TX;
171         brcm_sata_writereg(reg, p);
172         reg = brcm_sata_readreg(p);
173         reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
174         brcm_sata_writereg(reg, p);
175         reg = brcm_sata_readreg(p);
176         reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
177         brcm_sata_writereg(reg, p);
178         (void)brcm_sata_readreg(p);
179 }
180
181 static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
182 {
183         void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
184                                 (port * SATA_TOP_CTRL_PHY_OFFS);
185         void __iomem *p;
186         u32 reg;
187
188         if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
189                 return;
190
191         /* power-off the PHY digital logic */
192         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
193         reg = brcm_sata_readreg(p);
194         reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
195                 SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX |
196                 SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
197         brcm_sata_writereg(reg, p);
198
199         /* set PHY_DEFAULT_POWER_STATE */
200         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
201         reg = brcm_sata_readreg(p);
202         reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
203         brcm_sata_writereg(reg, p);
204 }
205
206 static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv)
207 {
208         int i;
209
210         for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
211                 if (priv->port_mask & BIT(i))
212                         brcm_sata_phy_enable(priv, i);
213 }
214
215 static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv)
216 {
217         int i;
218
219         for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
220                 if (priv->port_mask & BIT(i))
221                         brcm_sata_phy_disable(priv, i);
222 }
223
224 static u32 brcm_ahci_get_portmask(struct platform_device *pdev,
225                                   struct brcm_ahci_priv *priv)
226 {
227         void __iomem *ahci;
228         struct resource *res;
229         u32 impl;
230
231         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci");
232         ahci = devm_ioremap_resource(&pdev->dev, res);
233         if (IS_ERR(ahci))
234                 return 0;
235
236         impl = readl(ahci + HOST_PORTS_IMPL);
237
238         if (fls(impl) > SATA_TOP_MAX_PHYS)
239                 dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n",
240                          impl);
241         else if (!impl)
242                 dev_info(priv->dev, "no ports found\n");
243
244         devm_iounmap(&pdev->dev, ahci);
245         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
246
247         return impl;
248 }
249
250 static void brcm_sata_init(struct brcm_ahci_priv *priv)
251 {
252         void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL;
253
254         /* Configure endianness */
255         if (priv->version ==  BRCM_SATA_NSP) {
256                 u32 data = brcm_sata_readreg(ctrl);
257
258                 data &= ~((0x03 << DMADATA_ENDIAN_SHIFT) |
259                         (0x03 << DMADESC_ENDIAN_SHIFT));
260                 data |= (0x02 << DMADATA_ENDIAN_SHIFT) |
261                         (0x02 << DMADESC_ENDIAN_SHIFT);
262                 brcm_sata_writereg(data, ctrl);
263         } else
264                 brcm_sata_writereg(BUS_CTRL_ENDIAN_CONF, ctrl);
265 }
266
267 #ifdef CONFIG_PM_SLEEP
268 static int brcm_ahci_suspend(struct device *dev)
269 {
270         struct ata_host *host = dev_get_drvdata(dev);
271         struct ahci_host_priv *hpriv = host->private_data;
272         struct brcm_ahci_priv *priv = hpriv->plat_data;
273         int ret;
274
275         ret = ahci_platform_suspend(dev);
276         brcm_sata_phys_disable(priv);
277         return ret;
278 }
279
280 static int brcm_ahci_resume(struct device *dev)
281 {
282         struct ata_host *host = dev_get_drvdata(dev);
283         struct ahci_host_priv *hpriv = host->private_data;
284         struct brcm_ahci_priv *priv = hpriv->plat_data;
285
286         brcm_sata_init(priv);
287         brcm_sata_phys_enable(priv);
288         brcm_sata_alpm_init(hpriv);
289         return ahci_platform_resume(dev);
290 }
291 #endif
292
293 static struct scsi_host_template ahci_platform_sht = {
294         AHCI_SHT(DRV_NAME),
295 };
296
297 static const struct of_device_id ahci_of_match[] = {
298         {.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
299         {.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
300         {.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
301         {},
302 };
303 MODULE_DEVICE_TABLE(of, ahci_of_match);
304
305 static int brcm_ahci_probe(struct platform_device *pdev)
306 {
307         const struct of_device_id *of_id;
308         struct device *dev = &pdev->dev;
309         struct brcm_ahci_priv *priv;
310         struct ahci_host_priv *hpriv;
311         struct resource *res;
312         int ret;
313
314         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
315         if (!priv)
316                 return -ENOMEM;
317
318         of_id = of_match_node(ahci_of_match, pdev->dev.of_node);
319         if (!of_id)
320                 return -ENODEV;
321
322         priv->version = (enum brcm_ahci_version)of_id->data;
323         priv->dev = dev;
324
325         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
326         priv->top_ctrl = devm_ioremap_resource(dev, res);
327         if (IS_ERR(priv->top_ctrl))
328                 return PTR_ERR(priv->top_ctrl);
329
330         if ((priv->version == BRCM_SATA_BCM7425) ||
331                 (priv->version == BRCM_SATA_NSP)) {
332                 priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
333                 priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
334         }
335
336         brcm_sata_init(priv);
337
338         priv->port_mask = brcm_ahci_get_portmask(pdev, priv);
339         if (!priv->port_mask)
340                 return -ENODEV;
341
342         brcm_sata_phys_enable(priv);
343
344         hpriv = ahci_platform_get_resources(pdev);
345         if (IS_ERR(hpriv))
346                 return PTR_ERR(hpriv);
347         hpriv->plat_data = priv;
348         hpriv->flags = AHCI_HFLAG_WAKE_BEFORE_STOP;
349
350         brcm_sata_alpm_init(hpriv);
351
352         ret = ahci_platform_enable_resources(hpriv);
353         if (ret)
354                 return ret;
355
356         if (priv->quirks & BRCM_AHCI_QUIRK_NO_NCQ)
357                 hpriv->flags |= AHCI_HFLAG_NO_NCQ;
358         hpriv->flags |= AHCI_HFLAG_NO_WRITE_TO_RO;
359
360         ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
361                                       &ahci_platform_sht);
362         if (ret)
363                 return ret;
364
365         dev_info(dev, "Broadcom AHCI SATA3 registered\n");
366
367         return 0;
368 }
369
370 static int brcm_ahci_remove(struct platform_device *pdev)
371 {
372         struct ata_host *host = dev_get_drvdata(&pdev->dev);
373         struct ahci_host_priv *hpriv = host->private_data;
374         struct brcm_ahci_priv *priv = hpriv->plat_data;
375         int ret;
376
377         ret = ata_platform_remove_one(pdev);
378         if (ret)
379                 return ret;
380
381         brcm_sata_phys_disable(priv);
382
383         return 0;
384 }
385
386 static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
387
388 static struct platform_driver brcm_ahci_driver = {
389         .probe = brcm_ahci_probe,
390         .remove = brcm_ahci_remove,
391         .driver = {
392                 .name = DRV_NAME,
393                 .of_match_table = ahci_of_match,
394                 .pm = &ahci_brcm_pm_ops,
395         },
396 };
397 module_platform_driver(brcm_ahci_driver);
398
399 MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
400 MODULE_AUTHOR("Brian Norris");
401 MODULE_LICENSE("GPL");
402 MODULE_ALIAS("platform:sata-brcmstb");