ata: ahci_brcm: BCM7425 AHCI requires AHCI_HFLAG_DELAY_ENGINE
[sfrench/cifs-2.6.git] / drivers / ata / ahci_brcm.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Broadcom SATA3 AHCI Controller Driver
4  *
5  * Copyright © 2009-2015 Broadcom Corporation
6  */
7
8 #include <linux/ahci_platform.h>
9 #include <linux/compiler.h>
10 #include <linux/device.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/libata.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/reset.h>
20 #include <linux/string.h>
21
22 #include "ahci.h"
23
24 #define DRV_NAME                                        "brcm-ahci"
25
26 #define SATA_TOP_CTRL_VERSION                           0x0
27 #define SATA_TOP_CTRL_BUS_CTRL                          0x4
28  #define MMIO_ENDIAN_SHIFT                              0 /* CPU->AHCI */
29  #define DMADESC_ENDIAN_SHIFT                           2 /* AHCI->DDR */
30  #define DMADATA_ENDIAN_SHIFT                           4 /* AHCI->DDR */
31  #define PIODATA_ENDIAN_SHIFT                           6
32   #define ENDIAN_SWAP_NONE                              0
33   #define ENDIAN_SWAP_FULL                              2
34 #define SATA_TOP_CTRL_TP_CTRL                           0x8
35 #define SATA_TOP_CTRL_PHY_CTRL                          0xc
36  #define SATA_TOP_CTRL_PHY_CTRL_1                       0x0
37   #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE       BIT(14)
38  #define SATA_TOP_CTRL_PHY_CTRL_2                       0x4
39   #define SATA_TOP_CTRL_2_SW_RST_MDIOREG                BIT(0)
40   #define SATA_TOP_CTRL_2_SW_RST_OOB                    BIT(1)
41   #define SATA_TOP_CTRL_2_SW_RST_RX                     BIT(2)
42   #define SATA_TOP_CTRL_2_SW_RST_TX                     BIT(3)
43   #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET              BIT(14)
44  #define SATA_TOP_CTRL_PHY_OFFS                         0x8
45  #define SATA_TOP_MAX_PHYS                              2
46
47 #define SATA_FIRST_PORT_CTRL                            0x700
48 #define SATA_NEXT_PORT_CTRL_OFFSET                      0x80
49 #define SATA_PORT_PCTRL6(reg_base)                      (reg_base + 0x18)
50
51 /* On big-endian MIPS, buses are reversed to big endian, so switch them back */
52 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
53 #define DATA_ENDIAN                      2 /* AHCI->DDR inbound accesses */
54 #define MMIO_ENDIAN                      2 /* CPU->AHCI outbound accesses */
55 #else
56 #define DATA_ENDIAN                      0
57 #define MMIO_ENDIAN                      0
58 #endif
59
60 #define BUS_CTRL_ENDIAN_CONF                            \
61         ((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) |        \
62         (DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) |         \
63         (MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
64
65 #define BUS_CTRL_ENDIAN_NSP_CONF                        \
66         (0x02 << DMADATA_ENDIAN_SHIFT | 0x02 << DMADESC_ENDIAN_SHIFT)
67
68 #define BUS_CTRL_ENDIAN_CONF_MASK                       \
69         (0x3 << MMIO_ENDIAN_SHIFT | 0x3 << DMADESC_ENDIAN_SHIFT |       \
70          0x3 << DMADATA_ENDIAN_SHIFT | 0x3 << PIODATA_ENDIAN_SHIFT)
71
72 enum brcm_ahci_version {
73         BRCM_SATA_BCM7425 = 1,
74         BRCM_SATA_BCM7445,
75         BRCM_SATA_NSP,
76 };
77
78 enum brcm_ahci_quirks {
79         BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(0),
80 };
81
82 struct brcm_ahci_priv {
83         struct device *dev;
84         void __iomem *top_ctrl;
85         u32 port_mask;
86         u32 quirks;
87         enum brcm_ahci_version version;
88         struct reset_control *rcdev;
89 };
90
91 static inline u32 brcm_sata_readreg(void __iomem *addr)
92 {
93         /*
94          * MIPS endianness is configured by boot strap, which also reverses all
95          * bus endianness (i.e., big-endian CPU + big endian bus ==> native
96          * endian I/O).
97          *
98          * Other architectures (e.g., ARM) either do not support big endian, or
99          * else leave I/O in little endian mode.
100          */
101         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
102                 return __raw_readl(addr);
103         else
104                 return readl_relaxed(addr);
105 }
106
107 static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
108 {
109         /* See brcm_sata_readreg() comments */
110         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
111                 __raw_writel(val, addr);
112         else
113                 writel_relaxed(val, addr);
114 }
115
116 static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv)
117 {
118         struct brcm_ahci_priv *priv = hpriv->plat_data;
119         u32 port_ctrl, host_caps;
120         int i;
121
122         /* Enable support for ALPM */
123         host_caps = readl(hpriv->mmio + HOST_CAP);
124         if (!(host_caps & HOST_CAP_ALPM))
125                 hpriv->flags |= AHCI_HFLAG_YES_ALPM;
126
127         /*
128          * Adjust timeout to allow PLL sufficient time to lock while waking
129          * up from slumber mode.
130          */
131         for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL;
132              i < SATA_TOP_MAX_PHYS;
133              i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET) {
134                 if (priv->port_mask & BIT(i))
135                         writel(0xff1003fc,
136                                hpriv->mmio + SATA_PORT_PCTRL6(port_ctrl));
137         }
138 }
139
140 static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
141 {
142         void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
143                                 (port * SATA_TOP_CTRL_PHY_OFFS);
144         void __iomem *p;
145         u32 reg;
146
147         if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
148                 return;
149
150         /* clear PHY_DEFAULT_POWER_STATE */
151         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
152         reg = brcm_sata_readreg(p);
153         reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
154         brcm_sata_writereg(reg, p);
155
156         /* reset the PHY digital logic */
157         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
158         reg = brcm_sata_readreg(p);
159         reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
160                  SATA_TOP_CTRL_2_SW_RST_RX);
161         reg |= SATA_TOP_CTRL_2_SW_RST_TX;
162         brcm_sata_writereg(reg, p);
163         reg = brcm_sata_readreg(p);
164         reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
165         brcm_sata_writereg(reg, p);
166         reg = brcm_sata_readreg(p);
167         reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
168         brcm_sata_writereg(reg, p);
169         (void)brcm_sata_readreg(p);
170 }
171
172 static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
173 {
174         void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
175                                 (port * SATA_TOP_CTRL_PHY_OFFS);
176         void __iomem *p;
177         u32 reg;
178
179         if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
180                 return;
181
182         /* power-off the PHY digital logic */
183         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
184         reg = brcm_sata_readreg(p);
185         reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
186                 SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX |
187                 SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
188         brcm_sata_writereg(reg, p);
189
190         /* set PHY_DEFAULT_POWER_STATE */
191         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
192         reg = brcm_sata_readreg(p);
193         reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
194         brcm_sata_writereg(reg, p);
195 }
196
197 static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv)
198 {
199         int i;
200
201         for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
202                 if (priv->port_mask & BIT(i))
203                         brcm_sata_phy_enable(priv, i);
204 }
205
206 static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv)
207 {
208         int i;
209
210         for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
211                 if (priv->port_mask & BIT(i))
212                         brcm_sata_phy_disable(priv, i);
213 }
214
215 static u32 brcm_ahci_get_portmask(struct ahci_host_priv *hpriv,
216                                   struct brcm_ahci_priv *priv)
217 {
218         u32 impl;
219
220         impl = readl(hpriv->mmio + HOST_PORTS_IMPL);
221
222         if (fls(impl) > SATA_TOP_MAX_PHYS)
223                 dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n",
224                          impl);
225         else if (!impl)
226                 dev_info(priv->dev, "no ports found\n");
227
228         return impl;
229 }
230
231 static void brcm_sata_init(struct brcm_ahci_priv *priv)
232 {
233         void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL;
234         u32 data;
235
236         /* Configure endianness */
237         data = brcm_sata_readreg(ctrl);
238         data &= ~BUS_CTRL_ENDIAN_CONF_MASK;
239         if (priv->version == BRCM_SATA_NSP)
240                 data |= BUS_CTRL_ENDIAN_NSP_CONF;
241         else
242                 data |= BUS_CTRL_ENDIAN_CONF;
243         brcm_sata_writereg(data, ctrl);
244 }
245
246 static unsigned int brcm_ahci_read_id(struct ata_device *dev,
247                                       struct ata_taskfile *tf, u16 *id)
248 {
249         struct ata_port *ap = dev->link->ap;
250         struct ata_host *host = ap->host;
251         struct ahci_host_priv *hpriv = host->private_data;
252         struct brcm_ahci_priv *priv = hpriv->plat_data;
253         void __iomem *mmio = hpriv->mmio;
254         unsigned int err_mask;
255         unsigned long flags;
256         int i, rc;
257         u32 ctl;
258
259         /* Try to read the device ID and, if this fails, proceed with the
260          * recovery sequence below
261          */
262         err_mask = ata_do_dev_read_id(dev, tf, id);
263         if (likely(!err_mask))
264                 return err_mask;
265
266         /* Disable host interrupts */
267         spin_lock_irqsave(&host->lock, flags);
268         ctl = readl(mmio + HOST_CTL);
269         ctl &= ~HOST_IRQ_EN;
270         writel(ctl, mmio + HOST_CTL);
271         readl(mmio + HOST_CTL); /* flush */
272         spin_unlock_irqrestore(&host->lock, flags);
273
274         /* Perform the SATA PHY reset sequence */
275         brcm_sata_phy_disable(priv, ap->port_no);
276
277         /* Bring the PHY back on */
278         brcm_sata_phy_enable(priv, ap->port_no);
279
280         /* Re-initialize and calibrate the PHY */
281         for (i = 0; i < hpriv->nports; i++) {
282                 rc = phy_init(hpriv->phys[i]);
283                 if (rc)
284                         goto disable_phys;
285
286                 rc = phy_calibrate(hpriv->phys[i]);
287                 if (rc) {
288                         phy_exit(hpriv->phys[i]);
289                         goto disable_phys;
290                 }
291         }
292
293         /* Re-enable host interrupts */
294         spin_lock_irqsave(&host->lock, flags);
295         ctl = readl(mmio + HOST_CTL);
296         ctl |= HOST_IRQ_EN;
297         writel(ctl, mmio + HOST_CTL);
298         readl(mmio + HOST_CTL); /* flush */
299         spin_unlock_irqrestore(&host->lock, flags);
300
301         return ata_do_dev_read_id(dev, tf, id);
302
303 disable_phys:
304         while (--i >= 0) {
305                 phy_power_off(hpriv->phys[i]);
306                 phy_exit(hpriv->phys[i]);
307         }
308
309         return AC_ERR_OTHER;
310 }
311
312 static void brcm_ahci_host_stop(struct ata_host *host)
313 {
314         struct ahci_host_priv *hpriv = host->private_data;
315
316         ahci_platform_disable_resources(hpriv);
317 }
318
319 static struct ata_port_operations ahci_brcm_platform_ops = {
320         .inherits       = &ahci_ops,
321         .host_stop      = brcm_ahci_host_stop,
322         .read_id        = brcm_ahci_read_id,
323 };
324
325 static const struct ata_port_info ahci_brcm_port_info = {
326         .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
327         .link_flags     = ATA_LFLAG_NO_DB_DELAY,
328         .pio_mask       = ATA_PIO4,
329         .udma_mask      = ATA_UDMA6,
330         .port_ops       = &ahci_brcm_platform_ops,
331 };
332
333 #ifdef CONFIG_PM_SLEEP
334 static int brcm_ahci_suspend(struct device *dev)
335 {
336         struct ata_host *host = dev_get_drvdata(dev);
337         struct ahci_host_priv *hpriv = host->private_data;
338         struct brcm_ahci_priv *priv = hpriv->plat_data;
339
340         brcm_sata_phys_disable(priv);
341
342         return ahci_platform_suspend(dev);
343 }
344
345 static int brcm_ahci_resume(struct device *dev)
346 {
347         struct ata_host *host = dev_get_drvdata(dev);
348         struct ahci_host_priv *hpriv = host->private_data;
349         struct brcm_ahci_priv *priv = hpriv->plat_data;
350         int ret;
351
352         /* Make sure clocks are turned on before re-configuration */
353         ret = ahci_platform_enable_clks(hpriv);
354         if (ret)
355                 return ret;
356
357         brcm_sata_init(priv);
358         brcm_sata_phys_enable(priv);
359         brcm_sata_alpm_init(hpriv);
360
361         /* Since we had to enable clocks earlier on, we cannot use
362          * ahci_platform_resume() as-is since a second call to
363          * ahci_platform_enable_resources() would bump up the resources
364          * (regulators, clocks, PHYs) count artificially so we copy the part
365          * after ahci_platform_enable_resources().
366          */
367         ret = ahci_platform_enable_phys(hpriv);
368         if (ret)
369                 goto out_disable_phys;
370
371         ret = ahci_platform_resume_host(dev);
372         if (ret)
373                 goto out_disable_platform_phys;
374
375         /* We resumed so update PM runtime state */
376         pm_runtime_disable(dev);
377         pm_runtime_set_active(dev);
378         pm_runtime_enable(dev);
379
380         return 0;
381
382 out_disable_platform_phys:
383         ahci_platform_disable_phys(hpriv);
384 out_disable_phys:
385         brcm_sata_phys_disable(priv);
386         ahci_platform_disable_clks(hpriv);
387         return ret;
388 }
389 #endif
390
391 static struct scsi_host_template ahci_platform_sht = {
392         AHCI_SHT(DRV_NAME),
393 };
394
395 static const struct of_device_id ahci_of_match[] = {
396         {.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
397         {.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
398         {.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445},
399         {.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
400         {},
401 };
402 MODULE_DEVICE_TABLE(of, ahci_of_match);
403
404 static int brcm_ahci_probe(struct platform_device *pdev)
405 {
406         const struct of_device_id *of_id;
407         struct device *dev = &pdev->dev;
408         struct brcm_ahci_priv *priv;
409         struct ahci_host_priv *hpriv;
410         struct resource *res;
411         int ret;
412
413         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
414         if (!priv)
415                 return -ENOMEM;
416
417         of_id = of_match_node(ahci_of_match, pdev->dev.of_node);
418         if (!of_id)
419                 return -ENODEV;
420
421         priv->version = (enum brcm_ahci_version)of_id->data;
422         priv->dev = dev;
423
424         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
425         priv->top_ctrl = devm_ioremap_resource(dev, res);
426         if (IS_ERR(priv->top_ctrl))
427                 return PTR_ERR(priv->top_ctrl);
428
429         /* Reset is optional depending on platform */
430         priv->rcdev = devm_reset_control_get(&pdev->dev, "ahci");
431         if (!IS_ERR_OR_NULL(priv->rcdev))
432                 reset_control_deassert(priv->rcdev);
433
434         hpriv = ahci_platform_get_resources(pdev, 0);
435         if (IS_ERR(hpriv)) {
436                 ret = PTR_ERR(hpriv);
437                 goto out_reset;
438         }
439
440         hpriv->plat_data = priv;
441         hpriv->flags = AHCI_HFLAG_WAKE_BEFORE_STOP | AHCI_HFLAG_NO_WRITE_TO_RO;
442
443         switch (priv->version) {
444         case BRCM_SATA_BCM7425:
445                 hpriv->flags |= AHCI_HFLAG_DELAY_ENGINE;
446                 /* fall through */
447         case BRCM_SATA_NSP:
448                 hpriv->flags |= AHCI_HFLAG_NO_NCQ;
449                 priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
450                 break;
451         default:
452                 break;
453         }
454
455         ret = ahci_platform_enable_clks(hpriv);
456         if (ret)
457                 goto out_reset;
458
459         /* Must be first so as to configure endianness including that
460          * of the standard AHCI register space.
461          */
462         brcm_sata_init(priv);
463
464         /* Initializes priv->port_mask which is used below */
465         priv->port_mask = brcm_ahci_get_portmask(hpriv, priv);
466         if (!priv->port_mask) {
467                 ret = -ENODEV;
468                 goto out_disable_clks;
469         }
470
471         /* Must be done before ahci_platform_enable_phys() */
472         brcm_sata_phys_enable(priv);
473
474         brcm_sata_alpm_init(hpriv);
475
476         ret = ahci_platform_enable_phys(hpriv);
477         if (ret)
478                 goto out_disable_phys;
479
480         ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
481                                       &ahci_platform_sht);
482         if (ret)
483                 goto out_disable_platform_phys;
484
485         dev_info(dev, "Broadcom AHCI SATA3 registered\n");
486
487         return 0;
488
489 out_disable_platform_phys:
490         ahci_platform_disable_phys(hpriv);
491 out_disable_phys:
492         brcm_sata_phys_disable(priv);
493 out_disable_clks:
494         ahci_platform_disable_clks(hpriv);
495 out_reset:
496         if (!IS_ERR_OR_NULL(priv->rcdev))
497                 reset_control_assert(priv->rcdev);
498         return ret;
499 }
500
501 static int brcm_ahci_remove(struct platform_device *pdev)
502 {
503         struct ata_host *host = dev_get_drvdata(&pdev->dev);
504         struct ahci_host_priv *hpriv = host->private_data;
505         struct brcm_ahci_priv *priv = hpriv->plat_data;
506         int ret;
507
508         brcm_sata_phys_disable(priv);
509
510         ret = ata_platform_remove_one(pdev);
511         if (ret)
512                 return ret;
513
514         return 0;
515 }
516
517 static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
518
519 static struct platform_driver brcm_ahci_driver = {
520         .probe = brcm_ahci_probe,
521         .remove = brcm_ahci_remove,
522         .driver = {
523                 .name = DRV_NAME,
524                 .of_match_table = ahci_of_match,
525                 .pm = &ahci_brcm_pm_ops,
526         },
527 };
528 module_platform_driver(brcm_ahci_driver);
529
530 MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
531 MODULE_AUTHOR("Brian Norris");
532 MODULE_LICENSE("GPL");
533 MODULE_ALIAS("platform:sata-brcmstb");