drivers/acpi/cppc_acpi.c

   1 /*
   2  * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
   3  *
   4  * (C) Copyright 2014, 2015 Linaro Ltd.
   5  * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; version 2
  10  * of the License.
  11  *
  12  * CPPC describes a few methods for controlling CPU performance using
  13  * information from a per CPU table called CPC. This table is described in
  14  * the ACPI v5.0+ specification. The table consists of a list of
  15  * registers which may be memory mapped or hardware registers and also may
  16  * include some static integer values.
  17  *
  18  * CPU performance is on an abstract continuous scale as against a discretized
  19  * P-state scale which is tied to CPU frequency only. In brief, the basic
  20  * operation involves:
  21  *
  22  * - OS makes a CPU performance request. (Can provide min and max bounds)
  23  *
  24  * - Platform (such as BMC) is free to optimize request within requested bounds
  25  *   depending on power/thermal budgets etc.
  26  *
  27  * - Platform conveys its decision back to OS
  28  *
  29  * The communication between OS and platform occurs through another medium
  30  * called (PCC) Platform Communication Channel. This is a generic mailbox like
  31  * mechanism which includes doorbell semantics to indicate register updates.
  32  * See drivers/mailbox/pcc.c for details on PCC.
  33  *
  34  * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
  35  * above specifications.
  36  */
  37
  38 #define pr_fmt(fmt)     "ACPI CPPC: " fmt
  39
  40 #include <linux/cpufreq.h>
  41 #include <linux/delay.h>
  42 #include <linux/ktime.h>
  43
  44 #include <acpi/cppc_acpi.h>
  45 /*
  46  * Lock to provide mutually exclusive access to the PCC
  47  * channel. e.g. When the remote updates the shared region
  48  * with new data, the reader needs to be protected from
  49  * other CPUs activity on the same channel.
  50  */
  51 static DEFINE_SPINLOCK(pcc_lock);
  52
  53 /*
  54  * The cpc_desc structure contains the ACPI register details
  55  * as described in the per CPU _CPC tables. The details
  56  * include the type of register (e.g. PCC, System IO, FFH etc.)
  57  * and destination addresses which lets us READ/WRITE CPU performance
  58  * information using the appropriate I/O methods.
  59  */
  60 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
  61
  62 /* This layer handles all the PCC specifics for CPPC. */
  63 static struct mbox_chan *pcc_channel;
  64 static void __iomem *pcc_comm_addr;
  65 static u64 comm_base_addr;
  66 static int pcc_subspace_idx = -1;
  67 static bool pcc_channel_acquired;
  68 static ktime_t deadline;
  69 static unsigned int pcc_mpar, pcc_mrtt;
  70
  71 /* pcc mapped address + header size + offset within PCC subspace */
  72 #define GET_PCC_VADDR(offs) (pcc_comm_addr + 0x8 + (offs))
  73
  74 /*
  75  * Arbitrary Retries in case the remote processor is slow to respond
  76  * to PCC commands. Keeping it high enough to cover emulators where
  77  * the processors run painfully slow.
  78  */
  79 #define NUM_RETRIES 500
  80
  81 static int check_pcc_chan(void)
  82 {
  83         int ret = -EIO;
  84         struct acpi_pcct_shared_memory __iomem *generic_comm_base = pcc_comm_addr;
  85         ktime_t next_deadline = ktime_add(ktime_get(), deadline);
  86
  87         /* Retry in case the remote processor was too slow to catch up. */
  88         while (!ktime_after(ktime_get(), next_deadline)) {
  89                 /*
  90                  * Per spec, prior to boot the PCC space wil be initialized by
  91                  * platform and should have set the command completion bit when
  92                  * PCC can be used by OSPM
  93                  */
  94                 if (readw_relaxed(&generic_comm_base->status) & PCC_CMD_COMPLETE) {
  95                         ret = 0;
  96                         break;
  97                 }
  98                 /*
  99                  * Reducing the bus traffic in case this loop takes longer than
 100                  * a few retries.
 101                  */
 102                 udelay(3);
 103         }
 104
 105         return ret;
 106 }
 107
 108 static int send_pcc_cmd(u16 cmd)
 109 {
 110         int ret = -EIO;
 111         struct acpi_pcct_shared_memory *generic_comm_base =
 112                 (struct acpi_pcct_shared_memory *) pcc_comm_addr;
 113         static ktime_t last_cmd_cmpl_time, last_mpar_reset;
 114         static int mpar_count;
 115         unsigned int time_delta;
 116
 117         /*
 118          * For CMD_WRITE we know for a fact the caller should have checked
 119          * the channel before writing to PCC space
 120          */
 121         if (cmd == CMD_READ) {
 122                 ret = check_pcc_chan();
 123                 if (ret)
 124                         return ret;
 125         }
 126
 127         /*
 128          * Handle the Minimum Request Turnaround Time(MRTT)
 129          * "The minimum amount of time that OSPM must wait after the completion
 130          * of a command before issuing the next command, in microseconds"
 131          */
 132         if (pcc_mrtt) {
 133                 time_delta = ktime_us_delta(ktime_get(), last_cmd_cmpl_time);
 134                 if (pcc_mrtt > time_delta)
 135                         udelay(pcc_mrtt - time_delta);
 136         }
 137
 138         /*
 139          * Handle the non-zero Maximum Periodic Access Rate(MPAR)
 140          * "The maximum number of periodic requests that the subspace channel can
 141          * support, reported in commands per minute. 0 indicates no limitation."
 142          *
 143          * This parameter should be ideally zero or large enough so that it can
 144          * handle maximum number of requests that all the cores in the system can
 145          * collectively generate. If it is not, we will follow the spec and just
 146          * not send the request to the platform after hitting the MPAR limit in
 147          * any 60s window
 148          */
 149         if (pcc_mpar) {
 150                 if (mpar_count == 0) {
 151                         time_delta = ktime_ms_delta(ktime_get(), last_mpar_reset);
 152                         if (time_delta < 60 * MSEC_PER_SEC) {
 153                                 pr_debug("PCC cmd not sent due to MPAR limit");
 154                                 return -EIO;
 155                         }
 156                         last_mpar_reset = ktime_get();
 157                         mpar_count = pcc_mpar;
 158                 }
 159                 mpar_count--;
 160         }
 161
 162         /* Write to the shared comm region. */
 163         writew_relaxed(cmd, &generic_comm_base->command);
 164
 165         /* Flip CMD COMPLETE bit */
 166         writew_relaxed(0, &generic_comm_base->status);
 167
 168         /* Ring doorbell */
 169         ret = mbox_send_message(pcc_channel, &cmd);
 170         if (ret < 0) {
 171                 pr_err("Err sending PCC mbox message. cmd:%d, ret:%d\n",
 172                                 cmd, ret);
 173                 return ret;
 174         }
 175
 176         /*
 177          * For READs we need to ensure the cmd completed to ensure
 178          * the ensuing read()s can proceed. For WRITEs we dont care
 179          * because the actual write()s are done before coming here
 180          * and the next READ or WRITE will check if the channel
 181          * is busy/free at the entry of this call.
 182          *
 183          * If Minimum Request Turnaround Time is non-zero, we need
 184          * to record the completion time of both READ and WRITE
 185          * command for proper handling of MRTT, so we need to check
 186          * for pcc_mrtt in addition to CMD_READ
 187          */
 188         if (cmd == CMD_READ || pcc_mrtt) {
 189                 ret = check_pcc_chan();
 190                 if (pcc_mrtt)
 191                         last_cmd_cmpl_time = ktime_get();
 192         }
 193
 194         mbox_client_txdone(pcc_channel, ret);
 195         return ret;
 196 }
 197
 198 static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
 199 {
 200         if (ret < 0)
 201                 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
 202                                 *(u16 *)msg, ret);
 203         else
 204                 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
 205                                 *(u16 *)msg, ret);
 206 }
 207
 208 struct mbox_client cppc_mbox_cl = {
 209         .tx_done = cppc_chan_tx_done,
 210         .knows_txdone = true,
 211 };
 212
 213 static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
 214 {
 215         int result = -EFAULT;
 216         acpi_status status = AE_OK;
 217         struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
 218         struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
 219         struct acpi_buffer state = {0, NULL};
 220         union acpi_object  *psd = NULL;
 221         struct acpi_psd_package *pdomain;
 222
 223         status = acpi_evaluate_object_typed(handle, "_PSD", NULL, &buffer,
 224                         ACPI_TYPE_PACKAGE);
 225         if (ACPI_FAILURE(status))
 226                 return -ENODEV;
 227
 228         psd = buffer.pointer;
 229         if (!psd || psd->package.count != 1) {
 230                 pr_debug("Invalid _PSD data\n");
 231                 goto end;
 232         }
 233
 234         pdomain = &(cpc_ptr->domain_info);
 235
 236         state.length = sizeof(struct acpi_psd_package);
 237         state.pointer = pdomain;
 238
 239         status = acpi_extract_package(&(psd->package.elements[0]),
 240                 &format, &state);
 241         if (ACPI_FAILURE(status)) {
 242                 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
 243                 goto end;
 244         }
 245
 246         if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
 247                 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
 248                 goto end;
 249         }
 250
 251         if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
 252                 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
 253                 goto end;
 254         }
 255
 256         if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
 257             pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
 258             pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
 259                 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
 260                 goto end;
 261         }
 262
 263         result = 0;
 264 end:
 265         kfree(buffer.pointer);
 266         return result;
 267 }
 268
 269 /**
 270  * acpi_get_psd_map - Map the CPUs in a common freq domain.
 271  * @all_cpu_data: Ptrs to CPU specific CPPC data including PSD info.
 272  *
 273  *      Return: 0 for success or negative value for err.
 274  */
 275 int acpi_get_psd_map(struct cpudata **all_cpu_data)
 276 {
 277         int count_target;
 278         int retval = 0;
 279         unsigned int i, j;
 280         cpumask_var_t covered_cpus;
 281         struct cpudata *pr, *match_pr;
 282         struct acpi_psd_package *pdomain;
 283         struct acpi_psd_package *match_pdomain;
 284         struct cpc_desc *cpc_ptr, *match_cpc_ptr;
 285
 286         if (!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL))
 287                 return -ENOMEM;
 288
 289         /*
 290          * Now that we have _PSD data from all CPUs, lets setup P-state
 291          * domain info.
 292          */
 293         for_each_possible_cpu(i) {
 294                 pr = all_cpu_data[i];
 295                 if (!pr)
 296                         continue;
 297
 298                 if (cpumask_test_cpu(i, covered_cpus))
 299                         continue;
 300
 301                 cpc_ptr = per_cpu(cpc_desc_ptr, i);
 302                 if (!cpc_ptr) {
 303                         retval = -EFAULT;
 304                         goto err_ret;
 305                 }
 306
 307                 pdomain = &(cpc_ptr->domain_info);
 308                 cpumask_set_cpu(i, pr->shared_cpu_map);
 309                 cpumask_set_cpu(i, covered_cpus);
 310                 if (pdomain->num_processors <= 1)
 311                         continue;
 312
 313                 /* Validate the Domain info */
 314                 count_target = pdomain->num_processors;
 315                 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
 316                         pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
 317                 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
 318                         pr->shared_type = CPUFREQ_SHARED_TYPE_HW;
 319                 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
 320                         pr->shared_type = CPUFREQ_SHARED_TYPE_ANY;
 321
 322                 for_each_possible_cpu(j) {
 323                         if (i == j)
 324                                 continue;
 325
 326                         match_cpc_ptr = per_cpu(cpc_desc_ptr, j);
 327                         if (!match_cpc_ptr) {
 328                                 retval = -EFAULT;
 329                                 goto err_ret;
 330                         }
 331
 332                         match_pdomain = &(match_cpc_ptr->domain_info);
 333                         if (match_pdomain->domain != pdomain->domain)
 334                                 continue;
 335
 336                         /* Here i and j are in the same domain */
 337                         if (match_pdomain->num_processors != count_target) {
 338                                 retval = -EFAULT;
 339                                 goto err_ret;
 340                         }
 341
 342                         if (pdomain->coord_type != match_pdomain->coord_type) {
 343                                 retval = -EFAULT;
 344                                 goto err_ret;
 345                         }
 346
 347                         cpumask_set_cpu(j, covered_cpus);
 348                         cpumask_set_cpu(j, pr->shared_cpu_map);
 349                 }
 350
 351                 for_each_possible_cpu(j) {
 352                         if (i == j)
 353                                 continue;
 354
 355                         match_pr = all_cpu_data[j];
 356                         if (!match_pr)
 357                                 continue;
 358
 359                         match_cpc_ptr = per_cpu(cpc_desc_ptr, j);
 360                         if (!match_cpc_ptr) {
 361                                 retval = -EFAULT;
 362                                 goto err_ret;
 363                         }
 364
 365                         match_pdomain = &(match_cpc_ptr->domain_info);
 366                         if (match_pdomain->domain != pdomain->domain)
 367                                 continue;
 368
 369                         match_pr->shared_type = pr->shared_type;
 370                         cpumask_copy(match_pr->shared_cpu_map,
 371                                      pr->shared_cpu_map);
 372                 }
 373         }
 374
 375 err_ret:
 376         for_each_possible_cpu(i) {
 377                 pr = all_cpu_data[i];
 378                 if (!pr)
 379                         continue;
 380
 381                 /* Assume no coordination on any error parsing domain info */
 382                 if (retval) {
 383                         cpumask_clear(pr->shared_cpu_map);
 384                         cpumask_set_cpu(i, pr->shared_cpu_map);
 385                         pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
 386                 }
 387         }
 388
 389         free_cpumask_var(covered_cpus);
 390         return retval;
 391 }
 392 EXPORT_SYMBOL_GPL(acpi_get_psd_map);
 393
 394 static int register_pcc_channel(int pcc_subspace_idx)
 395 {
 396         struct acpi_pcct_hw_reduced *cppc_ss;
 397         unsigned int len;
 398         u64 usecs_lat;
 399
 400         if (pcc_subspace_idx >= 0) {
 401                 pcc_channel = pcc_mbox_request_channel(&cppc_mbox_cl,
 402                                 pcc_subspace_idx);
 403
 404                 if (IS_ERR(pcc_channel)) {
 405                         pr_err("Failed to find PCC communication channel\n");
 406                         return -ENODEV;
 407                 }
 408
 409                 /*
 410                  * The PCC mailbox controller driver should
 411                  * have parsed the PCCT (global table of all
 412                  * PCC channels) and stored pointers to the
 413                  * subspace communication region in con_priv.
 414                  */
 415                 cppc_ss = pcc_channel->con_priv;
 416
 417                 if (!cppc_ss) {
 418                         pr_err("No PCC subspace found for CPPC\n");
 419                         return -ENODEV;
 420                 }
 421
 422                 /*
 423                  * This is the shared communication region
 424                  * for the OS and Platform to communicate over.
 425                  */
 426                 comm_base_addr = cppc_ss->base_address;
 427                 len = cppc_ss->length;
 428
 429                 /*
 430                  * cppc_ss->latency is just a Nominal value. In reality
 431                  * the remote processor could be much slower to reply.
 432                  * So add an arbitrary amount of wait on top of Nominal.
 433                  */
 434                 usecs_lat = NUM_RETRIES * cppc_ss->latency;
 435                 deadline = ns_to_ktime(usecs_lat * NSEC_PER_USEC);
 436                 pcc_mrtt = cppc_ss->min_turnaround_time;
 437                 pcc_mpar = cppc_ss->max_access_rate;
 438
 439                 pcc_comm_addr = acpi_os_ioremap(comm_base_addr, len);
 440                 if (!pcc_comm_addr) {
 441                         pr_err("Failed to ioremap PCC comm region mem\n");
 442                         return -ENOMEM;
 443                 }
 444
 445                 /* Set flag so that we dont come here for each CPU. */
 446                 pcc_channel_acquired = true;
 447         }
 448
 449         return 0;
 450 }
 451
 452 /*
 453  * An example CPC table looks like the following.
 454  *
 455  *      Name(_CPC, Package()
 456  *                      {
 457  *                      17,
 458  *                      NumEntries
 459  *                      1,
 460  *                      // Revision
 461  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)},
 462  *                      // Highest Performance
 463  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)},
 464  *                      // Nominal Performance
 465  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)},
 466  *                      // Lowest Nonlinear Performance
 467  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)},
 468  *                      // Lowest Performance
 469  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)},
 470  *                      // Guaranteed Performance Register
 471  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)},
 472  *                      // Desired Performance Register
 473  *                      ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)},
 474  *                      ..
 475  *                      ..
 476  *                      ..
 477  *
 478  *              }
 479  * Each Register() encodes how to access that specific register.
 480  * e.g. a sample PCC entry has the following encoding:
 481  *
 482  *      Register (
 483  *              PCC,
 484  *              AddressSpaceKeyword
 485  *              8,
 486  *              //RegisterBitWidth
 487  *              8,
 488  *              //RegisterBitOffset
 489  *              0x30,
 490  *              //RegisterAddress
 491  *              9
 492  *              //AccessSize (subspace ID)
 493  *              0
 494  *              )
 495  *      }
 496  */
 497
 498 /**
 499  * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
 500  * @pr: Ptr to acpi_processor containing this CPUs logical Id.
 501  *
 502  *      Return: 0 for success or negative value for err.
 503  */
 504 int acpi_cppc_processor_probe(struct acpi_processor *pr)
 505 {
 506         struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
 507         union acpi_object *out_obj, *cpc_obj;
 508         struct cpc_desc *cpc_ptr;
 509         struct cpc_reg *gas_t;
 510         acpi_handle handle = pr->handle;
 511         unsigned int num_ent, i, cpc_rev;
 512         acpi_status status;
 513         int ret = -EFAULT;
 514
 515         /* Parse the ACPI _CPC table for this cpu. */
 516         status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
 517                         ACPI_TYPE_PACKAGE);
 518         if (ACPI_FAILURE(status)) {
 519                 ret = -ENODEV;
 520                 goto out_buf_free;
 521         }
 522
 523         out_obj = (union acpi_object *) output.pointer;
 524
 525         cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
 526         if (!cpc_ptr) {
 527                 ret = -ENOMEM;
 528                 goto out_buf_free;
 529         }
 530
 531         /* First entry is NumEntries. */
 532         cpc_obj = &out_obj->package.elements[0];
 533         if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 534                 num_ent = cpc_obj->integer.value;
 535         } else {
 536                 pr_debug("Unexpected entry type(%d) for NumEntries\n",
 537                                 cpc_obj->type);
 538                 goto out_free;
 539         }
 540
 541         /* Only support CPPCv2. Bail otherwise. */
 542         if (num_ent != CPPC_NUM_ENT) {
 543                 pr_debug("Firmware exports %d entries. Expected: %d\n",
 544                                 num_ent, CPPC_NUM_ENT);
 545                 goto out_free;
 546         }
 547
 548         /* Second entry should be revision. */
 549         cpc_obj = &out_obj->package.elements[1];
 550         if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 551                 cpc_rev = cpc_obj->integer.value;
 552         } else {
 553                 pr_debug("Unexpected entry type(%d) for Revision\n",
 554                                 cpc_obj->type);
 555                 goto out_free;
 556         }
 557
 558         if (cpc_rev != CPPC_REV) {
 559                 pr_debug("Firmware exports revision:%d. Expected:%d\n",
 560                                 cpc_rev, CPPC_REV);
 561                 goto out_free;
 562         }
 563
 564         /* Iterate through remaining entries in _CPC */
 565         for (i = 2; i < num_ent; i++) {
 566                 cpc_obj = &out_obj->package.elements[i];
 567
 568                 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 569                         cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
 570                         cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
 571                 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
 572                         gas_t = (struct cpc_reg *)
 573                                 cpc_obj->buffer.pointer;
 574
 575                         /*
 576                          * The PCC Subspace index is encoded inside
 577                          * the CPC table entries. The same PCC index
 578                          * will be used for all the PCC entries,
 579                          * so extract it only once.
 580                          */
 581                         if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
 582                                 if (pcc_subspace_idx < 0)
 583                                         pcc_subspace_idx = gas_t->access_width;
 584                                 else if (pcc_subspace_idx != gas_t->access_width) {
 585                                         pr_debug("Mismatched PCC ids.\n");
 586                                         goto out_free;
 587                                 }
 588                         } else if (gas_t->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) {
 589                                 /* Support only PCC and SYS MEM type regs */
 590                                 pr_debug("Unsupported register type: %d\n", gas_t->space_id);
 591                                 goto out_free;
 592                         }
 593
 594                         cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
 595                         memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
 596                 } else {
 597                         pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id);
 598                         goto out_free;
 599                 }
 600         }
 601         /* Store CPU Logical ID */
 602         cpc_ptr->cpu_id = pr->id;
 603
 604         /* Parse PSD data for this CPU */
 605         ret = acpi_get_psd(cpc_ptr, handle);
 606         if (ret)
 607                 goto out_free;
 608
 609         /* Register PCC channel once for all CPUs. */
 610         if (!pcc_channel_acquired) {
 611                 ret = register_pcc_channel(pcc_subspace_idx);
 612                 if (ret)
 613                         goto out_free;
 614         }
 615
 616         /* Plug PSD data into this CPUs CPC descriptor. */
 617         per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
 618
 619         /* Everything looks okay */
 620         pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
 621
 622         kfree(output.pointer);
 623         return 0;
 624
 625 out_free:
 626         kfree(cpc_ptr);
 627
 628 out_buf_free:
 629         kfree(output.pointer);
 630         return ret;
 631 }
 632 EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
 633
 634 /**
 635  * acpi_cppc_processor_exit - Cleanup CPC structs.
 636  * @pr: Ptr to acpi_processor containing this CPUs logical Id.
 637  *
 638  * Return: Void
 639  */
 640 void acpi_cppc_processor_exit(struct acpi_processor *pr)
 641 {
 642         struct cpc_desc *cpc_ptr;
 643         cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
 644         kfree(cpc_ptr);
 645 }
 646 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
 647
 648 /*
 649  * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
 650  * as fast as possible. We have already mapped the PCC subspace during init, so
 651  * we can directly write to it.
 652  */
 653
 654 static int cpc_read(struct cpc_reg *reg, u64 *val)
 655 {
 656         int ret_val = 0;
 657
 658         *val = 0;
 659         if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
 660                 void __iomem *vaddr = GET_PCC_VADDR(reg->address);
 661
 662                 switch (reg->bit_width) {
 663                 case 8:
 664                         *val = readb_relaxed(vaddr);
 665                         break;
 666                 case 16:
 667                         *val = readw_relaxed(vaddr);
 668                         break;
 669                 case 32:
 670                         *val = readl_relaxed(vaddr);
 671                         break;
 672                 case 64:
 673                         *val = readq_relaxed(vaddr);
 674                         break;
 675                 default:
 676                         pr_debug("Error: Cannot read %u bit width from PCC\n",
 677                                 reg->bit_width);
 678                         ret_val = -EFAULT;
 679                 }
 680         } else
 681                 ret_val = acpi_os_read_memory((acpi_physical_address)reg->address,
 682                                         val, reg->bit_width);
 683         return ret_val;
 684 }
 685
 686 static int cpc_write(struct cpc_reg *reg, u64 val)
 687 {
 688         int ret_val = 0;
 689
 690         if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
 691                 void __iomem *vaddr = GET_PCC_VADDR(reg->address);
 692
 693                 switch (reg->bit_width) {
 694                 case 8:
 695                         writeb_relaxed(val, vaddr);
 696                         break;
 697                 case 16:
 698                         writew_relaxed(val, vaddr);
 699                         break;
 700                 case 32:
 701                         writel_relaxed(val, vaddr);
 702                         break;
 703                 case 64:
 704                         writeq_relaxed(val, vaddr);
 705                         break;
 706                 default:
 707                         pr_debug("Error: Cannot write %u bit width to PCC\n",
 708                                 reg->bit_width);
 709                         ret_val = -EFAULT;
 710                         break;
 711                 }
 712         } else
 713                 ret_val = acpi_os_write_memory((acpi_physical_address)reg->address,
 714                                 val, reg->bit_width);
 715         return ret_val;
 716 }
 717
 718 /**
 719  * cppc_get_perf_caps - Get a CPUs performance capabilities.
 720  * @cpunum: CPU from which to get capabilities info.
 721  * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
 722  *
 723  * Return: 0 for success with perf_caps populated else -ERRNO.
 724  */
 725 int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
 726 {
 727         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
 728         struct cpc_register_resource *highest_reg, *lowest_reg, *ref_perf,
 729                                                                  *nom_perf;
 730         u64 high, low, ref, nom;
 731         int ret = 0;
 732
 733         if (!cpc_desc) {
 734                 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
 735                 return -ENODEV;
 736         }
 737
 738         highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
 739         lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
 740         ref_perf = &cpc_desc->cpc_regs[REFERENCE_PERF];
 741         nom_perf = &cpc_desc->cpc_regs[NOMINAL_PERF];
 742
 743         spin_lock(&pcc_lock);
 744
 745         /* Are any of the regs PCC ?*/
 746         if ((highest_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) ||
 747                         (lowest_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) ||
 748                         (ref_perf->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) ||
 749                         (nom_perf->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM)) {
 750                 /* Ring doorbell once to update PCC subspace */
 751                 if (send_pcc_cmd(CMD_READ) < 0) {
 752                         ret = -EIO;
 753                         goto out_err;
 754                 }
 755         }
 756
 757         cpc_read(&highest_reg->cpc_entry.reg, &high);
 758         perf_caps->highest_perf = high;
 759
 760         cpc_read(&lowest_reg->cpc_entry.reg, &low);
 761         perf_caps->lowest_perf = low;
 762
 763         cpc_read(&ref_perf->cpc_entry.reg, &ref);
 764         perf_caps->reference_perf = ref;
 765
 766         cpc_read(&nom_perf->cpc_entry.reg, &nom);
 767         perf_caps->nominal_perf = nom;
 768
 769         if (!ref)
 770                 perf_caps->reference_perf = perf_caps->nominal_perf;
 771
 772         if (!high || !low || !nom)
 773                 ret = -EFAULT;
 774
 775 out_err:
 776         spin_unlock(&pcc_lock);
 777         return ret;
 778 }
 779 EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
 780
 781 /**
 782  * cppc_get_perf_ctrs - Read a CPUs performance feedback counters.
 783  * @cpunum: CPU from which to read counters.
 784  * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
 785  *
 786  * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
 787  */
 788 int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
 789 {
 790         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
 791         struct cpc_register_resource *delivered_reg, *reference_reg;
 792         u64 delivered, reference;
 793         int ret = 0;
 794
 795         if (!cpc_desc) {
 796                 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
 797                 return -ENODEV;
 798         }
 799
 800         delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
 801         reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
 802
 803         spin_lock(&pcc_lock);
 804
 805         /* Are any of the regs PCC ?*/
 806         if ((delivered_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) ||
 807                         (reference_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM)) {
 808                 /* Ring doorbell once to update PCC subspace */
 809                 if (send_pcc_cmd(CMD_READ) < 0) {
 810                         ret = -EIO;
 811                         goto out_err;
 812                 }
 813         }
 814
 815         cpc_read(&delivered_reg->cpc_entry.reg, &delivered);
 816         cpc_read(&reference_reg->cpc_entry.reg, &reference);
 817
 818         if (!delivered || !reference) {
 819                 ret = -EFAULT;
 820                 goto out_err;
 821         }
 822
 823         perf_fb_ctrs->delivered = delivered;
 824         perf_fb_ctrs->reference = reference;
 825
 826         perf_fb_ctrs->delivered -= perf_fb_ctrs->prev_delivered;
 827         perf_fb_ctrs->reference -= perf_fb_ctrs->prev_reference;
 828
 829         perf_fb_ctrs->prev_delivered = delivered;
 830         perf_fb_ctrs->prev_reference = reference;
 831
 832 out_err:
 833         spin_unlock(&pcc_lock);
 834         return ret;
 835 }
 836 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
 837
 838 /**
 839  * cppc_set_perf - Set a CPUs performance controls.
 840  * @cpu: CPU for which to set performance controls.
 841  * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
 842  *
 843  * Return: 0 for success, -ERRNO otherwise.
 844  */
 845 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 846 {
 847         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
 848         struct cpc_register_resource *desired_reg;
 849         int ret = 0;
 850
 851         if (!cpc_desc) {
 852                 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
 853                 return -ENODEV;
 854         }
 855
 856         desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
 857
 858         spin_lock(&pcc_lock);
 859
 860         /* If this is PCC reg, check if channel is free before writing */
 861         if (desired_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
 862                 ret = check_pcc_chan();
 863                 if (ret)
 864                         goto busy_channel;
 865         }
 866
 867         /*
 868          * Skip writing MIN/MAX until Linux knows how to come up with
 869          * useful values.
 870          */
 871         cpc_write(&desired_reg->cpc_entry.reg, perf_ctrls->desired_perf);
 872
 873         /* Is this a PCC reg ?*/
 874         if (desired_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
 875                 /* Ring doorbell so Remote can get our perf request. */
 876                 if (send_pcc_cmd(CMD_WRITE) < 0)
 877                         ret = -EIO;
 878         }
 879 busy_channel:
 880         spin_unlock(&pcc_lock);
 881
 882         return ret;
 883 }
 884 EXPORT_SYMBOL_GPL(cppc_set_perf);