arch/xtensa/kernel/setup.c

   1 /*
   2  * arch/xtensa/kernel/setup.c
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1995  Linus Torvalds
   9  * Copyright (C) 2001 - 2005  Tensilica Inc.
  10  *
  11  * Chris Zankel <chris@zankel.net>
  12  * Joe Taylor   <joe@tensilica.com, joetylr@yahoo.com>
  13  * Kevin Chea
  14  * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/init.h>
  19 #include <linux/mm.h>
  20 #include <linux/proc_fs.h>
  21 #include <linux/screen_info.h>
  22 #include <linux/bootmem.h>
  23 #include <linux/kernel.h>
  24 #include <linux/percpu.h>
  25 #include <linux/clk-provider.h>
  26 #include <linux/cpu.h>
  27 #include <linux/of.h>
  28 #include <linux/of_fdt.h>
  29
  30 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
  31 # include <linux/console.h>
  32 #endif
  33
  34 #ifdef CONFIG_RTC
  35 # include <linux/timex.h>
  36 #endif
  37
  38 #ifdef CONFIG_PROC_FS
  39 # include <linux/seq_file.h>
  40 #endif
  41
  42 #include <asm/bootparam.h>
  43 #include <asm/mmu_context.h>
  44 #include <asm/pgtable.h>
  45 #include <asm/processor.h>
  46 #include <asm/timex.h>
  47 #include <asm/platform.h>
  48 #include <asm/page.h>
  49 #include <asm/setup.h>
  50 #include <asm/param.h>
  51 #include <asm/traps.h>
  52 #include <asm/smp.h>
  53 #include <asm/sysmem.h>
  54
  55 #include <platform/hardware.h>
  56
  57 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
  58 struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
  59 #endif
  60
  61 #ifdef CONFIG_BLK_DEV_FD
  62 extern struct fd_ops no_fd_ops;
  63 struct fd_ops *fd_ops;
  64 #endif
  65
  66 extern struct rtc_ops no_rtc_ops;
  67 struct rtc_ops *rtc_ops;
  68
  69 #ifdef CONFIG_BLK_DEV_INITRD
  70 extern unsigned long initrd_start;
  71 extern unsigned long initrd_end;
  72 int initrd_is_mapped = 0;
  73 extern int initrd_below_start_ok;
  74 #endif
  75
  76 #ifdef CONFIG_OF
  77 void *dtb_start = __dtb_start;
  78 #endif
  79
  80 unsigned char aux_device_present;
  81 extern unsigned long loops_per_jiffy;
  82
  83 /* Command line specified as configuration option. */
  84
  85 static char __initdata command_line[COMMAND_LINE_SIZE];
  86
  87 #ifdef CONFIG_CMDLINE_BOOL
  88 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
  89 #endif
  90
  91 /*
  92  * Boot parameter parsing.
  93  *
  94  * The Xtensa port uses a list of variable-sized tags to pass data to
  95  * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
  96  * to be recognised. The list is terminated with a zero-sized
  97  * BP_TAG_LAST tag.
  98  */
  99
 100 typedef struct tagtable {
 101         u32 tag;
 102         int (*parse)(const bp_tag_t*);
 103 } tagtable_t;
 104
 105 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn           \
 106         __attribute__((used, section(".taglist"))) = { tag, fn }
 107
 108 /* parse current tag */
 109
 110 static int __init parse_tag_mem(const bp_tag_t *tag)
 111 {
 112         struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
 113
 114         if (mi->type != MEMORY_TYPE_CONVENTIONAL)
 115                 return -1;
 116
 117         return add_sysmem_bank(mi->start, mi->end);
 118 }
 119
 120 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
 121
 122 #ifdef CONFIG_BLK_DEV_INITRD
 123
 124 static int __init parse_tag_initrd(const bp_tag_t* tag)
 125 {
 126         struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
 127
 128         initrd_start = (unsigned long)__va(mi->start);
 129         initrd_end = (unsigned long)__va(mi->end);
 130
 131         return 0;
 132 }
 133
 134 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
 135
 136 #ifdef CONFIG_OF
 137
 138 static int __init parse_tag_fdt(const bp_tag_t *tag)
 139 {
 140         dtb_start = __va(tag->data[0]);
 141         return 0;
 142 }
 143
 144 __tagtable(BP_TAG_FDT, parse_tag_fdt);
 145
 146 #endif /* CONFIG_OF */
 147
 148 #endif /* CONFIG_BLK_DEV_INITRD */
 149
 150 static int __init parse_tag_cmdline(const bp_tag_t* tag)
 151 {
 152         strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
 153         return 0;
 154 }
 155
 156 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
 157
 158 static int __init parse_bootparam(const bp_tag_t* tag)
 159 {
 160         extern tagtable_t __tagtable_begin, __tagtable_end;
 161         tagtable_t *t;
 162
 163         /* Boot parameters must start with a BP_TAG_FIRST tag. */
 164
 165         if (tag->id != BP_TAG_FIRST) {
 166                 printk(KERN_WARNING "Invalid boot parameters!\n");
 167                 return 0;
 168         }
 169
 170         tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
 171
 172         /* Parse all tags. */
 173
 174         while (tag != NULL && tag->id != BP_TAG_LAST) {
 175                 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
 176                         if (tag->id == t->tag) {
 177                                 t->parse(tag);
 178                                 break;
 179                         }
 180                 }
 181                 if (t == &__tagtable_end)
 182                         printk(KERN_WARNING "Ignoring tag "
 183                                "0x%08x\n", tag->id);
 184                 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
 185         }
 186
 187         return 0;
 188 }
 189
 190 #ifdef CONFIG_OF
 191 bool __initdata dt_memory_scan = false;
 192
 193 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
 194 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
 195 EXPORT_SYMBOL(xtensa_kio_paddr);
 196
 197 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
 198                 int depth, void *data)
 199 {
 200         const __be32 *ranges;
 201         int len;
 202
 203         if (depth > 1)
 204                 return 0;
 205
 206         if (!of_flat_dt_is_compatible(node, "simple-bus"))
 207                 return 0;
 208
 209         ranges = of_get_flat_dt_prop(node, "ranges", &len);
 210         if (!ranges)
 211                 return 1;
 212         if (len == 0)
 213                 return 1;
 214
 215         xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
 216         /* round down to nearest 256MB boundary */
 217         xtensa_kio_paddr &= 0xf0000000;
 218
 219         return 1;
 220 }
 221 #else
 222 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
 223                 int depth, void *data)
 224 {
 225         return 1;
 226 }
 227 #endif
 228
 229 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
 230 {
 231         if (!dt_memory_scan)
 232                 return;
 233
 234         size &= PAGE_MASK;
 235         add_sysmem_bank(base, base + size);
 236 }
 237
 238 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
 239 {
 240         return __alloc_bootmem(size, align, 0);
 241 }
 242
 243 void __init early_init_devtree(void *params)
 244 {
 245         if (sysmem.nr_banks == 0)
 246                 dt_memory_scan = true;
 247
 248         early_init_dt_scan(params);
 249         of_scan_flat_dt(xtensa_dt_io_area, NULL);
 250
 251         if (!command_line[0])
 252                 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
 253 }
 254
 255 static int __init xtensa_device_probe(void)
 256 {
 257         of_clk_init(NULL);
 258         return 0;
 259 }
 260
 261 device_initcall(xtensa_device_probe);
 262
 263 #endif /* CONFIG_OF */
 264
 265 /*
 266  * Initialize architecture. (Early stage)
 267  */
 268
 269 void __init init_arch(bp_tag_t *bp_start)
 270 {
 271         /* Parse boot parameters */
 272
 273         if (bp_start)
 274                 parse_bootparam(bp_start);
 275
 276 #ifdef CONFIG_OF
 277         early_init_devtree(dtb_start);
 278 #endif
 279
 280         if (sysmem.nr_banks == 0) {
 281                 add_sysmem_bank(PLATFORM_DEFAULT_MEM_START,
 282                                 PLATFORM_DEFAULT_MEM_START +
 283                                 PLATFORM_DEFAULT_MEM_SIZE);
 284         }
 285
 286 #ifdef CONFIG_CMDLINE_BOOL
 287         if (!command_line[0])
 288                 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
 289 #endif
 290
 291         /* Early hook for platforms */
 292
 293         platform_init(bp_start);
 294
 295         /* Initialize MMU. */
 296
 297         init_mmu();
 298 }
 299
 300 /*
 301  * Initialize system. Setup memory and reserve regions.
 302  */
 303
 304 extern char _end;
 305 extern char _stext;
 306 extern char _WindowVectors_text_start;
 307 extern char _WindowVectors_text_end;
 308 extern char _DebugInterruptVector_literal_start;
 309 extern char _DebugInterruptVector_text_end;
 310 extern char _KernelExceptionVector_literal_start;
 311 extern char _KernelExceptionVector_text_end;
 312 extern char _UserExceptionVector_literal_start;
 313 extern char _UserExceptionVector_text_end;
 314 extern char _DoubleExceptionVector_literal_start;
 315 extern char _DoubleExceptionVector_text_end;
 316 #if XCHAL_EXCM_LEVEL >= 2
 317 extern char _Level2InterruptVector_text_start;
 318 extern char _Level2InterruptVector_text_end;
 319 #endif
 320 #if XCHAL_EXCM_LEVEL >= 3
 321 extern char _Level3InterruptVector_text_start;
 322 extern char _Level3InterruptVector_text_end;
 323 #endif
 324 #if XCHAL_EXCM_LEVEL >= 4
 325 extern char _Level4InterruptVector_text_start;
 326 extern char _Level4InterruptVector_text_end;
 327 #endif
 328 #if XCHAL_EXCM_LEVEL >= 5
 329 extern char _Level5InterruptVector_text_start;
 330 extern char _Level5InterruptVector_text_end;
 331 #endif
 332 #if XCHAL_EXCM_LEVEL >= 6
 333 extern char _Level6InterruptVector_text_start;
 334 extern char _Level6InterruptVector_text_end;
 335 #endif
 336 #ifdef CONFIG_SMP
 337 extern char _SecondaryResetVector_text_start;
 338 extern char _SecondaryResetVector_text_end;
 339 #endif
 340
 341
 342 #ifdef CONFIG_S32C1I_SELFTEST
 343 #if XCHAL_HAVE_S32C1I
 344
 345 static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
 346
 347 /*
 348  * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
 349  *
 350  * If *v == cmp, set *v = set.  Return previous *v.
 351  */
 352 static inline int probed_compare_swap(int *v, int cmp, int set)
 353 {
 354         int tmp;
 355
 356         __asm__ __volatile__(
 357                         "       movi    %1, 1f\n"
 358                         "       s32i    %1, %4, 0\n"
 359                         "       wsr     %2, scompare1\n"
 360                         "1:     s32c1i  %0, %3, 0\n"
 361                         : "=a" (set), "=&a" (tmp)
 362                         : "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
 363                         : "memory"
 364                         );
 365         return set;
 366 }
 367
 368 /* Handle probed exception */
 369
 370 static void __init do_probed_exception(struct pt_regs *regs,
 371                 unsigned long exccause)
 372 {
 373         if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */
 374                 regs->pc += 3;          /* skip the s32c1i instruction */
 375                 rcw_exc = exccause;
 376         } else {
 377                 do_unhandled(regs, exccause);
 378         }
 379 }
 380
 381 /* Simple test of S32C1I (soc bringup assist) */
 382
 383 static int __init check_s32c1i(void)
 384 {
 385         int n, cause1, cause2;
 386         void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
 387
 388         rcw_probe_pc = 0;
 389         handbus  = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
 390                         do_probed_exception);
 391         handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
 392                         do_probed_exception);
 393         handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
 394                         do_probed_exception);
 395
 396         /* First try an S32C1I that does not store: */
 397         rcw_exc = 0;
 398         rcw_word = 1;
 399         n = probed_compare_swap(&rcw_word, 0, 2);
 400         cause1 = rcw_exc;
 401
 402         /* took exception? */
 403         if (cause1 != 0) {
 404                 /* unclean exception? */
 405                 if (n != 2 || rcw_word != 1)
 406                         panic("S32C1I exception error");
 407         } else if (rcw_word != 1 || n != 1) {
 408                 panic("S32C1I compare error");
 409         }
 410
 411         /* Then an S32C1I that stores: */
 412         rcw_exc = 0;
 413         rcw_word = 0x1234567;
 414         n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
 415         cause2 = rcw_exc;
 416
 417         if (cause2 != 0) {
 418                 /* unclean exception? */
 419                 if (n != 0xabcde || rcw_word != 0x1234567)
 420                         panic("S32C1I exception error (b)");
 421         } else if (rcw_word != 0xabcde || n != 0x1234567) {
 422                 panic("S32C1I store error");
 423         }
 424
 425         /* Verify consistency of exceptions: */
 426         if (cause1 || cause2) {
 427                 pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
 428                 /* If emulation of S32C1I upon bus error gets implemented,
 429                    we can get rid of this panic for single core (not SMP) */
 430                 panic("S32C1I exceptions not currently supported");
 431         }
 432         if (cause1 != cause2)
 433                 panic("inconsistent S32C1I exceptions");
 434
 435         trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
 436         trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
 437         trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
 438         return 0;
 439 }
 440
 441 #else /* XCHAL_HAVE_S32C1I */
 442
 443 /* This condition should not occur with a commercially deployed processor.
 444    Display reminder for early engr test or demo chips / FPGA bitstreams */
 445 static int __init check_s32c1i(void)
 446 {
 447         pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
 448         return 0;
 449 }
 450
 451 #endif /* XCHAL_HAVE_S32C1I */
 452 early_initcall(check_s32c1i);
 453 #endif /* CONFIG_S32C1I_SELFTEST */
 454
 455
 456 void __init setup_arch(char **cmdline_p)
 457 {
 458         strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
 459         *cmdline_p = command_line;
 460
 461         /* Reserve some memory regions */
 462
 463 #ifdef CONFIG_BLK_DEV_INITRD
 464         if (initrd_start < initrd_end) {
 465                 initrd_is_mapped = mem_reserve(__pa(initrd_start),
 466                                                __pa(initrd_end), 0) == 0;
 467                 initrd_below_start_ok = 1;
 468         } else {
 469                 initrd_start = 0;
 470         }
 471 #endif
 472
 473         mem_reserve(__pa(&_stext),__pa(&_end), 1);
 474
 475         mem_reserve(__pa(&_WindowVectors_text_start),
 476                     __pa(&_WindowVectors_text_end), 0);
 477
 478         mem_reserve(__pa(&_DebugInterruptVector_literal_start),
 479                     __pa(&_DebugInterruptVector_text_end), 0);
 480
 481         mem_reserve(__pa(&_KernelExceptionVector_literal_start),
 482                     __pa(&_KernelExceptionVector_text_end), 0);
 483
 484         mem_reserve(__pa(&_UserExceptionVector_literal_start),
 485                     __pa(&_UserExceptionVector_text_end), 0);
 486
 487         mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
 488                     __pa(&_DoubleExceptionVector_text_end), 0);
 489
 490 #if XCHAL_EXCM_LEVEL >= 2
 491         mem_reserve(__pa(&_Level2InterruptVector_text_start),
 492                     __pa(&_Level2InterruptVector_text_end), 0);
 493 #endif
 494 #if XCHAL_EXCM_LEVEL >= 3
 495         mem_reserve(__pa(&_Level3InterruptVector_text_start),
 496                     __pa(&_Level3InterruptVector_text_end), 0);
 497 #endif
 498 #if XCHAL_EXCM_LEVEL >= 4
 499         mem_reserve(__pa(&_Level4InterruptVector_text_start),
 500                     __pa(&_Level4InterruptVector_text_end), 0);
 501 #endif
 502 #if XCHAL_EXCM_LEVEL >= 5
 503         mem_reserve(__pa(&_Level5InterruptVector_text_start),
 504                     __pa(&_Level5InterruptVector_text_end), 0);
 505 #endif
 506 #if XCHAL_EXCM_LEVEL >= 6
 507         mem_reserve(__pa(&_Level6InterruptVector_text_start),
 508                     __pa(&_Level6InterruptVector_text_end), 0);
 509 #endif
 510
 511 #ifdef CONFIG_SMP
 512         mem_reserve(__pa(&_SecondaryResetVector_text_start),
 513                     __pa(&_SecondaryResetVector_text_end), 0);
 514 #endif
 515         parse_early_param();
 516         bootmem_init();
 517
 518         unflatten_and_copy_device_tree();
 519
 520         platform_setup(cmdline_p);
 521
 522 #ifdef CONFIG_SMP
 523         smp_init_cpus();
 524 #endif
 525
 526         paging_init();
 527         zones_init();
 528
 529 #ifdef CONFIG_VT
 530 # if defined(CONFIG_VGA_CONSOLE)
 531         conswitchp = &vga_con;
 532 # elif defined(CONFIG_DUMMY_CONSOLE)
 533         conswitchp = &dummy_con;
 534 # endif
 535 #endif
 536
 537 #ifdef CONFIG_PCI
 538         platform_pcibios_init();
 539 #endif
 540 }
 541
 542 static DEFINE_PER_CPU(struct cpu, cpu_data);
 543
 544 static int __init topology_init(void)
 545 {
 546         int i;
 547
 548         for_each_possible_cpu(i) {
 549                 struct cpu *cpu = &per_cpu(cpu_data, i);
 550                 cpu->hotpluggable = !!i;
 551                 register_cpu(cpu, i);
 552         }
 553
 554         return 0;
 555 }
 556 subsys_initcall(topology_init);
 557
 558 void machine_restart(char * cmd)
 559 {
 560         platform_restart();
 561 }
 562
 563 void machine_halt(void)
 564 {
 565         platform_halt();
 566         while (1);
 567 }
 568
 569 void machine_power_off(void)
 570 {
 571         platform_power_off();
 572         while (1);
 573 }
 574 #ifdef CONFIG_PROC_FS
 575
 576 /*
 577  * Display some core information through /proc/cpuinfo.
 578  */
 579
 580 static int
 581 c_show(struct seq_file *f, void *slot)
 582 {
 583         /* high-level stuff */
 584         seq_printf(f, "CPU count\t: %u\n"
 585                       "CPU list\t: %*pbl\n"
 586                       "vendor_id\t: Tensilica\n"
 587                       "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
 588                       "core ID\t\t: " XCHAL_CORE_ID "\n"
 589                       "build ID\t: 0x%x\n"
 590                       "byte order\t: %s\n"
 591                       "cpu MHz\t\t: %lu.%02lu\n"
 592                       "bogomips\t: %lu.%02lu\n",
 593                       num_online_cpus(),
 594                       cpumask_pr_args(cpu_online_mask),
 595                       XCHAL_BUILD_UNIQUE_ID,
 596                       XCHAL_HAVE_BE ?  "big" : "little",
 597                       ccount_freq/1000000,
 598                       (ccount_freq/10000) % 100,
 599                       loops_per_jiffy/(500000/HZ),
 600                       (loops_per_jiffy/(5000/HZ)) % 100);
 601
 602         seq_printf(f,"flags\t\t: "
 603 #if XCHAL_HAVE_NMI
 604                      "nmi "
 605 #endif
 606 #if XCHAL_HAVE_DEBUG
 607                      "debug "
 608 # if XCHAL_HAVE_OCD
 609                      "ocd "
 610 # endif
 611 #endif
 612 #if XCHAL_HAVE_DENSITY
 613                      "density "
 614 #endif
 615 #if XCHAL_HAVE_BOOLEANS
 616                      "boolean "
 617 #endif
 618 #if XCHAL_HAVE_LOOPS
 619                      "loop "
 620 #endif
 621 #if XCHAL_HAVE_NSA
 622                      "nsa "
 623 #endif
 624 #if XCHAL_HAVE_MINMAX
 625                      "minmax "
 626 #endif
 627 #if XCHAL_HAVE_SEXT
 628                      "sext "
 629 #endif
 630 #if XCHAL_HAVE_CLAMPS
 631                      "clamps "
 632 #endif
 633 #if XCHAL_HAVE_MAC16
 634                      "mac16 "
 635 #endif
 636 #if XCHAL_HAVE_MUL16
 637                      "mul16 "
 638 #endif
 639 #if XCHAL_HAVE_MUL32
 640                      "mul32 "
 641 #endif
 642 #if XCHAL_HAVE_MUL32_HIGH
 643                      "mul32h "
 644 #endif
 645 #if XCHAL_HAVE_FP
 646                      "fpu "
 647 #endif
 648 #if XCHAL_HAVE_S32C1I
 649                      "s32c1i "
 650 #endif
 651                      "\n");
 652
 653         /* Registers. */
 654         seq_printf(f,"physical aregs\t: %d\n"
 655                      "misc regs\t: %d\n"
 656                      "ibreak\t\t: %d\n"
 657                      "dbreak\t\t: %d\n",
 658                      XCHAL_NUM_AREGS,
 659                      XCHAL_NUM_MISC_REGS,
 660                      XCHAL_NUM_IBREAK,
 661                      XCHAL_NUM_DBREAK);
 662
 663
 664         /* Interrupt. */
 665         seq_printf(f,"num ints\t: %d\n"
 666                      "ext ints\t: %d\n"
 667                      "int levels\t: %d\n"
 668                      "timers\t\t: %d\n"
 669                      "debug level\t: %d\n",
 670                      XCHAL_NUM_INTERRUPTS,
 671                      XCHAL_NUM_EXTINTERRUPTS,
 672                      XCHAL_NUM_INTLEVELS,
 673                      XCHAL_NUM_TIMERS,
 674                      XCHAL_DEBUGLEVEL);
 675
 676         /* Cache */
 677         seq_printf(f,"icache line size: %d\n"
 678                      "icache ways\t: %d\n"
 679                      "icache size\t: %d\n"
 680                      "icache flags\t: "
 681 #if XCHAL_ICACHE_LINE_LOCKABLE
 682                      "lock "
 683 #endif
 684                      "\n"
 685                      "dcache line size: %d\n"
 686                      "dcache ways\t: %d\n"
 687                      "dcache size\t: %d\n"
 688                      "dcache flags\t: "
 689 #if XCHAL_DCACHE_IS_WRITEBACK
 690                      "writeback "
 691 #endif
 692 #if XCHAL_DCACHE_LINE_LOCKABLE
 693                      "lock "
 694 #endif
 695                      "\n",
 696                      XCHAL_ICACHE_LINESIZE,
 697                      XCHAL_ICACHE_WAYS,
 698                      XCHAL_ICACHE_SIZE,
 699                      XCHAL_DCACHE_LINESIZE,
 700                      XCHAL_DCACHE_WAYS,
 701                      XCHAL_DCACHE_SIZE);
 702
 703         return 0;
 704 }
 705
 706 /*
 707  * We show only CPU #0 info.
 708  */
 709 static void *
 710 c_start(struct seq_file *f, loff_t *pos)
 711 {
 712         return (*pos == 0) ? (void *)1 : NULL;
 713 }
 714
 715 static void *
 716 c_next(struct seq_file *f, void *v, loff_t *pos)
 717 {
 718         return NULL;
 719 }
 720
 721 static void
 722 c_stop(struct seq_file *f, void *v)
 723 {
 724 }
 725
 726 const struct seq_operations cpuinfo_op =
 727 {
 728         .start  = c_start,
 729         .next   = c_next,
 730         .stop   = c_stop,
 731         .show   = c_show,
 732 };
 733
 734 #endif /* CONFIG_PROC_FS */