arch/x86_64/kernel/nmi.c

   1 /*
   2  *  linux/arch/x86_64/nmi.c
   3  *
   4  *  NMI watchdog support on APIC systems
   5  *
   6  *  Started by Ingo Molnar <mingo@redhat.com>
   7  *
   8  *  Fixes:
   9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
  10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
  11  *  Pavel Machek and
  12  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  13  */
  14
  15 #include <linux/nmi.h>
  16 #include <linux/mm.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/sysctl.h>
  22 #include <linux/kprobes.h>
  23 #include <linux/cpumask.h>
  24
  25 #include <asm/smp.h>
  26 #include <asm/nmi.h>
  27 #include <asm/proto.h>
  28 #include <asm/kdebug.h>
  29 #include <asm/mce.h>
  30 #include <asm/intel_arch_perfmon.h>
  31
  32 int unknown_nmi_panic;
  33 int nmi_watchdog_enabled;
  34 int panic_on_unrecovered_nmi;
  35
  36 /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
  37  * evtsel_nmi_owner tracks the ownership of the event selection
  38  * - different performance counters/ event selection may be reserved for
  39  *   different subsystems this reservation system just tries to coordinate
  40  *   things a little
  41  */
  42 static DEFINE_PER_CPU(unsigned, perfctr_nmi_owner);
  43 static DEFINE_PER_CPU(unsigned, evntsel_nmi_owner[2]);
  44
  45 static cpumask_t backtrace_mask = CPU_MASK_NONE;
  46
  47 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
  48  * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
  49  */
  50 #define NMI_MAX_COUNTER_BITS 66
  51
  52 /* nmi_active:
  53  * >0: the lapic NMI watchdog is active, but can be disabled
  54  * <0: the lapic NMI watchdog has not been set up, and cannot
  55  *     be enabled
  56  *  0: the lapic NMI watchdog is disabled, but can be enabled
  57  */
  58 atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
  59 int panic_on_timeout;
  60
  61 unsigned int nmi_watchdog = NMI_DEFAULT;
  62 static unsigned int nmi_hz = HZ;
  63
  64 struct nmi_watchdog_ctlblk {
  65         int enabled;
  66         u64 check_bit;
  67         unsigned int cccr_msr;
  68         unsigned int perfctr_msr;  /* the MSR to reset in NMI handler */
  69         unsigned int evntsel_msr;  /* the MSR to select the events to handle */
  70 };
  71 static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
  72
  73 /* local prototypes */
  74 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu);
  75
  76 /* converts an msr to an appropriate reservation bit */
  77 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
  78 {
  79         /* returns the bit offset of the performance counter register */
  80         switch (boot_cpu_data.x86_vendor) {
  81         case X86_VENDOR_AMD:
  82                 return (msr - MSR_K7_PERFCTR0);
  83         case X86_VENDOR_INTEL:
  84                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
  85                         return (msr - MSR_ARCH_PERFMON_PERFCTR0);
  86                 else
  87                         return (msr - MSR_P4_BPU_PERFCTR0);
  88         }
  89         return 0;
  90 }
  91
  92 /* converts an msr to an appropriate reservation bit */
  93 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
  94 {
  95         /* returns the bit offset of the event selection register */
  96         switch (boot_cpu_data.x86_vendor) {
  97         case X86_VENDOR_AMD:
  98                 return (msr - MSR_K7_EVNTSEL0);
  99         case X86_VENDOR_INTEL:
 100                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 101                         return (msr - MSR_ARCH_PERFMON_EVENTSEL0);
 102                 else
 103                         return (msr - MSR_P4_BSU_ESCR0);
 104         }
 105         return 0;
 106 }
 107
 108 /* checks for a bit availability (hack for oprofile) */
 109 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
 110 {
 111         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 112
 113         return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
 114 }
 115
 116 /* checks the an msr for availability */
 117 int avail_to_resrv_perfctr_nmi(unsigned int msr)
 118 {
 119         unsigned int counter;
 120
 121         counter = nmi_perfctr_msr_to_bit(msr);
 122         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 123
 124         return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
 125 }
 126
 127 int reserve_perfctr_nmi(unsigned int msr)
 128 {
 129         unsigned int counter;
 130
 131         counter = nmi_perfctr_msr_to_bit(msr);
 132         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 133
 134         if (!test_and_set_bit(counter, &__get_cpu_var(perfctr_nmi_owner)))
 135                 return 1;
 136         return 0;
 137 }
 138
 139 void release_perfctr_nmi(unsigned int msr)
 140 {
 141         unsigned int counter;
 142
 143         counter = nmi_perfctr_msr_to_bit(msr);
 144         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 145
 146         clear_bit(counter, &__get_cpu_var(perfctr_nmi_owner));
 147 }
 148
 149 int reserve_evntsel_nmi(unsigned int msr)
 150 {
 151         unsigned int counter;
 152
 153         counter = nmi_evntsel_msr_to_bit(msr);
 154         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 155
 156         if (!test_and_set_bit(counter, &__get_cpu_var(evntsel_nmi_owner)))
 157                 return 1;
 158         return 0;
 159 }
 160
 161 void release_evntsel_nmi(unsigned int msr)
 162 {
 163         unsigned int counter;
 164
 165         counter = nmi_evntsel_msr_to_bit(msr);
 166         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 167
 168         clear_bit(counter, &__get_cpu_var(evntsel_nmi_owner));
 169 }
 170
 171 static __cpuinit inline int nmi_known_cpu(void)
 172 {
 173         switch (boot_cpu_data.x86_vendor) {
 174         case X86_VENDOR_AMD:
 175                 return boot_cpu_data.x86 == 15 || boot_cpu_data.x86 == 16;
 176         case X86_VENDOR_INTEL:
 177                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 178                         return 1;
 179                 else
 180                         return (boot_cpu_data.x86 == 15);
 181         }
 182         return 0;
 183 }
 184
 185 /* Run after command line and cpu_init init, but before all other checks */
 186 void nmi_watchdog_default(void)
 187 {
 188         if (nmi_watchdog != NMI_DEFAULT)
 189                 return;
 190         if (nmi_known_cpu())
 191                 nmi_watchdog = NMI_LOCAL_APIC;
 192         else
 193                 nmi_watchdog = NMI_IO_APIC;
 194 }
 195
 196 static int endflag __initdata = 0;
 197
 198 #ifdef CONFIG_SMP
 199 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
 200  * the CPU is idle. To make sure the NMI watchdog really ticks on all
 201  * CPUs during the test make them busy.
 202  */
 203 static __init void nmi_cpu_busy(void *data)
 204 {
 205         local_irq_enable_in_hardirq();
 206         /* Intentionally don't use cpu_relax here. This is
 207            to make sure that the performance counter really ticks,
 208            even if there is a simulator or similar that catches the
 209            pause instruction. On a real HT machine this is fine because
 210            all other CPUs are busy with "useless" delay loops and don't
 211            care if they get somewhat less cycles. */
 212         while (endflag == 0)
 213                 mb();
 214 }
 215 #endif
 216
 217 static unsigned int adjust_for_32bit_ctr(unsigned int hz)
 218 {
 219         unsigned int retval = hz;
 220
 221         /*
 222          * On Intel CPUs with ARCH_PERFMON only 32 bits in the counter
 223          * are writable, with higher bits sign extending from bit 31.
 224          * So, we can only program the counter with 31 bit values and
 225          * 32nd bit should be 1, for 33.. to be 1.
 226          * Find the appropriate nmi_hz
 227          */
 228         if ((((u64)cpu_khz * 1000) / retval) > 0x7fffffffULL) {
 229                 retval = ((u64)cpu_khz * 1000) / 0x7fffffffUL + 1;
 230         }
 231         return retval;
 232 }
 233
 234 int __init check_nmi_watchdog (void)
 235 {
 236         int *counts;
 237         int cpu;
 238
 239         if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DEFAULT))
 240                 return 0;
 241
 242         if (!atomic_read(&nmi_active))
 243                 return 0;
 244
 245         counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
 246         if (!counts)
 247                 return -1;
 248
 249         printk(KERN_INFO "testing NMI watchdog ... ");
 250
 251 #ifdef CONFIG_SMP
 252         if (nmi_watchdog == NMI_LOCAL_APIC)
 253                 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
 254 #endif
 255
 256         for (cpu = 0; cpu < NR_CPUS; cpu++)
 257                 counts[cpu] = cpu_pda(cpu)->__nmi_count;
 258         local_irq_enable();
 259         mdelay((10*1000)/nmi_hz); // wait 10 ticks
 260
 261         for_each_online_cpu(cpu) {
 262                 if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
 263                         continue;
 264                 if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) {
 265                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
 266                                cpu,
 267                                counts[cpu],
 268                                cpu_pda(cpu)->__nmi_count);
 269                         per_cpu(nmi_watchdog_ctlblk, cpu).enabled = 0;
 270                         atomic_dec(&nmi_active);
 271                 }
 272         }
 273         if (!atomic_read(&nmi_active)) {
 274                 kfree(counts);
 275                 atomic_set(&nmi_active, -1);
 276                 endflag = 1;
 277                 return -1;
 278         }
 279         endflag = 1;
 280         printk("OK.\n");
 281
 282         /* now that we know it works we can reduce NMI frequency to
 283            something more reasonable; makes a difference in some configs */
 284         if (nmi_watchdog == NMI_LOCAL_APIC) {
 285                 struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 286
 287                 nmi_hz = 1;
 288                 if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0)
 289                         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 290         }
 291
 292         kfree(counts);
 293         return 0;
 294 }
 295
 296 int __init setup_nmi_watchdog(char *str)
 297 {
 298         int nmi;
 299
 300         if (!strncmp(str,"panic",5)) {
 301                 panic_on_timeout = 1;
 302                 str = strchr(str, ',');
 303                 if (!str)
 304                         return 1;
 305                 ++str;
 306         }
 307
 308         get_option(&str, &nmi);
 309
 310         if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
 311                 return 0;
 312
 313         nmi_watchdog = nmi;
 314         return 1;
 315 }
 316
 317 __setup("nmi_watchdog=", setup_nmi_watchdog);
 318
 319 static void disable_lapic_nmi_watchdog(void)
 320 {
 321         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 322
 323         if (atomic_read(&nmi_active) <= 0)
 324                 return;
 325
 326         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 327
 328         BUG_ON(atomic_read(&nmi_active) != 0);
 329 }
 330
 331 static void enable_lapic_nmi_watchdog(void)
 332 {
 333         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 334
 335         /* are we already enabled */
 336         if (atomic_read(&nmi_active) != 0)
 337                 return;
 338
 339         /* are we lapic aware */
 340         if (nmi_known_cpu() <= 0)
 341                 return;
 342
 343         on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 344         touch_nmi_watchdog();
 345 }
 346
 347 void disable_timer_nmi_watchdog(void)
 348 {
 349         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 350
 351         if (atomic_read(&nmi_active) <= 0)
 352                 return;
 353
 354         disable_irq(0);
 355         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 356
 357         BUG_ON(atomic_read(&nmi_active) != 0);
 358 }
 359
 360 void enable_timer_nmi_watchdog(void)
 361 {
 362         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 363
 364         if (atomic_read(&nmi_active) == 0) {
 365                 touch_nmi_watchdog();
 366                 on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 367                 enable_irq(0);
 368         }
 369 }
 370
 371 static void __acpi_nmi_disable(void *__unused)
 372 {
 373         apic_write(APIC_LVT0, APIC_DM_NMI | APIC_LVT_MASKED);
 374 }
 375
 376 /*
 377  * Disable timer based NMIs on all CPUs:
 378  */
 379 void acpi_nmi_disable(void)
 380 {
 381         if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
 382                 on_each_cpu(__acpi_nmi_disable, NULL, 0, 1);
 383 }
 384
 385 static void __acpi_nmi_enable(void *__unused)
 386 {
 387         apic_write(APIC_LVT0, APIC_DM_NMI);
 388 }
 389
 390 /*
 391  * Enable timer based NMIs on all CPUs:
 392  */
 393 void acpi_nmi_enable(void)
 394 {
 395         if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
 396                 on_each_cpu(__acpi_nmi_enable, NULL, 0, 1);
 397 }
 398 #ifdef CONFIG_PM
 399
 400 static int nmi_pm_active; /* nmi_active before suspend */
 401
 402 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
 403 {
 404         /* only CPU0 goes here, other CPUs should be offline */
 405         nmi_pm_active = atomic_read(&nmi_active);
 406         stop_apic_nmi_watchdog(NULL);
 407         BUG_ON(atomic_read(&nmi_active) != 0);
 408         return 0;
 409 }
 410
 411 static int lapic_nmi_resume(struct sys_device *dev)
 412 {
 413         /* only CPU0 goes here, other CPUs should be offline */
 414         if (nmi_pm_active > 0) {
 415                 setup_apic_nmi_watchdog(NULL);
 416                 touch_nmi_watchdog();
 417         }
 418         return 0;
 419 }
 420
 421 static struct sysdev_class nmi_sysclass = {
 422         set_kset_name("lapic_nmi"),
 423         .resume         = lapic_nmi_resume,
 424         .suspend        = lapic_nmi_suspend,
 425 };
 426
 427 static struct sys_device device_lapic_nmi = {
 428         .id             = 0,
 429         .cls    = &nmi_sysclass,
 430 };
 431
 432 static int __init init_lapic_nmi_sysfs(void)
 433 {
 434         int error;
 435
 436         /* should really be a BUG_ON but b/c this is an
 437          * init call, it just doesn't work.  -dcz
 438          */
 439         if (nmi_watchdog != NMI_LOCAL_APIC)
 440                 return 0;
 441
 442         if ( atomic_read(&nmi_active) < 0 )
 443                 return 0;
 444
 445         error = sysdev_class_register(&nmi_sysclass);
 446         if (!error)
 447                 error = sysdev_register(&device_lapic_nmi);
 448         return error;
 449 }
 450 /* must come after the local APIC's device_initcall() */
 451 late_initcall(init_lapic_nmi_sysfs);
 452
 453 #endif  /* CONFIG_PM */
 454
 455 /*
 456  * Activate the NMI watchdog via the local APIC.
 457  * Original code written by Keith Owens.
 458  */
 459
 460 /* Note that these events don't tick when the CPU idles. This means
 461    the frequency varies with CPU load. */
 462
 463 #define K7_EVNTSEL_ENABLE       (1 << 22)
 464 #define K7_EVNTSEL_INT          (1 << 20)
 465 #define K7_EVNTSEL_OS           (1 << 17)
 466 #define K7_EVNTSEL_USR          (1 << 16)
 467 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
 468 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
 469
 470 static int setup_k7_watchdog(void)
 471 {
 472         unsigned int perfctr_msr, evntsel_msr;
 473         unsigned int evntsel;
 474         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 475
 476         perfctr_msr = MSR_K7_PERFCTR0;
 477         evntsel_msr = MSR_K7_EVNTSEL0;
 478         if (!reserve_perfctr_nmi(perfctr_msr))
 479                 goto fail;
 480
 481         if (!reserve_evntsel_nmi(evntsel_msr))
 482                 goto fail1;
 483
 484         /* Simulator may not support it */
 485         if (checking_wrmsrl(evntsel_msr, 0UL))
 486                 goto fail2;
 487         wrmsrl(perfctr_msr, 0UL);
 488
 489         evntsel = K7_EVNTSEL_INT
 490                 | K7_EVNTSEL_OS
 491                 | K7_EVNTSEL_USR
 492                 | K7_NMI_EVENT;
 493
 494         /* setup the timer */
 495         wrmsr(evntsel_msr, evntsel, 0);
 496         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
 497         apic_write(APIC_LVTPC, APIC_DM_NMI);
 498         evntsel |= K7_EVNTSEL_ENABLE;
 499         wrmsr(evntsel_msr, evntsel, 0);
 500
 501         wd->perfctr_msr = perfctr_msr;
 502         wd->evntsel_msr = evntsel_msr;
 503         wd->cccr_msr = 0;  //unused
 504         wd->check_bit = 1ULL<<63;
 505         return 1;
 506 fail2:
 507         release_evntsel_nmi(evntsel_msr);
 508 fail1:
 509         release_perfctr_nmi(perfctr_msr);
 510 fail:
 511         return 0;
 512 }
 513
 514 static void stop_k7_watchdog(void)
 515 {
 516         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 517
 518         wrmsr(wd->evntsel_msr, 0, 0);
 519
 520         release_evntsel_nmi(wd->evntsel_msr);
 521         release_perfctr_nmi(wd->perfctr_msr);
 522 }
 523
 524 /* Note that these events don't tick when the CPU idles. This means
 525    the frequency varies with CPU load. */
 526
 527 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
 528 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
 529 #define P4_ESCR_OS              (1<<3)
 530 #define P4_ESCR_USR             (1<<2)
 531 #define P4_CCCR_OVF_PMI0        (1<<26)
 532 #define P4_CCCR_OVF_PMI1        (1<<27)
 533 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
 534 #define P4_CCCR_COMPLEMENT      (1<<19)
 535 #define P4_CCCR_COMPARE         (1<<18)
 536 #define P4_CCCR_REQUIRED        (3<<16)
 537 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
 538 #define P4_CCCR_ENABLE          (1<<12)
 539 #define P4_CCCR_OVF             (1<<31)
 540 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
 541    CRU_ESCR0 (with any non-null event selector) through a complemented
 542    max threshold. [IA32-Vol3, Section 14.9.9] */
 543
 544 static int setup_p4_watchdog(void)
 545 {
 546         unsigned int perfctr_msr, evntsel_msr, cccr_msr;
 547         unsigned int evntsel, cccr_val;
 548         unsigned int misc_enable, dummy;
 549         unsigned int ht_num;
 550         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 551
 552         rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
 553         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 554                 return 0;
 555
 556 #ifdef CONFIG_SMP
 557         /* detect which hyperthread we are on */
 558         if (smp_num_siblings == 2) {
 559                 unsigned int ebx, apicid;
 560
 561                 ebx = cpuid_ebx(1);
 562                 apicid = (ebx >> 24) & 0xff;
 563                 ht_num = apicid & 1;
 564         } else
 565 #endif
 566                 ht_num = 0;
 567
 568         /* performance counters are shared resources
 569          * assign each hyperthread its own set
 570          * (re-use the ESCR0 register, seems safe
 571          * and keeps the cccr_val the same)
 572          */
 573         if (!ht_num) {
 574                 /* logical cpu 0 */
 575                 perfctr_msr = MSR_P4_IQ_PERFCTR0;
 576                 evntsel_msr = MSR_P4_CRU_ESCR0;
 577                 cccr_msr = MSR_P4_IQ_CCCR0;
 578                 cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
 579         } else {
 580                 /* logical cpu 1 */
 581                 perfctr_msr = MSR_P4_IQ_PERFCTR1;
 582                 evntsel_msr = MSR_P4_CRU_ESCR0;
 583                 cccr_msr = MSR_P4_IQ_CCCR1;
 584                 cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
 585         }
 586
 587         if (!reserve_perfctr_nmi(perfctr_msr))
 588                 goto fail;
 589
 590         if (!reserve_evntsel_nmi(evntsel_msr))
 591                 goto fail1;
 592
 593         evntsel = P4_ESCR_EVENT_SELECT(0x3F)
 594                 | P4_ESCR_OS
 595                 | P4_ESCR_USR;
 596
 597         cccr_val |= P4_CCCR_THRESHOLD(15)
 598                  | P4_CCCR_COMPLEMENT
 599                  | P4_CCCR_COMPARE
 600                  | P4_CCCR_REQUIRED;
 601
 602         wrmsr(evntsel_msr, evntsel, 0);
 603         wrmsr(cccr_msr, cccr_val, 0);
 604         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
 605         apic_write(APIC_LVTPC, APIC_DM_NMI);
 606         cccr_val |= P4_CCCR_ENABLE;
 607         wrmsr(cccr_msr, cccr_val, 0);
 608
 609         wd->perfctr_msr = perfctr_msr;
 610         wd->evntsel_msr = evntsel_msr;
 611         wd->cccr_msr = cccr_msr;
 612         wd->check_bit = 1ULL<<39;
 613         return 1;
 614 fail1:
 615         release_perfctr_nmi(perfctr_msr);
 616 fail:
 617         return 0;
 618 }
 619
 620 static void stop_p4_watchdog(void)
 621 {
 622         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 623
 624         wrmsr(wd->cccr_msr, 0, 0);
 625         wrmsr(wd->evntsel_msr, 0, 0);
 626
 627         release_evntsel_nmi(wd->evntsel_msr);
 628         release_perfctr_nmi(wd->perfctr_msr);
 629 }
 630
 631 #define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
 632 #define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
 633
 634 static int setup_intel_arch_watchdog(void)
 635 {
 636         unsigned int ebx;
 637         union cpuid10_eax eax;
 638         unsigned int unused;
 639         unsigned int perfctr_msr, evntsel_msr;
 640         unsigned int evntsel;
 641         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 642
 643         /*
 644          * Check whether the Architectural PerfMon supports
 645          * Unhalted Core Cycles Event or not.
 646          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 647          */
 648         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 649         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 650             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 651                 goto fail;
 652
 653         perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
 654         evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0;
 655
 656         if (!reserve_perfctr_nmi(perfctr_msr))
 657                 goto fail;
 658
 659         if (!reserve_evntsel_nmi(evntsel_msr))
 660                 goto fail1;
 661
 662         wrmsrl(perfctr_msr, 0UL);
 663
 664         evntsel = ARCH_PERFMON_EVENTSEL_INT
 665                 | ARCH_PERFMON_EVENTSEL_OS
 666                 | ARCH_PERFMON_EVENTSEL_USR
 667                 | ARCH_PERFMON_NMI_EVENT_SEL
 668                 | ARCH_PERFMON_NMI_EVENT_UMASK;
 669
 670         /* setup the timer */
 671         wrmsr(evntsel_msr, evntsel, 0);
 672
 673         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 674         wrmsr(perfctr_msr, (u32)(-((u64)cpu_khz * 1000 / nmi_hz)), 0);
 675
 676         apic_write(APIC_LVTPC, APIC_DM_NMI);
 677         evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 678         wrmsr(evntsel_msr, evntsel, 0);
 679
 680         wd->perfctr_msr = perfctr_msr;
 681         wd->evntsel_msr = evntsel_msr;
 682         wd->cccr_msr = 0;  //unused
 683         wd->check_bit = 1ULL << (eax.split.bit_width - 1);
 684         return 1;
 685 fail1:
 686         release_perfctr_nmi(perfctr_msr);
 687 fail:
 688         return 0;
 689 }
 690
 691 static void stop_intel_arch_watchdog(void)
 692 {
 693         unsigned int ebx;
 694         union cpuid10_eax eax;
 695         unsigned int unused;
 696         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 697
 698         /*
 699          * Check whether the Architectural PerfMon supports
 700          * Unhalted Core Cycles Event or not.
 701          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 702          */
 703         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 704         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 705             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 706                 return;
 707
 708         wrmsr(wd->evntsel_msr, 0, 0);
 709
 710         release_evntsel_nmi(wd->evntsel_msr);
 711         release_perfctr_nmi(wd->perfctr_msr);
 712 }
 713
 714 void setup_apic_nmi_watchdog(void *unused)
 715 {
 716         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 717
 718         /* only support LOCAL and IO APICs for now */
 719         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 720             (nmi_watchdog != NMI_IO_APIC))
 721                 return;
 722
 723         if (wd->enabled == 1)
 724                 return;
 725
 726         /* cheap hack to support suspend/resume */
 727         /* if cpu0 is not active neither should the other cpus */
 728         if ((smp_processor_id() != 0) && (atomic_read(&nmi_active) <= 0))
 729                 return;
 730
 731         if (nmi_watchdog == NMI_LOCAL_APIC) {
 732                 switch (boot_cpu_data.x86_vendor) {
 733                 case X86_VENDOR_AMD:
 734                         if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
 735                                 return;
 736                         if (!setup_k7_watchdog())
 737                                 return;
 738                         break;
 739                 case X86_VENDOR_INTEL:
 740                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 741                                 if (!setup_intel_arch_watchdog())
 742                                         return;
 743                                 break;
 744                         }
 745                         if (!setup_p4_watchdog())
 746                                 return;
 747                         break;
 748                 default:
 749                         return;
 750                 }
 751         }
 752         wd->enabled = 1;
 753         atomic_inc(&nmi_active);
 754 }
 755
 756 void stop_apic_nmi_watchdog(void *unused)
 757 {
 758         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 759
 760         /* only support LOCAL and IO APICs for now */
 761         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 762             (nmi_watchdog != NMI_IO_APIC))
 763                 return;
 764
 765         if (wd->enabled == 0)
 766                 return;
 767
 768         if (nmi_watchdog == NMI_LOCAL_APIC) {
 769                 switch (boot_cpu_data.x86_vendor) {
 770                 case X86_VENDOR_AMD:
 771                         if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
 772                                 return;
 773                         stop_k7_watchdog();
 774                         break;
 775                 case X86_VENDOR_INTEL:
 776                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 777                                 stop_intel_arch_watchdog();
 778                                 break;
 779                         }
 780                         stop_p4_watchdog();
 781                         break;
 782                 default:
 783                         return;
 784                 }
 785         }
 786         wd->enabled = 0;
 787         atomic_dec(&nmi_active);
 788 }
 789
 790 /*
 791  * the best way to detect whether a CPU has a 'hard lockup' problem
 792  * is to check it's local APIC timer IRQ counts. If they are not
 793  * changing then that CPU has some problem.
 794  *
 795  * as these watchdog NMI IRQs are generated on every CPU, we only
 796  * have to check the current processor.
 797  */
 798
 799 static DEFINE_PER_CPU(unsigned, last_irq_sum);
 800 static DEFINE_PER_CPU(local_t, alert_counter);
 801 static DEFINE_PER_CPU(int, nmi_touch);
 802
 803 void touch_nmi_watchdog (void)
 804 {
 805         if (nmi_watchdog > 0) {
 806                 unsigned cpu;
 807
 808                 /*
 809                  * Tell other CPUs to reset their alert counters. We cannot
 810                  * do it ourselves because the alert count increase is not
 811                  * atomic.
 812                  */
 813                 for_each_present_cpu (cpu)
 814                         per_cpu(nmi_touch, cpu) = 1;
 815         }
 816
 817         touch_softlockup_watchdog();
 818 }
 819
 820 int __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
 821 {
 822         int sum;
 823         int touched = 0;
 824         int cpu = smp_processor_id();
 825         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 826         u64 dummy;
 827         int rc=0;
 828
 829         /* check for other users first */
 830         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
 831                         == NOTIFY_STOP) {
 832                 rc = 1;
 833                 touched = 1;
 834         }
 835
 836         sum = read_pda(apic_timer_irqs);
 837         if (__get_cpu_var(nmi_touch)) {
 838                 __get_cpu_var(nmi_touch) = 0;
 839                 touched = 1;
 840         }
 841
 842         if (cpu_isset(cpu, backtrace_mask)) {
 843                 static DEFINE_SPINLOCK(lock);   /* Serialise the printks */
 844
 845                 spin_lock(&lock);
 846                 printk("NMI backtrace for cpu %d\n", cpu);
 847                 dump_stack();
 848                 spin_unlock(&lock);
 849                 cpu_clear(cpu, backtrace_mask);
 850         }
 851
 852 #ifdef CONFIG_X86_MCE
 853         /* Could check oops_in_progress here too, but it's safer
 854            not too */
 855         if (atomic_read(&mce_entry) > 0)
 856                 touched = 1;
 857 #endif
 858         /* if the apic timer isn't firing, this cpu isn't doing much */
 859         if (!touched && __get_cpu_var(last_irq_sum) == sum) {
 860                 /*
 861                  * Ayiee, looks like this CPU is stuck ...
 862                  * wait a few IRQs (5 seconds) before doing the oops ...
 863                  */
 864                 local_inc(&__get_cpu_var(alert_counter));
 865                 if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz)
 866                         die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs,
 867                                 panic_on_timeout);
 868         } else {
 869                 __get_cpu_var(last_irq_sum) = sum;
 870                 local_set(&__get_cpu_var(alert_counter), 0);
 871         }
 872
 873         /* see if the nmi watchdog went off */
 874         if (wd->enabled) {
 875                 if (nmi_watchdog == NMI_LOCAL_APIC) {
 876                         rdmsrl(wd->perfctr_msr, dummy);
 877                         if (dummy & wd->check_bit){
 878                                 /* this wasn't a watchdog timer interrupt */
 879                                 goto done;
 880                         }
 881
 882                         /* only Intel uses the cccr msr */
 883                         if (wd->cccr_msr != 0) {
 884                                 /*
 885                                  * P4 quirks:
 886                                  * - An overflown perfctr will assert its interrupt
 887                                  *   until the OVF flag in its CCCR is cleared.
 888                                  * - LVTPC is masked on interrupt and must be
 889                                  *   unmasked by the LVTPC handler.
 890                                  */
 891                                 rdmsrl(wd->cccr_msr, dummy);
 892                                 dummy &= ~P4_CCCR_OVF;
 893                                 wrmsrl(wd->cccr_msr, dummy);
 894                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
 895                                 /* start the cycle over again */
 896                                 wrmsrl(wd->perfctr_msr,
 897                                        -((u64)cpu_khz * 1000 / nmi_hz));
 898                         } else if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
 899                                 /*
 900                                  * ArchPerfom/Core Duo needs to re-unmask
 901                                  * the apic vector
 902                                  */
 903                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
 904                                 /* ARCH_PERFMON has 32 bit counter writes */
 905                                 wrmsr(wd->perfctr_msr,
 906                                      (u32)(-((u64)cpu_khz * 1000 / nmi_hz)), 0);
 907                         } else {
 908                                 /* start the cycle over again */
 909                                 wrmsrl(wd->perfctr_msr,
 910                                        -((u64)cpu_khz * 1000 / nmi_hz));
 911                         }
 912                         rc = 1;
 913                 } else  if (nmi_watchdog == NMI_IO_APIC) {
 914                         /* don't know how to accurately check for this.
 915                          * just assume it was a watchdog timer interrupt
 916                          * This matches the old behaviour.
 917                          */
 918                         rc = 1;
 919                 } else
 920                         printk(KERN_WARNING "Unknown enabled NMI hardware?!\n");
 921         }
 922 done:
 923         return rc;
 924 }
 925
 926 asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code)
 927 {
 928         nmi_enter();
 929         add_pda(__nmi_count,1);
 930         default_do_nmi(regs);
 931         nmi_exit();
 932 }
 933
 934 int do_nmi_callback(struct pt_regs * regs, int cpu)
 935 {
 936 #ifdef CONFIG_SYSCTL
 937         if (unknown_nmi_panic)
 938                 return unknown_nmi_panic_callback(regs, cpu);
 939 #endif
 940         return 0;
 941 }
 942
 943 #ifdef CONFIG_SYSCTL
 944
 945 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
 946 {
 947         unsigned char reason = get_nmi_reason();
 948         char buf[64];
 949
 950         sprintf(buf, "NMI received for unknown reason %02x\n", reason);
 951         die_nmi(buf, regs, 1);  /* Always panic here */
 952         return 0;
 953 }
 954
 955 /*
 956  * proc handler for /proc/sys/kernel/nmi
 957  */
 958 int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
 959                         void __user *buffer, size_t *length, loff_t *ppos)
 960 {
 961         int old_state;
 962
 963         nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
 964         old_state = nmi_watchdog_enabled;
 965         proc_dointvec(table, write, file, buffer, length, ppos);
 966         if (!!old_state == !!nmi_watchdog_enabled)
 967                 return 0;
 968
 969         if (atomic_read(&nmi_active) < 0) {
 970                 printk( KERN_WARNING "NMI watchdog is permanently disabled\n");
 971                 return -EIO;
 972         }
 973
 974         /* if nmi_watchdog is not set yet, then set it */
 975         nmi_watchdog_default();
 976
 977         if (nmi_watchdog == NMI_LOCAL_APIC) {
 978                 if (nmi_watchdog_enabled)
 979                         enable_lapic_nmi_watchdog();
 980                 else
 981                         disable_lapic_nmi_watchdog();
 982         } else {
 983                 printk( KERN_WARNING
 984                         "NMI watchdog doesn't know what hardware to touch\n");
 985                 return -EIO;
 986         }
 987         return 0;
 988 }
 989
 990 #endif
 991
 992 void __trigger_all_cpu_backtrace(void)
 993 {
 994         int i;
 995
 996         backtrace_mask = cpu_online_map;
 997         /* Wait for up to 10 seconds for all CPUs to do the backtrace */
 998         for (i = 0; i < 10 * 1000; i++) {
 999                 if (cpus_empty(backtrace_mask))
1000                         break;
1001                 mdelay(1);
1002         }
1003 }
1004
1005 EXPORT_SYMBOL(nmi_active);
1006 EXPORT_SYMBOL(nmi_watchdog);
1007 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
1008 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
1009 EXPORT_SYMBOL(reserve_perfctr_nmi);
1010 EXPORT_SYMBOL(release_perfctr_nmi);
1011 EXPORT_SYMBOL(reserve_evntsel_nmi);
1012 EXPORT_SYMBOL(release_evntsel_nmi);
1013 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
1014 EXPORT_SYMBOL(enable_timer_nmi_watchdog);
1015 EXPORT_SYMBOL(touch_nmi_watchdog);