2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/config.h>
29 #include <linux/smp_lock.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
34 #include <acpi/acpi_bus.h>
40 #include <asm/proto.h>
41 #include <asm/mach_apic.h>
46 #define __apicdebuginit __init
48 int sis_apic_bug; /* not actually supported, dummy for compile */
50 static int no_timer_check;
52 int disable_timer_pin_1 __initdata;
54 int timer_over_8254 __initdata = 0;
56 /* Where if anywhere is the i8259 connect in external int mode */
57 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
59 static DEFINE_SPINLOCK(ioapic_lock);
60 static DEFINE_SPINLOCK(vector_lock);
63 * # of IRQ routing registers
65 int nr_ioapic_registers[MAX_IO_APICS];
68 * Rough estimation of how many shared IRQs there are, can
71 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
72 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
75 * This is performance-critical, we want to do it O(1)
77 * the indexing order of this array favors 1:1 mappings
78 * between pins and IRQs.
81 static struct irq_pin_list {
82 short apic, pin, next;
83 } irq_2_pin[PIN_MAP_SIZE];
85 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
87 #define vector_to_irq(vector) \
88 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
90 #define vector_to_irq(vector) (vector)
93 #define __DO_ACTION(R, ACTION, FINAL) \
97 struct irq_pin_list *entry = irq_2_pin + irq; \
99 BUG_ON(irq >= NR_IRQS); \
105 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
107 io_apic_modify(entry->apic, reg); \
110 entry = irq_2_pin + entry->next; \
116 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
122 cpus_and(tmp, mask, cpu_online_map);
126 cpus_and(mask, tmp, CPU_MASK_ALL);
128 dest = cpu_mask_to_apicid(mask);
131 * Only the high 8 bits are valid.
133 dest = SET_APIC_LOGICAL_ID(dest);
135 spin_lock_irqsave(&ioapic_lock, flags);
136 __DO_ACTION(1, = dest, )
137 set_irq_info(irq, mask);
138 spin_unlock_irqrestore(&ioapic_lock, flags);
142 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
145 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
146 * shared ISA-space IRQs, so we have to support them. We are super
147 * fast in the common case, and fast for shared ISA-space IRQs.
149 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
151 static int first_free_entry = NR_IRQS;
152 struct irq_pin_list *entry = irq_2_pin + irq;
154 BUG_ON(irq >= NR_IRQS);
156 entry = irq_2_pin + entry->next;
158 if (entry->pin != -1) {
159 entry->next = first_free_entry;
160 entry = irq_2_pin + entry->next;
161 if (++first_free_entry >= PIN_MAP_SIZE)
162 panic("io_apic.c: ran out of irq_2_pin entries!");
169 #define DO_ACTION(name,R,ACTION, FINAL) \
171 static void name##_IO_APIC_irq (unsigned int irq) \
172 __DO_ACTION(R, ACTION, FINAL)
174 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
176 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
179 static void mask_IO_APIC_irq (unsigned int irq)
183 spin_lock_irqsave(&ioapic_lock, flags);
184 __mask_IO_APIC_irq(irq);
185 spin_unlock_irqrestore(&ioapic_lock, flags);
188 static void unmask_IO_APIC_irq (unsigned int irq)
192 spin_lock_irqsave(&ioapic_lock, flags);
193 __unmask_IO_APIC_irq(irq);
194 spin_unlock_irqrestore(&ioapic_lock, flags);
197 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
199 struct IO_APIC_route_entry entry;
202 /* Check delivery_mode to be sure we're not clearing an SMI pin */
203 spin_lock_irqsave(&ioapic_lock, flags);
204 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
205 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
206 spin_unlock_irqrestore(&ioapic_lock, flags);
207 if (entry.delivery_mode == dest_SMI)
210 * Disable it in the IO-APIC irq-routing table:
212 memset(&entry, 0, sizeof(entry));
214 spin_lock_irqsave(&ioapic_lock, flags);
215 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
216 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
217 spin_unlock_irqrestore(&ioapic_lock, flags);
220 static void clear_IO_APIC (void)
224 for (apic = 0; apic < nr_ioapics; apic++)
225 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
226 clear_IO_APIC_pin(apic, pin);
230 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
231 * specific CPU-side IRQs.
235 static int pirq_entries [MAX_PIRQS];
236 static int pirqs_enabled;
237 int skip_ioapic_setup;
240 /* dummy parsing: see setup.c */
242 static int __init disable_ioapic_setup(char *str)
244 skip_ioapic_setup = 1;
248 static int __init enable_ioapic_setup(char *str)
251 skip_ioapic_setup = 0;
255 __setup("noapic", disable_ioapic_setup);
256 __setup("apic", enable_ioapic_setup);
258 static int __init setup_disable_8254_timer(char *s)
260 timer_over_8254 = -1;
263 static int __init setup_enable_8254_timer(char *s)
269 __setup("disable_8254_timer", setup_disable_8254_timer);
270 __setup("enable_8254_timer", setup_enable_8254_timer);
272 #include <asm/pci-direct.h>
273 #include <linux/pci_ids.h>
274 #include <linux/pci.h>
279 static int nvidia_hpet_detected __initdata;
281 static int __init nvidia_hpet_check(unsigned long phys, unsigned long size)
283 nvidia_hpet_detected = 1;
288 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
289 off. Check for an Nvidia or VIA PCI bridge and turn it off.
290 Use pci direct infrastructure because this runs before the PCI subsystem.
292 Can be overwritten with "apic"
294 And another hack to disable the IOMMU on VIA chipsets.
296 ... and others. Really should move this somewhere else.
299 void __init check_ioapic(void)
302 /* Poor man's PCI discovery */
303 for (num = 0; num < 32; num++) {
304 for (slot = 0; slot < 32; slot++) {
305 for (func = 0; func < 8; func++) {
309 class = read_pci_config(num,slot,func,
311 if (class == 0xffffffff)
314 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
317 vendor = read_pci_config(num, slot, func,
321 case PCI_VENDOR_ID_VIA:
323 if ((end_pfn > MAX_DMA32_PFN ||
325 !iommu_aperture_allowed) {
327 "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n");
328 iommu_aperture_disabled = 1;
332 case PCI_VENDOR_ID_NVIDIA:
335 * All timer overrides on Nvidia are
336 * wrong unless HPET is enabled.
338 nvidia_hpet_detected = 0;
339 acpi_table_parse(ACPI_HPET,
341 if (nvidia_hpet_detected == 0) {
342 acpi_skip_timer_override = 1;
343 printk(KERN_INFO "Nvidia board "
344 "detected. Ignoring ACPI "
345 "timer override.\n");
348 /* RED-PEN skip them on mptables too? */
351 /* This should be actually default, but
352 for 2.6.16 let's do it for ATI only where
353 it's really needed. */
354 case PCI_VENDOR_ID_ATI:
355 if (timer_over_8254 == 1) {
358 "ATI board detected. Disabling timer routing over 8254.\n");
364 /* No multi-function device? */
365 type = read_pci_config_byte(num,slot,func,
374 static int __init ioapic_pirq_setup(char *str)
377 int ints[MAX_PIRQS+1];
379 get_options(str, ARRAY_SIZE(ints), ints);
381 for (i = 0; i < MAX_PIRQS; i++)
382 pirq_entries[i] = -1;
385 apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
387 if (ints[0] < MAX_PIRQS)
390 for (i = 0; i < max; i++) {
391 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
393 * PIRQs are mapped upside down, usually.
395 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
400 __setup("pirq=", ioapic_pirq_setup);
403 * Find the IRQ entry number of a certain pin.
405 static int find_irq_entry(int apic, int pin, int type)
409 for (i = 0; i < mp_irq_entries; i++)
410 if (mp_irqs[i].mpc_irqtype == type &&
411 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
412 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
413 mp_irqs[i].mpc_dstirq == pin)
420 * Find the pin to which IRQ[irq] (ISA) is connected
422 static int __init find_isa_irq_pin(int irq, int type)
426 for (i = 0; i < mp_irq_entries; i++) {
427 int lbus = mp_irqs[i].mpc_srcbus;
429 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
430 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
431 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
432 (mp_irqs[i].mpc_irqtype == type) &&
433 (mp_irqs[i].mpc_srcbusirq == irq))
435 return mp_irqs[i].mpc_dstirq;
440 static int __init find_isa_irq_apic(int irq, int type)
444 for (i = 0; i < mp_irq_entries; i++) {
445 int lbus = mp_irqs[i].mpc_srcbus;
447 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
448 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
449 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
450 (mp_irqs[i].mpc_irqtype == type) &&
451 (mp_irqs[i].mpc_srcbusirq == irq))
454 if (i < mp_irq_entries) {
456 for(apic = 0; apic < nr_ioapics; apic++) {
457 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
466 * Find a specific PCI IRQ entry.
467 * Not an __init, possibly needed by modules
469 static int pin_2_irq(int idx, int apic, int pin);
471 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
473 int apic, i, best_guess = -1;
475 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
477 if (mp_bus_id_to_pci_bus[bus] == -1) {
478 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
481 for (i = 0; i < mp_irq_entries; i++) {
482 int lbus = mp_irqs[i].mpc_srcbus;
484 for (apic = 0; apic < nr_ioapics; apic++)
485 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
486 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
489 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
490 !mp_irqs[i].mpc_irqtype &&
492 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
493 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
495 if (!(apic || IO_APIC_IRQ(irq)))
498 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
501 * Use the first all-but-pin matching entry as a
502 * best-guess fuzzy result for broken mptables.
508 BUG_ON(best_guess >= NR_IRQS);
513 * EISA Edge/Level control register, ELCR
515 static int EISA_ELCR(unsigned int irq)
518 unsigned int port = 0x4d0 + (irq >> 3);
519 return (inb(port) >> (irq & 7)) & 1;
521 apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
525 /* EISA interrupts are always polarity zero and can be edge or level
526 * trigger depending on the ELCR value. If an interrupt is listed as
527 * EISA conforming in the MP table, that means its trigger type must
528 * be read in from the ELCR */
530 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
531 #define default_EISA_polarity(idx) (0)
533 /* ISA interrupts are always polarity zero edge triggered,
534 * when listed as conforming in the MP table. */
536 #define default_ISA_trigger(idx) (0)
537 #define default_ISA_polarity(idx) (0)
539 /* PCI interrupts are always polarity one level triggered,
540 * when listed as conforming in the MP table. */
542 #define default_PCI_trigger(idx) (1)
543 #define default_PCI_polarity(idx) (1)
545 /* MCA interrupts are always polarity zero level triggered,
546 * when listed as conforming in the MP table. */
548 #define default_MCA_trigger(idx) (1)
549 #define default_MCA_polarity(idx) (0)
551 static int __init MPBIOS_polarity(int idx)
553 int bus = mp_irqs[idx].mpc_srcbus;
557 * Determine IRQ line polarity (high active or low active):
559 switch (mp_irqs[idx].mpc_irqflag & 3)
561 case 0: /* conforms, ie. bus-type dependent polarity */
563 switch (mp_bus_id_to_type[bus])
565 case MP_BUS_ISA: /* ISA pin */
567 polarity = default_ISA_polarity(idx);
570 case MP_BUS_EISA: /* EISA pin */
572 polarity = default_EISA_polarity(idx);
575 case MP_BUS_PCI: /* PCI pin */
577 polarity = default_PCI_polarity(idx);
580 case MP_BUS_MCA: /* MCA pin */
582 polarity = default_MCA_polarity(idx);
587 printk(KERN_WARNING "broken BIOS!!\n");
594 case 1: /* high active */
599 case 2: /* reserved */
601 printk(KERN_WARNING "broken BIOS!!\n");
605 case 3: /* low active */
610 default: /* invalid */
612 printk(KERN_WARNING "broken BIOS!!\n");
620 static int MPBIOS_trigger(int idx)
622 int bus = mp_irqs[idx].mpc_srcbus;
626 * Determine IRQ trigger mode (edge or level sensitive):
628 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
630 case 0: /* conforms, ie. bus-type dependent */
632 switch (mp_bus_id_to_type[bus])
634 case MP_BUS_ISA: /* ISA pin */
636 trigger = default_ISA_trigger(idx);
639 case MP_BUS_EISA: /* EISA pin */
641 trigger = default_EISA_trigger(idx);
644 case MP_BUS_PCI: /* PCI pin */
646 trigger = default_PCI_trigger(idx);
649 case MP_BUS_MCA: /* MCA pin */
651 trigger = default_MCA_trigger(idx);
656 printk(KERN_WARNING "broken BIOS!!\n");
668 case 2: /* reserved */
670 printk(KERN_WARNING "broken BIOS!!\n");
679 default: /* invalid */
681 printk(KERN_WARNING "broken BIOS!!\n");
689 static inline int irq_polarity(int idx)
691 return MPBIOS_polarity(idx);
694 static inline int irq_trigger(int idx)
696 return MPBIOS_trigger(idx);
699 static int next_irq = 16;
702 * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ
703 * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
704 * from ACPI, which can reach 800 in large boxen.
706 * Compact the sparse GSI space into a sequential IRQ series and reuse
707 * vectors if possible.
709 int gsi_irq_sharing(int gsi)
711 int i, tries, vector;
713 BUG_ON(gsi >= NR_IRQ_VECTORS);
715 if (platform_legacy_irq(gsi))
718 if (gsi_2_irq[gsi] != 0xFF)
719 return (int)gsi_2_irq[gsi];
723 vector = assign_irq_vector(gsi);
726 * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
727 * use of vector and if found, return that IRQ. However, we never want
728 * to share legacy IRQs, which usually have a different trigger mode
731 for (i = 0; i < NR_IRQS; i++)
732 if (IO_APIC_VECTOR(i) == vector)
734 if (platform_legacy_irq(i)) {
736 IO_APIC_VECTOR(i) = 0;
739 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
743 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
749 BUG_ON(i >= NR_IRQS);
751 IO_APIC_VECTOR(i) = vector;
752 printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
757 static int pin_2_irq(int idx, int apic, int pin)
760 int bus = mp_irqs[idx].mpc_srcbus;
763 * Debugging check, we are in big trouble if this message pops up!
765 if (mp_irqs[idx].mpc_dstirq != pin)
766 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
768 switch (mp_bus_id_to_type[bus])
770 case MP_BUS_ISA: /* ISA pin */
774 irq = mp_irqs[idx].mpc_srcbusirq;
777 case MP_BUS_PCI: /* PCI pin */
780 * PCI IRQs are mapped in order
784 irq += nr_ioapic_registers[i++];
786 irq = gsi_irq_sharing(irq);
791 printk(KERN_ERR "unknown bus type %d.\n",bus);
796 BUG_ON(irq >= NR_IRQS);
799 * PCI IRQ command line redirection. Yes, limits are hardcoded.
801 if ((pin >= 16) && (pin <= 23)) {
802 if (pirq_entries[pin-16] != -1) {
803 if (!pirq_entries[pin-16]) {
804 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
806 irq = pirq_entries[pin-16];
807 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
812 BUG_ON(irq >= NR_IRQS);
816 static inline int IO_APIC_irq_trigger(int irq)
820 for (apic = 0; apic < nr_ioapics; apic++) {
821 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
822 idx = find_irq_entry(apic,pin,mp_INT);
823 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
824 return irq_trigger(idx);
828 * nonexistent IRQs are edge default
833 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
834 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
836 int assign_irq_vector(int irq)
838 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
842 BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
844 spin_lock_irqsave(&vector_lock, flags);
846 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
847 spin_unlock_irqrestore(&vector_lock, flags);
848 return IO_APIC_VECTOR(irq);
852 if (current_vector == IA32_SYSCALL_VECTOR)
855 if (current_vector >= FIRST_SYSTEM_VECTOR) {
856 /* If we run out of vectors on large boxen, must share them. */
857 offset = (offset + 1) % 8;
858 current_vector = FIRST_DEVICE_VECTOR + offset;
861 vector = current_vector;
862 vector_irq[vector] = irq;
863 if (irq != AUTO_ASSIGN)
864 IO_APIC_VECTOR(irq) = vector;
866 spin_unlock_irqrestore(&vector_lock, flags);
871 extern void (*interrupt[NR_IRQS])(void);
872 static struct hw_interrupt_type ioapic_level_type;
873 static struct hw_interrupt_type ioapic_edge_type;
875 #define IOAPIC_AUTO -1
876 #define IOAPIC_EDGE 0
877 #define IOAPIC_LEVEL 1
879 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
883 idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
885 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
886 trigger == IOAPIC_LEVEL)
887 irq_desc[idx].chip = &ioapic_level_type;
889 irq_desc[idx].chip = &ioapic_edge_type;
890 set_intr_gate(vector, interrupt[idx]);
893 static void __init setup_IO_APIC_irqs(void)
895 struct IO_APIC_route_entry entry;
896 int apic, pin, idx, irq, first_notcon = 1, vector;
899 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
901 for (apic = 0; apic < nr_ioapics; apic++) {
902 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
905 * add it to the IO-APIC irq-routing table:
907 memset(&entry,0,sizeof(entry));
909 entry.delivery_mode = INT_DELIVERY_MODE;
910 entry.dest_mode = INT_DEST_MODE;
911 entry.mask = 0; /* enable IRQ */
912 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
914 idx = find_irq_entry(apic,pin,mp_INT);
917 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
920 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
924 entry.trigger = irq_trigger(idx);
925 entry.polarity = irq_polarity(idx);
927 if (irq_trigger(idx)) {
930 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
933 irq = pin_2_irq(idx, apic, pin);
934 add_pin_to_irq(irq, apic, pin);
936 if (!apic && !IO_APIC_IRQ(irq))
939 if (IO_APIC_IRQ(irq)) {
940 vector = assign_irq_vector(irq);
941 entry.vector = vector;
943 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
944 if (!apic && (irq < 16))
945 disable_8259A_irq(irq);
947 spin_lock_irqsave(&ioapic_lock, flags);
948 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
949 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
950 set_native_irq_info(irq, TARGET_CPUS);
951 spin_unlock_irqrestore(&ioapic_lock, flags);
956 apic_printk(APIC_VERBOSE," not connected.\n");
960 * Set up the 8259A-master output pin as broadcast to all
963 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
965 struct IO_APIC_route_entry entry;
968 memset(&entry,0,sizeof(entry));
970 disable_8259A_irq(0);
973 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
976 * We use logical delivery to get the timer IRQ
979 entry.dest_mode = INT_DEST_MODE;
980 entry.mask = 0; /* unmask IRQ now */
981 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
982 entry.delivery_mode = INT_DELIVERY_MODE;
985 entry.vector = vector;
988 * The timer IRQ doesn't have to know that behind the
989 * scene we have a 8259A-master in AEOI mode ...
991 irq_desc[0].chip = &ioapic_edge_type;
994 * Add it to the IO-APIC irq-routing table:
996 spin_lock_irqsave(&ioapic_lock, flags);
997 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
998 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
999 spin_unlock_irqrestore(&ioapic_lock, flags);
1001 enable_8259A_irq(0);
1004 void __init UNEXPECTED_IO_APIC(void)
1008 void __apicdebuginit print_IO_APIC(void)
1011 union IO_APIC_reg_00 reg_00;
1012 union IO_APIC_reg_01 reg_01;
1013 union IO_APIC_reg_02 reg_02;
1014 unsigned long flags;
1016 if (apic_verbosity == APIC_QUIET)
1019 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1020 for (i = 0; i < nr_ioapics; i++)
1021 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1022 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1025 * We are a bit conservative about what we expect. We have to
1026 * know about every hardware change ASAP.
1028 printk(KERN_INFO "testing the IO APIC.......................\n");
1030 for (apic = 0; apic < nr_ioapics; apic++) {
1032 spin_lock_irqsave(&ioapic_lock, flags);
1033 reg_00.raw = io_apic_read(apic, 0);
1034 reg_01.raw = io_apic_read(apic, 1);
1035 if (reg_01.bits.version >= 0x10)
1036 reg_02.raw = io_apic_read(apic, 2);
1037 spin_unlock_irqrestore(&ioapic_lock, flags);
1040 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1041 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1042 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1043 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1044 UNEXPECTED_IO_APIC();
1046 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1047 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1048 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1049 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1050 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1051 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1052 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1053 (reg_01.bits.entries != 0x2E) &&
1054 (reg_01.bits.entries != 0x3F) &&
1055 (reg_01.bits.entries != 0x03)
1057 UNEXPECTED_IO_APIC();
1059 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1060 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1061 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1062 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
1063 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1064 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1065 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1066 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1068 UNEXPECTED_IO_APIC();
1069 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1070 UNEXPECTED_IO_APIC();
1072 if (reg_01.bits.version >= 0x10) {
1073 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1074 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1075 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1076 UNEXPECTED_IO_APIC();
1079 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1081 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1082 " Stat Dest Deli Vect: \n");
1084 for (i = 0; i <= reg_01.bits.entries; i++) {
1085 struct IO_APIC_route_entry entry;
1087 spin_lock_irqsave(&ioapic_lock, flags);
1088 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1089 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1090 spin_unlock_irqrestore(&ioapic_lock, flags);
1092 printk(KERN_DEBUG " %02x %03X %02X ",
1094 entry.dest.logical.logical_dest,
1095 entry.dest.physical.physical_dest
1098 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1103 entry.delivery_status,
1105 entry.delivery_mode,
1110 if (use_pci_vector())
1111 printk(KERN_INFO "Using vector-based indexing\n");
1112 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1113 for (i = 0; i < NR_IRQS; i++) {
1114 struct irq_pin_list *entry = irq_2_pin + i;
1117 if (use_pci_vector() && !platform_legacy_irq(i))
1118 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1120 printk(KERN_DEBUG "IRQ%d ", i);
1122 printk("-> %d:%d", entry->apic, entry->pin);
1125 entry = irq_2_pin + entry->next;
1130 printk(KERN_INFO ".................................... done.\n");
1137 static __apicdebuginit void print_APIC_bitfield (int base)
1142 if (apic_verbosity == APIC_QUIET)
1145 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1146 for (i = 0; i < 8; i++) {
1147 v = apic_read(base + i*0x10);
1148 for (j = 0; j < 32; j++) {
1158 void __apicdebuginit print_local_APIC(void * dummy)
1160 unsigned int v, ver, maxlvt;
1162 if (apic_verbosity == APIC_QUIET)
1165 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1166 smp_processor_id(), hard_smp_processor_id());
1167 v = apic_read(APIC_ID);
1168 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1169 v = apic_read(APIC_LVR);
1170 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1171 ver = GET_APIC_VERSION(v);
1172 maxlvt = get_maxlvt();
1174 v = apic_read(APIC_TASKPRI);
1175 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1177 v = apic_read(APIC_ARBPRI);
1178 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1179 v & APIC_ARBPRI_MASK);
1180 v = apic_read(APIC_PROCPRI);
1181 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1183 v = apic_read(APIC_EOI);
1184 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1185 v = apic_read(APIC_RRR);
1186 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1187 v = apic_read(APIC_LDR);
1188 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1189 v = apic_read(APIC_DFR);
1190 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1191 v = apic_read(APIC_SPIV);
1192 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1194 printk(KERN_DEBUG "... APIC ISR field:\n");
1195 print_APIC_bitfield(APIC_ISR);
1196 printk(KERN_DEBUG "... APIC TMR field:\n");
1197 print_APIC_bitfield(APIC_TMR);
1198 printk(KERN_DEBUG "... APIC IRR field:\n");
1199 print_APIC_bitfield(APIC_IRR);
1201 v = apic_read(APIC_ESR);
1202 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1204 v = apic_read(APIC_ICR);
1205 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1206 v = apic_read(APIC_ICR2);
1207 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1209 v = apic_read(APIC_LVTT);
1210 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1212 if (maxlvt > 3) { /* PC is LVT#4. */
1213 v = apic_read(APIC_LVTPC);
1214 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1216 v = apic_read(APIC_LVT0);
1217 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1218 v = apic_read(APIC_LVT1);
1219 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1221 if (maxlvt > 2) { /* ERR is LVT#3. */
1222 v = apic_read(APIC_LVTERR);
1223 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1226 v = apic_read(APIC_TMICT);
1227 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1228 v = apic_read(APIC_TMCCT);
1229 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1230 v = apic_read(APIC_TDCR);
1231 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1235 void print_all_local_APICs (void)
1237 on_each_cpu(print_local_APIC, NULL, 1, 1);
1240 void __apicdebuginit print_PIC(void)
1243 unsigned long flags;
1245 if (apic_verbosity == APIC_QUIET)
1248 printk(KERN_DEBUG "\nprinting PIC contents\n");
1250 spin_lock_irqsave(&i8259A_lock, flags);
1252 v = inb(0xa1) << 8 | inb(0x21);
1253 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1255 v = inb(0xa0) << 8 | inb(0x20);
1256 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1260 v = inb(0xa0) << 8 | inb(0x20);
1264 spin_unlock_irqrestore(&i8259A_lock, flags);
1266 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1268 v = inb(0x4d1) << 8 | inb(0x4d0);
1269 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1274 static void __init enable_IO_APIC(void)
1276 union IO_APIC_reg_01 reg_01;
1277 int i8259_apic, i8259_pin;
1279 unsigned long flags;
1281 for (i = 0; i < PIN_MAP_SIZE; i++) {
1282 irq_2_pin[i].pin = -1;
1283 irq_2_pin[i].next = 0;
1286 for (i = 0; i < MAX_PIRQS; i++)
1287 pirq_entries[i] = -1;
1290 * The number of IO-APIC IRQ registers (== #pins):
1292 for (apic = 0; apic < nr_ioapics; apic++) {
1293 spin_lock_irqsave(&ioapic_lock, flags);
1294 reg_01.raw = io_apic_read(apic, 1);
1295 spin_unlock_irqrestore(&ioapic_lock, flags);
1296 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1298 for(apic = 0; apic < nr_ioapics; apic++) {
1300 /* See if any of the pins is in ExtINT mode */
1301 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1302 struct IO_APIC_route_entry entry;
1303 spin_lock_irqsave(&ioapic_lock, flags);
1304 *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1305 *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1306 spin_unlock_irqrestore(&ioapic_lock, flags);
1309 /* If the interrupt line is enabled and in ExtInt mode
1310 * I have found the pin where the i8259 is connected.
1312 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1313 ioapic_i8259.apic = apic;
1314 ioapic_i8259.pin = pin;
1320 /* Look to see what if the MP table has reported the ExtINT */
1321 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1322 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1323 /* Trust the MP table if nothing is setup in the hardware */
1324 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1325 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1326 ioapic_i8259.pin = i8259_pin;
1327 ioapic_i8259.apic = i8259_apic;
1329 /* Complain if the MP table and the hardware disagree */
1330 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1331 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1333 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1337 * Do not trust the IO-APIC being empty at bootup
1343 * Not an __init, needed by the reboot code
1345 void disable_IO_APIC(void)
1348 * Clear the IO-APIC before rebooting:
1353 * If the i8259 is routed through an IOAPIC
1354 * Put that IOAPIC in virtual wire mode
1355 * so legacy interrupts can be delivered.
1357 if (ioapic_i8259.pin != -1) {
1358 struct IO_APIC_route_entry entry;
1359 unsigned long flags;
1361 memset(&entry, 0, sizeof(entry));
1362 entry.mask = 0; /* Enabled */
1363 entry.trigger = 0; /* Edge */
1365 entry.polarity = 0; /* High */
1366 entry.delivery_status = 0;
1367 entry.dest_mode = 0; /* Physical */
1368 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1370 entry.dest.physical.physical_dest =
1371 GET_APIC_ID(apic_read(APIC_ID));
1374 * Add it to the IO-APIC irq-routing table:
1376 spin_lock_irqsave(&ioapic_lock, flags);
1377 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1378 *(((int *)&entry)+1));
1379 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1380 *(((int *)&entry)+0));
1381 spin_unlock_irqrestore(&ioapic_lock, flags);
1384 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1388 * function to set the IO-APIC physical IDs based on the
1389 * values stored in the MPC table.
1391 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1394 static void __init setup_ioapic_ids_from_mpc (void)
1396 union IO_APIC_reg_00 reg_00;
1399 unsigned char old_id;
1400 unsigned long flags;
1403 * Set the IOAPIC ID to the value stored in the MPC table.
1405 for (apic = 0; apic < nr_ioapics; apic++) {
1407 /* Read the register 0 value */
1408 spin_lock_irqsave(&ioapic_lock, flags);
1409 reg_00.raw = io_apic_read(apic, 0);
1410 spin_unlock_irqrestore(&ioapic_lock, flags);
1412 old_id = mp_ioapics[apic].mpc_apicid;
1415 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1419 * We need to adjust the IRQ routing table
1420 * if the ID changed.
1422 if (old_id != mp_ioapics[apic].mpc_apicid)
1423 for (i = 0; i < mp_irq_entries; i++)
1424 if (mp_irqs[i].mpc_dstapic == old_id)
1425 mp_irqs[i].mpc_dstapic
1426 = mp_ioapics[apic].mpc_apicid;
1429 * Read the right value from the MPC table and
1430 * write it into the ID register.
1432 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1433 mp_ioapics[apic].mpc_apicid);
1435 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1436 spin_lock_irqsave(&ioapic_lock, flags);
1437 io_apic_write(apic, 0, reg_00.raw);
1438 spin_unlock_irqrestore(&ioapic_lock, flags);
1443 spin_lock_irqsave(&ioapic_lock, flags);
1444 reg_00.raw = io_apic_read(apic, 0);
1445 spin_unlock_irqrestore(&ioapic_lock, flags);
1446 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1447 printk("could not set ID!\n");
1449 apic_printk(APIC_VERBOSE," ok.\n");
1454 * There is a nasty bug in some older SMP boards, their mptable lies
1455 * about the timer IRQ. We do the following to work around the situation:
1457 * - timer IRQ defaults to IO-APIC IRQ
1458 * - if this function detects that timer IRQs are defunct, then we fall
1459 * back to ISA timer IRQs
1461 static int __init timer_irq_works(void)
1463 unsigned long t1 = jiffies;
1466 /* Let ten ticks pass... */
1467 mdelay((10 * 1000) / HZ);
1470 * Expect a few ticks at least, to be sure some possible
1471 * glue logic does not lock up after one or two first
1472 * ticks in a non-ExtINT mode. Also the local APIC
1473 * might have cached one ExtINT interrupt. Finally, at
1474 * least one tick may be lost due to delays.
1478 if (jiffies - t1 > 4)
1484 * In the SMP+IOAPIC case it might happen that there are an unspecified
1485 * number of pending IRQ events unhandled. These cases are very rare,
1486 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1487 * better to do it this way as thus we do not have to be aware of
1488 * 'pending' interrupts in the IRQ path, except at this point.
1491 * Edge triggered needs to resend any interrupt
1492 * that was delayed but this is now handled in the device
1497 * Starting up a edge-triggered IO-APIC interrupt is
1498 * nasty - we need to make sure that we get the edge.
1499 * If it is already asserted for some reason, we need
1500 * return 1 to indicate that is was pending.
1502 * This is not complete - we should be able to fake
1503 * an edge even if it isn't on the 8259A...
1506 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1508 int was_pending = 0;
1509 unsigned long flags;
1511 spin_lock_irqsave(&ioapic_lock, flags);
1513 disable_8259A_irq(irq);
1514 if (i8259A_irq_pending(irq))
1517 __unmask_IO_APIC_irq(irq);
1518 spin_unlock_irqrestore(&ioapic_lock, flags);
1524 * Once we have recorded IRQ_PENDING already, we can mask the
1525 * interrupt for real. This prevents IRQ storms from unhandled
1528 static void ack_edge_ioapic_irq(unsigned int irq)
1531 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1532 == (IRQ_PENDING | IRQ_DISABLED))
1533 mask_IO_APIC_irq(irq);
1538 * Level triggered interrupts can just be masked,
1539 * and shutting down and starting up the interrupt
1540 * is the same as enabling and disabling them -- except
1541 * with a startup need to return a "was pending" value.
1543 * Level triggered interrupts are special because we
1544 * do not touch any IO-APIC register while handling
1545 * them. We ack the APIC in the end-IRQ handler, not
1546 * in the start-IRQ-handler. Protection against reentrance
1547 * from the same interrupt is still provided, both by the
1548 * generic IRQ layer and by the fact that an unacked local
1549 * APIC does not accept IRQs.
1551 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1553 unmask_IO_APIC_irq(irq);
1555 return 0; /* don't check for pending */
1558 static void end_level_ioapic_irq (unsigned int irq)
1564 #ifdef CONFIG_PCI_MSI
1565 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1567 int irq = vector_to_irq(vector);
1569 return startup_edge_ioapic_irq(irq);
1572 static void ack_edge_ioapic_vector(unsigned int vector)
1574 int irq = vector_to_irq(vector);
1576 move_native_irq(vector);
1577 ack_edge_ioapic_irq(irq);
1580 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1582 int irq = vector_to_irq(vector);
1584 return startup_level_ioapic_irq (irq);
1587 static void end_level_ioapic_vector (unsigned int vector)
1589 int irq = vector_to_irq(vector);
1591 move_native_irq(vector);
1592 end_level_ioapic_irq(irq);
1595 static void mask_IO_APIC_vector (unsigned int vector)
1597 int irq = vector_to_irq(vector);
1599 mask_IO_APIC_irq(irq);
1602 static void unmask_IO_APIC_vector (unsigned int vector)
1604 int irq = vector_to_irq(vector);
1606 unmask_IO_APIC_irq(irq);
1610 static void set_ioapic_affinity_vector (unsigned int vector,
1613 int irq = vector_to_irq(vector);
1615 set_native_irq_info(vector, cpu_mask);
1616 set_ioapic_affinity_irq(irq, cpu_mask);
1618 #endif // CONFIG_SMP
1619 #endif // CONFIG_PCI_MSI
1621 static int ioapic_retrigger(unsigned int irq)
1623 send_IPI_self(IO_APIC_VECTOR(irq));
1629 * Level and edge triggered IO-APIC interrupts need different handling,
1630 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1631 * handled with the level-triggered descriptor, but that one has slightly
1632 * more overhead. Level-triggered interrupts cannot be handled with the
1633 * edge-triggered handler, without risking IRQ storms and other ugly
1637 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1638 .typename = "IO-APIC-edge",
1639 .startup = startup_edge_ioapic,
1640 .shutdown = shutdown_edge_ioapic,
1641 .enable = enable_edge_ioapic,
1642 .disable = disable_edge_ioapic,
1643 .ack = ack_edge_ioapic,
1644 .end = end_edge_ioapic,
1646 .set_affinity = set_ioapic_affinity,
1648 .retrigger = ioapic_retrigger,
1651 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1652 .typename = "IO-APIC-level",
1653 .startup = startup_level_ioapic,
1654 .shutdown = shutdown_level_ioapic,
1655 .enable = enable_level_ioapic,
1656 .disable = disable_level_ioapic,
1657 .ack = mask_and_ack_level_ioapic,
1658 .end = end_level_ioapic,
1660 .set_affinity = set_ioapic_affinity,
1662 .retrigger = ioapic_retrigger,
1665 static inline void init_IO_APIC_traps(void)
1670 * NOTE! The local APIC isn't very good at handling
1671 * multiple interrupts at the same interrupt level.
1672 * As the interrupt level is determined by taking the
1673 * vector number and shifting that right by 4, we
1674 * want to spread these out a bit so that they don't
1675 * all fall in the same interrupt level.
1677 * Also, we've got to be careful not to trash gate
1678 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1680 for (irq = 0; irq < NR_IRQS ; irq++) {
1682 if (use_pci_vector()) {
1683 if (!platform_legacy_irq(tmp))
1684 if ((tmp = vector_to_irq(tmp)) == -1)
1687 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1689 * Hmm.. We don't have an entry for this,
1690 * so default to an old-fashioned 8259
1691 * interrupt if we can..
1694 make_8259A_irq(irq);
1696 /* Strange. Oh, well.. */
1697 irq_desc[irq].chip = &no_irq_type;
1702 static void enable_lapic_irq (unsigned int irq)
1706 v = apic_read(APIC_LVT0);
1707 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1710 static void disable_lapic_irq (unsigned int irq)
1714 v = apic_read(APIC_LVT0);
1715 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1718 static void ack_lapic_irq (unsigned int irq)
1723 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1725 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1726 .typename = "local-APIC-edge",
1727 .startup = NULL, /* startup_irq() not used for IRQ0 */
1728 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1729 .enable = enable_lapic_irq,
1730 .disable = disable_lapic_irq,
1731 .ack = ack_lapic_irq,
1732 .end = end_lapic_irq,
1735 static void setup_nmi (void)
1738 * Dirty trick to enable the NMI watchdog ...
1739 * We put the 8259A master into AEOI mode and
1740 * unmask on all local APICs LVT0 as NMI.
1742 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1743 * is from Maciej W. Rozycki - so we do not have to EOI from
1744 * the NMI handler or the timer interrupt.
1746 printk(KERN_INFO "activating NMI Watchdog ...");
1748 enable_NMI_through_LVT0(NULL);
1754 * This looks a bit hackish but it's about the only one way of sending
1755 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1756 * not support the ExtINT mode, unfortunately. We need to send these
1757 * cycles as some i82489DX-based boards have glue logic that keeps the
1758 * 8259A interrupt line asserted until INTA. --macro
1760 static inline void unlock_ExtINT_logic(void)
1763 struct IO_APIC_route_entry entry0, entry1;
1764 unsigned char save_control, save_freq_select;
1765 unsigned long flags;
1767 pin = find_isa_irq_pin(8, mp_INT);
1768 apic = find_isa_irq_apic(8, mp_INT);
1772 spin_lock_irqsave(&ioapic_lock, flags);
1773 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1774 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1775 spin_unlock_irqrestore(&ioapic_lock, flags);
1776 clear_IO_APIC_pin(apic, pin);
1778 memset(&entry1, 0, sizeof(entry1));
1780 entry1.dest_mode = 0; /* physical delivery */
1781 entry1.mask = 0; /* unmask IRQ now */
1782 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1783 entry1.delivery_mode = dest_ExtINT;
1784 entry1.polarity = entry0.polarity;
1788 spin_lock_irqsave(&ioapic_lock, flags);
1789 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1790 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1791 spin_unlock_irqrestore(&ioapic_lock, flags);
1793 save_control = CMOS_READ(RTC_CONTROL);
1794 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1795 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1797 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1802 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1806 CMOS_WRITE(save_control, RTC_CONTROL);
1807 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1808 clear_IO_APIC_pin(apic, pin);
1810 spin_lock_irqsave(&ioapic_lock, flags);
1811 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1812 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1813 spin_unlock_irqrestore(&ioapic_lock, flags);
1816 int timer_uses_ioapic_pin_0;
1819 * This code may look a bit paranoid, but it's supposed to cooperate with
1820 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1821 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1822 * fanatically on his truly buggy board.
1824 * FIXME: really need to revamp this for modern platforms only.
1826 static inline void check_timer(void)
1828 int apic1, pin1, apic2, pin2;
1832 * get/set the timer IRQ vector:
1834 disable_8259A_irq(0);
1835 vector = assign_irq_vector(0);
1836 set_intr_gate(vector, interrupt[0]);
1839 * Subtle, code in do_timer_interrupt() expects an AEOI
1840 * mode for the 8259A whenever interrupts are routed
1841 * through I/O APICs. Also IRQ0 has to be enabled in
1842 * the 8259A which implies the virtual wire has to be
1843 * disabled in the local APIC.
1845 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1847 if (timer_over_8254 > 0)
1848 enable_8259A_irq(0);
1850 pin1 = find_isa_irq_pin(0, mp_INT);
1851 apic1 = find_isa_irq_apic(0, mp_INT);
1852 pin2 = ioapic_i8259.pin;
1853 apic2 = ioapic_i8259.apic;
1856 timer_uses_ioapic_pin_0 = 1;
1858 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1859 vector, apic1, pin1, apic2, pin2);
1863 * Ok, does IRQ0 through the IOAPIC work?
1865 unmask_IO_APIC_irq(0);
1866 if (!no_timer_check && timer_irq_works()) {
1867 nmi_watchdog_default();
1868 if (nmi_watchdog == NMI_IO_APIC) {
1869 disable_8259A_irq(0);
1871 enable_8259A_irq(0);
1873 if (disable_timer_pin_1 > 0)
1874 clear_IO_APIC_pin(0, pin1);
1877 clear_IO_APIC_pin(apic1, pin1);
1878 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1879 "connected to IO-APIC\n");
1882 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1883 "through the 8259A ... ");
1885 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1888 * legacy devices should be connected to IO APIC #0
1890 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1891 if (timer_irq_works()) {
1892 apic_printk(APIC_VERBOSE," works.\n");
1893 nmi_watchdog_default();
1894 if (nmi_watchdog == NMI_IO_APIC) {
1900 * Cleanup, just in case ...
1902 clear_IO_APIC_pin(apic2, pin2);
1904 apic_printk(APIC_VERBOSE," failed.\n");
1906 if (nmi_watchdog == NMI_IO_APIC) {
1907 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1911 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1913 disable_8259A_irq(0);
1914 irq_desc[0].chip = &lapic_irq_type;
1915 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1916 enable_8259A_irq(0);
1918 if (timer_irq_works()) {
1919 apic_printk(APIC_VERBOSE," works.\n");
1922 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1923 apic_printk(APIC_VERBOSE," failed.\n");
1925 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1929 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1931 unlock_ExtINT_logic();
1933 if (timer_irq_works()) {
1934 apic_printk(APIC_VERBOSE," works.\n");
1937 apic_printk(APIC_VERBOSE," failed :(.\n");
1938 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1941 static int __init notimercheck(char *s)
1946 __setup("no_timer_check", notimercheck);
1950 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1951 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1952 * Linux doesn't really care, as it's not actually used
1953 * for any interrupt handling anyway.
1955 #define PIC_IRQS (1<<2)
1957 void __init setup_IO_APIC(void)
1962 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1964 io_apic_irqs = ~PIC_IRQS;
1966 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1969 * Set up the IO-APIC IRQ routing table.
1972 setup_ioapic_ids_from_mpc();
1974 setup_IO_APIC_irqs();
1975 init_IO_APIC_traps();
1981 struct sysfs_ioapic_data {
1982 struct sys_device dev;
1983 struct IO_APIC_route_entry entry[0];
1985 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1987 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1989 struct IO_APIC_route_entry *entry;
1990 struct sysfs_ioapic_data *data;
1991 unsigned long flags;
1994 data = container_of(dev, struct sysfs_ioapic_data, dev);
1995 entry = data->entry;
1996 spin_lock_irqsave(&ioapic_lock, flags);
1997 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1998 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1999 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2001 spin_unlock_irqrestore(&ioapic_lock, flags);
2006 static int ioapic_resume(struct sys_device *dev)
2008 struct IO_APIC_route_entry *entry;
2009 struct sysfs_ioapic_data *data;
2010 unsigned long flags;
2011 union IO_APIC_reg_00 reg_00;
2014 data = container_of(dev, struct sysfs_ioapic_data, dev);
2015 entry = data->entry;
2017 spin_lock_irqsave(&ioapic_lock, flags);
2018 reg_00.raw = io_apic_read(dev->id, 0);
2019 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2020 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2021 io_apic_write(dev->id, 0, reg_00.raw);
2023 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2024 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2025 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2027 spin_unlock_irqrestore(&ioapic_lock, flags);
2032 static struct sysdev_class ioapic_sysdev_class = {
2033 set_kset_name("ioapic"),
2034 .suspend = ioapic_suspend,
2035 .resume = ioapic_resume,
2038 static int __init ioapic_init_sysfs(void)
2040 struct sys_device * dev;
2041 int i, size, error = 0;
2043 error = sysdev_class_register(&ioapic_sysdev_class);
2047 for (i = 0; i < nr_ioapics; i++ ) {
2048 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2049 * sizeof(struct IO_APIC_route_entry);
2050 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2051 if (!mp_ioapic_data[i]) {
2052 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2055 memset(mp_ioapic_data[i], 0, size);
2056 dev = &mp_ioapic_data[i]->dev;
2058 dev->cls = &ioapic_sysdev_class;
2059 error = sysdev_register(dev);
2061 kfree(mp_ioapic_data[i]);
2062 mp_ioapic_data[i] = NULL;
2063 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2071 device_initcall(ioapic_init_sysfs);
2073 /* --------------------------------------------------------------------------
2074 ACPI-based IOAPIC Configuration
2075 -------------------------------------------------------------------------- */
2079 #define IO_APIC_MAX_ID 0xFE
2081 int __init io_apic_get_version (int ioapic)
2083 union IO_APIC_reg_01 reg_01;
2084 unsigned long flags;
2086 spin_lock_irqsave(&ioapic_lock, flags);
2087 reg_01.raw = io_apic_read(ioapic, 1);
2088 spin_unlock_irqrestore(&ioapic_lock, flags);
2090 return reg_01.bits.version;
2094 int __init io_apic_get_redir_entries (int ioapic)
2096 union IO_APIC_reg_01 reg_01;
2097 unsigned long flags;
2099 spin_lock_irqsave(&ioapic_lock, flags);
2100 reg_01.raw = io_apic_read(ioapic, 1);
2101 spin_unlock_irqrestore(&ioapic_lock, flags);
2103 return reg_01.bits.entries;
2107 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2109 struct IO_APIC_route_entry entry;
2110 unsigned long flags;
2112 if (!IO_APIC_IRQ(irq)) {
2113 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2119 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2120 * Note that we mask (disable) IRQs now -- these get enabled when the
2121 * corresponding device driver registers for this IRQ.
2124 memset(&entry,0,sizeof(entry));
2126 entry.delivery_mode = INT_DELIVERY_MODE;
2127 entry.dest_mode = INT_DEST_MODE;
2128 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2129 entry.trigger = triggering;
2130 entry.polarity = polarity;
2131 entry.mask = 1; /* Disabled (masked) */
2133 irq = gsi_irq_sharing(irq);
2135 * IRQs < 16 are already in the irq_2_pin[] map
2138 add_pin_to_irq(irq, ioapic, pin);
2140 entry.vector = assign_irq_vector(irq);
2142 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2143 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2144 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2145 triggering, polarity);
2147 ioapic_register_intr(irq, entry.vector, triggering);
2149 if (!ioapic && (irq < 16))
2150 disable_8259A_irq(irq);
2152 spin_lock_irqsave(&ioapic_lock, flags);
2153 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2154 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2155 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2156 spin_unlock_irqrestore(&ioapic_lock, flags);
2161 #endif /* CONFIG_ACPI */
2165 * This function currently is only a helper for the i386 smp boot process where
2166 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2167 * so mask in all cases should simply be TARGET_CPUS
2170 void __init setup_ioapic_dest(void)
2172 int pin, ioapic, irq, irq_entry;
2174 if (skip_ioapic_setup == 1)
2177 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2178 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2179 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2180 if (irq_entry == -1)
2182 irq = pin_2_irq(irq_entry, ioapic, pin);
2183 set_ioapic_affinity_irq(irq, TARGET_CPUS);