arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/acpi.h>
  31 #include <linux/sysdev.h>
  32 #ifdef CONFIG_ACPI
  33 #include <acpi/acpi_bus.h>
  34 #endif
  35
  36 #include <asm/io.h>
  37 #include <asm/smp.h>
  38 #include <asm/desc.h>
  39 #include <asm/proto.h>
  40 #include <asm/mach_apic.h>
  41 #include <asm/acpi.h>
  42 #include <asm/dma.h>
  43 #include <asm/nmi.h>
  44
  45 #define __apicdebuginit  __init
  46
  47 int sis_apic_bug; /* not actually supported, dummy for compile */
  48
  49 static int no_timer_check;
  50
  51 int disable_timer_pin_1 __initdata;
  52
  53 int timer_over_8254 __initdata = 0;
  54
  55 /* Where if anywhere is the i8259 connect in external int mode */
  56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  57
  58 static DEFINE_SPINLOCK(ioapic_lock);
  59 static DEFINE_SPINLOCK(vector_lock);
  60
  61 /*
  62  * # of IRQ routing registers
  63  */
  64 int nr_ioapic_registers[MAX_IO_APICS];
  65
  66 /*
  67  * Rough estimation of how many shared IRQs there are, can
  68  * be changed anytime.
  69  */
  70 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  71 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  72
  73 /*
  74  * This is performance-critical, we want to do it O(1)
  75  *
  76  * the indexing order of this array favors 1:1 mappings
  77  * between pins and IRQs.
  78  */
  79
  80 static struct irq_pin_list {
  81         short apic, pin, next;
  82 } irq_2_pin[PIN_MAP_SIZE];
  83
  84 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  85 #ifdef CONFIG_PCI_MSI
  86 #define vector_to_irq(vector)   \
  87         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  88 #else
  89 #define vector_to_irq(vector)   (vector)
  90 #endif
  91
  92 #define __DO_ACTION(R, ACTION, FINAL)                                   \
  93                                                                         \
  94 {                                                                       \
  95         int pin;                                                        \
  96         struct irq_pin_list *entry = irq_2_pin + irq;                   \
  97                                                                         \
  98         BUG_ON(irq >= NR_IRQS);                                         \
  99         for (;;) {                                                      \
 100                 unsigned int reg;                                       \
 101                 pin = entry->pin;                                       \
 102                 if (pin == -1)                                          \
 103                         break;                                          \
 104                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 105                 reg ACTION;                                             \
 106                 io_apic_modify(entry->apic, reg);                       \
 107                 if (!entry->next)                                       \
 108                         break;                                          \
 109                 entry = irq_2_pin + entry->next;                        \
 110         }                                                               \
 111         FINAL;                                                          \
 112 }
 113
 114 #ifdef CONFIG_SMP
 115 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 116 {
 117         unsigned long flags;
 118         unsigned int dest;
 119         cpumask_t tmp;
 120
 121         cpus_and(tmp, mask, cpu_online_map);
 122         if (cpus_empty(tmp))
 123                 tmp = TARGET_CPUS;
 124
 125         cpus_and(mask, tmp, CPU_MASK_ALL);
 126
 127         dest = cpu_mask_to_apicid(mask);
 128
 129         /*
 130          * Only the high 8 bits are valid.
 131          */
 132         dest = SET_APIC_LOGICAL_ID(dest);
 133
 134         spin_lock_irqsave(&ioapic_lock, flags);
 135         __DO_ACTION(1, = dest, )
 136         set_irq_info(irq, mask);
 137         spin_unlock_irqrestore(&ioapic_lock, flags);
 138 }
 139 #endif
 140
 141 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
 142
 143 /*
 144  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 145  * shared ISA-space IRQs, so we have to support them. We are super
 146  * fast in the common case, and fast for shared ISA-space IRQs.
 147  */
 148 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 149 {
 150         static int first_free_entry = NR_IRQS;
 151         struct irq_pin_list *entry = irq_2_pin + irq;
 152
 153         BUG_ON(irq >= NR_IRQS);
 154         while (entry->next)
 155                 entry = irq_2_pin + entry->next;
 156
 157         if (entry->pin != -1) {
 158                 entry->next = first_free_entry;
 159                 entry = irq_2_pin + entry->next;
 160                 if (++first_free_entry >= PIN_MAP_SIZE)
 161                         panic("io_apic.c: ran out of irq_2_pin entries!");
 162         }
 163         entry->apic = apic;
 164         entry->pin = pin;
 165 }
 166
 167
 168 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 169                                                                         \
 170         static void name##_IO_APIC_irq (unsigned int irq)               \
 171         __DO_ACTION(R, ACTION, FINAL)
 172
 173 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 174                                                 /* mask = 1 */
 175 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 176                                                 /* mask = 0 */
 177
 178 static void mask_IO_APIC_irq (unsigned int irq)
 179 {
 180         unsigned long flags;
 181
 182         spin_lock_irqsave(&ioapic_lock, flags);
 183         __mask_IO_APIC_irq(irq);
 184         spin_unlock_irqrestore(&ioapic_lock, flags);
 185 }
 186
 187 static void unmask_IO_APIC_irq (unsigned int irq)
 188 {
 189         unsigned long flags;
 190
 191         spin_lock_irqsave(&ioapic_lock, flags);
 192         __unmask_IO_APIC_irq(irq);
 193         spin_unlock_irqrestore(&ioapic_lock, flags);
 194 }
 195
 196 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 197 {
 198         struct IO_APIC_route_entry entry;
 199         unsigned long flags;
 200
 201         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 202         spin_lock_irqsave(&ioapic_lock, flags);
 203         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 204         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 205         spin_unlock_irqrestore(&ioapic_lock, flags);
 206         if (entry.delivery_mode == dest_SMI)
 207                 return;
 208         /*
 209          * Disable it in the IO-APIC irq-routing table:
 210          */
 211         memset(&entry, 0, sizeof(entry));
 212         entry.mask = 1;
 213         spin_lock_irqsave(&ioapic_lock, flags);
 214         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 215         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 216         spin_unlock_irqrestore(&ioapic_lock, flags);
 217 }
 218
 219 static void clear_IO_APIC (void)
 220 {
 221         int apic, pin;
 222
 223         for (apic = 0; apic < nr_ioapics; apic++)
 224                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 225                         clear_IO_APIC_pin(apic, pin);
 226 }
 227
 228 int skip_ioapic_setup;
 229 int ioapic_force;
 230
 231 /* dummy parsing: see setup.c */
 232
 233 static int __init disable_ioapic_setup(char *str)
 234 {
 235         skip_ioapic_setup = 1;
 236         return 1;
 237 }
 238
 239 static int __init enable_ioapic_setup(char *str)
 240 {
 241         ioapic_force = 1;
 242         skip_ioapic_setup = 0;
 243         return 1;
 244 }
 245
 246 __setup("noapic", disable_ioapic_setup);
 247 __setup("apic", enable_ioapic_setup);
 248
 249 static int __init setup_disable_8254_timer(char *s)
 250 {
 251         timer_over_8254 = -1;
 252         return 1;
 253 }
 254 static int __init setup_enable_8254_timer(char *s)
 255 {
 256         timer_over_8254 = 2;
 257         return 1;
 258 }
 259
 260 __setup("disable_8254_timer", setup_disable_8254_timer);
 261 __setup("enable_8254_timer", setup_enable_8254_timer);
 262
 263 #include <asm/pci-direct.h>
 264 #include <linux/pci_ids.h>
 265 #include <linux/pci.h>
 266
 267
 268 #ifdef CONFIG_ACPI
 269
 270 static int nvidia_hpet_detected __initdata;
 271
 272 static int __init nvidia_hpet_check(unsigned long phys, unsigned long size)
 273 {
 274         nvidia_hpet_detected = 1;
 275         return 0;
 276 }
 277 #endif
 278
 279 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 280    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 281    Use pci direct infrastructure because this runs before the PCI subsystem.
 282
 283    Can be overwritten with "apic"
 284
 285    And another hack to disable the IOMMU on VIA chipsets.
 286
 287    ... and others. Really should move this somewhere else.
 288
 289    Kludge-O-Rama. */
 290 void __init check_ioapic(void)
 291 {
 292         int num,slot,func;
 293         /* Poor man's PCI discovery */
 294         for (num = 0; num < 32; num++) {
 295                 for (slot = 0; slot < 32; slot++) {
 296                         for (func = 0; func < 8; func++) {
 297                                 u32 class;
 298                                 u32 vendor;
 299                                 u8 type;
 300                                 class = read_pci_config(num,slot,func,
 301                                                         PCI_CLASS_REVISION);
 302                                 if (class == 0xffffffff)
 303                                         break;
 304
 305                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 306                                         continue;
 307
 308                                 vendor = read_pci_config(num, slot, func,
 309                                                          PCI_VENDOR_ID);
 310                                 vendor &= 0xffff;
 311                                 switch (vendor) {
 312                                 case PCI_VENDOR_ID_VIA:
 313 #ifdef CONFIG_IOMMU
 314                                         if ((end_pfn > MAX_DMA32_PFN ||
 315                                              force_iommu) &&
 316                                             !iommu_aperture_allowed) {
 317                                                 printk(KERN_INFO
 318     "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n");
 319                                                 iommu_aperture_disabled = 1;
 320                                         }
 321 #endif
 322                                         return;
 323                                 case PCI_VENDOR_ID_NVIDIA:
 324 #ifdef CONFIG_ACPI
 325                                         /*
 326                                          * All timer overrides on Nvidia are
 327                                          * wrong unless HPET is enabled.
 328                                          */
 329                                         nvidia_hpet_detected = 0;
 330                                         acpi_table_parse(ACPI_HPET,
 331                                                         nvidia_hpet_check);
 332                                         if (nvidia_hpet_detected == 0) {
 333                                                 acpi_skip_timer_override = 1;
 334                                                 printk(KERN_INFO "Nvidia board "
 335                                                     "detected. Ignoring ACPI "
 336                                                     "timer override.\n");
 337                                         }
 338 #endif
 339                                         /* RED-PEN skip them on mptables too? */
 340                                         return;
 341
 342                                 /* This should be actually default, but
 343                                    for 2.6.16 let's do it for ATI only where
 344                                    it's really needed. */
 345                                 case PCI_VENDOR_ID_ATI:
 346                                         if (timer_over_8254 == 1) {
 347                                                 timer_over_8254 = 0;
 348                                         printk(KERN_INFO
 349                 "ATI board detected. Disabling timer routing over 8254.\n");
 350                                         }
 351                                         return;
 352                                 }
 353
 354
 355                                 /* No multi-function device? */
 356                                 type = read_pci_config_byte(num,slot,func,
 357                                                             PCI_HEADER_TYPE);
 358                                 if (!(type & 0x80))
 359                                         break;
 360                         }
 361                 }
 362         }
 363 }
 364
 365 /*
 366  * Find the IRQ entry number of a certain pin.
 367  */
 368 static int find_irq_entry(int apic, int pin, int type)
 369 {
 370         int i;
 371
 372         for (i = 0; i < mp_irq_entries; i++)
 373                 if (mp_irqs[i].mpc_irqtype == type &&
 374                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 375                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 376                     mp_irqs[i].mpc_dstirq == pin)
 377                         return i;
 378
 379         return -1;
 380 }
 381
 382 /*
 383  * Find the pin to which IRQ[irq] (ISA) is connected
 384  */
 385 static int __init find_isa_irq_pin(int irq, int type)
 386 {
 387         int i;
 388
 389         for (i = 0; i < mp_irq_entries; i++) {
 390                 int lbus = mp_irqs[i].mpc_srcbus;
 391
 392                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 393                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 394                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 395                     (mp_irqs[i].mpc_irqtype == type) &&
 396                     (mp_irqs[i].mpc_srcbusirq == irq))
 397
 398                         return mp_irqs[i].mpc_dstirq;
 399         }
 400         return -1;
 401 }
 402
 403 static int __init find_isa_irq_apic(int irq, int type)
 404 {
 405         int i;
 406
 407         for (i = 0; i < mp_irq_entries; i++) {
 408                 int lbus = mp_irqs[i].mpc_srcbus;
 409
 410                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 411                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 412                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 413                     (mp_irqs[i].mpc_irqtype == type) &&
 414                     (mp_irqs[i].mpc_srcbusirq == irq))
 415                         break;
 416         }
 417         if (i < mp_irq_entries) {
 418                 int apic;
 419                 for(apic = 0; apic < nr_ioapics; apic++) {
 420                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 421                                 return apic;
 422                 }
 423         }
 424
 425         return -1;
 426 }
 427
 428 /*
 429  * Find a specific PCI IRQ entry.
 430  * Not an __init, possibly needed by modules
 431  */
 432 static int pin_2_irq(int idx, int apic, int pin);
 433
 434 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 435 {
 436         int apic, i, best_guess = -1;
 437
 438         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 439                 bus, slot, pin);
 440         if (mp_bus_id_to_pci_bus[bus] == -1) {
 441                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 442                 return -1;
 443         }
 444         for (i = 0; i < mp_irq_entries; i++) {
 445                 int lbus = mp_irqs[i].mpc_srcbus;
 446
 447                 for (apic = 0; apic < nr_ioapics; apic++)
 448                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 449                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 450                                 break;
 451
 452                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 453                     !mp_irqs[i].mpc_irqtype &&
 454                     (bus == lbus) &&
 455                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 456                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 457
 458                         if (!(apic || IO_APIC_IRQ(irq)))
 459                                 continue;
 460
 461                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 462                                 return irq;
 463                         /*
 464                          * Use the first all-but-pin matching entry as a
 465                          * best-guess fuzzy result for broken mptables.
 466                          */
 467                         if (best_guess < 0)
 468                                 best_guess = irq;
 469                 }
 470         }
 471         BUG_ON(best_guess >= NR_IRQS);
 472         return best_guess;
 473 }
 474
 475 /*
 476  * EISA Edge/Level control register, ELCR
 477  */
 478 static int EISA_ELCR(unsigned int irq)
 479 {
 480         if (irq < 16) {
 481                 unsigned int port = 0x4d0 + (irq >> 3);
 482                 return (inb(port) >> (irq & 7)) & 1;
 483         }
 484         apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
 485         return 0;
 486 }
 487
 488 /* EISA interrupts are always polarity zero and can be edge or level
 489  * trigger depending on the ELCR value.  If an interrupt is listed as
 490  * EISA conforming in the MP table, that means its trigger type must
 491  * be read in from the ELCR */
 492
 493 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 494 #define default_EISA_polarity(idx)      (0)
 495
 496 /* ISA interrupts are always polarity zero edge triggered,
 497  * when listed as conforming in the MP table. */
 498
 499 #define default_ISA_trigger(idx)        (0)
 500 #define default_ISA_polarity(idx)       (0)
 501
 502 /* PCI interrupts are always polarity one level triggered,
 503  * when listed as conforming in the MP table. */
 504
 505 #define default_PCI_trigger(idx)        (1)
 506 #define default_PCI_polarity(idx)       (1)
 507
 508 /* MCA interrupts are always polarity zero level triggered,
 509  * when listed as conforming in the MP table. */
 510
 511 #define default_MCA_trigger(idx)        (1)
 512 #define default_MCA_polarity(idx)       (0)
 513
 514 static int __init MPBIOS_polarity(int idx)
 515 {
 516         int bus = mp_irqs[idx].mpc_srcbus;
 517         int polarity;
 518
 519         /*
 520          * Determine IRQ line polarity (high active or low active):
 521          */
 522         switch (mp_irqs[idx].mpc_irqflag & 3)
 523         {
 524                 case 0: /* conforms, ie. bus-type dependent polarity */
 525                 {
 526                         switch (mp_bus_id_to_type[bus])
 527                         {
 528                                 case MP_BUS_ISA: /* ISA pin */
 529                                 {
 530                                         polarity = default_ISA_polarity(idx);
 531                                         break;
 532                                 }
 533                                 case MP_BUS_EISA: /* EISA pin */
 534                                 {
 535                                         polarity = default_EISA_polarity(idx);
 536                                         break;
 537                                 }
 538                                 case MP_BUS_PCI: /* PCI pin */
 539                                 {
 540                                         polarity = default_PCI_polarity(idx);
 541                                         break;
 542                                 }
 543                                 case MP_BUS_MCA: /* MCA pin */
 544                                 {
 545                                         polarity = default_MCA_polarity(idx);
 546                                         break;
 547                                 }
 548                                 default:
 549                                 {
 550                                         printk(KERN_WARNING "broken BIOS!!\n");
 551                                         polarity = 1;
 552                                         break;
 553                                 }
 554                         }
 555                         break;
 556                 }
 557                 case 1: /* high active */
 558                 {
 559                         polarity = 0;
 560                         break;
 561                 }
 562                 case 2: /* reserved */
 563                 {
 564                         printk(KERN_WARNING "broken BIOS!!\n");
 565                         polarity = 1;
 566                         break;
 567                 }
 568                 case 3: /* low active */
 569                 {
 570                         polarity = 1;
 571                         break;
 572                 }
 573                 default: /* invalid */
 574                 {
 575                         printk(KERN_WARNING "broken BIOS!!\n");
 576                         polarity = 1;
 577                         break;
 578                 }
 579         }
 580         return polarity;
 581 }
 582
 583 static int MPBIOS_trigger(int idx)
 584 {
 585         int bus = mp_irqs[idx].mpc_srcbus;
 586         int trigger;
 587
 588         /*
 589          * Determine IRQ trigger mode (edge or level sensitive):
 590          */
 591         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 592         {
 593                 case 0: /* conforms, ie. bus-type dependent */
 594                 {
 595                         switch (mp_bus_id_to_type[bus])
 596                         {
 597                                 case MP_BUS_ISA: /* ISA pin */
 598                                 {
 599                                         trigger = default_ISA_trigger(idx);
 600                                         break;
 601                                 }
 602                                 case MP_BUS_EISA: /* EISA pin */
 603                                 {
 604                                         trigger = default_EISA_trigger(idx);
 605                                         break;
 606                                 }
 607                                 case MP_BUS_PCI: /* PCI pin */
 608                                 {
 609                                         trigger = default_PCI_trigger(idx);
 610                                         break;
 611                                 }
 612                                 case MP_BUS_MCA: /* MCA pin */
 613                                 {
 614                                         trigger = default_MCA_trigger(idx);
 615                                         break;
 616                                 }
 617                                 default:
 618                                 {
 619                                         printk(KERN_WARNING "broken BIOS!!\n");
 620                                         trigger = 1;
 621                                         break;
 622                                 }
 623                         }
 624                         break;
 625                 }
 626                 case 1: /* edge */
 627                 {
 628                         trigger = 0;
 629                         break;
 630                 }
 631                 case 2: /* reserved */
 632                 {
 633                         printk(KERN_WARNING "broken BIOS!!\n");
 634                         trigger = 1;
 635                         break;
 636                 }
 637                 case 3: /* level */
 638                 {
 639                         trigger = 1;
 640                         break;
 641                 }
 642                 default: /* invalid */
 643                 {
 644                         printk(KERN_WARNING "broken BIOS!!\n");
 645                         trigger = 0;
 646                         break;
 647                 }
 648         }
 649         return trigger;
 650 }
 651
 652 static inline int irq_polarity(int idx)
 653 {
 654         return MPBIOS_polarity(idx);
 655 }
 656
 657 static inline int irq_trigger(int idx)
 658 {
 659         return MPBIOS_trigger(idx);
 660 }
 661
 662 static int next_irq = 16;
 663
 664 /*
 665  * gsi_irq_sharing -- Name overload!  "irq" can be either a legacy IRQ
 666  * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
 667  * from ACPI, which can reach 800 in large boxen.
 668  *
 669  * Compact the sparse GSI space into a sequential IRQ series and reuse
 670  * vectors if possible.
 671  */
 672 int gsi_irq_sharing(int gsi)
 673 {
 674         int i, tries, vector;
 675
 676         BUG_ON(gsi >= NR_IRQ_VECTORS);
 677
 678         if (platform_legacy_irq(gsi))
 679                 return gsi;
 680
 681         if (gsi_2_irq[gsi] != 0xFF)
 682                 return (int)gsi_2_irq[gsi];
 683
 684         tries = NR_IRQS;
 685   try_again:
 686         vector = assign_irq_vector(gsi);
 687
 688         /*
 689          * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
 690          * use of vector and if found, return that IRQ.  However, we never want
 691          * to share legacy IRQs, which usually have a different trigger mode
 692          * than PCI.
 693          */
 694         for (i = 0; i < NR_IRQS; i++)
 695                 if (IO_APIC_VECTOR(i) == vector)
 696                         break;
 697         if (platform_legacy_irq(i)) {
 698                 if (--tries >= 0) {
 699                         IO_APIC_VECTOR(i) = 0;
 700                         goto try_again;
 701                 }
 702                 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
 703         }
 704         if (i < NR_IRQS) {
 705                 gsi_2_irq[gsi] = i;
 706                 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
 707                                 gsi, vector, i);
 708                 return i;
 709         }
 710
 711         i = next_irq++;
 712         BUG_ON(i >= NR_IRQS);
 713         gsi_2_irq[gsi] = i;
 714         IO_APIC_VECTOR(i) = vector;
 715         printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
 716                         gsi, vector, i);
 717         return i;
 718 }
 719
 720 static int pin_2_irq(int idx, int apic, int pin)
 721 {
 722         int irq, i;
 723         int bus = mp_irqs[idx].mpc_srcbus;
 724
 725         /*
 726          * Debugging check, we are in big trouble if this message pops up!
 727          */
 728         if (mp_irqs[idx].mpc_dstirq != pin)
 729                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 730
 731         switch (mp_bus_id_to_type[bus])
 732         {
 733                 case MP_BUS_ISA: /* ISA pin */
 734                 case MP_BUS_EISA:
 735                 case MP_BUS_MCA:
 736                 {
 737                         irq = mp_irqs[idx].mpc_srcbusirq;
 738                         break;
 739                 }
 740                 case MP_BUS_PCI: /* PCI pin */
 741                 {
 742                         /*
 743                          * PCI IRQs are mapped in order
 744                          */
 745                         i = irq = 0;
 746                         while (i < apic)
 747                                 irq += nr_ioapic_registers[i++];
 748                         irq += pin;
 749                         irq = gsi_irq_sharing(irq);
 750                         break;
 751                 }
 752                 default:
 753                 {
 754                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 755                         irq = 0;
 756                         break;
 757                 }
 758         }
 759         BUG_ON(irq >= NR_IRQS);
 760         return irq;
 761 }
 762
 763 static inline int IO_APIC_irq_trigger(int irq)
 764 {
 765         int apic, idx, pin;
 766
 767         for (apic = 0; apic < nr_ioapics; apic++) {
 768                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 769                         idx = find_irq_entry(apic,pin,mp_INT);
 770                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 771                                 return irq_trigger(idx);
 772                 }
 773         }
 774         /*
 775          * nonexistent IRQs are edge default
 776          */
 777         return 0;
 778 }
 779
 780 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 781 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
 782
 783 int assign_irq_vector(int irq)
 784 {
 785         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 786         unsigned long flags;
 787         int vector;
 788
 789         BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
 790
 791         spin_lock_irqsave(&vector_lock, flags);
 792
 793         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
 794                 spin_unlock_irqrestore(&vector_lock, flags);
 795                 return IO_APIC_VECTOR(irq);
 796         }
 797 next:
 798         current_vector += 8;
 799         if (current_vector == IA32_SYSCALL_VECTOR)
 800                 goto next;
 801
 802         if (current_vector >= FIRST_SYSTEM_VECTOR) {
 803                 /* If we run out of vectors on large boxen, must share them. */
 804                 offset = (offset + 1) % 8;
 805                 current_vector = FIRST_DEVICE_VECTOR + offset;
 806         }
 807
 808         vector = current_vector;
 809         vector_irq[vector] = irq;
 810         if (irq != AUTO_ASSIGN)
 811                 IO_APIC_VECTOR(irq) = vector;
 812
 813         spin_unlock_irqrestore(&vector_lock, flags);
 814
 815         return vector;
 816 }
 817
 818 extern void (*interrupt[NR_IRQS])(void);
 819 static struct hw_interrupt_type ioapic_level_type;
 820 static struct hw_interrupt_type ioapic_edge_type;
 821
 822 #define IOAPIC_AUTO     -1
 823 #define IOAPIC_EDGE     0
 824 #define IOAPIC_LEVEL    1
 825
 826 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 827 {
 828         unsigned idx;
 829
 830         idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
 831
 832         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 833                         trigger == IOAPIC_LEVEL)
 834                 irq_desc[idx].chip = &ioapic_level_type;
 835         else
 836                 irq_desc[idx].chip = &ioapic_edge_type;
 837         set_intr_gate(vector, interrupt[idx]);
 838 }
 839
 840 static void __init setup_IO_APIC_irqs(void)
 841 {
 842         struct IO_APIC_route_entry entry;
 843         int apic, pin, idx, irq, first_notcon = 1, vector;
 844         unsigned long flags;
 845
 846         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 847
 848         for (apic = 0; apic < nr_ioapics; apic++) {
 849         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 850
 851                 /*
 852                  * add it to the IO-APIC irq-routing table:
 853                  */
 854                 memset(&entry,0,sizeof(entry));
 855
 856                 entry.delivery_mode = INT_DELIVERY_MODE;
 857                 entry.dest_mode = INT_DEST_MODE;
 858                 entry.mask = 0;                         /* enable IRQ */
 859                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 860
 861                 idx = find_irq_entry(apic,pin,mp_INT);
 862                 if (idx == -1) {
 863                         if (first_notcon) {
 864                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 865                                 first_notcon = 0;
 866                         } else
 867                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 868                         continue;
 869                 }
 870
 871                 entry.trigger = irq_trigger(idx);
 872                 entry.polarity = irq_polarity(idx);
 873
 874                 if (irq_trigger(idx)) {
 875                         entry.trigger = 1;
 876                         entry.mask = 1;
 877                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 878                 }
 879
 880                 irq = pin_2_irq(idx, apic, pin);
 881                 add_pin_to_irq(irq, apic, pin);
 882
 883                 if (!apic && !IO_APIC_IRQ(irq))
 884                         continue;
 885
 886                 if (IO_APIC_IRQ(irq)) {
 887                         vector = assign_irq_vector(irq);
 888                         entry.vector = vector;
 889
 890                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 891                         if (!apic && (irq < 16))
 892                                 disable_8259A_irq(irq);
 893                 }
 894                 spin_lock_irqsave(&ioapic_lock, flags);
 895                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 896                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 897                 set_native_irq_info(irq, TARGET_CPUS);
 898                 spin_unlock_irqrestore(&ioapic_lock, flags);
 899         }
 900         }
 901
 902         if (!first_notcon)
 903                 apic_printk(APIC_VERBOSE," not connected.\n");
 904 }
 905
 906 /*
 907  * Set up the 8259A-master output pin as broadcast to all
 908  * CPUs.
 909  */
 910 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 911 {
 912         struct IO_APIC_route_entry entry;
 913         unsigned long flags;
 914
 915         memset(&entry,0,sizeof(entry));
 916
 917         disable_8259A_irq(0);
 918
 919         /* mask LVT0 */
 920         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 921
 922         /*
 923          * We use logical delivery to get the timer IRQ
 924          * to the first CPU.
 925          */
 926         entry.dest_mode = INT_DEST_MODE;
 927         entry.mask = 0;                                 /* unmask IRQ now */
 928         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 929         entry.delivery_mode = INT_DELIVERY_MODE;
 930         entry.polarity = 0;
 931         entry.trigger = 0;
 932         entry.vector = vector;
 933
 934         /*
 935          * The timer IRQ doesn't have to know that behind the
 936          * scene we have a 8259A-master in AEOI mode ...
 937          */
 938         irq_desc[0].chip = &ioapic_edge_type;
 939
 940         /*
 941          * Add it to the IO-APIC irq-routing table:
 942          */
 943         spin_lock_irqsave(&ioapic_lock, flags);
 944         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 945         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 946         spin_unlock_irqrestore(&ioapic_lock, flags);
 947
 948         enable_8259A_irq(0);
 949 }
 950
 951 void __init UNEXPECTED_IO_APIC(void)
 952 {
 953 }
 954
 955 void __apicdebuginit print_IO_APIC(void)
 956 {
 957         int apic, i;
 958         union IO_APIC_reg_00 reg_00;
 959         union IO_APIC_reg_01 reg_01;
 960         union IO_APIC_reg_02 reg_02;
 961         unsigned long flags;
 962
 963         if (apic_verbosity == APIC_QUIET)
 964                 return;
 965
 966         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 967         for (i = 0; i < nr_ioapics; i++)
 968                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 969                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 970
 971         /*
 972          * We are a bit conservative about what we expect.  We have to
 973          * know about every hardware change ASAP.
 974          */
 975         printk(KERN_INFO "testing the IO APIC.......................\n");
 976
 977         for (apic = 0; apic < nr_ioapics; apic++) {
 978
 979         spin_lock_irqsave(&ioapic_lock, flags);
 980         reg_00.raw = io_apic_read(apic, 0);
 981         reg_01.raw = io_apic_read(apic, 1);
 982         if (reg_01.bits.version >= 0x10)
 983                 reg_02.raw = io_apic_read(apic, 2);
 984         spin_unlock_irqrestore(&ioapic_lock, flags);
 985
 986         printk("\n");
 987         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 988         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 989         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 990         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 991                 UNEXPECTED_IO_APIC();
 992
 993         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 994         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 995         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 996                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 997                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 998                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 999                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1000                 (reg_01.bits.entries != 0x2E) &&
1001                 (reg_01.bits.entries != 0x3F) &&
1002                 (reg_01.bits.entries != 0x03)
1003         )
1004                 UNEXPECTED_IO_APIC();
1005
1006         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1007         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1008         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1009                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
1010                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1011                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1012                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1013                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1014         )
1015                 UNEXPECTED_IO_APIC();
1016         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1017                 UNEXPECTED_IO_APIC();
1018
1019         if (reg_01.bits.version >= 0x10) {
1020                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1021                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1022                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1023                         UNEXPECTED_IO_APIC();
1024         }
1025
1026         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1027
1028         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1029                           " Stat Dest Deli Vect:   \n");
1030
1031         for (i = 0; i <= reg_01.bits.entries; i++) {
1032                 struct IO_APIC_route_entry entry;
1033
1034                 spin_lock_irqsave(&ioapic_lock, flags);
1035                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1036                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1037                 spin_unlock_irqrestore(&ioapic_lock, flags);
1038
1039                 printk(KERN_DEBUG " %02x %03X %02X  ",
1040                         i,
1041                         entry.dest.logical.logical_dest,
1042                         entry.dest.physical.physical_dest
1043                 );
1044
1045                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1046                         entry.mask,
1047                         entry.trigger,
1048                         entry.irr,
1049                         entry.polarity,
1050                         entry.delivery_status,
1051                         entry.dest_mode,
1052                         entry.delivery_mode,
1053                         entry.vector
1054                 );
1055         }
1056         }
1057         if (use_pci_vector())
1058                 printk(KERN_INFO "Using vector-based indexing\n");
1059         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1060         for (i = 0; i < NR_IRQS; i++) {
1061                 struct irq_pin_list *entry = irq_2_pin + i;
1062                 if (entry->pin < 0)
1063                         continue;
1064                 if (use_pci_vector() && !platform_legacy_irq(i))
1065                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1066                 else
1067                         printk(KERN_DEBUG "IRQ%d ", i);
1068                 for (;;) {
1069                         printk("-> %d:%d", entry->apic, entry->pin);
1070                         if (!entry->next)
1071                                 break;
1072                         entry = irq_2_pin + entry->next;
1073                 }
1074                 printk("\n");
1075         }
1076
1077         printk(KERN_INFO ".................................... done.\n");
1078
1079         return;
1080 }
1081
1082 #if 0
1083
1084 static __apicdebuginit void print_APIC_bitfield (int base)
1085 {
1086         unsigned int v;
1087         int i, j;
1088
1089         if (apic_verbosity == APIC_QUIET)
1090                 return;
1091
1092         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1093         for (i = 0; i < 8; i++) {
1094                 v = apic_read(base + i*0x10);
1095                 for (j = 0; j < 32; j++) {
1096                         if (v & (1<<j))
1097                                 printk("1");
1098                         else
1099                                 printk("0");
1100                 }
1101                 printk("\n");
1102         }
1103 }
1104
1105 void __apicdebuginit print_local_APIC(void * dummy)
1106 {
1107         unsigned int v, ver, maxlvt;
1108
1109         if (apic_verbosity == APIC_QUIET)
1110                 return;
1111
1112         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1113                 smp_processor_id(), hard_smp_processor_id());
1114         v = apic_read(APIC_ID);
1115         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1116         v = apic_read(APIC_LVR);
1117         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1118         ver = GET_APIC_VERSION(v);
1119         maxlvt = get_maxlvt();
1120
1121         v = apic_read(APIC_TASKPRI);
1122         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1123
1124         v = apic_read(APIC_ARBPRI);
1125         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1126                 v & APIC_ARBPRI_MASK);
1127         v = apic_read(APIC_PROCPRI);
1128         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1129
1130         v = apic_read(APIC_EOI);
1131         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1132         v = apic_read(APIC_RRR);
1133         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1134         v = apic_read(APIC_LDR);
1135         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1136         v = apic_read(APIC_DFR);
1137         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1138         v = apic_read(APIC_SPIV);
1139         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1140
1141         printk(KERN_DEBUG "... APIC ISR field:\n");
1142         print_APIC_bitfield(APIC_ISR);
1143         printk(KERN_DEBUG "... APIC TMR field:\n");
1144         print_APIC_bitfield(APIC_TMR);
1145         printk(KERN_DEBUG "... APIC IRR field:\n");
1146         print_APIC_bitfield(APIC_IRR);
1147
1148         v = apic_read(APIC_ESR);
1149         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1150
1151         v = apic_read(APIC_ICR);
1152         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1153         v = apic_read(APIC_ICR2);
1154         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1155
1156         v = apic_read(APIC_LVTT);
1157         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1158
1159         if (maxlvt > 3) {                       /* PC is LVT#4. */
1160                 v = apic_read(APIC_LVTPC);
1161                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1162         }
1163         v = apic_read(APIC_LVT0);
1164         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1165         v = apic_read(APIC_LVT1);
1166         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1167
1168         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1169                 v = apic_read(APIC_LVTERR);
1170                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1171         }
1172
1173         v = apic_read(APIC_TMICT);
1174         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1175         v = apic_read(APIC_TMCCT);
1176         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1177         v = apic_read(APIC_TDCR);
1178         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1179         printk("\n");
1180 }
1181
1182 void print_all_local_APICs (void)
1183 {
1184         on_each_cpu(print_local_APIC, NULL, 1, 1);
1185 }
1186
1187 void __apicdebuginit print_PIC(void)
1188 {
1189         unsigned int v;
1190         unsigned long flags;
1191
1192         if (apic_verbosity == APIC_QUIET)
1193                 return;
1194
1195         printk(KERN_DEBUG "\nprinting PIC contents\n");
1196
1197         spin_lock_irqsave(&i8259A_lock, flags);
1198
1199         v = inb(0xa1) << 8 | inb(0x21);
1200         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1201
1202         v = inb(0xa0) << 8 | inb(0x20);
1203         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1204
1205         outb(0x0b,0xa0);
1206         outb(0x0b,0x20);
1207         v = inb(0xa0) << 8 | inb(0x20);
1208         outb(0x0a,0xa0);
1209         outb(0x0a,0x20);
1210
1211         spin_unlock_irqrestore(&i8259A_lock, flags);
1212
1213         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1214
1215         v = inb(0x4d1) << 8 | inb(0x4d0);
1216         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1217 }
1218
1219 #endif  /*  0  */
1220
1221 static void __init enable_IO_APIC(void)
1222 {
1223         union IO_APIC_reg_01 reg_01;
1224         int i8259_apic, i8259_pin;
1225         int i, apic;
1226         unsigned long flags;
1227
1228         for (i = 0; i < PIN_MAP_SIZE; i++) {
1229                 irq_2_pin[i].pin = -1;
1230                 irq_2_pin[i].next = 0;
1231         }
1232
1233         /*
1234          * The number of IO-APIC IRQ registers (== #pins):
1235          */
1236         for (apic = 0; apic < nr_ioapics; apic++) {
1237                 spin_lock_irqsave(&ioapic_lock, flags);
1238                 reg_01.raw = io_apic_read(apic, 1);
1239                 spin_unlock_irqrestore(&ioapic_lock, flags);
1240                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1241         }
1242         for(apic = 0; apic < nr_ioapics; apic++) {
1243                 int pin;
1244                 /* See if any of the pins is in ExtINT mode */
1245                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1246                         struct IO_APIC_route_entry entry;
1247                         spin_lock_irqsave(&ioapic_lock, flags);
1248                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1249                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1250                         spin_unlock_irqrestore(&ioapic_lock, flags);
1251
1252
1253                         /* If the interrupt line is enabled and in ExtInt mode
1254                          * I have found the pin where the i8259 is connected.
1255                          */
1256                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1257                                 ioapic_i8259.apic = apic;
1258                                 ioapic_i8259.pin  = pin;
1259                                 goto found_i8259;
1260                         }
1261                 }
1262         }
1263  found_i8259:
1264         /* Look to see what if the MP table has reported the ExtINT */
1265         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1266         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1267         /* Trust the MP table if nothing is setup in the hardware */
1268         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1269                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1270                 ioapic_i8259.pin  = i8259_pin;
1271                 ioapic_i8259.apic = i8259_apic;
1272         }
1273         /* Complain if the MP table and the hardware disagree */
1274         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1275                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1276         {
1277                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1278         }
1279
1280         /*
1281          * Do not trust the IO-APIC being empty at bootup
1282          */
1283         clear_IO_APIC();
1284 }
1285
1286 /*
1287  * Not an __init, needed by the reboot code
1288  */
1289 void disable_IO_APIC(void)
1290 {
1291         /*
1292          * Clear the IO-APIC before rebooting:
1293          */
1294         clear_IO_APIC();
1295
1296         /*
1297          * If the i8259 is routed through an IOAPIC
1298          * Put that IOAPIC in virtual wire mode
1299          * so legacy interrupts can be delivered.
1300          */
1301         if (ioapic_i8259.pin != -1) {
1302                 struct IO_APIC_route_entry entry;
1303                 unsigned long flags;
1304
1305                 memset(&entry, 0, sizeof(entry));
1306                 entry.mask            = 0; /* Enabled */
1307                 entry.trigger         = 0; /* Edge */
1308                 entry.irr             = 0;
1309                 entry.polarity        = 0; /* High */
1310                 entry.delivery_status = 0;
1311                 entry.dest_mode       = 0; /* Physical */
1312                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1313                 entry.vector          = 0;
1314                 entry.dest.physical.physical_dest =
1315                                         GET_APIC_ID(apic_read(APIC_ID));
1316
1317                 /*
1318                  * Add it to the IO-APIC irq-routing table:
1319                  */
1320                 spin_lock_irqsave(&ioapic_lock, flags);
1321                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1322                         *(((int *)&entry)+1));
1323                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1324                         *(((int *)&entry)+0));
1325                 spin_unlock_irqrestore(&ioapic_lock, flags);
1326         }
1327
1328         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1329 }
1330
1331 /*
1332  * function to set the IO-APIC physical IDs based on the
1333  * values stored in the MPC table.
1334  *
1335  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1336  */
1337
1338 static void __init setup_ioapic_ids_from_mpc (void)
1339 {
1340         union IO_APIC_reg_00 reg_00;
1341         int apic;
1342         int i;
1343         unsigned char old_id;
1344         unsigned long flags;
1345
1346         /*
1347          * Set the IOAPIC ID to the value stored in the MPC table.
1348          */
1349         for (apic = 0; apic < nr_ioapics; apic++) {
1350
1351                 /* Read the register 0 value */
1352                 spin_lock_irqsave(&ioapic_lock, flags);
1353                 reg_00.raw = io_apic_read(apic, 0);
1354                 spin_unlock_irqrestore(&ioapic_lock, flags);
1355
1356                 old_id = mp_ioapics[apic].mpc_apicid;
1357
1358
1359                 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1360
1361
1362                 /*
1363                  * We need to adjust the IRQ routing table
1364                  * if the ID changed.
1365                  */
1366                 if (old_id != mp_ioapics[apic].mpc_apicid)
1367                         for (i = 0; i < mp_irq_entries; i++)
1368                                 if (mp_irqs[i].mpc_dstapic == old_id)
1369                                         mp_irqs[i].mpc_dstapic
1370                                                 = mp_ioapics[apic].mpc_apicid;
1371
1372                 /*
1373                  * Read the right value from the MPC table and
1374                  * write it into the ID register.
1375                  */
1376                 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1377                                 mp_ioapics[apic].mpc_apicid);
1378
1379                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1380                 spin_lock_irqsave(&ioapic_lock, flags);
1381                 io_apic_write(apic, 0, reg_00.raw);
1382                 spin_unlock_irqrestore(&ioapic_lock, flags);
1383
1384                 /*
1385                  * Sanity check
1386                  */
1387                 spin_lock_irqsave(&ioapic_lock, flags);
1388                 reg_00.raw = io_apic_read(apic, 0);
1389                 spin_unlock_irqrestore(&ioapic_lock, flags);
1390                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1391                         printk("could not set ID!\n");
1392                 else
1393                         apic_printk(APIC_VERBOSE," ok.\n");
1394         }
1395 }
1396
1397 /*
1398  * There is a nasty bug in some older SMP boards, their mptable lies
1399  * about the timer IRQ. We do the following to work around the situation:
1400  *
1401  *      - timer IRQ defaults to IO-APIC IRQ
1402  *      - if this function detects that timer IRQs are defunct, then we fall
1403  *        back to ISA timer IRQs
1404  */
1405 static int __init timer_irq_works(void)
1406 {
1407         unsigned long t1 = jiffies;
1408
1409         local_irq_enable();
1410         /* Let ten ticks pass... */
1411         mdelay((10 * 1000) / HZ);
1412
1413         /*
1414          * Expect a few ticks at least, to be sure some possible
1415          * glue logic does not lock up after one or two first
1416          * ticks in a non-ExtINT mode.  Also the local APIC
1417          * might have cached one ExtINT interrupt.  Finally, at
1418          * least one tick may be lost due to delays.
1419          */
1420
1421         /* jiffies wrap? */
1422         if (jiffies - t1 > 4)
1423                 return 1;
1424         return 0;
1425 }
1426
1427 /*
1428  * In the SMP+IOAPIC case it might happen that there are an unspecified
1429  * number of pending IRQ events unhandled. These cases are very rare,
1430  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1431  * better to do it this way as thus we do not have to be aware of
1432  * 'pending' interrupts in the IRQ path, except at this point.
1433  */
1434 /*
1435  * Edge triggered needs to resend any interrupt
1436  * that was delayed but this is now handled in the device
1437  * independent code.
1438  */
1439
1440 /*
1441  * Starting up a edge-triggered IO-APIC interrupt is
1442  * nasty - we need to make sure that we get the edge.
1443  * If it is already asserted for some reason, we need
1444  * return 1 to indicate that is was pending.
1445  *
1446  * This is not complete - we should be able to fake
1447  * an edge even if it isn't on the 8259A...
1448  */
1449
1450 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1451 {
1452         int was_pending = 0;
1453         unsigned long flags;
1454
1455         spin_lock_irqsave(&ioapic_lock, flags);
1456         if (irq < 16) {
1457                 disable_8259A_irq(irq);
1458                 if (i8259A_irq_pending(irq))
1459                         was_pending = 1;
1460         }
1461         __unmask_IO_APIC_irq(irq);
1462         spin_unlock_irqrestore(&ioapic_lock, flags);
1463
1464         return was_pending;
1465 }
1466
1467 /*
1468  * Once we have recorded IRQ_PENDING already, we can mask the
1469  * interrupt for real. This prevents IRQ storms from unhandled
1470  * devices.
1471  */
1472 static void ack_edge_ioapic_irq(unsigned int irq)
1473 {
1474         move_irq(irq);
1475         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1476                                         == (IRQ_PENDING | IRQ_DISABLED))
1477                 mask_IO_APIC_irq(irq);
1478         ack_APIC_irq();
1479 }
1480
1481 /*
1482  * Level triggered interrupts can just be masked,
1483  * and shutting down and starting up the interrupt
1484  * is the same as enabling and disabling them -- except
1485  * with a startup need to return a "was pending" value.
1486  *
1487  * Level triggered interrupts are special because we
1488  * do not touch any IO-APIC register while handling
1489  * them. We ack the APIC in the end-IRQ handler, not
1490  * in the start-IRQ-handler. Protection against reentrance
1491  * from the same interrupt is still provided, both by the
1492  * generic IRQ layer and by the fact that an unacked local
1493  * APIC does not accept IRQs.
1494  */
1495 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1496 {
1497         unmask_IO_APIC_irq(irq);
1498
1499         return 0; /* don't check for pending */
1500 }
1501
1502 static void end_level_ioapic_irq (unsigned int irq)
1503 {
1504         move_irq(irq);
1505         ack_APIC_irq();
1506 }
1507
1508 #ifdef CONFIG_PCI_MSI
1509 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1510 {
1511         int irq = vector_to_irq(vector);
1512
1513         return startup_edge_ioapic_irq(irq);
1514 }
1515
1516 static void ack_edge_ioapic_vector(unsigned int vector)
1517 {
1518         int irq = vector_to_irq(vector);
1519
1520         move_native_irq(vector);
1521         ack_edge_ioapic_irq(irq);
1522 }
1523
1524 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1525 {
1526         int irq = vector_to_irq(vector);
1527
1528         return startup_level_ioapic_irq (irq);
1529 }
1530
1531 static void end_level_ioapic_vector (unsigned int vector)
1532 {
1533         int irq = vector_to_irq(vector);
1534
1535         move_native_irq(vector);
1536         end_level_ioapic_irq(irq);
1537 }
1538
1539 static void mask_IO_APIC_vector (unsigned int vector)
1540 {
1541         int irq = vector_to_irq(vector);
1542
1543         mask_IO_APIC_irq(irq);
1544 }
1545
1546 static void unmask_IO_APIC_vector (unsigned int vector)
1547 {
1548         int irq = vector_to_irq(vector);
1549
1550         unmask_IO_APIC_irq(irq);
1551 }
1552
1553 #ifdef CONFIG_SMP
1554 static void set_ioapic_affinity_vector (unsigned int vector,
1555                                         cpumask_t cpu_mask)
1556 {
1557         int irq = vector_to_irq(vector);
1558
1559         set_native_irq_info(vector, cpu_mask);
1560         set_ioapic_affinity_irq(irq, cpu_mask);
1561 }
1562 #endif // CONFIG_SMP
1563 #endif // CONFIG_PCI_MSI
1564
1565 static int ioapic_retrigger(unsigned int irq)
1566 {
1567         send_IPI_self(IO_APIC_VECTOR(irq));
1568
1569         return 1;
1570 }
1571
1572 /*
1573  * Level and edge triggered IO-APIC interrupts need different handling,
1574  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1575  * handled with the level-triggered descriptor, but that one has slightly
1576  * more overhead. Level-triggered interrupts cannot be handled with the
1577  * edge-triggered handler, without risking IRQ storms and other ugly
1578  * races.
1579  */
1580
1581 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1582         .typename = "IO-APIC-edge",
1583         .startup        = startup_edge_ioapic,
1584         .shutdown       = shutdown_edge_ioapic,
1585         .enable         = enable_edge_ioapic,
1586         .disable        = disable_edge_ioapic,
1587         .ack            = ack_edge_ioapic,
1588         .end            = end_edge_ioapic,
1589 #ifdef CONFIG_SMP
1590         .set_affinity = set_ioapic_affinity,
1591 #endif
1592         .retrigger      = ioapic_retrigger,
1593 };
1594
1595 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1596         .typename = "IO-APIC-level",
1597         .startup        = startup_level_ioapic,
1598         .shutdown       = shutdown_level_ioapic,
1599         .enable         = enable_level_ioapic,
1600         .disable        = disable_level_ioapic,
1601         .ack            = mask_and_ack_level_ioapic,
1602         .end            = end_level_ioapic,
1603 #ifdef CONFIG_SMP
1604         .set_affinity = set_ioapic_affinity,
1605 #endif
1606         .retrigger      = ioapic_retrigger,
1607 };
1608
1609 static inline void init_IO_APIC_traps(void)
1610 {
1611         int irq;
1612
1613         /*
1614          * NOTE! The local APIC isn't very good at handling
1615          * multiple interrupts at the same interrupt level.
1616          * As the interrupt level is determined by taking the
1617          * vector number and shifting that right by 4, we
1618          * want to spread these out a bit so that they don't
1619          * all fall in the same interrupt level.
1620          *
1621          * Also, we've got to be careful not to trash gate
1622          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1623          */
1624         for (irq = 0; irq < NR_IRQS ; irq++) {
1625                 int tmp = irq;
1626                 if (use_pci_vector()) {
1627                         if (!platform_legacy_irq(tmp))
1628                                 if ((tmp = vector_to_irq(tmp)) == -1)
1629                                         continue;
1630                 }
1631                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1632                         /*
1633                          * Hmm.. We don't have an entry for this,
1634                          * so default to an old-fashioned 8259
1635                          * interrupt if we can..
1636                          */
1637                         if (irq < 16)
1638                                 make_8259A_irq(irq);
1639                         else
1640                                 /* Strange. Oh, well.. */
1641                                 irq_desc[irq].chip = &no_irq_type;
1642                 }
1643         }
1644 }
1645
1646 static void enable_lapic_irq (unsigned int irq)
1647 {
1648         unsigned long v;
1649
1650         v = apic_read(APIC_LVT0);
1651         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1652 }
1653
1654 static void disable_lapic_irq (unsigned int irq)
1655 {
1656         unsigned long v;
1657
1658         v = apic_read(APIC_LVT0);
1659         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1660 }
1661
1662 static void ack_lapic_irq (unsigned int irq)
1663 {
1664         ack_APIC_irq();
1665 }
1666
1667 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1668
1669 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1670         .typename = "local-APIC-edge",
1671         .startup = NULL, /* startup_irq() not used for IRQ0 */
1672         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1673         .enable = enable_lapic_irq,
1674         .disable = disable_lapic_irq,
1675         .ack = ack_lapic_irq,
1676         .end = end_lapic_irq,
1677 };
1678
1679 static void setup_nmi (void)
1680 {
1681         /*
1682          * Dirty trick to enable the NMI watchdog ...
1683          * We put the 8259A master into AEOI mode and
1684          * unmask on all local APICs LVT0 as NMI.
1685          *
1686          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1687          * is from Maciej W. Rozycki - so we do not have to EOI from
1688          * the NMI handler or the timer interrupt.
1689          */
1690         printk(KERN_INFO "activating NMI Watchdog ...");
1691
1692         enable_NMI_through_LVT0(NULL);
1693
1694         printk(" done.\n");
1695 }
1696
1697 /*
1698  * This looks a bit hackish but it's about the only one way of sending
1699  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1700  * not support the ExtINT mode, unfortunately.  We need to send these
1701  * cycles as some i82489DX-based boards have glue logic that keeps the
1702  * 8259A interrupt line asserted until INTA.  --macro
1703  */
1704 static inline void unlock_ExtINT_logic(void)
1705 {
1706         int apic, pin, i;
1707         struct IO_APIC_route_entry entry0, entry1;
1708         unsigned char save_control, save_freq_select;
1709         unsigned long flags;
1710
1711         pin  = find_isa_irq_pin(8, mp_INT);
1712         apic = find_isa_irq_apic(8, mp_INT);
1713         if (pin == -1)
1714                 return;
1715
1716         spin_lock_irqsave(&ioapic_lock, flags);
1717         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1718         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1719         spin_unlock_irqrestore(&ioapic_lock, flags);
1720         clear_IO_APIC_pin(apic, pin);
1721
1722         memset(&entry1, 0, sizeof(entry1));
1723
1724         entry1.dest_mode = 0;                   /* physical delivery */
1725         entry1.mask = 0;                        /* unmask IRQ now */
1726         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1727         entry1.delivery_mode = dest_ExtINT;
1728         entry1.polarity = entry0.polarity;
1729         entry1.trigger = 0;
1730         entry1.vector = 0;
1731
1732         spin_lock_irqsave(&ioapic_lock, flags);
1733         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1734         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1735         spin_unlock_irqrestore(&ioapic_lock, flags);
1736
1737         save_control = CMOS_READ(RTC_CONTROL);
1738         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1739         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1740                    RTC_FREQ_SELECT);
1741         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1742
1743         i = 100;
1744         while (i-- > 0) {
1745                 mdelay(10);
1746                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1747                         i -= 10;
1748         }
1749
1750         CMOS_WRITE(save_control, RTC_CONTROL);
1751         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1752         clear_IO_APIC_pin(apic, pin);
1753
1754         spin_lock_irqsave(&ioapic_lock, flags);
1755         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1756         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1757         spin_unlock_irqrestore(&ioapic_lock, flags);
1758 }
1759
1760 int timer_uses_ioapic_pin_0;
1761
1762 /*
1763  * This code may look a bit paranoid, but it's supposed to cooperate with
1764  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1765  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1766  * fanatically on his truly buggy board.
1767  *
1768  * FIXME: really need to revamp this for modern platforms only.
1769  */
1770 static inline void check_timer(void)
1771 {
1772         int apic1, pin1, apic2, pin2;
1773         int vector;
1774
1775         /*
1776          * get/set the timer IRQ vector:
1777          */
1778         disable_8259A_irq(0);
1779         vector = assign_irq_vector(0);
1780         set_intr_gate(vector, interrupt[0]);
1781
1782         /*
1783          * Subtle, code in do_timer_interrupt() expects an AEOI
1784          * mode for the 8259A whenever interrupts are routed
1785          * through I/O APICs.  Also IRQ0 has to be enabled in
1786          * the 8259A which implies the virtual wire has to be
1787          * disabled in the local APIC.
1788          */
1789         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1790         init_8259A(1);
1791         if (timer_over_8254 > 0)
1792                 enable_8259A_irq(0);
1793
1794         pin1  = find_isa_irq_pin(0, mp_INT);
1795         apic1 = find_isa_irq_apic(0, mp_INT);
1796         pin2  = ioapic_i8259.pin;
1797         apic2 = ioapic_i8259.apic;
1798
1799         if (pin1 == 0)
1800                 timer_uses_ioapic_pin_0 = 1;
1801
1802         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1803                 vector, apic1, pin1, apic2, pin2);
1804
1805         if (pin1 != -1) {
1806                 /*
1807                  * Ok, does IRQ0 through the IOAPIC work?
1808                  */
1809                 unmask_IO_APIC_irq(0);
1810                 if (!no_timer_check && timer_irq_works()) {
1811                         nmi_watchdog_default();
1812                         if (nmi_watchdog == NMI_IO_APIC) {
1813                                 disable_8259A_irq(0);
1814                                 setup_nmi();
1815                                 enable_8259A_irq(0);
1816                         }
1817                         if (disable_timer_pin_1 > 0)
1818                                 clear_IO_APIC_pin(0, pin1);
1819                         return;
1820                 }
1821                 clear_IO_APIC_pin(apic1, pin1);
1822                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1823                                 "connected to IO-APIC\n");
1824         }
1825
1826         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1827                                 "through the 8259A ... ");
1828         if (pin2 != -1) {
1829                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1830                         apic2, pin2);
1831                 /*
1832                  * legacy devices should be connected to IO APIC #0
1833                  */
1834                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1835                 if (timer_irq_works()) {
1836                         apic_printk(APIC_VERBOSE," works.\n");
1837                         nmi_watchdog_default();
1838                         if (nmi_watchdog == NMI_IO_APIC) {
1839                                 setup_nmi();
1840                         }
1841                         return;
1842                 }
1843                 /*
1844                  * Cleanup, just in case ...
1845                  */
1846                 clear_IO_APIC_pin(apic2, pin2);
1847         }
1848         apic_printk(APIC_VERBOSE," failed.\n");
1849
1850         if (nmi_watchdog == NMI_IO_APIC) {
1851                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1852                 nmi_watchdog = 0;
1853         }
1854
1855         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1856
1857         disable_8259A_irq(0);
1858         irq_desc[0].chip = &lapic_irq_type;
1859         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1860         enable_8259A_irq(0);
1861
1862         if (timer_irq_works()) {
1863                 apic_printk(APIC_VERBOSE," works.\n");
1864                 return;
1865         }
1866         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1867         apic_printk(APIC_VERBOSE," failed.\n");
1868
1869         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1870
1871         init_8259A(0);
1872         make_8259A_irq(0);
1873         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1874
1875         unlock_ExtINT_logic();
1876
1877         if (timer_irq_works()) {
1878                 apic_printk(APIC_VERBOSE," works.\n");
1879                 return;
1880         }
1881         apic_printk(APIC_VERBOSE," failed :(.\n");
1882         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1883 }
1884
1885 static int __init notimercheck(char *s)
1886 {
1887         no_timer_check = 1;
1888         return 1;
1889 }
1890 __setup("no_timer_check", notimercheck);
1891
1892 /*
1893  *
1894  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1895  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1896  *   Linux doesn't really care, as it's not actually used
1897  *   for any interrupt handling anyway.
1898  */
1899 #define PIC_IRQS        (1<<2)
1900
1901 void __init setup_IO_APIC(void)
1902 {
1903         enable_IO_APIC();
1904
1905         if (acpi_ioapic)
1906                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1907         else
1908                 io_apic_irqs = ~PIC_IRQS;
1909
1910         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1911
1912         /*
1913          * Set up the IO-APIC IRQ routing table.
1914          */
1915         if (!acpi_ioapic)
1916                 setup_ioapic_ids_from_mpc();
1917         sync_Arb_IDs();
1918         setup_IO_APIC_irqs();
1919         init_IO_APIC_traps();
1920         check_timer();
1921         if (!acpi_ioapic)
1922                 print_IO_APIC();
1923 }
1924
1925 struct sysfs_ioapic_data {
1926         struct sys_device dev;
1927         struct IO_APIC_route_entry entry[0];
1928 };
1929 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1930
1931 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1932 {
1933         struct IO_APIC_route_entry *entry;
1934         struct sysfs_ioapic_data *data;
1935         unsigned long flags;
1936         int i;
1937
1938         data = container_of(dev, struct sysfs_ioapic_data, dev);
1939         entry = data->entry;
1940         spin_lock_irqsave(&ioapic_lock, flags);
1941         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1942                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1943                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1944         }
1945         spin_unlock_irqrestore(&ioapic_lock, flags);
1946
1947         return 0;
1948 }
1949
1950 static int ioapic_resume(struct sys_device *dev)
1951 {
1952         struct IO_APIC_route_entry *entry;
1953         struct sysfs_ioapic_data *data;
1954         unsigned long flags;
1955         union IO_APIC_reg_00 reg_00;
1956         int i;
1957
1958         data = container_of(dev, struct sysfs_ioapic_data, dev);
1959         entry = data->entry;
1960
1961         spin_lock_irqsave(&ioapic_lock, flags);
1962         reg_00.raw = io_apic_read(dev->id, 0);
1963         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1964                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1965                 io_apic_write(dev->id, 0, reg_00.raw);
1966         }
1967         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1968                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
1969                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
1970         }
1971         spin_unlock_irqrestore(&ioapic_lock, flags);
1972
1973         return 0;
1974 }
1975
1976 static struct sysdev_class ioapic_sysdev_class = {
1977         set_kset_name("ioapic"),
1978         .suspend = ioapic_suspend,
1979         .resume = ioapic_resume,
1980 };
1981
1982 static int __init ioapic_init_sysfs(void)
1983 {
1984         struct sys_device * dev;
1985         int i, size, error = 0;
1986
1987         error = sysdev_class_register(&ioapic_sysdev_class);
1988         if (error)
1989                 return error;
1990
1991         for (i = 0; i < nr_ioapics; i++ ) {
1992                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1993                         * sizeof(struct IO_APIC_route_entry);
1994                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1995                 if (!mp_ioapic_data[i]) {
1996                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1997                         continue;
1998                 }
1999                 memset(mp_ioapic_data[i], 0, size);
2000                 dev = &mp_ioapic_data[i]->dev;
2001                 dev->id = i;
2002                 dev->cls = &ioapic_sysdev_class;
2003                 error = sysdev_register(dev);
2004                 if (error) {
2005                         kfree(mp_ioapic_data[i]);
2006                         mp_ioapic_data[i] = NULL;
2007                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2008                         continue;
2009                 }
2010         }
2011
2012         return 0;
2013 }
2014
2015 device_initcall(ioapic_init_sysfs);
2016
2017 /* --------------------------------------------------------------------------
2018                           ACPI-based IOAPIC Configuration
2019    -------------------------------------------------------------------------- */
2020
2021 #ifdef CONFIG_ACPI
2022
2023 #define IO_APIC_MAX_ID          0xFE
2024
2025 int __init io_apic_get_version (int ioapic)
2026 {
2027         union IO_APIC_reg_01    reg_01;
2028         unsigned long flags;
2029
2030         spin_lock_irqsave(&ioapic_lock, flags);
2031         reg_01.raw = io_apic_read(ioapic, 1);
2032         spin_unlock_irqrestore(&ioapic_lock, flags);
2033
2034         return reg_01.bits.version;
2035 }
2036
2037
2038 int __init io_apic_get_redir_entries (int ioapic)
2039 {
2040         union IO_APIC_reg_01    reg_01;
2041         unsigned long flags;
2042
2043         spin_lock_irqsave(&ioapic_lock, flags);
2044         reg_01.raw = io_apic_read(ioapic, 1);
2045         spin_unlock_irqrestore(&ioapic_lock, flags);
2046
2047         return reg_01.bits.entries;
2048 }
2049
2050
2051 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2052 {
2053         struct IO_APIC_route_entry entry;
2054         unsigned long flags;
2055
2056         if (!IO_APIC_IRQ(irq)) {
2057                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2058                         ioapic);
2059                 return -EINVAL;
2060         }
2061
2062         /*
2063          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2064          * Note that we mask (disable) IRQs now -- these get enabled when the
2065          * corresponding device driver registers for this IRQ.
2066          */
2067
2068         memset(&entry,0,sizeof(entry));
2069
2070         entry.delivery_mode = INT_DELIVERY_MODE;
2071         entry.dest_mode = INT_DEST_MODE;
2072         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2073         entry.trigger = triggering;
2074         entry.polarity = polarity;
2075         entry.mask = 1;                                  /* Disabled (masked) */
2076
2077         irq = gsi_irq_sharing(irq);
2078         /*
2079          * IRQs < 16 are already in the irq_2_pin[] map
2080          */
2081         if (irq >= 16)
2082                 add_pin_to_irq(irq, ioapic, pin);
2083
2084         entry.vector = assign_irq_vector(irq);
2085
2086         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2087                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2088                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2089                triggering, polarity);
2090
2091         ioapic_register_intr(irq, entry.vector, triggering);
2092
2093         if (!ioapic && (irq < 16))
2094                 disable_8259A_irq(irq);
2095
2096         spin_lock_irqsave(&ioapic_lock, flags);
2097         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2098         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2099         set_native_irq_info(use_pci_vector() ?  entry.vector : irq, TARGET_CPUS);
2100         spin_unlock_irqrestore(&ioapic_lock, flags);
2101
2102         return 0;
2103 }
2104
2105 #endif /* CONFIG_ACPI */
2106
2107
2108 /*
2109  * This function currently is only a helper for the i386 smp boot process where
2110  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2111  * so mask in all cases should simply be TARGET_CPUS
2112  */
2113 #ifdef CONFIG_SMP
2114 void __init setup_ioapic_dest(void)
2115 {
2116         int pin, ioapic, irq, irq_entry;
2117
2118         if (skip_ioapic_setup == 1)
2119                 return;
2120
2121         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2122                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2123                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2124                         if (irq_entry == -1)
2125                                 continue;
2126                         irq = pin_2_irq(irq_entry, ioapic, pin);
2127                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
2128                 }
2129
2130         }
2131 }
2132 #endif