arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/acpi.h>
  31 #include <linux/sysdev.h>
  32 #ifdef CONFIG_ACPI
  33 #include <acpi/acpi_bus.h>
  34 #endif
  35
  36 #include <asm/io.h>
  37 #include <asm/smp.h>
  38 #include <asm/desc.h>
  39 #include <asm/proto.h>
  40 #include <asm/mach_apic.h>
  41 #include <asm/acpi.h>
  42 #include <asm/dma.h>
  43 #include <asm/nmi.h>
  44
  45 #define __apicdebuginit  __init
  46
  47 int sis_apic_bug; /* not actually supported, dummy for compile */
  48
  49 static int no_timer_check;
  50
  51 int disable_timer_pin_1 __initdata;
  52
  53 int timer_over_8254 __initdata = 0;
  54
  55 /* Where if anywhere is the i8259 connect in external int mode */
  56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  57
  58 static DEFINE_SPINLOCK(ioapic_lock);
  59 static DEFINE_SPINLOCK(vector_lock);
  60
  61 /*
  62  * # of IRQ routing registers
  63  */
  64 int nr_ioapic_registers[MAX_IO_APICS];
  65
  66 /*
  67  * Rough estimation of how many shared IRQs there are, can
  68  * be changed anytime.
  69  */
  70 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  71 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  72
  73 /*
  74  * This is performance-critical, we want to do it O(1)
  75  *
  76  * the indexing order of this array favors 1:1 mappings
  77  * between pins and IRQs.
  78  */
  79
  80 static struct irq_pin_list {
  81         short apic, pin, next;
  82 } irq_2_pin[PIN_MAP_SIZE];
  83
  84 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  85 #ifdef CONFIG_PCI_MSI
  86 #define vector_to_irq(vector)   \
  87         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  88 #else
  89 #define vector_to_irq(vector)   (vector)
  90 #endif
  91
  92 #define __DO_ACTION(R, ACTION, FINAL)                                   \
  93                                                                         \
  94 {                                                                       \
  95         int pin;                                                        \
  96         struct irq_pin_list *entry = irq_2_pin + irq;                   \
  97                                                                         \
  98         BUG_ON(irq >= NR_IRQS);                                         \
  99         for (;;) {                                                      \
 100                 unsigned int reg;                                       \
 101                 pin = entry->pin;                                       \
 102                 if (pin == -1)                                          \
 103                         break;                                          \
 104                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 105                 reg ACTION;                                             \
 106                 io_apic_modify(entry->apic, reg);                       \
 107                 if (!entry->next)                                       \
 108                         break;                                          \
 109                 entry = irq_2_pin + entry->next;                        \
 110         }                                                               \
 111         FINAL;                                                          \
 112 }
 113
 114 #ifdef CONFIG_SMP
 115 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 116 {
 117         unsigned long flags;
 118         unsigned int dest;
 119         cpumask_t tmp;
 120
 121         cpus_and(tmp, mask, cpu_online_map);
 122         if (cpus_empty(tmp))
 123                 tmp = TARGET_CPUS;
 124
 125         cpus_and(mask, tmp, CPU_MASK_ALL);
 126
 127         dest = cpu_mask_to_apicid(mask);
 128
 129         /*
 130          * Only the high 8 bits are valid.
 131          */
 132         dest = SET_APIC_LOGICAL_ID(dest);
 133
 134         spin_lock_irqsave(&ioapic_lock, flags);
 135         __DO_ACTION(1, = dest, )
 136         set_irq_info(irq, mask);
 137         spin_unlock_irqrestore(&ioapic_lock, flags);
 138 }
 139 #endif
 140
 141 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
 142
 143 /*
 144  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 145  * shared ISA-space IRQs, so we have to support them. We are super
 146  * fast in the common case, and fast for shared ISA-space IRQs.
 147  */
 148 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 149 {
 150         static int first_free_entry = NR_IRQS;
 151         struct irq_pin_list *entry = irq_2_pin + irq;
 152
 153         BUG_ON(irq >= NR_IRQS);
 154         while (entry->next)
 155                 entry = irq_2_pin + entry->next;
 156
 157         if (entry->pin != -1) {
 158                 entry->next = first_free_entry;
 159                 entry = irq_2_pin + entry->next;
 160                 if (++first_free_entry >= PIN_MAP_SIZE)
 161                         panic("io_apic.c: ran out of irq_2_pin entries!");
 162         }
 163         entry->apic = apic;
 164         entry->pin = pin;
 165 }
 166
 167
 168 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 169                                                                         \
 170         static void name##_IO_APIC_irq (unsigned int irq)               \
 171         __DO_ACTION(R, ACTION, FINAL)
 172
 173 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 174                                                 /* mask = 1 */
 175 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 176                                                 /* mask = 0 */
 177
 178 static void mask_IO_APIC_irq (unsigned int irq)
 179 {
 180         unsigned long flags;
 181
 182         spin_lock_irqsave(&ioapic_lock, flags);
 183         __mask_IO_APIC_irq(irq);
 184         spin_unlock_irqrestore(&ioapic_lock, flags);
 185 }
 186
 187 static void unmask_IO_APIC_irq (unsigned int irq)
 188 {
 189         unsigned long flags;
 190
 191         spin_lock_irqsave(&ioapic_lock, flags);
 192         __unmask_IO_APIC_irq(irq);
 193         spin_unlock_irqrestore(&ioapic_lock, flags);
 194 }
 195
 196 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 197 {
 198         struct IO_APIC_route_entry entry;
 199         unsigned long flags;
 200
 201         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 202         spin_lock_irqsave(&ioapic_lock, flags);
 203         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 204         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 205         spin_unlock_irqrestore(&ioapic_lock, flags);
 206         if (entry.delivery_mode == dest_SMI)
 207                 return;
 208         /*
 209          * Disable it in the IO-APIC irq-routing table:
 210          */
 211         memset(&entry, 0, sizeof(entry));
 212         entry.mask = 1;
 213         spin_lock_irqsave(&ioapic_lock, flags);
 214         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 215         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 216         spin_unlock_irqrestore(&ioapic_lock, flags);
 217 }
 218
 219 static void clear_IO_APIC (void)
 220 {
 221         int apic, pin;
 222
 223         for (apic = 0; apic < nr_ioapics; apic++)
 224                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 225                         clear_IO_APIC_pin(apic, pin);
 226 }
 227
 228 /*
 229  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 230  * specific CPU-side IRQs.
 231  */
 232
 233 #define MAX_PIRQS 8
 234 static int pirq_entries [MAX_PIRQS];
 235 static int pirqs_enabled;
 236 int skip_ioapic_setup;
 237 int ioapic_force;
 238
 239 /* dummy parsing: see setup.c */
 240
 241 static int __init disable_ioapic_setup(char *str)
 242 {
 243         skip_ioapic_setup = 1;
 244         return 1;
 245 }
 246
 247 static int __init enable_ioapic_setup(char *str)
 248 {
 249         ioapic_force = 1;
 250         skip_ioapic_setup = 0;
 251         return 1;
 252 }
 253
 254 __setup("noapic", disable_ioapic_setup);
 255 __setup("apic", enable_ioapic_setup);
 256
 257 static int __init setup_disable_8254_timer(char *s)
 258 {
 259         timer_over_8254 = -1;
 260         return 1;
 261 }
 262 static int __init setup_enable_8254_timer(char *s)
 263 {
 264         timer_over_8254 = 2;
 265         return 1;
 266 }
 267
 268 __setup("disable_8254_timer", setup_disable_8254_timer);
 269 __setup("enable_8254_timer", setup_enable_8254_timer);
 270
 271 #include <asm/pci-direct.h>
 272 #include <linux/pci_ids.h>
 273 #include <linux/pci.h>
 274
 275
 276 #ifdef CONFIG_ACPI
 277
 278 static int nvidia_hpet_detected __initdata;
 279
 280 static int __init nvidia_hpet_check(unsigned long phys, unsigned long size)
 281 {
 282         nvidia_hpet_detected = 1;
 283         return 0;
 284 }
 285 #endif
 286
 287 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 288    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 289    Use pci direct infrastructure because this runs before the PCI subsystem.
 290
 291    Can be overwritten with "apic"
 292
 293    And another hack to disable the IOMMU on VIA chipsets.
 294
 295    ... and others. Really should move this somewhere else.
 296
 297    Kludge-O-Rama. */
 298 void __init check_ioapic(void)
 299 {
 300         int num,slot,func;
 301         /* Poor man's PCI discovery */
 302         for (num = 0; num < 32; num++) {
 303                 for (slot = 0; slot < 32; slot++) {
 304                         for (func = 0; func < 8; func++) {
 305                                 u32 class;
 306                                 u32 vendor;
 307                                 u8 type;
 308                                 class = read_pci_config(num,slot,func,
 309                                                         PCI_CLASS_REVISION);
 310                                 if (class == 0xffffffff)
 311                                         break;
 312
 313                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 314                                         continue;
 315
 316                                 vendor = read_pci_config(num, slot, func,
 317                                                          PCI_VENDOR_ID);
 318                                 vendor &= 0xffff;
 319                                 switch (vendor) {
 320                                 case PCI_VENDOR_ID_VIA:
 321 #ifdef CONFIG_IOMMU
 322                                         if ((end_pfn > MAX_DMA32_PFN ||
 323                                              force_iommu) &&
 324                                             !iommu_aperture_allowed) {
 325                                                 printk(KERN_INFO
 326     "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n");
 327                                                 iommu_aperture_disabled = 1;
 328                                         }
 329 #endif
 330                                         return;
 331                                 case PCI_VENDOR_ID_NVIDIA:
 332 #ifdef CONFIG_ACPI
 333                                         /*
 334                                          * All timer overrides on Nvidia are
 335                                          * wrong unless HPET is enabled.
 336                                          */
 337                                         nvidia_hpet_detected = 0;
 338                                         acpi_table_parse(ACPI_HPET,
 339                                                         nvidia_hpet_check);
 340                                         if (nvidia_hpet_detected == 0) {
 341                                                 acpi_skip_timer_override = 1;
 342                                                 printk(KERN_INFO "Nvidia board "
 343                                                     "detected. Ignoring ACPI "
 344                                                     "timer override.\n");
 345                                         }
 346 #endif
 347                                         /* RED-PEN skip them on mptables too? */
 348                                         return;
 349
 350                                 /* This should be actually default, but
 351                                    for 2.6.16 let's do it for ATI only where
 352                                    it's really needed. */
 353                                 case PCI_VENDOR_ID_ATI:
 354                                         if (timer_over_8254 == 1) {
 355                                                 timer_over_8254 = 0;
 356                                         printk(KERN_INFO
 357                 "ATI board detected. Disabling timer routing over 8254.\n");
 358                                         }
 359                                         return;
 360                                 }
 361
 362
 363                                 /* No multi-function device? */
 364                                 type = read_pci_config_byte(num,slot,func,
 365                                                             PCI_HEADER_TYPE);
 366                                 if (!(type & 0x80))
 367                                         break;
 368                         }
 369                 }
 370         }
 371 }
 372
 373 static int __init ioapic_pirq_setup(char *str)
 374 {
 375         int i, max;
 376         int ints[MAX_PIRQS+1];
 377
 378         get_options(str, ARRAY_SIZE(ints), ints);
 379
 380         for (i = 0; i < MAX_PIRQS; i++)
 381                 pirq_entries[i] = -1;
 382
 383         pirqs_enabled = 1;
 384         apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
 385         max = MAX_PIRQS;
 386         if (ints[0] < MAX_PIRQS)
 387                 max = ints[0];
 388
 389         for (i = 0; i < max; i++) {
 390                 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 391                 /*
 392                  * PIRQs are mapped upside down, usually.
 393                  */
 394                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 395         }
 396         return 1;
 397 }
 398
 399 __setup("pirq=", ioapic_pirq_setup);
 400
 401 /*
 402  * Find the IRQ entry number of a certain pin.
 403  */
 404 static int find_irq_entry(int apic, int pin, int type)
 405 {
 406         int i;
 407
 408         for (i = 0; i < mp_irq_entries; i++)
 409                 if (mp_irqs[i].mpc_irqtype == type &&
 410                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 411                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 412                     mp_irqs[i].mpc_dstirq == pin)
 413                         return i;
 414
 415         return -1;
 416 }
 417
 418 /*
 419  * Find the pin to which IRQ[irq] (ISA) is connected
 420  */
 421 static int __init find_isa_irq_pin(int irq, int type)
 422 {
 423         int i;
 424
 425         for (i = 0; i < mp_irq_entries; i++) {
 426                 int lbus = mp_irqs[i].mpc_srcbus;
 427
 428                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 429                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 430                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 431                     (mp_irqs[i].mpc_irqtype == type) &&
 432                     (mp_irqs[i].mpc_srcbusirq == irq))
 433
 434                         return mp_irqs[i].mpc_dstirq;
 435         }
 436         return -1;
 437 }
 438
 439 static int __init find_isa_irq_apic(int irq, int type)
 440 {
 441         int i;
 442
 443         for (i = 0; i < mp_irq_entries; i++) {
 444                 int lbus = mp_irqs[i].mpc_srcbus;
 445
 446                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 447                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 448                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 449                     (mp_irqs[i].mpc_irqtype == type) &&
 450                     (mp_irqs[i].mpc_srcbusirq == irq))
 451                         break;
 452         }
 453         if (i < mp_irq_entries) {
 454                 int apic;
 455                 for(apic = 0; apic < nr_ioapics; apic++) {
 456                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 457                                 return apic;
 458                 }
 459         }
 460
 461         return -1;
 462 }
 463
 464 /*
 465  * Find a specific PCI IRQ entry.
 466  * Not an __init, possibly needed by modules
 467  */
 468 static int pin_2_irq(int idx, int apic, int pin);
 469
 470 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 471 {
 472         int apic, i, best_guess = -1;
 473
 474         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 475                 bus, slot, pin);
 476         if (mp_bus_id_to_pci_bus[bus] == -1) {
 477                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 478                 return -1;
 479         }
 480         for (i = 0; i < mp_irq_entries; i++) {
 481                 int lbus = mp_irqs[i].mpc_srcbus;
 482
 483                 for (apic = 0; apic < nr_ioapics; apic++)
 484                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 485                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 486                                 break;
 487
 488                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 489                     !mp_irqs[i].mpc_irqtype &&
 490                     (bus == lbus) &&
 491                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 492                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 493
 494                         if (!(apic || IO_APIC_IRQ(irq)))
 495                                 continue;
 496
 497                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 498                                 return irq;
 499                         /*
 500                          * Use the first all-but-pin matching entry as a
 501                          * best-guess fuzzy result for broken mptables.
 502                          */
 503                         if (best_guess < 0)
 504                                 best_guess = irq;
 505                 }
 506         }
 507         BUG_ON(best_guess >= NR_IRQS);
 508         return best_guess;
 509 }
 510
 511 /*
 512  * EISA Edge/Level control register, ELCR
 513  */
 514 static int EISA_ELCR(unsigned int irq)
 515 {
 516         if (irq < 16) {
 517                 unsigned int port = 0x4d0 + (irq >> 3);
 518                 return (inb(port) >> (irq & 7)) & 1;
 519         }
 520         apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
 521         return 0;
 522 }
 523
 524 /* EISA interrupts are always polarity zero and can be edge or level
 525  * trigger depending on the ELCR value.  If an interrupt is listed as
 526  * EISA conforming in the MP table, that means its trigger type must
 527  * be read in from the ELCR */
 528
 529 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 530 #define default_EISA_polarity(idx)      (0)
 531
 532 /* ISA interrupts are always polarity zero edge triggered,
 533  * when listed as conforming in the MP table. */
 534
 535 #define default_ISA_trigger(idx)        (0)
 536 #define default_ISA_polarity(idx)       (0)
 537
 538 /* PCI interrupts are always polarity one level triggered,
 539  * when listed as conforming in the MP table. */
 540
 541 #define default_PCI_trigger(idx)        (1)
 542 #define default_PCI_polarity(idx)       (1)
 543
 544 /* MCA interrupts are always polarity zero level triggered,
 545  * when listed as conforming in the MP table. */
 546
 547 #define default_MCA_trigger(idx)        (1)
 548 #define default_MCA_polarity(idx)       (0)
 549
 550 static int __init MPBIOS_polarity(int idx)
 551 {
 552         int bus = mp_irqs[idx].mpc_srcbus;
 553         int polarity;
 554
 555         /*
 556          * Determine IRQ line polarity (high active or low active):
 557          */
 558         switch (mp_irqs[idx].mpc_irqflag & 3)
 559         {
 560                 case 0: /* conforms, ie. bus-type dependent polarity */
 561                 {
 562                         switch (mp_bus_id_to_type[bus])
 563                         {
 564                                 case MP_BUS_ISA: /* ISA pin */
 565                                 {
 566                                         polarity = default_ISA_polarity(idx);
 567                                         break;
 568                                 }
 569                                 case MP_BUS_EISA: /* EISA pin */
 570                                 {
 571                                         polarity = default_EISA_polarity(idx);
 572                                         break;
 573                                 }
 574                                 case MP_BUS_PCI: /* PCI pin */
 575                                 {
 576                                         polarity = default_PCI_polarity(idx);
 577                                         break;
 578                                 }
 579                                 case MP_BUS_MCA: /* MCA pin */
 580                                 {
 581                                         polarity = default_MCA_polarity(idx);
 582                                         break;
 583                                 }
 584                                 default:
 585                                 {
 586                                         printk(KERN_WARNING "broken BIOS!!\n");
 587                                         polarity = 1;
 588                                         break;
 589                                 }
 590                         }
 591                         break;
 592                 }
 593                 case 1: /* high active */
 594                 {
 595                         polarity = 0;
 596                         break;
 597                 }
 598                 case 2: /* reserved */
 599                 {
 600                         printk(KERN_WARNING "broken BIOS!!\n");
 601                         polarity = 1;
 602                         break;
 603                 }
 604                 case 3: /* low active */
 605                 {
 606                         polarity = 1;
 607                         break;
 608                 }
 609                 default: /* invalid */
 610                 {
 611                         printk(KERN_WARNING "broken BIOS!!\n");
 612                         polarity = 1;
 613                         break;
 614                 }
 615         }
 616         return polarity;
 617 }
 618
 619 static int MPBIOS_trigger(int idx)
 620 {
 621         int bus = mp_irqs[idx].mpc_srcbus;
 622         int trigger;
 623
 624         /*
 625          * Determine IRQ trigger mode (edge or level sensitive):
 626          */
 627         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 628         {
 629                 case 0: /* conforms, ie. bus-type dependent */
 630                 {
 631                         switch (mp_bus_id_to_type[bus])
 632                         {
 633                                 case MP_BUS_ISA: /* ISA pin */
 634                                 {
 635                                         trigger = default_ISA_trigger(idx);
 636                                         break;
 637                                 }
 638                                 case MP_BUS_EISA: /* EISA pin */
 639                                 {
 640                                         trigger = default_EISA_trigger(idx);
 641                                         break;
 642                                 }
 643                                 case MP_BUS_PCI: /* PCI pin */
 644                                 {
 645                                         trigger = default_PCI_trigger(idx);
 646                                         break;
 647                                 }
 648                                 case MP_BUS_MCA: /* MCA pin */
 649                                 {
 650                                         trigger = default_MCA_trigger(idx);
 651                                         break;
 652                                 }
 653                                 default:
 654                                 {
 655                                         printk(KERN_WARNING "broken BIOS!!\n");
 656                                         trigger = 1;
 657                                         break;
 658                                 }
 659                         }
 660                         break;
 661                 }
 662                 case 1: /* edge */
 663                 {
 664                         trigger = 0;
 665                         break;
 666                 }
 667                 case 2: /* reserved */
 668                 {
 669                         printk(KERN_WARNING "broken BIOS!!\n");
 670                         trigger = 1;
 671                         break;
 672                 }
 673                 case 3: /* level */
 674                 {
 675                         trigger = 1;
 676                         break;
 677                 }
 678                 default: /* invalid */
 679                 {
 680                         printk(KERN_WARNING "broken BIOS!!\n");
 681                         trigger = 0;
 682                         break;
 683                 }
 684         }
 685         return trigger;
 686 }
 687
 688 static inline int irq_polarity(int idx)
 689 {
 690         return MPBIOS_polarity(idx);
 691 }
 692
 693 static inline int irq_trigger(int idx)
 694 {
 695         return MPBIOS_trigger(idx);
 696 }
 697
 698 static int next_irq = 16;
 699
 700 /*
 701  * gsi_irq_sharing -- Name overload!  "irq" can be either a legacy IRQ
 702  * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
 703  * from ACPI, which can reach 800 in large boxen.
 704  *
 705  * Compact the sparse GSI space into a sequential IRQ series and reuse
 706  * vectors if possible.
 707  */
 708 int gsi_irq_sharing(int gsi)
 709 {
 710         int i, tries, vector;
 711
 712         BUG_ON(gsi >= NR_IRQ_VECTORS);
 713
 714         if (platform_legacy_irq(gsi))
 715                 return gsi;
 716
 717         if (gsi_2_irq[gsi] != 0xFF)
 718                 return (int)gsi_2_irq[gsi];
 719
 720         tries = NR_IRQS;
 721   try_again:
 722         vector = assign_irq_vector(gsi);
 723
 724         /*
 725          * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
 726          * use of vector and if found, return that IRQ.  However, we never want
 727          * to share legacy IRQs, which usually have a different trigger mode
 728          * than PCI.
 729          */
 730         for (i = 0; i < NR_IRQS; i++)
 731                 if (IO_APIC_VECTOR(i) == vector)
 732                         break;
 733         if (platform_legacy_irq(i)) {
 734                 if (--tries >= 0) {
 735                         IO_APIC_VECTOR(i) = 0;
 736                         goto try_again;
 737                 }
 738                 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
 739         }
 740         if (i < NR_IRQS) {
 741                 gsi_2_irq[gsi] = i;
 742                 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
 743                                 gsi, vector, i);
 744                 return i;
 745         }
 746
 747         i = next_irq++;
 748         BUG_ON(i >= NR_IRQS);
 749         gsi_2_irq[gsi] = i;
 750         IO_APIC_VECTOR(i) = vector;
 751         printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
 752                         gsi, vector, i);
 753         return i;
 754 }
 755
 756 static int pin_2_irq(int idx, int apic, int pin)
 757 {
 758         int irq, i;
 759         int bus = mp_irqs[idx].mpc_srcbus;
 760
 761         /*
 762          * Debugging check, we are in big trouble if this message pops up!
 763          */
 764         if (mp_irqs[idx].mpc_dstirq != pin)
 765                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 766
 767         switch (mp_bus_id_to_type[bus])
 768         {
 769                 case MP_BUS_ISA: /* ISA pin */
 770                 case MP_BUS_EISA:
 771                 case MP_BUS_MCA:
 772                 {
 773                         irq = mp_irqs[idx].mpc_srcbusirq;
 774                         break;
 775                 }
 776                 case MP_BUS_PCI: /* PCI pin */
 777                 {
 778                         /*
 779                          * PCI IRQs are mapped in order
 780                          */
 781                         i = irq = 0;
 782                         while (i < apic)
 783                                 irq += nr_ioapic_registers[i++];
 784                         irq += pin;
 785                         irq = gsi_irq_sharing(irq);
 786                         break;
 787                 }
 788                 default:
 789                 {
 790                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 791                         irq = 0;
 792                         break;
 793                 }
 794         }
 795         BUG_ON(irq >= NR_IRQS);
 796
 797         /*
 798          * PCI IRQ command line redirection. Yes, limits are hardcoded.
 799          */
 800         if ((pin >= 16) && (pin <= 23)) {
 801                 if (pirq_entries[pin-16] != -1) {
 802                         if (!pirq_entries[pin-16]) {
 803                                 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
 804                         } else {
 805                                 irq = pirq_entries[pin-16];
 806                                 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
 807                                                 pin-16, irq);
 808                         }
 809                 }
 810         }
 811         BUG_ON(irq >= NR_IRQS);
 812         return irq;
 813 }
 814
 815 static inline int IO_APIC_irq_trigger(int irq)
 816 {
 817         int apic, idx, pin;
 818
 819         for (apic = 0; apic < nr_ioapics; apic++) {
 820                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 821                         idx = find_irq_entry(apic,pin,mp_INT);
 822                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 823                                 return irq_trigger(idx);
 824                 }
 825         }
 826         /*
 827          * nonexistent IRQs are edge default
 828          */
 829         return 0;
 830 }
 831
 832 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 833 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
 834
 835 int assign_irq_vector(int irq)
 836 {
 837         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 838         unsigned long flags;
 839         int vector;
 840
 841         BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
 842
 843         spin_lock_irqsave(&vector_lock, flags);
 844
 845         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
 846                 spin_unlock_irqrestore(&vector_lock, flags);
 847                 return IO_APIC_VECTOR(irq);
 848         }
 849 next:
 850         current_vector += 8;
 851         if (current_vector == IA32_SYSCALL_VECTOR)
 852                 goto next;
 853
 854         if (current_vector >= FIRST_SYSTEM_VECTOR) {
 855                 /* If we run out of vectors on large boxen, must share them. */
 856                 offset = (offset + 1) % 8;
 857                 current_vector = FIRST_DEVICE_VECTOR + offset;
 858         }
 859
 860         vector = current_vector;
 861         vector_irq[vector] = irq;
 862         if (irq != AUTO_ASSIGN)
 863                 IO_APIC_VECTOR(irq) = vector;
 864
 865         spin_unlock_irqrestore(&vector_lock, flags);
 866
 867         return vector;
 868 }
 869
 870 extern void (*interrupt[NR_IRQS])(void);
 871 static struct hw_interrupt_type ioapic_level_type;
 872 static struct hw_interrupt_type ioapic_edge_type;
 873
 874 #define IOAPIC_AUTO     -1
 875 #define IOAPIC_EDGE     0
 876 #define IOAPIC_LEVEL    1
 877
 878 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 879 {
 880         unsigned idx;
 881
 882         idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
 883
 884         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 885                         trigger == IOAPIC_LEVEL)
 886                 irq_desc[idx].chip = &ioapic_level_type;
 887         else
 888                 irq_desc[idx].chip = &ioapic_edge_type;
 889         set_intr_gate(vector, interrupt[idx]);
 890 }
 891
 892 static void __init setup_IO_APIC_irqs(void)
 893 {
 894         struct IO_APIC_route_entry entry;
 895         int apic, pin, idx, irq, first_notcon = 1, vector;
 896         unsigned long flags;
 897
 898         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 899
 900         for (apic = 0; apic < nr_ioapics; apic++) {
 901         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 902
 903                 /*
 904                  * add it to the IO-APIC irq-routing table:
 905                  */
 906                 memset(&entry,0,sizeof(entry));
 907
 908                 entry.delivery_mode = INT_DELIVERY_MODE;
 909                 entry.dest_mode = INT_DEST_MODE;
 910                 entry.mask = 0;                         /* enable IRQ */
 911                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 912
 913                 idx = find_irq_entry(apic,pin,mp_INT);
 914                 if (idx == -1) {
 915                         if (first_notcon) {
 916                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 917                                 first_notcon = 0;
 918                         } else
 919                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 920                         continue;
 921                 }
 922
 923                 entry.trigger = irq_trigger(idx);
 924                 entry.polarity = irq_polarity(idx);
 925
 926                 if (irq_trigger(idx)) {
 927                         entry.trigger = 1;
 928                         entry.mask = 1;
 929                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 930                 }
 931
 932                 irq = pin_2_irq(idx, apic, pin);
 933                 add_pin_to_irq(irq, apic, pin);
 934
 935                 if (!apic && !IO_APIC_IRQ(irq))
 936                         continue;
 937
 938                 if (IO_APIC_IRQ(irq)) {
 939                         vector = assign_irq_vector(irq);
 940                         entry.vector = vector;
 941
 942                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 943                         if (!apic && (irq < 16))
 944                                 disable_8259A_irq(irq);
 945                 }
 946                 spin_lock_irqsave(&ioapic_lock, flags);
 947                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 948                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 949                 set_native_irq_info(irq, TARGET_CPUS);
 950                 spin_unlock_irqrestore(&ioapic_lock, flags);
 951         }
 952         }
 953
 954         if (!first_notcon)
 955                 apic_printk(APIC_VERBOSE," not connected.\n");
 956 }
 957
 958 /*
 959  * Set up the 8259A-master output pin as broadcast to all
 960  * CPUs.
 961  */
 962 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 963 {
 964         struct IO_APIC_route_entry entry;
 965         unsigned long flags;
 966
 967         memset(&entry,0,sizeof(entry));
 968
 969         disable_8259A_irq(0);
 970
 971         /* mask LVT0 */
 972         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 973
 974         /*
 975          * We use logical delivery to get the timer IRQ
 976          * to the first CPU.
 977          */
 978         entry.dest_mode = INT_DEST_MODE;
 979         entry.mask = 0;                                 /* unmask IRQ now */
 980         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 981         entry.delivery_mode = INT_DELIVERY_MODE;
 982         entry.polarity = 0;
 983         entry.trigger = 0;
 984         entry.vector = vector;
 985
 986         /*
 987          * The timer IRQ doesn't have to know that behind the
 988          * scene we have a 8259A-master in AEOI mode ...
 989          */
 990         irq_desc[0].chip = &ioapic_edge_type;
 991
 992         /*
 993          * Add it to the IO-APIC irq-routing table:
 994          */
 995         spin_lock_irqsave(&ioapic_lock, flags);
 996         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 997         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 998         spin_unlock_irqrestore(&ioapic_lock, flags);
 999
1000         enable_8259A_irq(0);
1001 }
1002
1003 void __init UNEXPECTED_IO_APIC(void)
1004 {
1005 }
1006
1007 void __apicdebuginit print_IO_APIC(void)
1008 {
1009         int apic, i;
1010         union IO_APIC_reg_00 reg_00;
1011         union IO_APIC_reg_01 reg_01;
1012         union IO_APIC_reg_02 reg_02;
1013         unsigned long flags;
1014
1015         if (apic_verbosity == APIC_QUIET)
1016                 return;
1017
1018         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1019         for (i = 0; i < nr_ioapics; i++)
1020                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1021                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1022
1023         /*
1024          * We are a bit conservative about what we expect.  We have to
1025          * know about every hardware change ASAP.
1026          */
1027         printk(KERN_INFO "testing the IO APIC.......................\n");
1028
1029         for (apic = 0; apic < nr_ioapics; apic++) {
1030
1031         spin_lock_irqsave(&ioapic_lock, flags);
1032         reg_00.raw = io_apic_read(apic, 0);
1033         reg_01.raw = io_apic_read(apic, 1);
1034         if (reg_01.bits.version >= 0x10)
1035                 reg_02.raw = io_apic_read(apic, 2);
1036         spin_unlock_irqrestore(&ioapic_lock, flags);
1037
1038         printk("\n");
1039         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1040         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1041         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1042         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1043                 UNEXPECTED_IO_APIC();
1044
1045         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1046         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1047         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1048                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1049                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1050                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1051                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1052                 (reg_01.bits.entries != 0x2E) &&
1053                 (reg_01.bits.entries != 0x3F) &&
1054                 (reg_01.bits.entries != 0x03)
1055         )
1056                 UNEXPECTED_IO_APIC();
1057
1058         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1059         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1060         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1061                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
1062                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1063                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1064                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1065                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1066         )
1067                 UNEXPECTED_IO_APIC();
1068         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1069                 UNEXPECTED_IO_APIC();
1070
1071         if (reg_01.bits.version >= 0x10) {
1072                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1073                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1074                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1075                         UNEXPECTED_IO_APIC();
1076         }
1077
1078         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1079
1080         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1081                           " Stat Dest Deli Vect:   \n");
1082
1083         for (i = 0; i <= reg_01.bits.entries; i++) {
1084                 struct IO_APIC_route_entry entry;
1085
1086                 spin_lock_irqsave(&ioapic_lock, flags);
1087                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1088                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1089                 spin_unlock_irqrestore(&ioapic_lock, flags);
1090
1091                 printk(KERN_DEBUG " %02x %03X %02X  ",
1092                         i,
1093                         entry.dest.logical.logical_dest,
1094                         entry.dest.physical.physical_dest
1095                 );
1096
1097                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1098                         entry.mask,
1099                         entry.trigger,
1100                         entry.irr,
1101                         entry.polarity,
1102                         entry.delivery_status,
1103                         entry.dest_mode,
1104                         entry.delivery_mode,
1105                         entry.vector
1106                 );
1107         }
1108         }
1109         if (use_pci_vector())
1110                 printk(KERN_INFO "Using vector-based indexing\n");
1111         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1112         for (i = 0; i < NR_IRQS; i++) {
1113                 struct irq_pin_list *entry = irq_2_pin + i;
1114                 if (entry->pin < 0)
1115                         continue;
1116                 if (use_pci_vector() && !platform_legacy_irq(i))
1117                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1118                 else
1119                         printk(KERN_DEBUG "IRQ%d ", i);
1120                 for (;;) {
1121                         printk("-> %d:%d", entry->apic, entry->pin);
1122                         if (!entry->next)
1123                                 break;
1124                         entry = irq_2_pin + entry->next;
1125                 }
1126                 printk("\n");
1127         }
1128
1129         printk(KERN_INFO ".................................... done.\n");
1130
1131         return;
1132 }
1133
1134 #if 0
1135
1136 static __apicdebuginit void print_APIC_bitfield (int base)
1137 {
1138         unsigned int v;
1139         int i, j;
1140
1141         if (apic_verbosity == APIC_QUIET)
1142                 return;
1143
1144         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1145         for (i = 0; i < 8; i++) {
1146                 v = apic_read(base + i*0x10);
1147                 for (j = 0; j < 32; j++) {
1148                         if (v & (1<<j))
1149                                 printk("1");
1150                         else
1151                                 printk("0");
1152                 }
1153                 printk("\n");
1154         }
1155 }
1156
1157 void __apicdebuginit print_local_APIC(void * dummy)
1158 {
1159         unsigned int v, ver, maxlvt;
1160
1161         if (apic_verbosity == APIC_QUIET)
1162                 return;
1163
1164         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1165                 smp_processor_id(), hard_smp_processor_id());
1166         v = apic_read(APIC_ID);
1167         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1168         v = apic_read(APIC_LVR);
1169         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1170         ver = GET_APIC_VERSION(v);
1171         maxlvt = get_maxlvt();
1172
1173         v = apic_read(APIC_TASKPRI);
1174         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1175
1176         v = apic_read(APIC_ARBPRI);
1177         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1178                 v & APIC_ARBPRI_MASK);
1179         v = apic_read(APIC_PROCPRI);
1180         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1181
1182         v = apic_read(APIC_EOI);
1183         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1184         v = apic_read(APIC_RRR);
1185         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1186         v = apic_read(APIC_LDR);
1187         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1188         v = apic_read(APIC_DFR);
1189         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1190         v = apic_read(APIC_SPIV);
1191         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1192
1193         printk(KERN_DEBUG "... APIC ISR field:\n");
1194         print_APIC_bitfield(APIC_ISR);
1195         printk(KERN_DEBUG "... APIC TMR field:\n");
1196         print_APIC_bitfield(APIC_TMR);
1197         printk(KERN_DEBUG "... APIC IRR field:\n");
1198         print_APIC_bitfield(APIC_IRR);
1199
1200         v = apic_read(APIC_ESR);
1201         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1202
1203         v = apic_read(APIC_ICR);
1204         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1205         v = apic_read(APIC_ICR2);
1206         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1207
1208         v = apic_read(APIC_LVTT);
1209         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1210
1211         if (maxlvt > 3) {                       /* PC is LVT#4. */
1212                 v = apic_read(APIC_LVTPC);
1213                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1214         }
1215         v = apic_read(APIC_LVT0);
1216         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1217         v = apic_read(APIC_LVT1);
1218         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1219
1220         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1221                 v = apic_read(APIC_LVTERR);
1222                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1223         }
1224
1225         v = apic_read(APIC_TMICT);
1226         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1227         v = apic_read(APIC_TMCCT);
1228         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1229         v = apic_read(APIC_TDCR);
1230         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1231         printk("\n");
1232 }
1233
1234 void print_all_local_APICs (void)
1235 {
1236         on_each_cpu(print_local_APIC, NULL, 1, 1);
1237 }
1238
1239 void __apicdebuginit print_PIC(void)
1240 {
1241         unsigned int v;
1242         unsigned long flags;
1243
1244         if (apic_verbosity == APIC_QUIET)
1245                 return;
1246
1247         printk(KERN_DEBUG "\nprinting PIC contents\n");
1248
1249         spin_lock_irqsave(&i8259A_lock, flags);
1250
1251         v = inb(0xa1) << 8 | inb(0x21);
1252         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1253
1254         v = inb(0xa0) << 8 | inb(0x20);
1255         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1256
1257         outb(0x0b,0xa0);
1258         outb(0x0b,0x20);
1259         v = inb(0xa0) << 8 | inb(0x20);
1260         outb(0x0a,0xa0);
1261         outb(0x0a,0x20);
1262
1263         spin_unlock_irqrestore(&i8259A_lock, flags);
1264
1265         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1266
1267         v = inb(0x4d1) << 8 | inb(0x4d0);
1268         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1269 }
1270
1271 #endif  /*  0  */
1272
1273 static void __init enable_IO_APIC(void)
1274 {
1275         union IO_APIC_reg_01 reg_01;
1276         int i8259_apic, i8259_pin;
1277         int i, apic;
1278         unsigned long flags;
1279
1280         for (i = 0; i < PIN_MAP_SIZE; i++) {
1281                 irq_2_pin[i].pin = -1;
1282                 irq_2_pin[i].next = 0;
1283         }
1284         if (!pirqs_enabled)
1285                 for (i = 0; i < MAX_PIRQS; i++)
1286                         pirq_entries[i] = -1;
1287
1288         /*
1289          * The number of IO-APIC IRQ registers (== #pins):
1290          */
1291         for (apic = 0; apic < nr_ioapics; apic++) {
1292                 spin_lock_irqsave(&ioapic_lock, flags);
1293                 reg_01.raw = io_apic_read(apic, 1);
1294                 spin_unlock_irqrestore(&ioapic_lock, flags);
1295                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1296         }
1297         for(apic = 0; apic < nr_ioapics; apic++) {
1298                 int pin;
1299                 /* See if any of the pins is in ExtINT mode */
1300                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1301                         struct IO_APIC_route_entry entry;
1302                         spin_lock_irqsave(&ioapic_lock, flags);
1303                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1304                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1305                         spin_unlock_irqrestore(&ioapic_lock, flags);
1306
1307
1308                         /* If the interrupt line is enabled and in ExtInt mode
1309                          * I have found the pin where the i8259 is connected.
1310                          */
1311                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1312                                 ioapic_i8259.apic = apic;
1313                                 ioapic_i8259.pin  = pin;
1314                                 goto found_i8259;
1315                         }
1316                 }
1317         }
1318  found_i8259:
1319         /* Look to see what if the MP table has reported the ExtINT */
1320         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1321         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1322         /* Trust the MP table if nothing is setup in the hardware */
1323         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1324                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1325                 ioapic_i8259.pin  = i8259_pin;
1326                 ioapic_i8259.apic = i8259_apic;
1327         }
1328         /* Complain if the MP table and the hardware disagree */
1329         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1330                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1331         {
1332                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1333         }
1334
1335         /*
1336          * Do not trust the IO-APIC being empty at bootup
1337          */
1338         clear_IO_APIC();
1339 }
1340
1341 /*
1342  * Not an __init, needed by the reboot code
1343  */
1344 void disable_IO_APIC(void)
1345 {
1346         /*
1347          * Clear the IO-APIC before rebooting:
1348          */
1349         clear_IO_APIC();
1350
1351         /*
1352          * If the i8259 is routed through an IOAPIC
1353          * Put that IOAPIC in virtual wire mode
1354          * so legacy interrupts can be delivered.
1355          */
1356         if (ioapic_i8259.pin != -1) {
1357                 struct IO_APIC_route_entry entry;
1358                 unsigned long flags;
1359
1360                 memset(&entry, 0, sizeof(entry));
1361                 entry.mask            = 0; /* Enabled */
1362                 entry.trigger         = 0; /* Edge */
1363                 entry.irr             = 0;
1364                 entry.polarity        = 0; /* High */
1365                 entry.delivery_status = 0;
1366                 entry.dest_mode       = 0; /* Physical */
1367                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1368                 entry.vector          = 0;
1369                 entry.dest.physical.physical_dest =
1370                                         GET_APIC_ID(apic_read(APIC_ID));
1371
1372                 /*
1373                  * Add it to the IO-APIC irq-routing table:
1374                  */
1375                 spin_lock_irqsave(&ioapic_lock, flags);
1376                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1377                         *(((int *)&entry)+1));
1378                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1379                         *(((int *)&entry)+0));
1380                 spin_unlock_irqrestore(&ioapic_lock, flags);
1381         }
1382
1383         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1384 }
1385
1386 /*
1387  * function to set the IO-APIC physical IDs based on the
1388  * values stored in the MPC table.
1389  *
1390  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1391  */
1392
1393 static void __init setup_ioapic_ids_from_mpc (void)
1394 {
1395         union IO_APIC_reg_00 reg_00;
1396         int apic;
1397         int i;
1398         unsigned char old_id;
1399         unsigned long flags;
1400
1401         /*
1402          * Set the IOAPIC ID to the value stored in the MPC table.
1403          */
1404         for (apic = 0; apic < nr_ioapics; apic++) {
1405
1406                 /* Read the register 0 value */
1407                 spin_lock_irqsave(&ioapic_lock, flags);
1408                 reg_00.raw = io_apic_read(apic, 0);
1409                 spin_unlock_irqrestore(&ioapic_lock, flags);
1410
1411                 old_id = mp_ioapics[apic].mpc_apicid;
1412
1413
1414                 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1415
1416
1417                 /*
1418                  * We need to adjust the IRQ routing table
1419                  * if the ID changed.
1420                  */
1421                 if (old_id != mp_ioapics[apic].mpc_apicid)
1422                         for (i = 0; i < mp_irq_entries; i++)
1423                                 if (mp_irqs[i].mpc_dstapic == old_id)
1424                                         mp_irqs[i].mpc_dstapic
1425                                                 = mp_ioapics[apic].mpc_apicid;
1426
1427                 /*
1428                  * Read the right value from the MPC table and
1429                  * write it into the ID register.
1430                  */
1431                 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1432                                 mp_ioapics[apic].mpc_apicid);
1433
1434                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1435                 spin_lock_irqsave(&ioapic_lock, flags);
1436                 io_apic_write(apic, 0, reg_00.raw);
1437                 spin_unlock_irqrestore(&ioapic_lock, flags);
1438
1439                 /*
1440                  * Sanity check
1441                  */
1442                 spin_lock_irqsave(&ioapic_lock, flags);
1443                 reg_00.raw = io_apic_read(apic, 0);
1444                 spin_unlock_irqrestore(&ioapic_lock, flags);
1445                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1446                         printk("could not set ID!\n");
1447                 else
1448                         apic_printk(APIC_VERBOSE," ok.\n");
1449         }
1450 }
1451
1452 /*
1453  * There is a nasty bug in some older SMP boards, their mptable lies
1454  * about the timer IRQ. We do the following to work around the situation:
1455  *
1456  *      - timer IRQ defaults to IO-APIC IRQ
1457  *      - if this function detects that timer IRQs are defunct, then we fall
1458  *        back to ISA timer IRQs
1459  */
1460 static int __init timer_irq_works(void)
1461 {
1462         unsigned long t1 = jiffies;
1463
1464         local_irq_enable();
1465         /* Let ten ticks pass... */
1466         mdelay((10 * 1000) / HZ);
1467
1468         /*
1469          * Expect a few ticks at least, to be sure some possible
1470          * glue logic does not lock up after one or two first
1471          * ticks in a non-ExtINT mode.  Also the local APIC
1472          * might have cached one ExtINT interrupt.  Finally, at
1473          * least one tick may be lost due to delays.
1474          */
1475
1476         /* jiffies wrap? */
1477         if (jiffies - t1 > 4)
1478                 return 1;
1479         return 0;
1480 }
1481
1482 /*
1483  * In the SMP+IOAPIC case it might happen that there are an unspecified
1484  * number of pending IRQ events unhandled. These cases are very rare,
1485  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1486  * better to do it this way as thus we do not have to be aware of
1487  * 'pending' interrupts in the IRQ path, except at this point.
1488  */
1489 /*
1490  * Edge triggered needs to resend any interrupt
1491  * that was delayed but this is now handled in the device
1492  * independent code.
1493  */
1494
1495 /*
1496  * Starting up a edge-triggered IO-APIC interrupt is
1497  * nasty - we need to make sure that we get the edge.
1498  * If it is already asserted for some reason, we need
1499  * return 1 to indicate that is was pending.
1500  *
1501  * This is not complete - we should be able to fake
1502  * an edge even if it isn't on the 8259A...
1503  */
1504
1505 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1506 {
1507         int was_pending = 0;
1508         unsigned long flags;
1509
1510         spin_lock_irqsave(&ioapic_lock, flags);
1511         if (irq < 16) {
1512                 disable_8259A_irq(irq);
1513                 if (i8259A_irq_pending(irq))
1514                         was_pending = 1;
1515         }
1516         __unmask_IO_APIC_irq(irq);
1517         spin_unlock_irqrestore(&ioapic_lock, flags);
1518
1519         return was_pending;
1520 }
1521
1522 /*
1523  * Once we have recorded IRQ_PENDING already, we can mask the
1524  * interrupt for real. This prevents IRQ storms from unhandled
1525  * devices.
1526  */
1527 static void ack_edge_ioapic_irq(unsigned int irq)
1528 {
1529         move_irq(irq);
1530         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1531                                         == (IRQ_PENDING | IRQ_DISABLED))
1532                 mask_IO_APIC_irq(irq);
1533         ack_APIC_irq();
1534 }
1535
1536 /*
1537  * Level triggered interrupts can just be masked,
1538  * and shutting down and starting up the interrupt
1539  * is the same as enabling and disabling them -- except
1540  * with a startup need to return a "was pending" value.
1541  *
1542  * Level triggered interrupts are special because we
1543  * do not touch any IO-APIC register while handling
1544  * them. We ack the APIC in the end-IRQ handler, not
1545  * in the start-IRQ-handler. Protection against reentrance
1546  * from the same interrupt is still provided, both by the
1547  * generic IRQ layer and by the fact that an unacked local
1548  * APIC does not accept IRQs.
1549  */
1550 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1551 {
1552         unmask_IO_APIC_irq(irq);
1553
1554         return 0; /* don't check for pending */
1555 }
1556
1557 static void end_level_ioapic_irq (unsigned int irq)
1558 {
1559         move_irq(irq);
1560         ack_APIC_irq();
1561 }
1562
1563 #ifdef CONFIG_PCI_MSI
1564 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1565 {
1566         int irq = vector_to_irq(vector);
1567
1568         return startup_edge_ioapic_irq(irq);
1569 }
1570
1571 static void ack_edge_ioapic_vector(unsigned int vector)
1572 {
1573         int irq = vector_to_irq(vector);
1574
1575         move_native_irq(vector);
1576         ack_edge_ioapic_irq(irq);
1577 }
1578
1579 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1580 {
1581         int irq = vector_to_irq(vector);
1582
1583         return startup_level_ioapic_irq (irq);
1584 }
1585
1586 static void end_level_ioapic_vector (unsigned int vector)
1587 {
1588         int irq = vector_to_irq(vector);
1589
1590         move_native_irq(vector);
1591         end_level_ioapic_irq(irq);
1592 }
1593
1594 static void mask_IO_APIC_vector (unsigned int vector)
1595 {
1596         int irq = vector_to_irq(vector);
1597
1598         mask_IO_APIC_irq(irq);
1599 }
1600
1601 static void unmask_IO_APIC_vector (unsigned int vector)
1602 {
1603         int irq = vector_to_irq(vector);
1604
1605         unmask_IO_APIC_irq(irq);
1606 }
1607
1608 #ifdef CONFIG_SMP
1609 static void set_ioapic_affinity_vector (unsigned int vector,
1610                                         cpumask_t cpu_mask)
1611 {
1612         int irq = vector_to_irq(vector);
1613
1614         set_native_irq_info(vector, cpu_mask);
1615         set_ioapic_affinity_irq(irq, cpu_mask);
1616 }
1617 #endif // CONFIG_SMP
1618 #endif // CONFIG_PCI_MSI
1619
1620 static int ioapic_retrigger(unsigned int irq)
1621 {
1622         send_IPI_self(IO_APIC_VECTOR(irq));
1623
1624         return 1;
1625 }
1626
1627 /*
1628  * Level and edge triggered IO-APIC interrupts need different handling,
1629  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1630  * handled with the level-triggered descriptor, but that one has slightly
1631  * more overhead. Level-triggered interrupts cannot be handled with the
1632  * edge-triggered handler, without risking IRQ storms and other ugly
1633  * races.
1634  */
1635
1636 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1637         .typename = "IO-APIC-edge",
1638         .startup        = startup_edge_ioapic,
1639         .shutdown       = shutdown_edge_ioapic,
1640         .enable         = enable_edge_ioapic,
1641         .disable        = disable_edge_ioapic,
1642         .ack            = ack_edge_ioapic,
1643         .end            = end_edge_ioapic,
1644 #ifdef CONFIG_SMP
1645         .set_affinity = set_ioapic_affinity,
1646 #endif
1647         .retrigger      = ioapic_retrigger,
1648 };
1649
1650 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1651         .typename = "IO-APIC-level",
1652         .startup        = startup_level_ioapic,
1653         .shutdown       = shutdown_level_ioapic,
1654         .enable         = enable_level_ioapic,
1655         .disable        = disable_level_ioapic,
1656         .ack            = mask_and_ack_level_ioapic,
1657         .end            = end_level_ioapic,
1658 #ifdef CONFIG_SMP
1659         .set_affinity = set_ioapic_affinity,
1660 #endif
1661         .retrigger      = ioapic_retrigger,
1662 };
1663
1664 static inline void init_IO_APIC_traps(void)
1665 {
1666         int irq;
1667
1668         /*
1669          * NOTE! The local APIC isn't very good at handling
1670          * multiple interrupts at the same interrupt level.
1671          * As the interrupt level is determined by taking the
1672          * vector number and shifting that right by 4, we
1673          * want to spread these out a bit so that they don't
1674          * all fall in the same interrupt level.
1675          *
1676          * Also, we've got to be careful not to trash gate
1677          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1678          */
1679         for (irq = 0; irq < NR_IRQS ; irq++) {
1680                 int tmp = irq;
1681                 if (use_pci_vector()) {
1682                         if (!platform_legacy_irq(tmp))
1683                                 if ((tmp = vector_to_irq(tmp)) == -1)
1684                                         continue;
1685                 }
1686                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1687                         /*
1688                          * Hmm.. We don't have an entry for this,
1689                          * so default to an old-fashioned 8259
1690                          * interrupt if we can..
1691                          */
1692                         if (irq < 16)
1693                                 make_8259A_irq(irq);
1694                         else
1695                                 /* Strange. Oh, well.. */
1696                                 irq_desc[irq].chip = &no_irq_type;
1697                 }
1698         }
1699 }
1700
1701 static void enable_lapic_irq (unsigned int irq)
1702 {
1703         unsigned long v;
1704
1705         v = apic_read(APIC_LVT0);
1706         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1707 }
1708
1709 static void disable_lapic_irq (unsigned int irq)
1710 {
1711         unsigned long v;
1712
1713         v = apic_read(APIC_LVT0);
1714         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1715 }
1716
1717 static void ack_lapic_irq (unsigned int irq)
1718 {
1719         ack_APIC_irq();
1720 }
1721
1722 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1723
1724 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1725         .typename = "local-APIC-edge",
1726         .startup = NULL, /* startup_irq() not used for IRQ0 */
1727         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1728         .enable = enable_lapic_irq,
1729         .disable = disable_lapic_irq,
1730         .ack = ack_lapic_irq,
1731         .end = end_lapic_irq,
1732 };
1733
1734 static void setup_nmi (void)
1735 {
1736         /*
1737          * Dirty trick to enable the NMI watchdog ...
1738          * We put the 8259A master into AEOI mode and
1739          * unmask on all local APICs LVT0 as NMI.
1740          *
1741          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1742          * is from Maciej W. Rozycki - so we do not have to EOI from
1743          * the NMI handler or the timer interrupt.
1744          */
1745         printk(KERN_INFO "activating NMI Watchdog ...");
1746
1747         enable_NMI_through_LVT0(NULL);
1748
1749         printk(" done.\n");
1750 }
1751
1752 /*
1753  * This looks a bit hackish but it's about the only one way of sending
1754  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1755  * not support the ExtINT mode, unfortunately.  We need to send these
1756  * cycles as some i82489DX-based boards have glue logic that keeps the
1757  * 8259A interrupt line asserted until INTA.  --macro
1758  */
1759 static inline void unlock_ExtINT_logic(void)
1760 {
1761         int apic, pin, i;
1762         struct IO_APIC_route_entry entry0, entry1;
1763         unsigned char save_control, save_freq_select;
1764         unsigned long flags;
1765
1766         pin  = find_isa_irq_pin(8, mp_INT);
1767         apic = find_isa_irq_apic(8, mp_INT);
1768         if (pin == -1)
1769                 return;
1770
1771         spin_lock_irqsave(&ioapic_lock, flags);
1772         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1773         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1774         spin_unlock_irqrestore(&ioapic_lock, flags);
1775         clear_IO_APIC_pin(apic, pin);
1776
1777         memset(&entry1, 0, sizeof(entry1));
1778
1779         entry1.dest_mode = 0;                   /* physical delivery */
1780         entry1.mask = 0;                        /* unmask IRQ now */
1781         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1782         entry1.delivery_mode = dest_ExtINT;
1783         entry1.polarity = entry0.polarity;
1784         entry1.trigger = 0;
1785         entry1.vector = 0;
1786
1787         spin_lock_irqsave(&ioapic_lock, flags);
1788         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1789         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1790         spin_unlock_irqrestore(&ioapic_lock, flags);
1791
1792         save_control = CMOS_READ(RTC_CONTROL);
1793         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1794         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1795                    RTC_FREQ_SELECT);
1796         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1797
1798         i = 100;
1799         while (i-- > 0) {
1800                 mdelay(10);
1801                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1802                         i -= 10;
1803         }
1804
1805         CMOS_WRITE(save_control, RTC_CONTROL);
1806         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1807         clear_IO_APIC_pin(apic, pin);
1808
1809         spin_lock_irqsave(&ioapic_lock, flags);
1810         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1811         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1812         spin_unlock_irqrestore(&ioapic_lock, flags);
1813 }
1814
1815 int timer_uses_ioapic_pin_0;
1816
1817 /*
1818  * This code may look a bit paranoid, but it's supposed to cooperate with
1819  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1820  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1821  * fanatically on his truly buggy board.
1822  *
1823  * FIXME: really need to revamp this for modern platforms only.
1824  */
1825 static inline void check_timer(void)
1826 {
1827         int apic1, pin1, apic2, pin2;
1828         int vector;
1829
1830         /*
1831          * get/set the timer IRQ vector:
1832          */
1833         disable_8259A_irq(0);
1834         vector = assign_irq_vector(0);
1835         set_intr_gate(vector, interrupt[0]);
1836
1837         /*
1838          * Subtle, code in do_timer_interrupt() expects an AEOI
1839          * mode for the 8259A whenever interrupts are routed
1840          * through I/O APICs.  Also IRQ0 has to be enabled in
1841          * the 8259A which implies the virtual wire has to be
1842          * disabled in the local APIC.
1843          */
1844         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1845         init_8259A(1);
1846         if (timer_over_8254 > 0)
1847                 enable_8259A_irq(0);
1848
1849         pin1  = find_isa_irq_pin(0, mp_INT);
1850         apic1 = find_isa_irq_apic(0, mp_INT);
1851         pin2  = ioapic_i8259.pin;
1852         apic2 = ioapic_i8259.apic;
1853
1854         if (pin1 == 0)
1855                 timer_uses_ioapic_pin_0 = 1;
1856
1857         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1858                 vector, apic1, pin1, apic2, pin2);
1859
1860         if (pin1 != -1) {
1861                 /*
1862                  * Ok, does IRQ0 through the IOAPIC work?
1863                  */
1864                 unmask_IO_APIC_irq(0);
1865                 if (!no_timer_check && timer_irq_works()) {
1866                         nmi_watchdog_default();
1867                         if (nmi_watchdog == NMI_IO_APIC) {
1868                                 disable_8259A_irq(0);
1869                                 setup_nmi();
1870                                 enable_8259A_irq(0);
1871                         }
1872                         if (disable_timer_pin_1 > 0)
1873                                 clear_IO_APIC_pin(0, pin1);
1874                         return;
1875                 }
1876                 clear_IO_APIC_pin(apic1, pin1);
1877                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1878                                 "connected to IO-APIC\n");
1879         }
1880
1881         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1882                                 "through the 8259A ... ");
1883         if (pin2 != -1) {
1884                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1885                         apic2, pin2);
1886                 /*
1887                  * legacy devices should be connected to IO APIC #0
1888                  */
1889                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1890                 if (timer_irq_works()) {
1891                         apic_printk(APIC_VERBOSE," works.\n");
1892                         nmi_watchdog_default();
1893                         if (nmi_watchdog == NMI_IO_APIC) {
1894                                 setup_nmi();
1895                         }
1896                         return;
1897                 }
1898                 /*
1899                  * Cleanup, just in case ...
1900                  */
1901                 clear_IO_APIC_pin(apic2, pin2);
1902         }
1903         apic_printk(APIC_VERBOSE," failed.\n");
1904
1905         if (nmi_watchdog == NMI_IO_APIC) {
1906                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1907                 nmi_watchdog = 0;
1908         }
1909
1910         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1911
1912         disable_8259A_irq(0);
1913         irq_desc[0].chip = &lapic_irq_type;
1914         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1915         enable_8259A_irq(0);
1916
1917         if (timer_irq_works()) {
1918                 apic_printk(APIC_VERBOSE," works.\n");
1919                 return;
1920         }
1921         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1922         apic_printk(APIC_VERBOSE," failed.\n");
1923
1924         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1925
1926         init_8259A(0);
1927         make_8259A_irq(0);
1928         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1929
1930         unlock_ExtINT_logic();
1931
1932         if (timer_irq_works()) {
1933                 apic_printk(APIC_VERBOSE," works.\n");
1934                 return;
1935         }
1936         apic_printk(APIC_VERBOSE," failed :(.\n");
1937         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1938 }
1939
1940 static int __init notimercheck(char *s)
1941 {
1942         no_timer_check = 1;
1943         return 1;
1944 }
1945 __setup("no_timer_check", notimercheck);
1946
1947 /*
1948  *
1949  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1950  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1951  *   Linux doesn't really care, as it's not actually used
1952  *   for any interrupt handling anyway.
1953  */
1954 #define PIC_IRQS        (1<<2)
1955
1956 void __init setup_IO_APIC(void)
1957 {
1958         enable_IO_APIC();
1959
1960         if (acpi_ioapic)
1961                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1962         else
1963                 io_apic_irqs = ~PIC_IRQS;
1964
1965         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1966
1967         /*
1968          * Set up the IO-APIC IRQ routing table.
1969          */
1970         if (!acpi_ioapic)
1971                 setup_ioapic_ids_from_mpc();
1972         sync_Arb_IDs();
1973         setup_IO_APIC_irqs();
1974         init_IO_APIC_traps();
1975         check_timer();
1976         if (!acpi_ioapic)
1977                 print_IO_APIC();
1978 }
1979
1980 struct sysfs_ioapic_data {
1981         struct sys_device dev;
1982         struct IO_APIC_route_entry entry[0];
1983 };
1984 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1985
1986 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1987 {
1988         struct IO_APIC_route_entry *entry;
1989         struct sysfs_ioapic_data *data;
1990         unsigned long flags;
1991         int i;
1992
1993         data = container_of(dev, struct sysfs_ioapic_data, dev);
1994         entry = data->entry;
1995         spin_lock_irqsave(&ioapic_lock, flags);
1996         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1997                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1998                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1999         }
2000         spin_unlock_irqrestore(&ioapic_lock, flags);
2001
2002         return 0;
2003 }
2004
2005 static int ioapic_resume(struct sys_device *dev)
2006 {
2007         struct IO_APIC_route_entry *entry;
2008         struct sysfs_ioapic_data *data;
2009         unsigned long flags;
2010         union IO_APIC_reg_00 reg_00;
2011         int i;
2012
2013         data = container_of(dev, struct sysfs_ioapic_data, dev);
2014         entry = data->entry;
2015
2016         spin_lock_irqsave(&ioapic_lock, flags);
2017         reg_00.raw = io_apic_read(dev->id, 0);
2018         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2019                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2020                 io_apic_write(dev->id, 0, reg_00.raw);
2021         }
2022         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2023                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2024                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2025         }
2026         spin_unlock_irqrestore(&ioapic_lock, flags);
2027
2028         return 0;
2029 }
2030
2031 static struct sysdev_class ioapic_sysdev_class = {
2032         set_kset_name("ioapic"),
2033         .suspend = ioapic_suspend,
2034         .resume = ioapic_resume,
2035 };
2036
2037 static int __init ioapic_init_sysfs(void)
2038 {
2039         struct sys_device * dev;
2040         int i, size, error = 0;
2041
2042         error = sysdev_class_register(&ioapic_sysdev_class);
2043         if (error)
2044                 return error;
2045
2046         for (i = 0; i < nr_ioapics; i++ ) {
2047                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2048                         * sizeof(struct IO_APIC_route_entry);
2049                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2050                 if (!mp_ioapic_data[i]) {
2051                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2052                         continue;
2053                 }
2054                 memset(mp_ioapic_data[i], 0, size);
2055                 dev = &mp_ioapic_data[i]->dev;
2056                 dev->id = i;
2057                 dev->cls = &ioapic_sysdev_class;
2058                 error = sysdev_register(dev);
2059                 if (error) {
2060                         kfree(mp_ioapic_data[i]);
2061                         mp_ioapic_data[i] = NULL;
2062                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2063                         continue;
2064                 }
2065         }
2066
2067         return 0;
2068 }
2069
2070 device_initcall(ioapic_init_sysfs);
2071
2072 /* --------------------------------------------------------------------------
2073                           ACPI-based IOAPIC Configuration
2074    -------------------------------------------------------------------------- */
2075
2076 #ifdef CONFIG_ACPI
2077
2078 #define IO_APIC_MAX_ID          0xFE
2079
2080 int __init io_apic_get_version (int ioapic)
2081 {
2082         union IO_APIC_reg_01    reg_01;
2083         unsigned long flags;
2084
2085         spin_lock_irqsave(&ioapic_lock, flags);
2086         reg_01.raw = io_apic_read(ioapic, 1);
2087         spin_unlock_irqrestore(&ioapic_lock, flags);
2088
2089         return reg_01.bits.version;
2090 }
2091
2092
2093 int __init io_apic_get_redir_entries (int ioapic)
2094 {
2095         union IO_APIC_reg_01    reg_01;
2096         unsigned long flags;
2097
2098         spin_lock_irqsave(&ioapic_lock, flags);
2099         reg_01.raw = io_apic_read(ioapic, 1);
2100         spin_unlock_irqrestore(&ioapic_lock, flags);
2101
2102         return reg_01.bits.entries;
2103 }
2104
2105
2106 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2107 {
2108         struct IO_APIC_route_entry entry;
2109         unsigned long flags;
2110
2111         if (!IO_APIC_IRQ(irq)) {
2112                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2113                         ioapic);
2114                 return -EINVAL;
2115         }
2116
2117         /*
2118          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2119          * Note that we mask (disable) IRQs now -- these get enabled when the
2120          * corresponding device driver registers for this IRQ.
2121          */
2122
2123         memset(&entry,0,sizeof(entry));
2124
2125         entry.delivery_mode = INT_DELIVERY_MODE;
2126         entry.dest_mode = INT_DEST_MODE;
2127         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2128         entry.trigger = triggering;
2129         entry.polarity = polarity;
2130         entry.mask = 1;                                  /* Disabled (masked) */
2131
2132         irq = gsi_irq_sharing(irq);
2133         /*
2134          * IRQs < 16 are already in the irq_2_pin[] map
2135          */
2136         if (irq >= 16)
2137                 add_pin_to_irq(irq, ioapic, pin);
2138
2139         entry.vector = assign_irq_vector(irq);
2140
2141         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2142                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2143                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2144                triggering, polarity);
2145
2146         ioapic_register_intr(irq, entry.vector, triggering);
2147
2148         if (!ioapic && (irq < 16))
2149                 disable_8259A_irq(irq);
2150
2151         spin_lock_irqsave(&ioapic_lock, flags);
2152         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2153         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2154         set_native_irq_info(use_pci_vector() ?  entry.vector : irq, TARGET_CPUS);
2155         spin_unlock_irqrestore(&ioapic_lock, flags);
2156
2157         return 0;
2158 }
2159
2160 #endif /* CONFIG_ACPI */
2161
2162
2163 /*
2164  * This function currently is only a helper for the i386 smp boot process where
2165  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2166  * so mask in all cases should simply be TARGET_CPUS
2167  */
2168 #ifdef CONFIG_SMP
2169 void __init setup_ioapic_dest(void)
2170 {
2171         int pin, ioapic, irq, irq_entry;
2172
2173         if (skip_ioapic_setup == 1)
2174                 return;
2175
2176         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2177                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2178                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2179                         if (irq_entry == -1)
2180                                 continue;
2181                         irq = pin_2_irq(irq_entry, ioapic, pin);
2182                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
2183                 }
2184
2185         }
2186 }
2187 #endif