[PATCH] x86-64: typo in __assign_irq_vector when updating pos for vector and offset
[sfrench/cifs-2.6.git] / arch / x86_64 / kernel / io_apic.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
33 #include <linux/msi.h>
34 #include <linux/htirq.h>
35 #ifdef CONFIG_ACPI
36 #include <acpi/acpi_bus.h>
37 #endif
38
39 #include <asm/io.h>
40 #include <asm/smp.h>
41 #include <asm/desc.h>
42 #include <asm/proto.h>
43 #include <asm/mach_apic.h>
44 #include <asm/acpi.h>
45 #include <asm/dma.h>
46 #include <asm/nmi.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49
50 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result);
51
52 #define __apicdebuginit  __init
53
54 int sis_apic_bug; /* not actually supported, dummy for compile */
55
56 static int no_timer_check;
57
58 static int disable_timer_pin_1 __initdata;
59
60 int timer_over_8254 __initdata = 0;
61
62 /* Where if anywhere is the i8259 connect in external int mode */
63 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
64
65 static DEFINE_SPINLOCK(ioapic_lock);
66 static DEFINE_SPINLOCK(vector_lock);
67
68 /*
69  * # of IRQ routing registers
70  */
71 int nr_ioapic_registers[MAX_IO_APICS];
72
73 /*
74  * Rough estimation of how many shared IRQs there are, can
75  * be changed anytime.
76  */
77 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
78 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
79
80 /*
81  * This is performance-critical, we want to do it O(1)
82  *
83  * the indexing order of this array favors 1:1 mappings
84  * between pins and IRQs.
85  */
86
87 static struct irq_pin_list {
88         short apic, pin, next;
89 } irq_2_pin[PIN_MAP_SIZE];
90
91 #define __DO_ACTION(R, ACTION, FINAL)                                   \
92                                                                         \
93 {                                                                       \
94         int pin;                                                        \
95         struct irq_pin_list *entry = irq_2_pin + irq;                   \
96                                                                         \
97         BUG_ON(irq >= NR_IRQS);                                         \
98         for (;;) {                                                      \
99                 unsigned int reg;                                       \
100                 pin = entry->pin;                                       \
101                 if (pin == -1)                                          \
102                         break;                                          \
103                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
104                 reg ACTION;                                             \
105                 io_apic_modify(entry->apic, reg);                       \
106                 if (!entry->next)                                       \
107                         break;                                          \
108                 entry = irq_2_pin + entry->next;                        \
109         }                                                               \
110         FINAL;                                                          \
111 }
112
113 union entry_union {
114         struct { u32 w1, w2; };
115         struct IO_APIC_route_entry entry;
116 };
117
118 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
119 {
120         union entry_union eu;
121         unsigned long flags;
122         spin_lock_irqsave(&ioapic_lock, flags);
123         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
124         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
125         spin_unlock_irqrestore(&ioapic_lock, flags);
126         return eu.entry;
127 }
128
129 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
130 {
131         unsigned long flags;
132         union entry_union eu;
133         eu.entry = e;
134         spin_lock_irqsave(&ioapic_lock, flags);
135         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
136         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
137         spin_unlock_irqrestore(&ioapic_lock, flags);
138 }
139
140 #ifdef CONFIG_SMP
141 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
142 {
143         int apic, pin;
144         struct irq_pin_list *entry = irq_2_pin + irq;
145
146         BUG_ON(irq >= NR_IRQS);
147         for (;;) {
148                 unsigned int reg;
149                 apic = entry->apic;
150                 pin = entry->pin;
151                 if (pin == -1)
152                         break;
153                 io_apic_write(apic, 0x11 + pin*2, dest);
154                 reg = io_apic_read(apic, 0x10 + pin*2);
155                 reg &= ~0x000000ff;
156                 reg |= vector;
157                 io_apic_modify(apic, reg);
158                 if (!entry->next)
159                         break;
160                 entry = irq_2_pin + entry->next;
161         }
162 }
163
164 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
165 {
166         unsigned long flags;
167         unsigned int dest;
168         cpumask_t tmp;
169         int vector;
170
171         cpus_and(tmp, mask, cpu_online_map);
172         if (cpus_empty(tmp))
173                 tmp = TARGET_CPUS;
174
175         cpus_and(mask, tmp, CPU_MASK_ALL);
176
177         vector = assign_irq_vector(irq, mask, &tmp);
178         if (vector < 0)
179                 return;
180
181         dest = cpu_mask_to_apicid(tmp);
182
183         /*
184          * Only the high 8 bits are valid.
185          */
186         dest = SET_APIC_LOGICAL_ID(dest);
187
188         spin_lock_irqsave(&ioapic_lock, flags);
189         __target_IO_APIC_irq(irq, dest, vector);
190         set_native_irq_info(irq, mask);
191         spin_unlock_irqrestore(&ioapic_lock, flags);
192 }
193 #endif
194
195 /*
196  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
197  * shared ISA-space IRQs, so we have to support them. We are super
198  * fast in the common case, and fast for shared ISA-space IRQs.
199  */
200 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
201 {
202         static int first_free_entry = NR_IRQS;
203         struct irq_pin_list *entry = irq_2_pin + irq;
204
205         BUG_ON(irq >= NR_IRQS);
206         while (entry->next)
207                 entry = irq_2_pin + entry->next;
208
209         if (entry->pin != -1) {
210                 entry->next = first_free_entry;
211                 entry = irq_2_pin + entry->next;
212                 if (++first_free_entry >= PIN_MAP_SIZE)
213                         panic("io_apic.c: ran out of irq_2_pin entries!");
214         }
215         entry->apic = apic;
216         entry->pin = pin;
217 }
218
219
220 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
221                                                                         \
222         static void name##_IO_APIC_irq (unsigned int irq)               \
223         __DO_ACTION(R, ACTION, FINAL)
224
225 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
226                                                 /* mask = 1 */
227 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
228                                                 /* mask = 0 */
229
230 static void mask_IO_APIC_irq (unsigned int irq)
231 {
232         unsigned long flags;
233
234         spin_lock_irqsave(&ioapic_lock, flags);
235         __mask_IO_APIC_irq(irq);
236         spin_unlock_irqrestore(&ioapic_lock, flags);
237 }
238
239 static void unmask_IO_APIC_irq (unsigned int irq)
240 {
241         unsigned long flags;
242
243         spin_lock_irqsave(&ioapic_lock, flags);
244         __unmask_IO_APIC_irq(irq);
245         spin_unlock_irqrestore(&ioapic_lock, flags);
246 }
247
248 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
249 {
250         struct IO_APIC_route_entry entry;
251
252         /* Check delivery_mode to be sure we're not clearing an SMI pin */
253         entry = ioapic_read_entry(apic, pin);
254         if (entry.delivery_mode == dest_SMI)
255                 return;
256         /*
257          * Disable it in the IO-APIC irq-routing table:
258          */
259         memset(&entry, 0, sizeof(entry));
260         entry.mask = 1;
261         ioapic_write_entry(apic, pin, entry);
262 }
263
264 static void clear_IO_APIC (void)
265 {
266         int apic, pin;
267
268         for (apic = 0; apic < nr_ioapics; apic++)
269                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
270                         clear_IO_APIC_pin(apic, pin);
271 }
272
273 int skip_ioapic_setup;
274 int ioapic_force;
275
276 /* dummy parsing: see setup.c */
277
278 static int __init disable_ioapic_setup(char *str)
279 {
280         skip_ioapic_setup = 1;
281         return 0;
282 }
283 early_param("noapic", disable_ioapic_setup);
284
285 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
286 static int __init disable_timer_pin_setup(char *arg)
287 {
288         disable_timer_pin_1 = 1;
289         return 1;
290 }
291 __setup("disable_timer_pin_1", disable_timer_pin_setup);
292
293 static int __init setup_disable_8254_timer(char *s)
294 {
295         timer_over_8254 = -1;
296         return 1;
297 }
298 static int __init setup_enable_8254_timer(char *s)
299 {
300         timer_over_8254 = 2;
301         return 1;
302 }
303
304 __setup("disable_8254_timer", setup_disable_8254_timer);
305 __setup("enable_8254_timer", setup_enable_8254_timer);
306
307
308 /*
309  * Find the IRQ entry number of a certain pin.
310  */
311 static int find_irq_entry(int apic, int pin, int type)
312 {
313         int i;
314
315         for (i = 0; i < mp_irq_entries; i++)
316                 if (mp_irqs[i].mpc_irqtype == type &&
317                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
318                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
319                     mp_irqs[i].mpc_dstirq == pin)
320                         return i;
321
322         return -1;
323 }
324
325 /*
326  * Find the pin to which IRQ[irq] (ISA) is connected
327  */
328 static int __init find_isa_irq_pin(int irq, int type)
329 {
330         int i;
331
332         for (i = 0; i < mp_irq_entries; i++) {
333                 int lbus = mp_irqs[i].mpc_srcbus;
334
335                 if (test_bit(lbus, mp_bus_not_pci) &&
336                     (mp_irqs[i].mpc_irqtype == type) &&
337                     (mp_irqs[i].mpc_srcbusirq == irq))
338
339                         return mp_irqs[i].mpc_dstirq;
340         }
341         return -1;
342 }
343
344 static int __init find_isa_irq_apic(int irq, int type)
345 {
346         int i;
347
348         for (i = 0; i < mp_irq_entries; i++) {
349                 int lbus = mp_irqs[i].mpc_srcbus;
350
351                 if (test_bit(lbus, mp_bus_not_pci) &&
352                     (mp_irqs[i].mpc_irqtype == type) &&
353                     (mp_irqs[i].mpc_srcbusirq == irq))
354                         break;
355         }
356         if (i < mp_irq_entries) {
357                 int apic;
358                 for(apic = 0; apic < nr_ioapics; apic++) {
359                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
360                                 return apic;
361                 }
362         }
363
364         return -1;
365 }
366
367 /*
368  * Find a specific PCI IRQ entry.
369  * Not an __init, possibly needed by modules
370  */
371 static int pin_2_irq(int idx, int apic, int pin);
372
373 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
374 {
375         int apic, i, best_guess = -1;
376
377         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
378                 bus, slot, pin);
379         if (mp_bus_id_to_pci_bus[bus] == -1) {
380                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
381                 return -1;
382         }
383         for (i = 0; i < mp_irq_entries; i++) {
384                 int lbus = mp_irqs[i].mpc_srcbus;
385
386                 for (apic = 0; apic < nr_ioapics; apic++)
387                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
388                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
389                                 break;
390
391                 if (!test_bit(lbus, mp_bus_not_pci) &&
392                     !mp_irqs[i].mpc_irqtype &&
393                     (bus == lbus) &&
394                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
395                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
396
397                         if (!(apic || IO_APIC_IRQ(irq)))
398                                 continue;
399
400                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
401                                 return irq;
402                         /*
403                          * Use the first all-but-pin matching entry as a
404                          * best-guess fuzzy result for broken mptables.
405                          */
406                         if (best_guess < 0)
407                                 best_guess = irq;
408                 }
409         }
410         BUG_ON(best_guess >= NR_IRQS);
411         return best_guess;
412 }
413
414 /* ISA interrupts are always polarity zero edge triggered,
415  * when listed as conforming in the MP table. */
416
417 #define default_ISA_trigger(idx)        (0)
418 #define default_ISA_polarity(idx)       (0)
419
420 /* PCI interrupts are always polarity one level triggered,
421  * when listed as conforming in the MP table. */
422
423 #define default_PCI_trigger(idx)        (1)
424 #define default_PCI_polarity(idx)       (1)
425
426 static int __init MPBIOS_polarity(int idx)
427 {
428         int bus = mp_irqs[idx].mpc_srcbus;
429         int polarity;
430
431         /*
432          * Determine IRQ line polarity (high active or low active):
433          */
434         switch (mp_irqs[idx].mpc_irqflag & 3)
435         {
436                 case 0: /* conforms, ie. bus-type dependent polarity */
437                         if (test_bit(bus, mp_bus_not_pci))
438                                 polarity = default_ISA_polarity(idx);
439                         else
440                                 polarity = default_PCI_polarity(idx);
441                         break;
442                 case 1: /* high active */
443                 {
444                         polarity = 0;
445                         break;
446                 }
447                 case 2: /* reserved */
448                 {
449                         printk(KERN_WARNING "broken BIOS!!\n");
450                         polarity = 1;
451                         break;
452                 }
453                 case 3: /* low active */
454                 {
455                         polarity = 1;
456                         break;
457                 }
458                 default: /* invalid */
459                 {
460                         printk(KERN_WARNING "broken BIOS!!\n");
461                         polarity = 1;
462                         break;
463                 }
464         }
465         return polarity;
466 }
467
468 static int MPBIOS_trigger(int idx)
469 {
470         int bus = mp_irqs[idx].mpc_srcbus;
471         int trigger;
472
473         /*
474          * Determine IRQ trigger mode (edge or level sensitive):
475          */
476         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
477         {
478                 case 0: /* conforms, ie. bus-type dependent */
479                         if (test_bit(bus, mp_bus_not_pci))
480                                 trigger = default_ISA_trigger(idx);
481                         else
482                                 trigger = default_PCI_trigger(idx);
483                         break;
484                 case 1: /* edge */
485                 {
486                         trigger = 0;
487                         break;
488                 }
489                 case 2: /* reserved */
490                 {
491                         printk(KERN_WARNING "broken BIOS!!\n");
492                         trigger = 1;
493                         break;
494                 }
495                 case 3: /* level */
496                 {
497                         trigger = 1;
498                         break;
499                 }
500                 default: /* invalid */
501                 {
502                         printk(KERN_WARNING "broken BIOS!!\n");
503                         trigger = 0;
504                         break;
505                 }
506         }
507         return trigger;
508 }
509
510 static inline int irq_polarity(int idx)
511 {
512         return MPBIOS_polarity(idx);
513 }
514
515 static inline int irq_trigger(int idx)
516 {
517         return MPBIOS_trigger(idx);
518 }
519
520 static int pin_2_irq(int idx, int apic, int pin)
521 {
522         int irq, i;
523         int bus = mp_irqs[idx].mpc_srcbus;
524
525         /*
526          * Debugging check, we are in big trouble if this message pops up!
527          */
528         if (mp_irqs[idx].mpc_dstirq != pin)
529                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
530
531         if (test_bit(bus, mp_bus_not_pci)) {
532                 irq = mp_irqs[idx].mpc_srcbusirq;
533         } else {
534                 /*
535                  * PCI IRQs are mapped in order
536                  */
537                 i = irq = 0;
538                 while (i < apic)
539                         irq += nr_ioapic_registers[i++];
540                 irq += pin;
541         }
542         BUG_ON(irq >= NR_IRQS);
543         return irq;
544 }
545
546 static inline int IO_APIC_irq_trigger(int irq)
547 {
548         int apic, idx, pin;
549
550         for (apic = 0; apic < nr_ioapics; apic++) {
551                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
552                         idx = find_irq_entry(apic,pin,mp_INT);
553                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
554                                 return irq_trigger(idx);
555                 }
556         }
557         /*
558          * nonexistent IRQs are edge default
559          */
560         return 0;
561 }
562
563 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
564 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = {
565         [0] = FIRST_EXTERNAL_VECTOR + 0,
566         [1] = FIRST_EXTERNAL_VECTOR + 1,
567         [2] = FIRST_EXTERNAL_VECTOR + 2,
568         [3] = FIRST_EXTERNAL_VECTOR + 3,
569         [4] = FIRST_EXTERNAL_VECTOR + 4,
570         [5] = FIRST_EXTERNAL_VECTOR + 5,
571         [6] = FIRST_EXTERNAL_VECTOR + 6,
572         [7] = FIRST_EXTERNAL_VECTOR + 7,
573         [8] = FIRST_EXTERNAL_VECTOR + 8,
574         [9] = FIRST_EXTERNAL_VECTOR + 9,
575         [10] = FIRST_EXTERNAL_VECTOR + 10,
576         [11] = FIRST_EXTERNAL_VECTOR + 11,
577         [12] = FIRST_EXTERNAL_VECTOR + 12,
578         [13] = FIRST_EXTERNAL_VECTOR + 13,
579         [14] = FIRST_EXTERNAL_VECTOR + 14,
580         [15] = FIRST_EXTERNAL_VECTOR + 15,
581 };
582
583 static cpumask_t irq_domain[NR_IRQ_VECTORS] __read_mostly = {
584         [0] = CPU_MASK_ALL,
585         [1] = CPU_MASK_ALL,
586         [2] = CPU_MASK_ALL,
587         [3] = CPU_MASK_ALL,
588         [4] = CPU_MASK_ALL,
589         [5] = CPU_MASK_ALL,
590         [6] = CPU_MASK_ALL,
591         [7] = CPU_MASK_ALL,
592         [8] = CPU_MASK_ALL,
593         [9] = CPU_MASK_ALL,
594         [10] = CPU_MASK_ALL,
595         [11] = CPU_MASK_ALL,
596         [12] = CPU_MASK_ALL,
597         [13] = CPU_MASK_ALL,
598         [14] = CPU_MASK_ALL,
599         [15] = CPU_MASK_ALL,
600 };
601
602 static int __assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
603 {
604         /*
605          * NOTE! The local APIC isn't very good at handling
606          * multiple interrupts at the same interrupt level.
607          * As the interrupt level is determined by taking the
608          * vector number and shifting that right by 4, we
609          * want to spread these out a bit so that they don't
610          * all fall in the same interrupt level.
611          *
612          * Also, we've got to be careful not to trash gate
613          * 0x80, because int 0x80 is hm, kind of importantish. ;)
614          */
615         static struct {
616                 int vector;
617                 int offset;
618         } pos[NR_CPUS] = { [ 0 ... NR_CPUS - 1] = {FIRST_DEVICE_VECTOR, 0} };
619         int old_vector = -1;
620         int cpu;
621
622         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
623
624         if (irq_vector[irq] > 0)
625                 old_vector = irq_vector[irq];
626         if (old_vector > 0) {
627                 cpus_and(*result, irq_domain[irq], mask);
628                 if (!cpus_empty(*result))
629                         return old_vector;
630         }
631
632         for_each_cpu_mask(cpu, mask) {
633                 cpumask_t domain;
634                 int first, new_cpu;
635                 int vector, offset;
636
637                 domain = vector_allocation_domain(cpu);
638                 first = first_cpu(domain);
639
640                 vector = pos[first].vector;
641                 offset = pos[first].offset;
642 next:
643                 vector += 8;
644                 if (vector >= FIRST_SYSTEM_VECTOR) {
645                         /* If we run out of vectors on large boxen, must share them. */
646                         offset = (offset + 1) % 8;
647                         vector = FIRST_DEVICE_VECTOR + offset;
648                 }
649                 if (unlikely(pos[first].vector == vector))
650                         continue;
651                 if (vector == IA32_SYSCALL_VECTOR)
652                         goto next;
653                 for_each_cpu_mask(new_cpu, domain)
654                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
655                                 goto next;
656                 /* Found one! */
657                 for_each_cpu_mask(new_cpu, domain) {
658                         pos[new_cpu].vector = vector;
659                         pos[new_cpu].offset = offset;
660                 }
661                 if (old_vector >= 0) {
662                         int old_cpu;
663                         for_each_cpu_mask(old_cpu, irq_domain[irq])
664                                 per_cpu(vector_irq, old_cpu)[old_vector] = -1;
665                 }
666                 for_each_cpu_mask(new_cpu, domain)
667                         per_cpu(vector_irq, new_cpu)[vector] = irq;
668                 irq_vector[irq] = vector;
669                 irq_domain[irq] = domain;
670                 cpus_and(*result, domain, mask);
671                 return vector;
672         }
673         return -ENOSPC;
674 }
675
676 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
677 {
678         int vector;
679         unsigned long flags;
680
681         spin_lock_irqsave(&vector_lock, flags);
682         vector = __assign_irq_vector(irq, mask, result);
683         spin_unlock_irqrestore(&vector_lock, flags);
684         return vector;
685 }
686
687 extern void (*interrupt[NR_IRQS])(void);
688
689 static struct irq_chip ioapic_chip;
690
691 #define IOAPIC_AUTO     -1
692 #define IOAPIC_EDGE     0
693 #define IOAPIC_LEVEL    1
694
695 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
696 {
697         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
698                         trigger == IOAPIC_LEVEL)
699                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
700                                               handle_fasteoi_irq, "fasteoi");
701         else
702                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
703                                               handle_edge_irq, "edge");
704 }
705
706 static void __init setup_IO_APIC_irqs(void)
707 {
708         struct IO_APIC_route_entry entry;
709         int apic, pin, idx, irq, first_notcon = 1, vector;
710         unsigned long flags;
711
712         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
713
714         for (apic = 0; apic < nr_ioapics; apic++) {
715         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
716
717                 /*
718                  * add it to the IO-APIC irq-routing table:
719                  */
720                 memset(&entry,0,sizeof(entry));
721
722                 entry.delivery_mode = INT_DELIVERY_MODE;
723                 entry.dest_mode = INT_DEST_MODE;
724                 entry.mask = 0;                         /* enable IRQ */
725                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
726
727                 idx = find_irq_entry(apic,pin,mp_INT);
728                 if (idx == -1) {
729                         if (first_notcon) {
730                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
731                                 first_notcon = 0;
732                         } else
733                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
734                         continue;
735                 }
736
737                 entry.trigger = irq_trigger(idx);
738                 entry.polarity = irq_polarity(idx);
739
740                 if (irq_trigger(idx)) {
741                         entry.trigger = 1;
742                         entry.mask = 1;
743                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
744                 }
745
746                 irq = pin_2_irq(idx, apic, pin);
747                 add_pin_to_irq(irq, apic, pin);
748
749                 if (!apic && !IO_APIC_IRQ(irq))
750                         continue;
751
752                 if (IO_APIC_IRQ(irq)) {
753                         cpumask_t mask;
754                         vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
755                         if (vector < 0)
756                                 continue;
757
758                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
759                         entry.vector = vector;
760
761                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
762                         if (!apic && (irq < 16))
763                                 disable_8259A_irq(irq);
764                 }
765                 ioapic_write_entry(apic, pin, entry);
766
767                 spin_lock_irqsave(&ioapic_lock, flags);
768                 set_native_irq_info(irq, TARGET_CPUS);
769                 spin_unlock_irqrestore(&ioapic_lock, flags);
770         }
771         }
772
773         if (!first_notcon)
774                 apic_printk(APIC_VERBOSE," not connected.\n");
775 }
776
777 /*
778  * Set up the 8259A-master output pin as broadcast to all
779  * CPUs.
780  */
781 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
782 {
783         struct IO_APIC_route_entry entry;
784         unsigned long flags;
785
786         memset(&entry,0,sizeof(entry));
787
788         disable_8259A_irq(0);
789
790         /* mask LVT0 */
791         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
792
793         /*
794          * We use logical delivery to get the timer IRQ
795          * to the first CPU.
796          */
797         entry.dest_mode = INT_DEST_MODE;
798         entry.mask = 0;                                 /* unmask IRQ now */
799         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
800         entry.delivery_mode = INT_DELIVERY_MODE;
801         entry.polarity = 0;
802         entry.trigger = 0;
803         entry.vector = vector;
804
805         /*
806          * The timer IRQ doesn't have to know that behind the
807          * scene we have a 8259A-master in AEOI mode ...
808          */
809         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
810
811         /*
812          * Add it to the IO-APIC irq-routing table:
813          */
814         spin_lock_irqsave(&ioapic_lock, flags);
815         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
816         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
817         spin_unlock_irqrestore(&ioapic_lock, flags);
818
819         enable_8259A_irq(0);
820 }
821
822 void __init UNEXPECTED_IO_APIC(void)
823 {
824 }
825
826 void __apicdebuginit print_IO_APIC(void)
827 {
828         int apic, i;
829         union IO_APIC_reg_00 reg_00;
830         union IO_APIC_reg_01 reg_01;
831         union IO_APIC_reg_02 reg_02;
832         unsigned long flags;
833
834         if (apic_verbosity == APIC_QUIET)
835                 return;
836
837         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
838         for (i = 0; i < nr_ioapics; i++)
839                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
840                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
841
842         /*
843          * We are a bit conservative about what we expect.  We have to
844          * know about every hardware change ASAP.
845          */
846         printk(KERN_INFO "testing the IO APIC.......................\n");
847
848         for (apic = 0; apic < nr_ioapics; apic++) {
849
850         spin_lock_irqsave(&ioapic_lock, flags);
851         reg_00.raw = io_apic_read(apic, 0);
852         reg_01.raw = io_apic_read(apic, 1);
853         if (reg_01.bits.version >= 0x10)
854                 reg_02.raw = io_apic_read(apic, 2);
855         spin_unlock_irqrestore(&ioapic_lock, flags);
856
857         printk("\n");
858         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
859         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
860         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
861         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
862                 UNEXPECTED_IO_APIC();
863
864         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
865         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
866         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
867                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
868                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
869                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
870                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
871                 (reg_01.bits.entries != 0x2E) &&
872                 (reg_01.bits.entries != 0x3F) &&
873                 (reg_01.bits.entries != 0x03) 
874         )
875                 UNEXPECTED_IO_APIC();
876
877         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
878         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
879         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
880                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
881                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
882                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
883                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
884                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
885         )
886                 UNEXPECTED_IO_APIC();
887         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
888                 UNEXPECTED_IO_APIC();
889
890         if (reg_01.bits.version >= 0x10) {
891                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
892                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
893                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
894                         UNEXPECTED_IO_APIC();
895         }
896
897         printk(KERN_DEBUG ".... IRQ redirection table:\n");
898
899         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
900                           " Stat Dest Deli Vect:   \n");
901
902         for (i = 0; i <= reg_01.bits.entries; i++) {
903                 struct IO_APIC_route_entry entry;
904
905                 entry = ioapic_read_entry(apic, i);
906
907                 printk(KERN_DEBUG " %02x %03X %02X  ",
908                         i,
909                         entry.dest.logical.logical_dest,
910                         entry.dest.physical.physical_dest
911                 );
912
913                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
914                         entry.mask,
915                         entry.trigger,
916                         entry.irr,
917                         entry.polarity,
918                         entry.delivery_status,
919                         entry.dest_mode,
920                         entry.delivery_mode,
921                         entry.vector
922                 );
923         }
924         }
925         printk(KERN_DEBUG "IRQ to pin mappings:\n");
926         for (i = 0; i < NR_IRQS; i++) {
927                 struct irq_pin_list *entry = irq_2_pin + i;
928                 if (entry->pin < 0)
929                         continue;
930                 printk(KERN_DEBUG "IRQ%d ", i);
931                 for (;;) {
932                         printk("-> %d:%d", entry->apic, entry->pin);
933                         if (!entry->next)
934                                 break;
935                         entry = irq_2_pin + entry->next;
936                 }
937                 printk("\n");
938         }
939
940         printk(KERN_INFO ".................................... done.\n");
941
942         return;
943 }
944
945 #if 0
946
947 static __apicdebuginit void print_APIC_bitfield (int base)
948 {
949         unsigned int v;
950         int i, j;
951
952         if (apic_verbosity == APIC_QUIET)
953                 return;
954
955         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
956         for (i = 0; i < 8; i++) {
957                 v = apic_read(base + i*0x10);
958                 for (j = 0; j < 32; j++) {
959                         if (v & (1<<j))
960                                 printk("1");
961                         else
962                                 printk("0");
963                 }
964                 printk("\n");
965         }
966 }
967
968 void __apicdebuginit print_local_APIC(void * dummy)
969 {
970         unsigned int v, ver, maxlvt;
971
972         if (apic_verbosity == APIC_QUIET)
973                 return;
974
975         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
976                 smp_processor_id(), hard_smp_processor_id());
977         v = apic_read(APIC_ID);
978         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
979         v = apic_read(APIC_LVR);
980         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
981         ver = GET_APIC_VERSION(v);
982         maxlvt = get_maxlvt();
983
984         v = apic_read(APIC_TASKPRI);
985         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
986
987         v = apic_read(APIC_ARBPRI);
988         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
989                 v & APIC_ARBPRI_MASK);
990         v = apic_read(APIC_PROCPRI);
991         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
992
993         v = apic_read(APIC_EOI);
994         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
995         v = apic_read(APIC_RRR);
996         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
997         v = apic_read(APIC_LDR);
998         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
999         v = apic_read(APIC_DFR);
1000         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1001         v = apic_read(APIC_SPIV);
1002         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1003
1004         printk(KERN_DEBUG "... APIC ISR field:\n");
1005         print_APIC_bitfield(APIC_ISR);
1006         printk(KERN_DEBUG "... APIC TMR field:\n");
1007         print_APIC_bitfield(APIC_TMR);
1008         printk(KERN_DEBUG "... APIC IRR field:\n");
1009         print_APIC_bitfield(APIC_IRR);
1010
1011         v = apic_read(APIC_ESR);
1012         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1013
1014         v = apic_read(APIC_ICR);
1015         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1016         v = apic_read(APIC_ICR2);
1017         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1018
1019         v = apic_read(APIC_LVTT);
1020         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1021
1022         if (maxlvt > 3) {                       /* PC is LVT#4. */
1023                 v = apic_read(APIC_LVTPC);
1024                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1025         }
1026         v = apic_read(APIC_LVT0);
1027         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1028         v = apic_read(APIC_LVT1);
1029         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1030
1031         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1032                 v = apic_read(APIC_LVTERR);
1033                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1034         }
1035
1036         v = apic_read(APIC_TMICT);
1037         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1038         v = apic_read(APIC_TMCCT);
1039         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1040         v = apic_read(APIC_TDCR);
1041         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1042         printk("\n");
1043 }
1044
1045 void print_all_local_APICs (void)
1046 {
1047         on_each_cpu(print_local_APIC, NULL, 1, 1);
1048 }
1049
1050 void __apicdebuginit print_PIC(void)
1051 {
1052         unsigned int v;
1053         unsigned long flags;
1054
1055         if (apic_verbosity == APIC_QUIET)
1056                 return;
1057
1058         printk(KERN_DEBUG "\nprinting PIC contents\n");
1059
1060         spin_lock_irqsave(&i8259A_lock, flags);
1061
1062         v = inb(0xa1) << 8 | inb(0x21);
1063         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1064
1065         v = inb(0xa0) << 8 | inb(0x20);
1066         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1067
1068         outb(0x0b,0xa0);
1069         outb(0x0b,0x20);
1070         v = inb(0xa0) << 8 | inb(0x20);
1071         outb(0x0a,0xa0);
1072         outb(0x0a,0x20);
1073
1074         spin_unlock_irqrestore(&i8259A_lock, flags);
1075
1076         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1077
1078         v = inb(0x4d1) << 8 | inb(0x4d0);
1079         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1080 }
1081
1082 #endif  /*  0  */
1083
1084 static void __init enable_IO_APIC(void)
1085 {
1086         union IO_APIC_reg_01 reg_01;
1087         int i8259_apic, i8259_pin;
1088         int i, apic;
1089         unsigned long flags;
1090
1091         for (i = 0; i < PIN_MAP_SIZE; i++) {
1092                 irq_2_pin[i].pin = -1;
1093                 irq_2_pin[i].next = 0;
1094         }
1095
1096         /*
1097          * The number of IO-APIC IRQ registers (== #pins):
1098          */
1099         for (apic = 0; apic < nr_ioapics; apic++) {
1100                 spin_lock_irqsave(&ioapic_lock, flags);
1101                 reg_01.raw = io_apic_read(apic, 1);
1102                 spin_unlock_irqrestore(&ioapic_lock, flags);
1103                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1104         }
1105         for(apic = 0; apic < nr_ioapics; apic++) {
1106                 int pin;
1107                 /* See if any of the pins is in ExtINT mode */
1108                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1109                         struct IO_APIC_route_entry entry;
1110                         entry = ioapic_read_entry(apic, pin);
1111
1112                         /* If the interrupt line is enabled and in ExtInt mode
1113                          * I have found the pin where the i8259 is connected.
1114                          */
1115                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1116                                 ioapic_i8259.apic = apic;
1117                                 ioapic_i8259.pin  = pin;
1118                                 goto found_i8259;
1119                         }
1120                 }
1121         }
1122  found_i8259:
1123         /* Look to see what if the MP table has reported the ExtINT */
1124         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1125         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1126         /* Trust the MP table if nothing is setup in the hardware */
1127         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1128                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1129                 ioapic_i8259.pin  = i8259_pin;
1130                 ioapic_i8259.apic = i8259_apic;
1131         }
1132         /* Complain if the MP table and the hardware disagree */
1133         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1134                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1135         {
1136                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1137         }
1138
1139         /*
1140          * Do not trust the IO-APIC being empty at bootup
1141          */
1142         clear_IO_APIC();
1143 }
1144
1145 /*
1146  * Not an __init, needed by the reboot code
1147  */
1148 void disable_IO_APIC(void)
1149 {
1150         /*
1151          * Clear the IO-APIC before rebooting:
1152          */
1153         clear_IO_APIC();
1154
1155         /*
1156          * If the i8259 is routed through an IOAPIC
1157          * Put that IOAPIC in virtual wire mode
1158          * so legacy interrupts can be delivered.
1159          */
1160         if (ioapic_i8259.pin != -1) {
1161                 struct IO_APIC_route_entry entry;
1162
1163                 memset(&entry, 0, sizeof(entry));
1164                 entry.mask            = 0; /* Enabled */
1165                 entry.trigger         = 0; /* Edge */
1166                 entry.irr             = 0;
1167                 entry.polarity        = 0; /* High */
1168                 entry.delivery_status = 0;
1169                 entry.dest_mode       = 0; /* Physical */
1170                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1171                 entry.vector          = 0;
1172                 entry.dest.physical.physical_dest =
1173                                         GET_APIC_ID(apic_read(APIC_ID));
1174
1175                 /*
1176                  * Add it to the IO-APIC irq-routing table:
1177                  */
1178                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1179         }
1180
1181         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1182 }
1183
1184 /*
1185  * There is a nasty bug in some older SMP boards, their mptable lies
1186  * about the timer IRQ. We do the following to work around the situation:
1187  *
1188  *      - timer IRQ defaults to IO-APIC IRQ
1189  *      - if this function detects that timer IRQs are defunct, then we fall
1190  *        back to ISA timer IRQs
1191  */
1192 static int __init timer_irq_works(void)
1193 {
1194         unsigned long t1 = jiffies;
1195
1196         local_irq_enable();
1197         /* Let ten ticks pass... */
1198         mdelay((10 * 1000) / HZ);
1199
1200         /*
1201          * Expect a few ticks at least, to be sure some possible
1202          * glue logic does not lock up after one or two first
1203          * ticks in a non-ExtINT mode.  Also the local APIC
1204          * might have cached one ExtINT interrupt.  Finally, at
1205          * least one tick may be lost due to delays.
1206          */
1207
1208         /* jiffies wrap? */
1209         if (jiffies - t1 > 4)
1210                 return 1;
1211         return 0;
1212 }
1213
1214 /*
1215  * In the SMP+IOAPIC case it might happen that there are an unspecified
1216  * number of pending IRQ events unhandled. These cases are very rare,
1217  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1218  * better to do it this way as thus we do not have to be aware of
1219  * 'pending' interrupts in the IRQ path, except at this point.
1220  */
1221 /*
1222  * Edge triggered needs to resend any interrupt
1223  * that was delayed but this is now handled in the device
1224  * independent code.
1225  */
1226
1227 /*
1228  * Starting up a edge-triggered IO-APIC interrupt is
1229  * nasty - we need to make sure that we get the edge.
1230  * If it is already asserted for some reason, we need
1231  * return 1 to indicate that is was pending.
1232  *
1233  * This is not complete - we should be able to fake
1234  * an edge even if it isn't on the 8259A...
1235  */
1236
1237 static unsigned int startup_ioapic_irq(unsigned int irq)
1238 {
1239         int was_pending = 0;
1240         unsigned long flags;
1241
1242         spin_lock_irqsave(&ioapic_lock, flags);
1243         if (irq < 16) {
1244                 disable_8259A_irq(irq);
1245                 if (i8259A_irq_pending(irq))
1246                         was_pending = 1;
1247         }
1248         __unmask_IO_APIC_irq(irq);
1249         spin_unlock_irqrestore(&ioapic_lock, flags);
1250
1251         return was_pending;
1252 }
1253
1254 static int ioapic_retrigger_irq(unsigned int irq)
1255 {
1256         cpumask_t mask;
1257         unsigned vector;
1258
1259         vector = irq_vector[irq];
1260         cpus_clear(mask);
1261         cpu_set(vector >> 8, mask);
1262
1263         send_IPI_mask(mask, vector & 0xff);
1264
1265         return 1;
1266 }
1267
1268 /*
1269  * Level and edge triggered IO-APIC interrupts need different handling,
1270  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1271  * handled with the level-triggered descriptor, but that one has slightly
1272  * more overhead. Level-triggered interrupts cannot be handled with the
1273  * edge-triggered handler, without risking IRQ storms and other ugly
1274  * races.
1275  */
1276
1277 static void ack_apic_edge(unsigned int irq)
1278 {
1279         move_native_irq(irq);
1280         ack_APIC_irq();
1281 }
1282
1283 static void ack_apic_level(unsigned int irq)
1284 {
1285         int do_unmask_irq = 0;
1286
1287 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1288         /* If we are moving the irq we need to mask it */
1289         if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1290                 do_unmask_irq = 1;
1291                 mask_IO_APIC_irq(irq);
1292         }
1293 #endif
1294
1295         /*
1296          * We must acknowledge the irq before we move it or the acknowledge will
1297          * not propogate properly.
1298          */
1299         ack_APIC_irq();
1300
1301         /* Now we can move and renable the irq */
1302         move_masked_irq(irq);
1303         if (unlikely(do_unmask_irq))
1304                 unmask_IO_APIC_irq(irq);
1305 }
1306
1307 static struct irq_chip ioapic_chip __read_mostly = {
1308         .name           = "IO-APIC",
1309         .startup        = startup_ioapic_irq,
1310         .mask           = mask_IO_APIC_irq,
1311         .unmask         = unmask_IO_APIC_irq,
1312         .ack            = ack_apic_edge,
1313         .eoi            = ack_apic_level,
1314 #ifdef CONFIG_SMP
1315         .set_affinity   = set_ioapic_affinity_irq,
1316 #endif
1317         .retrigger      = ioapic_retrigger_irq,
1318 };
1319
1320 static inline void init_IO_APIC_traps(void)
1321 {
1322         int irq;
1323
1324         /*
1325          * NOTE! The local APIC isn't very good at handling
1326          * multiple interrupts at the same interrupt level.
1327          * As the interrupt level is determined by taking the
1328          * vector number and shifting that right by 4, we
1329          * want to spread these out a bit so that they don't
1330          * all fall in the same interrupt level.
1331          *
1332          * Also, we've got to be careful not to trash gate
1333          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1334          */
1335         for (irq = 0; irq < NR_IRQS ; irq++) {
1336                 int tmp = irq;
1337                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1338                         /*
1339                          * Hmm.. We don't have an entry for this,
1340                          * so default to an old-fashioned 8259
1341                          * interrupt if we can..
1342                          */
1343                         if (irq < 16)
1344                                 make_8259A_irq(irq);
1345                         else
1346                                 /* Strange. Oh, well.. */
1347                                 irq_desc[irq].chip = &no_irq_chip;
1348                 }
1349         }
1350 }
1351
1352 static void enable_lapic_irq (unsigned int irq)
1353 {
1354         unsigned long v;
1355
1356         v = apic_read(APIC_LVT0);
1357         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1358 }
1359
1360 static void disable_lapic_irq (unsigned int irq)
1361 {
1362         unsigned long v;
1363
1364         v = apic_read(APIC_LVT0);
1365         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1366 }
1367
1368 static void ack_lapic_irq (unsigned int irq)
1369 {
1370         ack_APIC_irq();
1371 }
1372
1373 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1374
1375 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1376         .typename = "local-APIC-edge",
1377         .startup = NULL, /* startup_irq() not used for IRQ0 */
1378         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1379         .enable = enable_lapic_irq,
1380         .disable = disable_lapic_irq,
1381         .ack = ack_lapic_irq,
1382         .end = end_lapic_irq,
1383 };
1384
1385 static void setup_nmi (void)
1386 {
1387         /*
1388          * Dirty trick to enable the NMI watchdog ...
1389          * We put the 8259A master into AEOI mode and
1390          * unmask on all local APICs LVT0 as NMI.
1391          *
1392          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1393          * is from Maciej W. Rozycki - so we do not have to EOI from
1394          * the NMI handler or the timer interrupt.
1395          */ 
1396         printk(KERN_INFO "activating NMI Watchdog ...");
1397
1398         enable_NMI_through_LVT0(NULL);
1399
1400         printk(" done.\n");
1401 }
1402
1403 /*
1404  * This looks a bit hackish but it's about the only one way of sending
1405  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1406  * not support the ExtINT mode, unfortunately.  We need to send these
1407  * cycles as some i82489DX-based boards have glue logic that keeps the
1408  * 8259A interrupt line asserted until INTA.  --macro
1409  */
1410 static inline void unlock_ExtINT_logic(void)
1411 {
1412         int apic, pin, i;
1413         struct IO_APIC_route_entry entry0, entry1;
1414         unsigned char save_control, save_freq_select;
1415         unsigned long flags;
1416
1417         pin  = find_isa_irq_pin(8, mp_INT);
1418         apic = find_isa_irq_apic(8, mp_INT);
1419         if (pin == -1)
1420                 return;
1421
1422         spin_lock_irqsave(&ioapic_lock, flags);
1423         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1424         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1425         spin_unlock_irqrestore(&ioapic_lock, flags);
1426         clear_IO_APIC_pin(apic, pin);
1427
1428         memset(&entry1, 0, sizeof(entry1));
1429
1430         entry1.dest_mode = 0;                   /* physical delivery */
1431         entry1.mask = 0;                        /* unmask IRQ now */
1432         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1433         entry1.delivery_mode = dest_ExtINT;
1434         entry1.polarity = entry0.polarity;
1435         entry1.trigger = 0;
1436         entry1.vector = 0;
1437
1438         spin_lock_irqsave(&ioapic_lock, flags);
1439         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1440         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1441         spin_unlock_irqrestore(&ioapic_lock, flags);
1442
1443         save_control = CMOS_READ(RTC_CONTROL);
1444         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1445         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1446                    RTC_FREQ_SELECT);
1447         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1448
1449         i = 100;
1450         while (i-- > 0) {
1451                 mdelay(10);
1452                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1453                         i -= 10;
1454         }
1455
1456         CMOS_WRITE(save_control, RTC_CONTROL);
1457         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1458         clear_IO_APIC_pin(apic, pin);
1459
1460         spin_lock_irqsave(&ioapic_lock, flags);
1461         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1462         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1463         spin_unlock_irqrestore(&ioapic_lock, flags);
1464 }
1465
1466 /*
1467  * This code may look a bit paranoid, but it's supposed to cooperate with
1468  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1469  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1470  * fanatically on his truly buggy board.
1471  *
1472  * FIXME: really need to revamp this for modern platforms only.
1473  */
1474 static inline void check_timer(void)
1475 {
1476         int apic1, pin1, apic2, pin2;
1477         int vector;
1478         cpumask_t mask;
1479
1480         /*
1481          * get/set the timer IRQ vector:
1482          */
1483         disable_8259A_irq(0);
1484         vector = assign_irq_vector(0, TARGET_CPUS, &mask);
1485
1486         /*
1487          * Subtle, code in do_timer_interrupt() expects an AEOI
1488          * mode for the 8259A whenever interrupts are routed
1489          * through I/O APICs.  Also IRQ0 has to be enabled in
1490          * the 8259A which implies the virtual wire has to be
1491          * disabled in the local APIC.
1492          */
1493         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1494         init_8259A(1);
1495         if (timer_over_8254 > 0)
1496                 enable_8259A_irq(0);
1497
1498         pin1  = find_isa_irq_pin(0, mp_INT);
1499         apic1 = find_isa_irq_apic(0, mp_INT);
1500         pin2  = ioapic_i8259.pin;
1501         apic2 = ioapic_i8259.apic;
1502
1503         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1504                 vector, apic1, pin1, apic2, pin2);
1505
1506         if (pin1 != -1) {
1507                 /*
1508                  * Ok, does IRQ0 through the IOAPIC work?
1509                  */
1510                 unmask_IO_APIC_irq(0);
1511                 if (!no_timer_check && timer_irq_works()) {
1512                         nmi_watchdog_default();
1513                         if (nmi_watchdog == NMI_IO_APIC) {
1514                                 disable_8259A_irq(0);
1515                                 setup_nmi();
1516                                 enable_8259A_irq(0);
1517                         }
1518                         if (disable_timer_pin_1 > 0)
1519                                 clear_IO_APIC_pin(0, pin1);
1520                         return;
1521                 }
1522                 clear_IO_APIC_pin(apic1, pin1);
1523                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1524                                 "connected to IO-APIC\n");
1525         }
1526
1527         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1528                                 "through the 8259A ... ");
1529         if (pin2 != -1) {
1530                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1531                         apic2, pin2);
1532                 /*
1533                  * legacy devices should be connected to IO APIC #0
1534                  */
1535                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1536                 if (timer_irq_works()) {
1537                         apic_printk(APIC_VERBOSE," works.\n");
1538                         nmi_watchdog_default();
1539                         if (nmi_watchdog == NMI_IO_APIC) {
1540                                 setup_nmi();
1541                         }
1542                         return;
1543                 }
1544                 /*
1545                  * Cleanup, just in case ...
1546                  */
1547                 clear_IO_APIC_pin(apic2, pin2);
1548         }
1549         apic_printk(APIC_VERBOSE," failed.\n");
1550
1551         if (nmi_watchdog == NMI_IO_APIC) {
1552                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1553                 nmi_watchdog = 0;
1554         }
1555
1556         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1557
1558         disable_8259A_irq(0);
1559         irq_desc[0].chip = &lapic_irq_type;
1560         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1561         enable_8259A_irq(0);
1562
1563         if (timer_irq_works()) {
1564                 apic_printk(APIC_VERBOSE," works.\n");
1565                 return;
1566         }
1567         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1568         apic_printk(APIC_VERBOSE," failed.\n");
1569
1570         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1571
1572         init_8259A(0);
1573         make_8259A_irq(0);
1574         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1575
1576         unlock_ExtINT_logic();
1577
1578         if (timer_irq_works()) {
1579                 apic_printk(APIC_VERBOSE," works.\n");
1580                 return;
1581         }
1582         apic_printk(APIC_VERBOSE," failed :(.\n");
1583         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1584 }
1585
1586 static int __init notimercheck(char *s)
1587 {
1588         no_timer_check = 1;
1589         return 1;
1590 }
1591 __setup("no_timer_check", notimercheck);
1592
1593 /*
1594  *
1595  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1596  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1597  *   Linux doesn't really care, as it's not actually used
1598  *   for any interrupt handling anyway.
1599  */
1600 #define PIC_IRQS        (1<<2)
1601
1602 void __init setup_IO_APIC(void)
1603 {
1604         enable_IO_APIC();
1605
1606         if (acpi_ioapic)
1607                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1608         else
1609                 io_apic_irqs = ~PIC_IRQS;
1610
1611         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1612
1613         sync_Arb_IDs();
1614         setup_IO_APIC_irqs();
1615         init_IO_APIC_traps();
1616         check_timer();
1617         if (!acpi_ioapic)
1618                 print_IO_APIC();
1619 }
1620
1621 struct sysfs_ioapic_data {
1622         struct sys_device dev;
1623         struct IO_APIC_route_entry entry[0];
1624 };
1625 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1626
1627 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1628 {
1629         struct IO_APIC_route_entry *entry;
1630         struct sysfs_ioapic_data *data;
1631         int i;
1632
1633         data = container_of(dev, struct sysfs_ioapic_data, dev);
1634         entry = data->entry;
1635         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1636                 *entry = ioapic_read_entry(dev->id, i);
1637
1638         return 0;
1639 }
1640
1641 static int ioapic_resume(struct sys_device *dev)
1642 {
1643         struct IO_APIC_route_entry *entry;
1644         struct sysfs_ioapic_data *data;
1645         unsigned long flags;
1646         union IO_APIC_reg_00 reg_00;
1647         int i;
1648
1649         data = container_of(dev, struct sysfs_ioapic_data, dev);
1650         entry = data->entry;
1651
1652         spin_lock_irqsave(&ioapic_lock, flags);
1653         reg_00.raw = io_apic_read(dev->id, 0);
1654         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1655                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1656                 io_apic_write(dev->id, 0, reg_00.raw);
1657         }
1658         spin_unlock_irqrestore(&ioapic_lock, flags);
1659         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1660                 ioapic_write_entry(dev->id, i, entry[i]);
1661
1662         return 0;
1663 }
1664
1665 static struct sysdev_class ioapic_sysdev_class = {
1666         set_kset_name("ioapic"),
1667         .suspend = ioapic_suspend,
1668         .resume = ioapic_resume,
1669 };
1670
1671 static int __init ioapic_init_sysfs(void)
1672 {
1673         struct sys_device * dev;
1674         int i, size, error = 0;
1675
1676         error = sysdev_class_register(&ioapic_sysdev_class);
1677         if (error)
1678                 return error;
1679
1680         for (i = 0; i < nr_ioapics; i++ ) {
1681                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1682                         * sizeof(struct IO_APIC_route_entry);
1683                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1684                 if (!mp_ioapic_data[i]) {
1685                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1686                         continue;
1687                 }
1688                 memset(mp_ioapic_data[i], 0, size);
1689                 dev = &mp_ioapic_data[i]->dev;
1690                 dev->id = i;
1691                 dev->cls = &ioapic_sysdev_class;
1692                 error = sysdev_register(dev);
1693                 if (error) {
1694                         kfree(mp_ioapic_data[i]);
1695                         mp_ioapic_data[i] = NULL;
1696                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1697                         continue;
1698                 }
1699         }
1700
1701         return 0;
1702 }
1703
1704 device_initcall(ioapic_init_sysfs);
1705
1706 /*
1707  * Dynamic irq allocate and deallocation
1708  */
1709 int create_irq(void)
1710 {
1711         /* Allocate an unused irq */
1712         int irq;
1713         int new;
1714         int vector = 0;
1715         unsigned long flags;
1716         cpumask_t mask;
1717
1718         irq = -ENOSPC;
1719         spin_lock_irqsave(&vector_lock, flags);
1720         for (new = (NR_IRQS - 1); new >= 0; new--) {
1721                 if (platform_legacy_irq(new))
1722                         continue;
1723                 if (irq_vector[new] != 0)
1724                         continue;
1725                 vector = __assign_irq_vector(new, TARGET_CPUS, &mask);
1726                 if (likely(vector > 0))
1727                         irq = new;
1728                 break;
1729         }
1730         spin_unlock_irqrestore(&vector_lock, flags);
1731
1732         if (irq >= 0) {
1733                 dynamic_irq_init(irq);
1734         }
1735         return irq;
1736 }
1737
1738 void destroy_irq(unsigned int irq)
1739 {
1740         unsigned long flags;
1741
1742         dynamic_irq_cleanup(irq);
1743
1744         spin_lock_irqsave(&vector_lock, flags);
1745         irq_vector[irq] = 0;
1746         spin_unlock_irqrestore(&vector_lock, flags);
1747 }
1748
1749 /*
1750  * MSI mesage composition
1751  */
1752 #ifdef CONFIG_PCI_MSI
1753 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1754 {
1755         int vector;
1756         unsigned dest;
1757         cpumask_t tmp;
1758
1759         vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1760         if (vector >= 0) {
1761                 dest = cpu_mask_to_apicid(tmp);
1762
1763                 msg->address_hi = MSI_ADDR_BASE_HI;
1764                 msg->address_lo =
1765                         MSI_ADDR_BASE_LO |
1766                         ((INT_DEST_MODE == 0) ?
1767                                 MSI_ADDR_DEST_MODE_PHYSICAL:
1768                                 MSI_ADDR_DEST_MODE_LOGICAL) |
1769                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1770                                 MSI_ADDR_REDIRECTION_CPU:
1771                                 MSI_ADDR_REDIRECTION_LOWPRI) |
1772                         MSI_ADDR_DEST_ID(dest);
1773
1774                 msg->data =
1775                         MSI_DATA_TRIGGER_EDGE |
1776                         MSI_DATA_LEVEL_ASSERT |
1777                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1778                                 MSI_DATA_DELIVERY_FIXED:
1779                                 MSI_DATA_DELIVERY_LOWPRI) |
1780                         MSI_DATA_VECTOR(vector);
1781         }
1782         return vector;
1783 }
1784
1785 #ifdef CONFIG_SMP
1786 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1787 {
1788         struct msi_msg msg;
1789         unsigned int dest;
1790         cpumask_t tmp;
1791         int vector;
1792
1793         cpus_and(tmp, mask, cpu_online_map);
1794         if (cpus_empty(tmp))
1795                 tmp = TARGET_CPUS;
1796
1797         cpus_and(mask, tmp, CPU_MASK_ALL);
1798
1799         vector = assign_irq_vector(irq, mask, &tmp);
1800         if (vector < 0)
1801                 return;
1802
1803         dest = cpu_mask_to_apicid(tmp);
1804
1805         read_msi_msg(irq, &msg);
1806
1807         msg.data &= ~MSI_DATA_VECTOR_MASK;
1808         msg.data |= MSI_DATA_VECTOR(vector);
1809         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1810         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1811
1812         write_msi_msg(irq, &msg);
1813         set_native_irq_info(irq, mask);
1814 }
1815 #endif /* CONFIG_SMP */
1816
1817 /*
1818  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1819  * which implement the MSI or MSI-X Capability Structure.
1820  */
1821 static struct irq_chip msi_chip = {
1822         .name           = "PCI-MSI",
1823         .unmask         = unmask_msi_irq,
1824         .mask           = mask_msi_irq,
1825         .ack            = ack_apic_edge,
1826 #ifdef CONFIG_SMP
1827         .set_affinity   = set_msi_irq_affinity,
1828 #endif
1829         .retrigger      = ioapic_retrigger_irq,
1830 };
1831
1832 int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
1833 {
1834         struct msi_msg msg;
1835         int ret;
1836         ret = msi_compose_msg(dev, irq, &msg);
1837         if (ret < 0)
1838                 return ret;
1839
1840         write_msi_msg(irq, &msg);
1841
1842         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1843
1844         return 0;
1845 }
1846
1847 void arch_teardown_msi_irq(unsigned int irq)
1848 {
1849         return;
1850 }
1851
1852 #endif /* CONFIG_PCI_MSI */
1853
1854 /*
1855  * Hypertransport interrupt support
1856  */
1857 #ifdef CONFIG_HT_IRQ
1858
1859 #ifdef CONFIG_SMP
1860
1861 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1862 {
1863         u32 low, high;
1864         low  = read_ht_irq_low(irq);
1865         high = read_ht_irq_high(irq);
1866
1867         low  &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1868         high &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1869
1870         low  |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1871         high |= HT_IRQ_HIGH_DEST_ID(dest);
1872
1873         write_ht_irq_low(irq, low);
1874         write_ht_irq_high(irq, high);
1875 }
1876
1877 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1878 {
1879         unsigned int dest;
1880         cpumask_t tmp;
1881         int vector;
1882
1883         cpus_and(tmp, mask, cpu_online_map);
1884         if (cpus_empty(tmp))
1885                 tmp = TARGET_CPUS;
1886
1887         cpus_and(mask, tmp, CPU_MASK_ALL);
1888
1889         vector = assign_irq_vector(irq, mask, &tmp);
1890         if (vector < 0)
1891                 return;
1892
1893         dest = cpu_mask_to_apicid(tmp);
1894
1895         target_ht_irq(irq, dest, vector & 0xff);
1896         set_native_irq_info(irq, mask);
1897 }
1898 #endif
1899
1900 static struct irq_chip ht_irq_chip = {
1901         .name           = "PCI-HT",
1902         .mask           = mask_ht_irq,
1903         .unmask         = unmask_ht_irq,
1904         .ack            = ack_apic_edge,
1905 #ifdef CONFIG_SMP
1906         .set_affinity   = set_ht_irq_affinity,
1907 #endif
1908         .retrigger      = ioapic_retrigger_irq,
1909 };
1910
1911 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
1912 {
1913         int vector;
1914         cpumask_t tmp;
1915
1916         vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1917         if (vector >= 0) {
1918                 u32 low, high;
1919                 unsigned dest;
1920
1921                 dest = cpu_mask_to_apicid(tmp);
1922
1923                 high =  HT_IRQ_HIGH_DEST_ID(dest);
1924
1925                 low =   HT_IRQ_LOW_BASE |
1926                         HT_IRQ_LOW_DEST_ID(dest) |
1927                         HT_IRQ_LOW_VECTOR(vector) |
1928                         ((INT_DEST_MODE == 0) ?
1929                                 HT_IRQ_LOW_DM_PHYSICAL :
1930                                 HT_IRQ_LOW_DM_LOGICAL) |
1931                         HT_IRQ_LOW_RQEOI_EDGE |
1932                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1933                                 HT_IRQ_LOW_MT_FIXED :
1934                                 HT_IRQ_LOW_MT_ARBITRATED);
1935
1936                 write_ht_irq_low(irq, low);
1937                 write_ht_irq_high(irq, high);
1938
1939                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
1940                                               handle_edge_irq, "edge");
1941         }
1942         return vector;
1943 }
1944 #endif /* CONFIG_HT_IRQ */
1945
1946 /* --------------------------------------------------------------------------
1947                           ACPI-based IOAPIC Configuration
1948    -------------------------------------------------------------------------- */
1949
1950 #ifdef CONFIG_ACPI
1951
1952 #define IO_APIC_MAX_ID          0xFE
1953
1954 int __init io_apic_get_redir_entries (int ioapic)
1955 {
1956         union IO_APIC_reg_01    reg_01;
1957         unsigned long flags;
1958
1959         spin_lock_irqsave(&ioapic_lock, flags);
1960         reg_01.raw = io_apic_read(ioapic, 1);
1961         spin_unlock_irqrestore(&ioapic_lock, flags);
1962
1963         return reg_01.bits.entries;
1964 }
1965
1966
1967 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1968 {
1969         struct IO_APIC_route_entry entry;
1970         unsigned long flags;
1971         int vector;
1972         cpumask_t mask;
1973
1974         if (!IO_APIC_IRQ(irq)) {
1975                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1976                         ioapic);
1977                 return -EINVAL;
1978         }
1979
1980         /*
1981          * IRQs < 16 are already in the irq_2_pin[] map
1982          */
1983         if (irq >= 16)
1984                 add_pin_to_irq(irq, ioapic, pin);
1985
1986
1987         vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
1988         if (vector < 0)
1989                 return vector;
1990
1991         /*
1992          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1993          * Note that we mask (disable) IRQs now -- these get enabled when the
1994          * corresponding device driver registers for this IRQ.
1995          */
1996
1997         memset(&entry,0,sizeof(entry));
1998
1999         entry.delivery_mode = INT_DELIVERY_MODE;
2000         entry.dest_mode = INT_DEST_MODE;
2001         entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
2002         entry.trigger = triggering;
2003         entry.polarity = polarity;
2004         entry.mask = 1;                                  /* Disabled (masked) */
2005         entry.vector = vector & 0xff;
2006
2007         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2008                 "IRQ %d Mode:%i Active:%i)\n", ioapic, 
2009                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2010                triggering, polarity);
2011
2012         ioapic_register_intr(irq, entry.vector, triggering);
2013
2014         if (!ioapic && (irq < 16))
2015                 disable_8259A_irq(irq);
2016
2017         ioapic_write_entry(ioapic, pin, entry);
2018
2019         spin_lock_irqsave(&ioapic_lock, flags);
2020         set_native_irq_info(irq, TARGET_CPUS);
2021         spin_unlock_irqrestore(&ioapic_lock, flags);
2022
2023         return 0;
2024 }
2025
2026 #endif /* CONFIG_ACPI */
2027
2028
2029 /*
2030  * This function currently is only a helper for the i386 smp boot process where
2031  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2032  * so mask in all cases should simply be TARGET_CPUS
2033  */
2034 #ifdef CONFIG_SMP
2035 void __init setup_ioapic_dest(void)
2036 {
2037         int pin, ioapic, irq, irq_entry;
2038
2039         if (skip_ioapic_setup == 1)
2040                 return;
2041
2042         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2043                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2044                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2045                         if (irq_entry == -1)
2046                                 continue;
2047                         irq = pin_2_irq(irq_entry, ioapic, pin);
2048                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
2049                 }
2050
2051         }
2052 }
2053 #endif