arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/pci.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/acpi.h>
  32 #include <linux/sysdev.h>
  33 #include <linux/msi.h>
  34 #include <linux/htirq.h>
  35 #ifdef CONFIG_ACPI
  36 #include <acpi/acpi_bus.h>
  37 #endif
  38
  39 #include <asm/idle.h>
  40 #include <asm/io.h>
  41 #include <asm/smp.h>
  42 #include <asm/desc.h>
  43 #include <asm/proto.h>
  44 #include <asm/mach_apic.h>
  45 #include <asm/acpi.h>
  46 #include <asm/dma.h>
  47 #include <asm/nmi.h>
  48 #include <asm/msidef.h>
  49 #include <asm/hypertransport.h>
  50
  51 struct irq_cfg {
  52         cpumask_t domain;
  53         cpumask_t old_domain;
  54         unsigned move_cleanup_count;
  55         u8 vector;
  56         u8 move_in_progress : 1;
  57 };
  58
  59 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
  60 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
  61         [0]  = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR,  },
  62         [1]  = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR,  },
  63         [2]  = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR,  },
  64         [3]  = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR,  },
  65         [4]  = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR,  },
  66         [5]  = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR,  },
  67         [6]  = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR,  },
  68         [7]  = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR,  },
  69         [8]  = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR,  },
  70         [9]  = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR,  },
  71         [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
  72         [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
  73         [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
  74         [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
  75         [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
  76         [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
  77 };
  78
  79 static int assign_irq_vector(int irq, cpumask_t mask);
  80
  81 #define __apicdebuginit  __init
  82
  83 int sis_apic_bug; /* not actually supported, dummy for compile */
  84
  85 static int no_timer_check;
  86
  87 static int disable_timer_pin_1 __initdata;
  88
  89 int timer_over_8254 __initdata = 1;
  90
  91 /* Where if anywhere is the i8259 connect in external int mode */
  92 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  93
  94 static DEFINE_SPINLOCK(ioapic_lock);
  95 DEFINE_SPINLOCK(vector_lock);
  96
  97 /*
  98  * # of IRQ routing registers
  99  */
 100 int nr_ioapic_registers[MAX_IO_APICS];
 101
 102 /*
 103  * Rough estimation of how many shared IRQs there are, can
 104  * be changed anytime.
 105  */
 106 #define MAX_PLUS_SHARED_IRQS NR_IRQS
 107 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
 108
 109 /*
 110  * This is performance-critical, we want to do it O(1)
 111  *
 112  * the indexing order of this array favors 1:1 mappings
 113  * between pins and IRQs.
 114  */
 115
 116 static struct irq_pin_list {
 117         short apic, pin, next;
 118 } irq_2_pin[PIN_MAP_SIZE];
 119
 120 struct io_apic {
 121         unsigned int index;
 122         unsigned int unused[3];
 123         unsigned int data;
 124 };
 125
 126 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 127 {
 128         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 129                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
 130 }
 131
 132 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 133 {
 134         struct io_apic __iomem *io_apic = io_apic_base(apic);
 135         writel(reg, &io_apic->index);
 136         return readl(&io_apic->data);
 137 }
 138
 139 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 140 {
 141         struct io_apic __iomem *io_apic = io_apic_base(apic);
 142         writel(reg, &io_apic->index);
 143         writel(value, &io_apic->data);
 144 }
 145
 146 /*
 147  * Re-write a value: to be used for read-modify-write
 148  * cycles where the read already set up the index register.
 149  */
 150 static inline void io_apic_modify(unsigned int apic, unsigned int value)
 151 {
 152         struct io_apic __iomem *io_apic = io_apic_base(apic);
 153         writel(value, &io_apic->data);
 154 }
 155
 156 /*
 157  * Synchronize the IO-APIC and the CPU by doing
 158  * a dummy read from the IO-APIC
 159  */
 160 static inline void io_apic_sync(unsigned int apic)
 161 {
 162         struct io_apic __iomem *io_apic = io_apic_base(apic);
 163         readl(&io_apic->data);
 164 }
 165
 166 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 167                                                                         \
 168 {                                                                       \
 169         int pin;                                                        \
 170         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 171                                                                         \
 172         BUG_ON(irq >= NR_IRQS);                                         \
 173         for (;;) {                                                      \
 174                 unsigned int reg;                                       \
 175                 pin = entry->pin;                                       \
 176                 if (pin == -1)                                          \
 177                         break;                                          \
 178                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 179                 reg ACTION;                                             \
 180                 io_apic_modify(entry->apic, reg);                       \
 181                 FINAL;                                                  \
 182                 if (!entry->next)                                       \
 183                         break;                                          \
 184                 entry = irq_2_pin + entry->next;                        \
 185         }                                                               \
 186 }
 187
 188 union entry_union {
 189         struct { u32 w1, w2; };
 190         struct IO_APIC_route_entry entry;
 191 };
 192
 193 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 194 {
 195         union entry_union eu;
 196         unsigned long flags;
 197         spin_lock_irqsave(&ioapic_lock, flags);
 198         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 199         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 200         spin_unlock_irqrestore(&ioapic_lock, flags);
 201         return eu.entry;
 202 }
 203
 204 /*
 205  * When we write a new IO APIC routing entry, we need to write the high
 206  * word first! If the mask bit in the low word is clear, we will enable
 207  * the interrupt, and we need to make sure the entry is fully populated
 208  * before that happens.
 209  */
 210 static void
 211 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 212 {
 213         union entry_union eu;
 214         eu.entry = e;
 215         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 216         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 217 }
 218
 219 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 220 {
 221         unsigned long flags;
 222         spin_lock_irqsave(&ioapic_lock, flags);
 223         __ioapic_write_entry(apic, pin, e);
 224         spin_unlock_irqrestore(&ioapic_lock, flags);
 225 }
 226
 227 /*
 228  * When we mask an IO APIC routing entry, we need to write the low
 229  * word first, in order to set the mask bit before we change the
 230  * high bits!
 231  */
 232 static void ioapic_mask_entry(int apic, int pin)
 233 {
 234         unsigned long flags;
 235         union entry_union eu = { .entry.mask = 1 };
 236
 237         spin_lock_irqsave(&ioapic_lock, flags);
 238         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 239         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 240         spin_unlock_irqrestore(&ioapic_lock, flags);
 241 }
 242
 243 #ifdef CONFIG_SMP
 244 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
 245 {
 246         int apic, pin;
 247         struct irq_pin_list *entry = irq_2_pin + irq;
 248
 249         BUG_ON(irq >= NR_IRQS);
 250         for (;;) {
 251                 unsigned int reg;
 252                 apic = entry->apic;
 253                 pin = entry->pin;
 254                 if (pin == -1)
 255                         break;
 256                 io_apic_write(apic, 0x11 + pin*2, dest);
 257                 reg = io_apic_read(apic, 0x10 + pin*2);
 258                 reg &= ~0x000000ff;
 259                 reg |= vector;
 260                 io_apic_modify(apic, reg);
 261                 if (!entry->next)
 262                         break;
 263                 entry = irq_2_pin + entry->next;
 264         }
 265 }
 266
 267 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 268 {
 269         struct irq_cfg *cfg = irq_cfg + irq;
 270         unsigned long flags;
 271         unsigned int dest;
 272         cpumask_t tmp;
 273
 274         cpus_and(tmp, mask, cpu_online_map);
 275         if (cpus_empty(tmp))
 276                 return;
 277
 278         if (assign_irq_vector(irq, mask))
 279                 return;
 280
 281         cpus_and(tmp, cfg->domain, mask);
 282         dest = cpu_mask_to_apicid(tmp);
 283
 284         /*
 285          * Only the high 8 bits are valid.
 286          */
 287         dest = SET_APIC_LOGICAL_ID(dest);
 288
 289         spin_lock_irqsave(&ioapic_lock, flags);
 290         __target_IO_APIC_irq(irq, dest, cfg->vector);
 291         irq_desc[irq].affinity = mask;
 292         spin_unlock_irqrestore(&ioapic_lock, flags);
 293 }
 294 #endif
 295
 296 /*
 297  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 298  * shared ISA-space IRQs, so we have to support them. We are super
 299  * fast in the common case, and fast for shared ISA-space IRQs.
 300  */
 301 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 302 {
 303         static int first_free_entry = NR_IRQS;
 304         struct irq_pin_list *entry = irq_2_pin + irq;
 305
 306         BUG_ON(irq >= NR_IRQS);
 307         while (entry->next)
 308                 entry = irq_2_pin + entry->next;
 309
 310         if (entry->pin != -1) {
 311                 entry->next = first_free_entry;
 312                 entry = irq_2_pin + entry->next;
 313                 if (++first_free_entry >= PIN_MAP_SIZE)
 314                         panic("io_apic.c: ran out of irq_2_pin entries!");
 315         }
 316         entry->apic = apic;
 317         entry->pin = pin;
 318 }
 319
 320
 321 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 322                                                                         \
 323         static void name##_IO_APIC_irq (unsigned int irq)               \
 324         __DO_ACTION(R, ACTION, FINAL)
 325
 326 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 327                                                 /* mask = 1 */
 328 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 329                                                 /* mask = 0 */
 330
 331 static void mask_IO_APIC_irq (unsigned int irq)
 332 {
 333         unsigned long flags;
 334
 335         spin_lock_irqsave(&ioapic_lock, flags);
 336         __mask_IO_APIC_irq(irq);
 337         spin_unlock_irqrestore(&ioapic_lock, flags);
 338 }
 339
 340 static void unmask_IO_APIC_irq (unsigned int irq)
 341 {
 342         unsigned long flags;
 343
 344         spin_lock_irqsave(&ioapic_lock, flags);
 345         __unmask_IO_APIC_irq(irq);
 346         spin_unlock_irqrestore(&ioapic_lock, flags);
 347 }
 348
 349 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 350 {
 351         struct IO_APIC_route_entry entry;
 352
 353         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 354         entry = ioapic_read_entry(apic, pin);
 355         if (entry.delivery_mode == dest_SMI)
 356                 return;
 357         /*
 358          * Disable it in the IO-APIC irq-routing table:
 359          */
 360         ioapic_mask_entry(apic, pin);
 361 }
 362
 363 static void clear_IO_APIC (void)
 364 {
 365         int apic, pin;
 366
 367         for (apic = 0; apic < nr_ioapics; apic++)
 368                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 369                         clear_IO_APIC_pin(apic, pin);
 370 }
 371
 372 int skip_ioapic_setup;
 373 int ioapic_force;
 374
 375 /* dummy parsing: see setup.c */
 376
 377 static int __init disable_ioapic_setup(char *str)
 378 {
 379         skip_ioapic_setup = 1;
 380         return 0;
 381 }
 382 early_param("noapic", disable_ioapic_setup);
 383
 384 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
 385 static int __init disable_timer_pin_setup(char *arg)
 386 {
 387         disable_timer_pin_1 = 1;
 388         return 1;
 389 }
 390 __setup("disable_timer_pin_1", disable_timer_pin_setup);
 391
 392 static int __init setup_disable_8254_timer(char *s)
 393 {
 394         timer_over_8254 = -1;
 395         return 1;
 396 }
 397 static int __init setup_enable_8254_timer(char *s)
 398 {
 399         timer_over_8254 = 2;
 400         return 1;
 401 }
 402
 403 __setup("disable_8254_timer", setup_disable_8254_timer);
 404 __setup("enable_8254_timer", setup_enable_8254_timer);
 405
 406
 407 /*
 408  * Find the IRQ entry number of a certain pin.
 409  */
 410 static int find_irq_entry(int apic, int pin, int type)
 411 {
 412         int i;
 413
 414         for (i = 0; i < mp_irq_entries; i++)
 415                 if (mp_irqs[i].mpc_irqtype == type &&
 416                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 417                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 418                     mp_irqs[i].mpc_dstirq == pin)
 419                         return i;
 420
 421         return -1;
 422 }
 423
 424 /*
 425  * Find the pin to which IRQ[irq] (ISA) is connected
 426  */
 427 static int __init find_isa_irq_pin(int irq, int type)
 428 {
 429         int i;
 430
 431         for (i = 0; i < mp_irq_entries; i++) {
 432                 int lbus = mp_irqs[i].mpc_srcbus;
 433
 434                 if (test_bit(lbus, mp_bus_not_pci) &&
 435                     (mp_irqs[i].mpc_irqtype == type) &&
 436                     (mp_irqs[i].mpc_srcbusirq == irq))
 437
 438                         return mp_irqs[i].mpc_dstirq;
 439         }
 440         return -1;
 441 }
 442
 443 static int __init find_isa_irq_apic(int irq, int type)
 444 {
 445         int i;
 446
 447         for (i = 0; i < mp_irq_entries; i++) {
 448                 int lbus = mp_irqs[i].mpc_srcbus;
 449
 450                 if (test_bit(lbus, mp_bus_not_pci) &&
 451                     (mp_irqs[i].mpc_irqtype == type) &&
 452                     (mp_irqs[i].mpc_srcbusirq == irq))
 453                         break;
 454         }
 455         if (i < mp_irq_entries) {
 456                 int apic;
 457                 for(apic = 0; apic < nr_ioapics; apic++) {
 458                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 459                                 return apic;
 460                 }
 461         }
 462
 463         return -1;
 464 }
 465
 466 /*
 467  * Find a specific PCI IRQ entry.
 468  * Not an __init, possibly needed by modules
 469  */
 470 static int pin_2_irq(int idx, int apic, int pin);
 471
 472 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 473 {
 474         int apic, i, best_guess = -1;
 475
 476         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 477                 bus, slot, pin);
 478         if (mp_bus_id_to_pci_bus[bus] == -1) {
 479                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 480                 return -1;
 481         }
 482         for (i = 0; i < mp_irq_entries; i++) {
 483                 int lbus = mp_irqs[i].mpc_srcbus;
 484
 485                 for (apic = 0; apic < nr_ioapics; apic++)
 486                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 487                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 488                                 break;
 489
 490                 if (!test_bit(lbus, mp_bus_not_pci) &&
 491                     !mp_irqs[i].mpc_irqtype &&
 492                     (bus == lbus) &&
 493                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 494                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 495
 496                         if (!(apic || IO_APIC_IRQ(irq)))
 497                                 continue;
 498
 499                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 500                                 return irq;
 501                         /*
 502                          * Use the first all-but-pin matching entry as a
 503                          * best-guess fuzzy result for broken mptables.
 504                          */
 505                         if (best_guess < 0)
 506                                 best_guess = irq;
 507                 }
 508         }
 509         BUG_ON(best_guess >= NR_IRQS);
 510         return best_guess;
 511 }
 512
 513 /* ISA interrupts are always polarity zero edge triggered,
 514  * when listed as conforming in the MP table. */
 515
 516 #define default_ISA_trigger(idx)        (0)
 517 #define default_ISA_polarity(idx)       (0)
 518
 519 /* PCI interrupts are always polarity one level triggered,
 520  * when listed as conforming in the MP table. */
 521
 522 #define default_PCI_trigger(idx)        (1)
 523 #define default_PCI_polarity(idx)       (1)
 524
 525 static int __init MPBIOS_polarity(int idx)
 526 {
 527         int bus = mp_irqs[idx].mpc_srcbus;
 528         int polarity;
 529
 530         /*
 531          * Determine IRQ line polarity (high active or low active):
 532          */
 533         switch (mp_irqs[idx].mpc_irqflag & 3)
 534         {
 535                 case 0: /* conforms, ie. bus-type dependent polarity */
 536                         if (test_bit(bus, mp_bus_not_pci))
 537                                 polarity = default_ISA_polarity(idx);
 538                         else
 539                                 polarity = default_PCI_polarity(idx);
 540                         break;
 541                 case 1: /* high active */
 542                 {
 543                         polarity = 0;
 544                         break;
 545                 }
 546                 case 2: /* reserved */
 547                 {
 548                         printk(KERN_WARNING "broken BIOS!!\n");
 549                         polarity = 1;
 550                         break;
 551                 }
 552                 case 3: /* low active */
 553                 {
 554                         polarity = 1;
 555                         break;
 556                 }
 557                 default: /* invalid */
 558                 {
 559                         printk(KERN_WARNING "broken BIOS!!\n");
 560                         polarity = 1;
 561                         break;
 562                 }
 563         }
 564         return polarity;
 565 }
 566
 567 static int MPBIOS_trigger(int idx)
 568 {
 569         int bus = mp_irqs[idx].mpc_srcbus;
 570         int trigger;
 571
 572         /*
 573          * Determine IRQ trigger mode (edge or level sensitive):
 574          */
 575         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 576         {
 577                 case 0: /* conforms, ie. bus-type dependent */
 578                         if (test_bit(bus, mp_bus_not_pci))
 579                                 trigger = default_ISA_trigger(idx);
 580                         else
 581                                 trigger = default_PCI_trigger(idx);
 582                         break;
 583                 case 1: /* edge */
 584                 {
 585                         trigger = 0;
 586                         break;
 587                 }
 588                 case 2: /* reserved */
 589                 {
 590                         printk(KERN_WARNING "broken BIOS!!\n");
 591                         trigger = 1;
 592                         break;
 593                 }
 594                 case 3: /* level */
 595                 {
 596                         trigger = 1;
 597                         break;
 598                 }
 599                 default: /* invalid */
 600                 {
 601                         printk(KERN_WARNING "broken BIOS!!\n");
 602                         trigger = 0;
 603                         break;
 604                 }
 605         }
 606         return trigger;
 607 }
 608
 609 static inline int irq_polarity(int idx)
 610 {
 611         return MPBIOS_polarity(idx);
 612 }
 613
 614 static inline int irq_trigger(int idx)
 615 {
 616         return MPBIOS_trigger(idx);
 617 }
 618
 619 static int pin_2_irq(int idx, int apic, int pin)
 620 {
 621         int irq, i;
 622         int bus = mp_irqs[idx].mpc_srcbus;
 623
 624         /*
 625          * Debugging check, we are in big trouble if this message pops up!
 626          */
 627         if (mp_irqs[idx].mpc_dstirq != pin)
 628                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 629
 630         if (test_bit(bus, mp_bus_not_pci)) {
 631                 irq = mp_irqs[idx].mpc_srcbusirq;
 632         } else {
 633                 /*
 634                  * PCI IRQs are mapped in order
 635                  */
 636                 i = irq = 0;
 637                 while (i < apic)
 638                         irq += nr_ioapic_registers[i++];
 639                 irq += pin;
 640         }
 641         BUG_ON(irq >= NR_IRQS);
 642         return irq;
 643 }
 644
 645 static int __assign_irq_vector(int irq, cpumask_t mask)
 646 {
 647         /*
 648          * NOTE! The local APIC isn't very good at handling
 649          * multiple interrupts at the same interrupt level.
 650          * As the interrupt level is determined by taking the
 651          * vector number and shifting that right by 4, we
 652          * want to spread these out a bit so that they don't
 653          * all fall in the same interrupt level.
 654          *
 655          * Also, we've got to be careful not to trash gate
 656          * 0x80, because int 0x80 is hm, kind of importantish. ;)
 657          */
 658         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
 659         unsigned int old_vector;
 660         int cpu;
 661         struct irq_cfg *cfg;
 662
 663         BUG_ON((unsigned)irq >= NR_IRQS);
 664         cfg = &irq_cfg[irq];
 665
 666         /* Only try and allocate irqs on cpus that are present */
 667         cpus_and(mask, mask, cpu_online_map);
 668
 669         if ((cfg->move_in_progress) || cfg->move_cleanup_count)
 670                 return -EBUSY;
 671
 672         old_vector = cfg->vector;
 673         if (old_vector) {
 674                 cpumask_t tmp;
 675                 cpus_and(tmp, cfg->domain, mask);
 676                 if (!cpus_empty(tmp))
 677                         return 0;
 678         }
 679
 680         for_each_cpu_mask(cpu, mask) {
 681                 cpumask_t domain, new_mask;
 682                 int new_cpu;
 683                 int vector, offset;
 684
 685                 domain = vector_allocation_domain(cpu);
 686                 cpus_and(new_mask, domain, cpu_online_map);
 687
 688                 vector = current_vector;
 689                 offset = current_offset;
 690 next:
 691                 vector += 8;
 692                 if (vector >= FIRST_SYSTEM_VECTOR) {
 693                         /* If we run out of vectors on large boxen, must share them. */
 694                         offset = (offset + 1) % 8;
 695                         vector = FIRST_DEVICE_VECTOR + offset;
 696                 }
 697                 if (unlikely(current_vector == vector))
 698                         continue;
 699                 if (vector == IA32_SYSCALL_VECTOR)
 700                         goto next;
 701                 for_each_cpu_mask(new_cpu, new_mask)
 702                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
 703                                 goto next;
 704                 /* Found one! */
 705                 current_vector = vector;
 706                 current_offset = offset;
 707                 if (old_vector) {
 708                         cfg->move_in_progress = 1;
 709                         cfg->old_domain = cfg->domain;
 710                 }
 711                 for_each_cpu_mask(new_cpu, new_mask)
 712                         per_cpu(vector_irq, new_cpu)[vector] = irq;
 713                 cfg->vector = vector;
 714                 cfg->domain = domain;
 715                 return 0;
 716         }
 717         return -ENOSPC;
 718 }
 719
 720 static int assign_irq_vector(int irq, cpumask_t mask)
 721 {
 722         int err;
 723         unsigned long flags;
 724
 725         spin_lock_irqsave(&vector_lock, flags);
 726         err = __assign_irq_vector(irq, mask);
 727         spin_unlock_irqrestore(&vector_lock, flags);
 728         return err;
 729 }
 730
 731 static void __clear_irq_vector(int irq)
 732 {
 733         struct irq_cfg *cfg;
 734         cpumask_t mask;
 735         int cpu, vector;
 736
 737         BUG_ON((unsigned)irq >= NR_IRQS);
 738         cfg = &irq_cfg[irq];
 739         BUG_ON(!cfg->vector);
 740
 741         vector = cfg->vector;
 742         cpus_and(mask, cfg->domain, cpu_online_map);
 743         for_each_cpu_mask(cpu, mask)
 744                 per_cpu(vector_irq, cpu)[vector] = -1;
 745
 746         cfg->vector = 0;
 747         cfg->domain = CPU_MASK_NONE;
 748 }
 749
 750 void __setup_vector_irq(int cpu)
 751 {
 752         /* Initialize vector_irq on a new cpu */
 753         /* This function must be called with vector_lock held */
 754         int irq, vector;
 755
 756         /* Mark the inuse vectors */
 757         for (irq = 0; irq < NR_IRQS; ++irq) {
 758                 if (!cpu_isset(cpu, irq_cfg[irq].domain))
 759                         continue;
 760                 vector = irq_cfg[irq].vector;
 761                 per_cpu(vector_irq, cpu)[vector] = irq;
 762         }
 763         /* Mark the free vectors */
 764         for (vector = 0; vector < NR_VECTORS; ++vector) {
 765                 irq = per_cpu(vector_irq, cpu)[vector];
 766                 if (irq < 0)
 767                         continue;
 768                 if (!cpu_isset(cpu, irq_cfg[irq].domain))
 769                         per_cpu(vector_irq, cpu)[vector] = -1;
 770         }
 771 }
 772
 773
 774 static struct irq_chip ioapic_chip;
 775
 776 static void ioapic_register_intr(int irq, unsigned long trigger)
 777 {
 778         if (trigger)
 779                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 780                                               handle_fasteoi_irq, "fasteoi");
 781         else
 782                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 783                                               handle_edge_irq, "edge");
 784 }
 785
 786 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
 787                               int trigger, int polarity)
 788 {
 789         struct irq_cfg *cfg = irq_cfg + irq;
 790         struct IO_APIC_route_entry entry;
 791         cpumask_t mask;
 792
 793         if (!IO_APIC_IRQ(irq))
 794                 return;
 795
 796         mask = TARGET_CPUS;
 797         if (assign_irq_vector(irq, mask))
 798                 return;
 799
 800         cpus_and(mask, cfg->domain, mask);
 801
 802         apic_printk(APIC_VERBOSE,KERN_DEBUG
 803                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
 804                     "IRQ %d Mode:%i Active:%i)\n",
 805                     apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
 806                     irq, trigger, polarity);
 807
 808         /*
 809          * add it to the IO-APIC irq-routing table:
 810          */
 811         memset(&entry,0,sizeof(entry));
 812
 813         entry.delivery_mode = INT_DELIVERY_MODE;
 814         entry.dest_mode = INT_DEST_MODE;
 815         entry.dest = cpu_mask_to_apicid(mask);
 816         entry.mask = 0;                         /* enable IRQ */
 817         entry.trigger = trigger;
 818         entry.polarity = polarity;
 819         entry.vector = cfg->vector;
 820
 821         /* Mask level triggered irqs.
 822          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
 823          */
 824         if (trigger)
 825                 entry.mask = 1;
 826
 827         ioapic_register_intr(irq, trigger);
 828         if (irq < 16)
 829                 disable_8259A_irq(irq);
 830
 831         ioapic_write_entry(apic, pin, entry);
 832 }
 833
 834 static void __init setup_IO_APIC_irqs(void)
 835 {
 836         int apic, pin, idx, irq, first_notcon = 1;
 837
 838         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 839
 840         for (apic = 0; apic < nr_ioapics; apic++) {
 841         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 842
 843                 idx = find_irq_entry(apic,pin,mp_INT);
 844                 if (idx == -1) {
 845                         if (first_notcon) {
 846                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 847                                 first_notcon = 0;
 848                         } else
 849                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 850                         continue;
 851                 }
 852
 853                 irq = pin_2_irq(idx, apic, pin);
 854                 add_pin_to_irq(irq, apic, pin);
 855
 856                 setup_IO_APIC_irq(apic, pin, irq,
 857                                   irq_trigger(idx), irq_polarity(idx));
 858         }
 859         }
 860
 861         if (!first_notcon)
 862                 apic_printk(APIC_VERBOSE," not connected.\n");
 863 }
 864
 865 /*
 866  * Set up the 8259A-master output pin as broadcast to all
 867  * CPUs.
 868  */
 869 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 870 {
 871         struct IO_APIC_route_entry entry;
 872         unsigned long flags;
 873
 874         memset(&entry,0,sizeof(entry));
 875
 876         disable_8259A_irq(0);
 877
 878         /* mask LVT0 */
 879         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 880
 881         /*
 882          * We use logical delivery to get the timer IRQ
 883          * to the first CPU.
 884          */
 885         entry.dest_mode = INT_DEST_MODE;
 886         entry.mask = 0;                                 /* unmask IRQ now */
 887         entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
 888         entry.delivery_mode = INT_DELIVERY_MODE;
 889         entry.polarity = 0;
 890         entry.trigger = 0;
 891         entry.vector = vector;
 892
 893         /*
 894          * The timer IRQ doesn't have to know that behind the
 895          * scene we have a 8259A-master in AEOI mode ...
 896          */
 897         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
 898
 899         /*
 900          * Add it to the IO-APIC irq-routing table:
 901          */
 902         spin_lock_irqsave(&ioapic_lock, flags);
 903         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 904         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 905         spin_unlock_irqrestore(&ioapic_lock, flags);
 906
 907         enable_8259A_irq(0);
 908 }
 909
 910 void __apicdebuginit print_IO_APIC(void)
 911 {
 912         int apic, i;
 913         union IO_APIC_reg_00 reg_00;
 914         union IO_APIC_reg_01 reg_01;
 915         union IO_APIC_reg_02 reg_02;
 916         unsigned long flags;
 917
 918         if (apic_verbosity == APIC_QUIET)
 919                 return;
 920
 921         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 922         for (i = 0; i < nr_ioapics; i++)
 923                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 924                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 925
 926         /*
 927          * We are a bit conservative about what we expect.  We have to
 928          * know about every hardware change ASAP.
 929          */
 930         printk(KERN_INFO "testing the IO APIC.......................\n");
 931
 932         for (apic = 0; apic < nr_ioapics; apic++) {
 933
 934         spin_lock_irqsave(&ioapic_lock, flags);
 935         reg_00.raw = io_apic_read(apic, 0);
 936         reg_01.raw = io_apic_read(apic, 1);
 937         if (reg_01.bits.version >= 0x10)
 938                 reg_02.raw = io_apic_read(apic, 2);
 939         spin_unlock_irqrestore(&ioapic_lock, flags);
 940
 941         printk("\n");
 942         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 943         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 944         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 945
 946         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 947         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 948
 949         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 950         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 951
 952         if (reg_01.bits.version >= 0x10) {
 953                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 954                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 955         }
 956
 957         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 958
 959         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
 960                           " Stat Dmod Deli Vect:   \n");
 961
 962         for (i = 0; i <= reg_01.bits.entries; i++) {
 963                 struct IO_APIC_route_entry entry;
 964
 965                 entry = ioapic_read_entry(apic, i);
 966
 967                 printk(KERN_DEBUG " %02x %03X ",
 968                         i,
 969                         entry.dest
 970                 );
 971
 972                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
 973                         entry.mask,
 974                         entry.trigger,
 975                         entry.irr,
 976                         entry.polarity,
 977                         entry.delivery_status,
 978                         entry.dest_mode,
 979                         entry.delivery_mode,
 980                         entry.vector
 981                 );
 982         }
 983         }
 984         printk(KERN_DEBUG "IRQ to pin mappings:\n");
 985         for (i = 0; i < NR_IRQS; i++) {
 986                 struct irq_pin_list *entry = irq_2_pin + i;
 987                 if (entry->pin < 0)
 988                         continue;
 989                 printk(KERN_DEBUG "IRQ%d ", i);
 990                 for (;;) {
 991                         printk("-> %d:%d", entry->apic, entry->pin);
 992                         if (!entry->next)
 993                                 break;
 994                         entry = irq_2_pin + entry->next;
 995                 }
 996                 printk("\n");
 997         }
 998
 999         printk(KERN_INFO ".................................... done.\n");
1000
1001         return;
1002 }
1003
1004 #if 0
1005
1006 static __apicdebuginit void print_APIC_bitfield (int base)
1007 {
1008         unsigned int v;
1009         int i, j;
1010
1011         if (apic_verbosity == APIC_QUIET)
1012                 return;
1013
1014         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1015         for (i = 0; i < 8; i++) {
1016                 v = apic_read(base + i*0x10);
1017                 for (j = 0; j < 32; j++) {
1018                         if (v & (1<<j))
1019                                 printk("1");
1020                         else
1021                                 printk("0");
1022                 }
1023                 printk("\n");
1024         }
1025 }
1026
1027 void __apicdebuginit print_local_APIC(void * dummy)
1028 {
1029         unsigned int v, ver, maxlvt;
1030
1031         if (apic_verbosity == APIC_QUIET)
1032                 return;
1033
1034         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1035                 smp_processor_id(), hard_smp_processor_id());
1036         v = apic_read(APIC_ID);
1037         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1038         v = apic_read(APIC_LVR);
1039         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1040         ver = GET_APIC_VERSION(v);
1041         maxlvt = get_maxlvt();
1042
1043         v = apic_read(APIC_TASKPRI);
1044         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1045
1046         v = apic_read(APIC_ARBPRI);
1047         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1048                 v & APIC_ARBPRI_MASK);
1049         v = apic_read(APIC_PROCPRI);
1050         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1051
1052         v = apic_read(APIC_EOI);
1053         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1054         v = apic_read(APIC_RRR);
1055         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1056         v = apic_read(APIC_LDR);
1057         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1058         v = apic_read(APIC_DFR);
1059         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1060         v = apic_read(APIC_SPIV);
1061         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1062
1063         printk(KERN_DEBUG "... APIC ISR field:\n");
1064         print_APIC_bitfield(APIC_ISR);
1065         printk(KERN_DEBUG "... APIC TMR field:\n");
1066         print_APIC_bitfield(APIC_TMR);
1067         printk(KERN_DEBUG "... APIC IRR field:\n");
1068         print_APIC_bitfield(APIC_IRR);
1069
1070         v = apic_read(APIC_ESR);
1071         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1072
1073         v = apic_read(APIC_ICR);
1074         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1075         v = apic_read(APIC_ICR2);
1076         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1077
1078         v = apic_read(APIC_LVTT);
1079         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1080
1081         if (maxlvt > 3) {                       /* PC is LVT#4. */
1082                 v = apic_read(APIC_LVTPC);
1083                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1084         }
1085         v = apic_read(APIC_LVT0);
1086         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1087         v = apic_read(APIC_LVT1);
1088         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1089
1090         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1091                 v = apic_read(APIC_LVTERR);
1092                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1093         }
1094
1095         v = apic_read(APIC_TMICT);
1096         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1097         v = apic_read(APIC_TMCCT);
1098         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1099         v = apic_read(APIC_TDCR);
1100         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1101         printk("\n");
1102 }
1103
1104 void print_all_local_APICs (void)
1105 {
1106         on_each_cpu(print_local_APIC, NULL, 1, 1);
1107 }
1108
1109 void __apicdebuginit print_PIC(void)
1110 {
1111         unsigned int v;
1112         unsigned long flags;
1113
1114         if (apic_verbosity == APIC_QUIET)
1115                 return;
1116
1117         printk(KERN_DEBUG "\nprinting PIC contents\n");
1118
1119         spin_lock_irqsave(&i8259A_lock, flags);
1120
1121         v = inb(0xa1) << 8 | inb(0x21);
1122         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1123
1124         v = inb(0xa0) << 8 | inb(0x20);
1125         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1126
1127         outb(0x0b,0xa0);
1128         outb(0x0b,0x20);
1129         v = inb(0xa0) << 8 | inb(0x20);
1130         outb(0x0a,0xa0);
1131         outb(0x0a,0x20);
1132
1133         spin_unlock_irqrestore(&i8259A_lock, flags);
1134
1135         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1136
1137         v = inb(0x4d1) << 8 | inb(0x4d0);
1138         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1139 }
1140
1141 #endif  /*  0  */
1142
1143 static void __init enable_IO_APIC(void)
1144 {
1145         union IO_APIC_reg_01 reg_01;
1146         int i8259_apic, i8259_pin;
1147         int i, apic;
1148         unsigned long flags;
1149
1150         for (i = 0; i < PIN_MAP_SIZE; i++) {
1151                 irq_2_pin[i].pin = -1;
1152                 irq_2_pin[i].next = 0;
1153         }
1154
1155         /*
1156          * The number of IO-APIC IRQ registers (== #pins):
1157          */
1158         for (apic = 0; apic < nr_ioapics; apic++) {
1159                 spin_lock_irqsave(&ioapic_lock, flags);
1160                 reg_01.raw = io_apic_read(apic, 1);
1161                 spin_unlock_irqrestore(&ioapic_lock, flags);
1162                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1163         }
1164         for(apic = 0; apic < nr_ioapics; apic++) {
1165                 int pin;
1166                 /* See if any of the pins is in ExtINT mode */
1167                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1168                         struct IO_APIC_route_entry entry;
1169                         entry = ioapic_read_entry(apic, pin);
1170
1171                         /* If the interrupt line is enabled and in ExtInt mode
1172                          * I have found the pin where the i8259 is connected.
1173                          */
1174                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1175                                 ioapic_i8259.apic = apic;
1176                                 ioapic_i8259.pin  = pin;
1177                                 goto found_i8259;
1178                         }
1179                 }
1180         }
1181  found_i8259:
1182         /* Look to see what if the MP table has reported the ExtINT */
1183         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1184         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1185         /* Trust the MP table if nothing is setup in the hardware */
1186         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1187                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1188                 ioapic_i8259.pin  = i8259_pin;
1189                 ioapic_i8259.apic = i8259_apic;
1190         }
1191         /* Complain if the MP table and the hardware disagree */
1192         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1193                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1194         {
1195                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1196         }
1197
1198         /*
1199          * Do not trust the IO-APIC being empty at bootup
1200          */
1201         clear_IO_APIC();
1202 }
1203
1204 /*
1205  * Not an __init, needed by the reboot code
1206  */
1207 void disable_IO_APIC(void)
1208 {
1209         /*
1210          * Clear the IO-APIC before rebooting:
1211          */
1212         clear_IO_APIC();
1213
1214         /*
1215          * If the i8259 is routed through an IOAPIC
1216          * Put that IOAPIC in virtual wire mode
1217          * so legacy interrupts can be delivered.
1218          */
1219         if (ioapic_i8259.pin != -1) {
1220                 struct IO_APIC_route_entry entry;
1221
1222                 memset(&entry, 0, sizeof(entry));
1223                 entry.mask            = 0; /* Enabled */
1224                 entry.trigger         = 0; /* Edge */
1225                 entry.irr             = 0;
1226                 entry.polarity        = 0; /* High */
1227                 entry.delivery_status = 0;
1228                 entry.dest_mode       = 0; /* Physical */
1229                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1230                 entry.vector          = 0;
1231                 entry.dest          = GET_APIC_ID(apic_read(APIC_ID));
1232
1233                 /*
1234                  * Add it to the IO-APIC irq-routing table:
1235                  */
1236                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1237         }
1238
1239         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1240 }
1241
1242 /*
1243  * There is a nasty bug in some older SMP boards, their mptable lies
1244  * about the timer IRQ. We do the following to work around the situation:
1245  *
1246  *      - timer IRQ defaults to IO-APIC IRQ
1247  *      - if this function detects that timer IRQs are defunct, then we fall
1248  *        back to ISA timer IRQs
1249  */
1250 static int __init timer_irq_works(void)
1251 {
1252         unsigned long t1 = jiffies;
1253
1254         local_irq_enable();
1255         /* Let ten ticks pass... */
1256         mdelay((10 * 1000) / HZ);
1257
1258         /*
1259          * Expect a few ticks at least, to be sure some possible
1260          * glue logic does not lock up after one or two first
1261          * ticks in a non-ExtINT mode.  Also the local APIC
1262          * might have cached one ExtINT interrupt.  Finally, at
1263          * least one tick may be lost due to delays.
1264          */
1265
1266         /* jiffies wrap? */
1267         if (jiffies - t1 > 4)
1268                 return 1;
1269         return 0;
1270 }
1271
1272 /*
1273  * In the SMP+IOAPIC case it might happen that there are an unspecified
1274  * number of pending IRQ events unhandled. These cases are very rare,
1275  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1276  * better to do it this way as thus we do not have to be aware of
1277  * 'pending' interrupts in the IRQ path, except at this point.
1278  */
1279 /*
1280  * Edge triggered needs to resend any interrupt
1281  * that was delayed but this is now handled in the device
1282  * independent code.
1283  */
1284
1285 /*
1286  * Starting up a edge-triggered IO-APIC interrupt is
1287  * nasty - we need to make sure that we get the edge.
1288  * If it is already asserted for some reason, we need
1289  * return 1 to indicate that is was pending.
1290  *
1291  * This is not complete - we should be able to fake
1292  * an edge even if it isn't on the 8259A...
1293  */
1294
1295 static unsigned int startup_ioapic_irq(unsigned int irq)
1296 {
1297         int was_pending = 0;
1298         unsigned long flags;
1299
1300         spin_lock_irqsave(&ioapic_lock, flags);
1301         if (irq < 16) {
1302                 disable_8259A_irq(irq);
1303                 if (i8259A_irq_pending(irq))
1304                         was_pending = 1;
1305         }
1306         __unmask_IO_APIC_irq(irq);
1307         spin_unlock_irqrestore(&ioapic_lock, flags);
1308
1309         return was_pending;
1310 }
1311
1312 static int ioapic_retrigger_irq(unsigned int irq)
1313 {
1314         struct irq_cfg *cfg = &irq_cfg[irq];
1315         cpumask_t mask;
1316         unsigned long flags;
1317
1318         spin_lock_irqsave(&vector_lock, flags);
1319         cpus_clear(mask);
1320         cpu_set(first_cpu(cfg->domain), mask);
1321
1322         send_IPI_mask(mask, cfg->vector);
1323         spin_unlock_irqrestore(&vector_lock, flags);
1324
1325         return 1;
1326 }
1327
1328 /*
1329  * Level and edge triggered IO-APIC interrupts need different handling,
1330  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1331  * handled with the level-triggered descriptor, but that one has slightly
1332  * more overhead. Level-triggered interrupts cannot be handled with the
1333  * edge-triggered handler, without risking IRQ storms and other ugly
1334  * races.
1335  */
1336
1337 #ifdef CONFIG_SMP
1338 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1339 {
1340         unsigned vector, me;
1341         ack_APIC_irq();
1342         exit_idle();
1343         irq_enter();
1344
1345         me = smp_processor_id();
1346         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1347                 unsigned int irq;
1348                 struct irq_desc *desc;
1349                 struct irq_cfg *cfg;
1350                 irq = __get_cpu_var(vector_irq)[vector];
1351                 if (irq >= NR_IRQS)
1352                         continue;
1353
1354                 desc = irq_desc + irq;
1355                 cfg = irq_cfg + irq;
1356                 spin_lock(&desc->lock);
1357                 if (!cfg->move_cleanup_count)
1358                         goto unlock;
1359
1360                 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1361                         goto unlock;
1362
1363                 __get_cpu_var(vector_irq)[vector] = -1;
1364                 cfg->move_cleanup_count--;
1365 unlock:
1366                 spin_unlock(&desc->lock);
1367         }
1368
1369         irq_exit();
1370 }
1371
1372 static void irq_complete_move(unsigned int irq)
1373 {
1374         struct irq_cfg *cfg = irq_cfg + irq;
1375         unsigned vector, me;
1376
1377         if (likely(!cfg->move_in_progress))
1378                 return;
1379
1380         vector = ~get_irq_regs()->orig_rax;
1381         me = smp_processor_id();
1382         if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1383                 cpumask_t cleanup_mask;
1384
1385                 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1386                 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1387                 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1388                 cfg->move_in_progress = 0;
1389         }
1390 }
1391 #else
1392 static inline void irq_complete_move(unsigned int irq) {}
1393 #endif
1394
1395 static void ack_apic_edge(unsigned int irq)
1396 {
1397         irq_complete_move(irq);
1398         move_native_irq(irq);
1399         ack_APIC_irq();
1400 }
1401
1402 static void ack_apic_level(unsigned int irq)
1403 {
1404         int do_unmask_irq = 0;
1405
1406         irq_complete_move(irq);
1407 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1408         /* If we are moving the irq we need to mask it */
1409         if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1410                 do_unmask_irq = 1;
1411                 mask_IO_APIC_irq(irq);
1412         }
1413 #endif
1414
1415         /*
1416          * We must acknowledge the irq before we move it or the acknowledge will
1417          * not propogate properly.
1418          */
1419         ack_APIC_irq();
1420
1421         /* Now we can move and renable the irq */
1422         move_masked_irq(irq);
1423         if (unlikely(do_unmask_irq))
1424                 unmask_IO_APIC_irq(irq);
1425 }
1426
1427 static struct irq_chip ioapic_chip __read_mostly = {
1428         .name           = "IO-APIC",
1429         .startup        = startup_ioapic_irq,
1430         .mask           = mask_IO_APIC_irq,
1431         .unmask         = unmask_IO_APIC_irq,
1432         .ack            = ack_apic_edge,
1433         .eoi            = ack_apic_level,
1434 #ifdef CONFIG_SMP
1435         .set_affinity   = set_ioapic_affinity_irq,
1436 #endif
1437         .retrigger      = ioapic_retrigger_irq,
1438 };
1439
1440 static inline void init_IO_APIC_traps(void)
1441 {
1442         int irq;
1443
1444         /*
1445          * NOTE! The local APIC isn't very good at handling
1446          * multiple interrupts at the same interrupt level.
1447          * As the interrupt level is determined by taking the
1448          * vector number and shifting that right by 4, we
1449          * want to spread these out a bit so that they don't
1450          * all fall in the same interrupt level.
1451          *
1452          * Also, we've got to be careful not to trash gate
1453          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1454          */
1455         for (irq = 0; irq < NR_IRQS ; irq++) {
1456                 int tmp = irq;
1457                 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1458                         /*
1459                          * Hmm.. We don't have an entry for this,
1460                          * so default to an old-fashioned 8259
1461                          * interrupt if we can..
1462                          */
1463                         if (irq < 16)
1464                                 make_8259A_irq(irq);
1465                         else
1466                                 /* Strange. Oh, well.. */
1467                                 irq_desc[irq].chip = &no_irq_chip;
1468                 }
1469         }
1470 }
1471
1472 static void enable_lapic_irq (unsigned int irq)
1473 {
1474         unsigned long v;
1475
1476         v = apic_read(APIC_LVT0);
1477         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1478 }
1479
1480 static void disable_lapic_irq (unsigned int irq)
1481 {
1482         unsigned long v;
1483
1484         v = apic_read(APIC_LVT0);
1485         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1486 }
1487
1488 static void ack_lapic_irq (unsigned int irq)
1489 {
1490         ack_APIC_irq();
1491 }
1492
1493 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1494
1495 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1496         .typename = "local-APIC-edge",
1497         .startup = NULL, /* startup_irq() not used for IRQ0 */
1498         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1499         .enable = enable_lapic_irq,
1500         .disable = disable_lapic_irq,
1501         .ack = ack_lapic_irq,
1502         .end = end_lapic_irq,
1503 };
1504
1505 static void setup_nmi (void)
1506 {
1507         /*
1508          * Dirty trick to enable the NMI watchdog ...
1509          * We put the 8259A master into AEOI mode and
1510          * unmask on all local APICs LVT0 as NMI.
1511          *
1512          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1513          * is from Maciej W. Rozycki - so we do not have to EOI from
1514          * the NMI handler or the timer interrupt.
1515          */
1516         printk(KERN_INFO "activating NMI Watchdog ...");
1517
1518         enable_NMI_through_LVT0(NULL);
1519
1520         printk(" done.\n");
1521 }
1522
1523 /*
1524  * This looks a bit hackish but it's about the only one way of sending
1525  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1526  * not support the ExtINT mode, unfortunately.  We need to send these
1527  * cycles as some i82489DX-based boards have glue logic that keeps the
1528  * 8259A interrupt line asserted until INTA.  --macro
1529  */
1530 static inline void unlock_ExtINT_logic(void)
1531 {
1532         int apic, pin, i;
1533         struct IO_APIC_route_entry entry0, entry1;
1534         unsigned char save_control, save_freq_select;
1535         unsigned long flags;
1536
1537         pin  = find_isa_irq_pin(8, mp_INT);
1538         apic = find_isa_irq_apic(8, mp_INT);
1539         if (pin == -1)
1540                 return;
1541
1542         spin_lock_irqsave(&ioapic_lock, flags);
1543         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1544         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1545         spin_unlock_irqrestore(&ioapic_lock, flags);
1546         clear_IO_APIC_pin(apic, pin);
1547
1548         memset(&entry1, 0, sizeof(entry1));
1549
1550         entry1.dest_mode = 0;                   /* physical delivery */
1551         entry1.mask = 0;                        /* unmask IRQ now */
1552         entry1.dest = hard_smp_processor_id();
1553         entry1.delivery_mode = dest_ExtINT;
1554         entry1.polarity = entry0.polarity;
1555         entry1.trigger = 0;
1556         entry1.vector = 0;
1557
1558         spin_lock_irqsave(&ioapic_lock, flags);
1559         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1560         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1561         spin_unlock_irqrestore(&ioapic_lock, flags);
1562
1563         save_control = CMOS_READ(RTC_CONTROL);
1564         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1565         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1566                    RTC_FREQ_SELECT);
1567         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1568
1569         i = 100;
1570         while (i-- > 0) {
1571                 mdelay(10);
1572                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1573                         i -= 10;
1574         }
1575
1576         CMOS_WRITE(save_control, RTC_CONTROL);
1577         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1578         clear_IO_APIC_pin(apic, pin);
1579
1580         spin_lock_irqsave(&ioapic_lock, flags);
1581         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1582         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1583         spin_unlock_irqrestore(&ioapic_lock, flags);
1584 }
1585
1586 /*
1587  * This code may look a bit paranoid, but it's supposed to cooperate with
1588  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1589  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1590  * fanatically on his truly buggy board.
1591  *
1592  * FIXME: really need to revamp this for modern platforms only.
1593  */
1594 static inline void check_timer(void)
1595 {
1596         struct irq_cfg *cfg = irq_cfg + 0;
1597         int apic1, pin1, apic2, pin2;
1598
1599         /*
1600          * get/set the timer IRQ vector:
1601          */
1602         disable_8259A_irq(0);
1603         assign_irq_vector(0, TARGET_CPUS);
1604
1605         /*
1606          * Subtle, code in do_timer_interrupt() expects an AEOI
1607          * mode for the 8259A whenever interrupts are routed
1608          * through I/O APICs.  Also IRQ0 has to be enabled in
1609          * the 8259A which implies the virtual wire has to be
1610          * disabled in the local APIC.
1611          */
1612         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1613         init_8259A(1);
1614         if (timer_over_8254 > 0)
1615                 enable_8259A_irq(0);
1616
1617         pin1  = find_isa_irq_pin(0, mp_INT);
1618         apic1 = find_isa_irq_apic(0, mp_INT);
1619         pin2  = ioapic_i8259.pin;
1620         apic2 = ioapic_i8259.apic;
1621
1622         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1623                 cfg->vector, apic1, pin1, apic2, pin2);
1624
1625         if (pin1 != -1) {
1626                 /*
1627                  * Ok, does IRQ0 through the IOAPIC work?
1628                  */
1629                 unmask_IO_APIC_irq(0);
1630                 if (!no_timer_check && timer_irq_works()) {
1631                         nmi_watchdog_default();
1632                         if (nmi_watchdog == NMI_IO_APIC) {
1633                                 disable_8259A_irq(0);
1634                                 setup_nmi();
1635                                 enable_8259A_irq(0);
1636                         }
1637                         if (disable_timer_pin_1 > 0)
1638                                 clear_IO_APIC_pin(0, pin1);
1639                         return;
1640                 }
1641                 clear_IO_APIC_pin(apic1, pin1);
1642                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1643                                 "connected to IO-APIC\n");
1644         }
1645
1646         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1647                                 "through the 8259A ... ");
1648         if (pin2 != -1) {
1649                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1650                         apic2, pin2);
1651                 /*
1652                  * legacy devices should be connected to IO APIC #0
1653                  */
1654                 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
1655                 if (timer_irq_works()) {
1656                         apic_printk(APIC_VERBOSE," works.\n");
1657                         nmi_watchdog_default();
1658                         if (nmi_watchdog == NMI_IO_APIC) {
1659                                 setup_nmi();
1660                         }
1661                         return;
1662                 }
1663                 /*
1664                  * Cleanup, just in case ...
1665                  */
1666                 clear_IO_APIC_pin(apic2, pin2);
1667         }
1668         apic_printk(APIC_VERBOSE," failed.\n");
1669
1670         if (nmi_watchdog == NMI_IO_APIC) {
1671                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1672                 nmi_watchdog = 0;
1673         }
1674
1675         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1676
1677         disable_8259A_irq(0);
1678         irq_desc[0].chip = &lapic_irq_type;
1679         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
1680         enable_8259A_irq(0);
1681
1682         if (timer_irq_works()) {
1683                 apic_printk(APIC_VERBOSE," works.\n");
1684                 return;
1685         }
1686         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1687         apic_printk(APIC_VERBOSE," failed.\n");
1688
1689         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1690
1691         init_8259A(0);
1692         make_8259A_irq(0);
1693         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1694
1695         unlock_ExtINT_logic();
1696
1697         if (timer_irq_works()) {
1698                 apic_printk(APIC_VERBOSE," works.\n");
1699                 return;
1700         }
1701         apic_printk(APIC_VERBOSE," failed :(.\n");
1702         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1703 }
1704
1705 static int __init notimercheck(char *s)
1706 {
1707         no_timer_check = 1;
1708         return 1;
1709 }
1710 __setup("no_timer_check", notimercheck);
1711
1712 /*
1713  *
1714  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1715  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1716  *   Linux doesn't really care, as it's not actually used
1717  *   for any interrupt handling anyway.
1718  */
1719 #define PIC_IRQS        (1<<2)
1720
1721 void __init setup_IO_APIC(void)
1722 {
1723         enable_IO_APIC();
1724
1725         if (acpi_ioapic)
1726                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1727         else
1728                 io_apic_irqs = ~PIC_IRQS;
1729
1730         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1731
1732         sync_Arb_IDs();
1733         setup_IO_APIC_irqs();
1734         init_IO_APIC_traps();
1735         check_timer();
1736         if (!acpi_ioapic)
1737                 print_IO_APIC();
1738 }
1739
1740 struct sysfs_ioapic_data {
1741         struct sys_device dev;
1742         struct IO_APIC_route_entry entry[0];
1743 };
1744 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1745
1746 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1747 {
1748         struct IO_APIC_route_entry *entry;
1749         struct sysfs_ioapic_data *data;
1750         int i;
1751
1752         data = container_of(dev, struct sysfs_ioapic_data, dev);
1753         entry = data->entry;
1754         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1755                 *entry = ioapic_read_entry(dev->id, i);
1756
1757         return 0;
1758 }
1759
1760 static int ioapic_resume(struct sys_device *dev)
1761 {
1762         struct IO_APIC_route_entry *entry;
1763         struct sysfs_ioapic_data *data;
1764         unsigned long flags;
1765         union IO_APIC_reg_00 reg_00;
1766         int i;
1767
1768         data = container_of(dev, struct sysfs_ioapic_data, dev);
1769         entry = data->entry;
1770
1771         spin_lock_irqsave(&ioapic_lock, flags);
1772         reg_00.raw = io_apic_read(dev->id, 0);
1773         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1774                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1775                 io_apic_write(dev->id, 0, reg_00.raw);
1776         }
1777         spin_unlock_irqrestore(&ioapic_lock, flags);
1778         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1779                 ioapic_write_entry(dev->id, i, entry[i]);
1780
1781         return 0;
1782 }
1783
1784 static struct sysdev_class ioapic_sysdev_class = {
1785         set_kset_name("ioapic"),
1786         .suspend = ioapic_suspend,
1787         .resume = ioapic_resume,
1788 };
1789
1790 static int __init ioapic_init_sysfs(void)
1791 {
1792         struct sys_device * dev;
1793         int i, size, error = 0;
1794
1795         error = sysdev_class_register(&ioapic_sysdev_class);
1796         if (error)
1797                 return error;
1798
1799         for (i = 0; i < nr_ioapics; i++ ) {
1800                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1801                         * sizeof(struct IO_APIC_route_entry);
1802                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1803                 if (!mp_ioapic_data[i]) {
1804                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1805                         continue;
1806                 }
1807                 memset(mp_ioapic_data[i], 0, size);
1808                 dev = &mp_ioapic_data[i]->dev;
1809                 dev->id = i;
1810                 dev->cls = &ioapic_sysdev_class;
1811                 error = sysdev_register(dev);
1812                 if (error) {
1813                         kfree(mp_ioapic_data[i]);
1814                         mp_ioapic_data[i] = NULL;
1815                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1816                         continue;
1817                 }
1818         }
1819
1820         return 0;
1821 }
1822
1823 device_initcall(ioapic_init_sysfs);
1824
1825 /*
1826  * Dynamic irq allocate and deallocation
1827  */
1828 int create_irq(void)
1829 {
1830         /* Allocate an unused irq */
1831         int irq;
1832         int new;
1833         unsigned long flags;
1834
1835         irq = -ENOSPC;
1836         spin_lock_irqsave(&vector_lock, flags);
1837         for (new = (NR_IRQS - 1); new >= 0; new--) {
1838                 if (platform_legacy_irq(new))
1839                         continue;
1840                 if (irq_cfg[new].vector != 0)
1841                         continue;
1842                 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1843                         irq = new;
1844                 break;
1845         }
1846         spin_unlock_irqrestore(&vector_lock, flags);
1847
1848         if (irq >= 0) {
1849                 dynamic_irq_init(irq);
1850         }
1851         return irq;
1852 }
1853
1854 void destroy_irq(unsigned int irq)
1855 {
1856         unsigned long flags;
1857
1858         dynamic_irq_cleanup(irq);
1859
1860         spin_lock_irqsave(&vector_lock, flags);
1861         __clear_irq_vector(irq);
1862         spin_unlock_irqrestore(&vector_lock, flags);
1863 }
1864
1865 /*
1866  * MSI mesage composition
1867  */
1868 #ifdef CONFIG_PCI_MSI
1869 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1870 {
1871         struct irq_cfg *cfg = irq_cfg + irq;
1872         int err;
1873         unsigned dest;
1874         cpumask_t tmp;
1875
1876         tmp = TARGET_CPUS;
1877         err = assign_irq_vector(irq, tmp);
1878         if (!err) {
1879                 cpus_and(tmp, cfg->domain, tmp);
1880                 dest = cpu_mask_to_apicid(tmp);
1881
1882                 msg->address_hi = MSI_ADDR_BASE_HI;
1883                 msg->address_lo =
1884                         MSI_ADDR_BASE_LO |
1885                         ((INT_DEST_MODE == 0) ?
1886                                 MSI_ADDR_DEST_MODE_PHYSICAL:
1887                                 MSI_ADDR_DEST_MODE_LOGICAL) |
1888                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1889                                 MSI_ADDR_REDIRECTION_CPU:
1890                                 MSI_ADDR_REDIRECTION_LOWPRI) |
1891                         MSI_ADDR_DEST_ID(dest);
1892
1893                 msg->data =
1894                         MSI_DATA_TRIGGER_EDGE |
1895                         MSI_DATA_LEVEL_ASSERT |
1896                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1897                                 MSI_DATA_DELIVERY_FIXED:
1898                                 MSI_DATA_DELIVERY_LOWPRI) |
1899                         MSI_DATA_VECTOR(cfg->vector);
1900         }
1901         return err;
1902 }
1903
1904 #ifdef CONFIG_SMP
1905 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1906 {
1907         struct irq_cfg *cfg = irq_cfg + irq;
1908         struct msi_msg msg;
1909         unsigned int dest;
1910         cpumask_t tmp;
1911
1912         cpus_and(tmp, mask, cpu_online_map);
1913         if (cpus_empty(tmp))
1914                 return;
1915
1916         if (assign_irq_vector(irq, mask))
1917                 return;
1918
1919         cpus_and(tmp, cfg->domain, mask);
1920         dest = cpu_mask_to_apicid(tmp);
1921
1922         read_msi_msg(irq, &msg);
1923
1924         msg.data &= ~MSI_DATA_VECTOR_MASK;
1925         msg.data |= MSI_DATA_VECTOR(cfg->vector);
1926         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1927         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1928
1929         write_msi_msg(irq, &msg);
1930         irq_desc[irq].affinity = mask;
1931 }
1932 #endif /* CONFIG_SMP */
1933
1934 /*
1935  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1936  * which implement the MSI or MSI-X Capability Structure.
1937  */
1938 static struct irq_chip msi_chip = {
1939         .name           = "PCI-MSI",
1940         .unmask         = unmask_msi_irq,
1941         .mask           = mask_msi_irq,
1942         .ack            = ack_apic_edge,
1943 #ifdef CONFIG_SMP
1944         .set_affinity   = set_msi_irq_affinity,
1945 #endif
1946         .retrigger      = ioapic_retrigger_irq,
1947 };
1948
1949 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
1950 {
1951         struct msi_msg msg;
1952         int irq, ret;
1953         irq = create_irq();
1954         if (irq < 0)
1955                 return irq;
1956
1957         ret = msi_compose_msg(dev, irq, &msg);
1958         if (ret < 0) {
1959                 destroy_irq(irq);
1960                 return ret;
1961         }
1962
1963         set_irq_msi(irq, desc);
1964         write_msi_msg(irq, &msg);
1965
1966         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1967
1968         return 0;
1969 }
1970
1971 void arch_teardown_msi_irq(unsigned int irq)
1972 {
1973         destroy_irq(irq);
1974 }
1975
1976 #endif /* CONFIG_PCI_MSI */
1977
1978 /*
1979  * Hypertransport interrupt support
1980  */
1981 #ifdef CONFIG_HT_IRQ
1982
1983 #ifdef CONFIG_SMP
1984
1985 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1986 {
1987         struct ht_irq_msg msg;
1988         fetch_ht_irq_msg(irq, &msg);
1989
1990         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1991         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1992
1993         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1994         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
1995
1996         write_ht_irq_msg(irq, &msg);
1997 }
1998
1999 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2000 {
2001         struct irq_cfg *cfg = irq_cfg + irq;
2002         unsigned int dest;
2003         cpumask_t tmp;
2004
2005         cpus_and(tmp, mask, cpu_online_map);
2006         if (cpus_empty(tmp))
2007                 return;
2008
2009         if (assign_irq_vector(irq, mask))
2010                 return;
2011
2012         cpus_and(tmp, cfg->domain, mask);
2013         dest = cpu_mask_to_apicid(tmp);
2014
2015         target_ht_irq(irq, dest, cfg->vector);
2016         irq_desc[irq].affinity = mask;
2017 }
2018 #endif
2019
2020 static struct irq_chip ht_irq_chip = {
2021         .name           = "PCI-HT",
2022         .mask           = mask_ht_irq,
2023         .unmask         = unmask_ht_irq,
2024         .ack            = ack_apic_edge,
2025 #ifdef CONFIG_SMP
2026         .set_affinity   = set_ht_irq_affinity,
2027 #endif
2028         .retrigger      = ioapic_retrigger_irq,
2029 };
2030
2031 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2032 {
2033         struct irq_cfg *cfg = irq_cfg + irq;
2034         int err;
2035         cpumask_t tmp;
2036
2037         tmp = TARGET_CPUS;
2038         err = assign_irq_vector(irq, tmp);
2039         if (!err) {
2040                 struct ht_irq_msg msg;
2041                 unsigned dest;
2042
2043                 cpus_and(tmp, cfg->domain, tmp);
2044                 dest = cpu_mask_to_apicid(tmp);
2045
2046                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2047
2048                 msg.address_lo =
2049                         HT_IRQ_LOW_BASE |
2050                         HT_IRQ_LOW_DEST_ID(dest) |
2051                         HT_IRQ_LOW_VECTOR(cfg->vector) |
2052                         ((INT_DEST_MODE == 0) ?
2053                                 HT_IRQ_LOW_DM_PHYSICAL :
2054                                 HT_IRQ_LOW_DM_LOGICAL) |
2055                         HT_IRQ_LOW_RQEOI_EDGE |
2056                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2057                                 HT_IRQ_LOW_MT_FIXED :
2058                                 HT_IRQ_LOW_MT_ARBITRATED) |
2059                         HT_IRQ_LOW_IRQ_MASKED;
2060
2061                 write_ht_irq_msg(irq, &msg);
2062
2063                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2064                                               handle_edge_irq, "edge");
2065         }
2066         return err;
2067 }
2068 #endif /* CONFIG_HT_IRQ */
2069
2070 /* --------------------------------------------------------------------------
2071                           ACPI-based IOAPIC Configuration
2072    -------------------------------------------------------------------------- */
2073
2074 #ifdef CONFIG_ACPI
2075
2076 #define IO_APIC_MAX_ID          0xFE
2077
2078 int __init io_apic_get_redir_entries (int ioapic)
2079 {
2080         union IO_APIC_reg_01    reg_01;
2081         unsigned long flags;
2082
2083         spin_lock_irqsave(&ioapic_lock, flags);
2084         reg_01.raw = io_apic_read(ioapic, 1);
2085         spin_unlock_irqrestore(&ioapic_lock, flags);
2086
2087         return reg_01.bits.entries;
2088 }
2089
2090
2091 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2092 {
2093         if (!IO_APIC_IRQ(irq)) {
2094                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2095                         ioapic);
2096                 return -EINVAL;
2097         }
2098
2099         /*
2100          * IRQs < 16 are already in the irq_2_pin[] map
2101          */
2102         if (irq >= 16)
2103                 add_pin_to_irq(irq, ioapic, pin);
2104
2105         setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2106
2107         return 0;
2108 }
2109
2110 #endif /* CONFIG_ACPI */
2111
2112
2113 /*
2114  * This function currently is only a helper for the i386 smp boot process where
2115  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2116  * so mask in all cases should simply be TARGET_CPUS
2117  */
2118 #ifdef CONFIG_SMP
2119 void __init setup_ioapic_dest(void)
2120 {
2121         int pin, ioapic, irq, irq_entry;
2122
2123         if (skip_ioapic_setup == 1)
2124                 return;
2125
2126         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2127                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2128                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2129                         if (irq_entry == -1)
2130                                 continue;
2131                         irq = pin_2_irq(irq_entry, ioapic, pin);
2132
2133                         /* setup_IO_APIC_irqs could fail to get vector for some device
2134                          * when you have too many devices, because at that time only boot
2135                          * cpu is online.
2136                          */
2137                         if (!irq_cfg[irq].vector)
2138                                 setup_IO_APIC_irq(ioapic, pin, irq,
2139                                                   irq_trigger(irq_entry),
2140                                                   irq_polarity(irq_entry));
2141                         else
2142                                 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2143                 }
2144
2145         }
2146 }
2147 #endif